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authorHarninder Rai2017-03-28 11:33:08 -0500
committerShawn Guo2017-03-28 22:53:19 -0500
commit7a5d73479fe46532783dcf97e751e15bab385576 (patch)
treeb9370c5781f044e6f43714d612765242b44ef5b6
parent85b85c56950790f45b10a5a3f436575537ab2c94 (diff)
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arm64: dts: Add support for FSL's LS1088A SoC
LS1088A contains eight ARM v8 CortexA53 processor cores with 32 KB L1-D cache and 32 KB L1-I cache Features summary Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Arranged as two clusters of four cores sharing a 1 MB L2 cache - Speed Up to 1.5 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 700 MHz One 64-bit DDR4 SDRAM memory controller with ECC Data path acceleration architecture 2.0 (DPAA2) Three PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Three high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1088A SoC family: - fsl-ls1088a.dtsi: DTS-Include file for NXP LS1088A SoC. - fsl-ls1088a-qds.dts: DTS file for NXP LS1088A QDS board. - fsl-ls1088a-rdb.dts: DTS file for NXP LS1088A RDB board Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>` Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/Makefile2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts123
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts107
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi275
4 files changed, 507 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6d5df45bd705..72c4b525726f 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
5dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb 5dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
6dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb 6dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
7dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb 7dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
8dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
9dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
8dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb 10dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
9dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb 11dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
10dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb 12dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
new file mode 100644
index 000000000000..8c3cae530f8f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
@@ -0,0 +1,123 @@
1/*
2 * Device Tree file for NXP LS1088A QDS Board.
3 *
4 * Copyright 2017 NXP
5 *
6 * Harninder Rai <harninder.rai@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls1088a.dtsi"
50
51/ {
52 model = "LS1088A QDS Board";
53 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
54};
55
56&i2c0 {
57 status = "okay";
58
59 i2c-switch@77 {
60 compatible = "nxp,pca9547";
61 reg = <0x77>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 i2c@2 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = <0x2>;
69
70 ina220@40 {
71 compatible = "ti,ina220";
72 reg = <0x40>;
73 shunt-resistor = <1000>;
74 };
75
76 ina220@41 {
77 compatible = "ti,ina220";
78 reg = <0x41>;
79 shunt-resistor = <1000>;
80 };
81 };
82
83 i2c@3 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0x3>;
87
88 temp-sensor@4c {
89 compatible = "adi,adt7461a";
90 reg = <0x4c>;
91 };
92
93 rtc@51 {
94 compatible = "nxp,pcf2129";
95 reg = <0x51>;
96 /* IRQ10_B */
97 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
98 };
99
100 eeprom@56 {
101 compatible = "atmel,24c512";
102 reg = <0x56>;
103 };
104
105 eeprom@57 {
106 compatible = "atmel,24c512";
107 reg = <0x57>;
108 };
109 };
110 };
111};
112
113&duart0 {
114 status = "okay";
115};
116
117&duart1 {
118 status = "okay";
119};
120
121&sata {
122 status = "okay";
123};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
new file mode 100644
index 000000000000..8a04fbb25cb4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -0,0 +1,107 @@
1/*
2 * Device Tree file for NXP LS1088A RDB Board.
3 *
4 * Copyright 2017 NXP
5 *
6 * Harninder Rai <harninder.rai@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls1088a.dtsi"
50
51/ {
52 model = "L1088A RDB Board";
53 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
54};
55
56&i2c0 {
57 status = "okay";
58
59 i2c-switch@77 {
60 compatible = "nxp,pca9547";
61 reg = <0x77>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 i2c@2 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = <0x2>;
69
70 ina220@40 {
71 compatible = "ti,ina220";
72 reg = <0x40>;
73 shunt-resistor = <1000>;
74 };
75 };
76
77 i2c@3 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0x3>;
81
82 temp-sensor@4c {
83 compatible = "adi,adt7461a";
84 reg = <0x4c>;
85 };
86
87 rtc@51 {
88 compatible = "nxp,pcf2129";
89 reg = <0x51>;
90 /* IRQ10_B */
91 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
92 };
93 };
94 };
95};
96
97&duart0 {
98 status = "okay";
99};
100
101&duart1 {
102 status = "okay";
103};
104
105&sata {
106 status = "okay";
107};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
new file mode 100644
index 000000000000..2946fd797121
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -0,0 +1,275 @@
1/*
2 * Device Tree Include file for NXP Layerscape-1088A family SoC.
3 *
4 * Copyright 2017 NXP
5 *
6 * Harninder Rai <harninder.rai@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46#include <dt-bindings/interrupt-controller/arm-gic.h>
47
48/ {
49 compatible = "fsl,ls1088a";
50 interrupt-parent = <&gic>;
51 #address-cells = <2>;
52 #size-cells = <2>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 /* We have 2 clusters having 4 Cortex-A53 cores each */
59 cpu0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clocks = <&clockgen 1 0>;
64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a53";
69 reg = <0x1>;
70 clocks = <&clockgen 1 0>;
71 };
72
73 cpu2: cpu@2 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a53";
76 reg = <0x2>;
77 clocks = <&clockgen 1 0>;
78 };
79
80 cpu3: cpu@3 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a53";
83 reg = <0x3>;
84 clocks = <&clockgen 1 0>;
85 };
86
87 cpu4: cpu@100 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x100>;
91 clocks = <&clockgen 1 1>;
92 };
93
94 cpu5: cpu@101 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a53";
97 reg = <0x101>;
98 clocks = <&clockgen 1 1>;
99 };
100
101 cpu6: cpu@102 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a53";
104 reg = <0x102>;
105 clocks = <&clockgen 1 1>;
106 };
107
108 cpu7: cpu@103 {
109 device_type = "cpu";
110 compatible = "arm,cortex-a53";
111 reg = <0x103>;
112 clocks = <&clockgen 1 1>;
113 };
114 };
115
116 gic: interrupt-controller@6000000 {
117 compatible = "arm,gic-v3";
118 #interrupt-cells = <3>;
119 interrupt-controller;
120 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
121 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
122 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
123 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
124 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
125 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
128 timer {
129 compatible = "arm,armv8-timer";
130 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
131 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
132 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
133 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
134 };
135
136 sysclk: sysclk {
137 compatible = "fixed-clock";
138 #clock-cells = <0>;
139 clock-frequency = <100000000>;
140 clock-output-names = "sysclk";
141 };
142
143 soc {
144 compatible = "simple-bus";
145 #address-cells = <2>;
146 #size-cells = <2>;
147 ranges;
148
149 clockgen: clocking@1300000 {
150 compatible = "fsl,ls1088a-clockgen";
151 reg = <0 0x1300000 0 0xa0000>;
152 #clock-cells = <2>;
153 clocks = <&sysclk>;
154 };
155
156 duart0: serial@21c0500 {
157 compatible = "fsl,ns16550", "ns16550a";
158 reg = <0x0 0x21c0500 0x0 0x100>;
159 clocks = <&clockgen 4 3>;
160 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
161 status = "disabled";
162 };
163
164 duart1: serial@21c0600 {
165 compatible = "fsl,ns16550", "ns16550a";
166 reg = <0x0 0x21c0600 0x0 0x100>;
167 clocks = <&clockgen 4 3>;
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
169 status = "disabled";
170 };
171
172 gpio0: gpio@2300000 {
173 compatible = "fsl,qoriq-gpio";
174 reg = <0x0 0x2300000 0x0 0x10000>;
175 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-controller;
177 #gpio-cells = <2>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 };
181
182 gpio1: gpio@2310000 {
183 compatible = "fsl,qoriq-gpio";
184 reg = <0x0 0x2310000 0x0 0x10000>;
185 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
186 gpio-controller;
187 #gpio-cells = <2>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 };
191
192 gpio2: gpio@2320000 {
193 compatible = "fsl,qoriq-gpio";
194 reg = <0x0 0x2320000 0x0 0x10000>;
195 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 gpio3: gpio@2330000 {
203 compatible = "fsl,qoriq-gpio";
204 reg = <0x0 0x2330000 0x0 0x10000>;
205 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 };
211
212 ifc: ifc@2240000 {
213 compatible = "fsl,ifc", "simple-bus";
214 reg = <0x0 0x2240000 0x0 0x20000>;
215 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
216 little-endian;
217 #address-cells = <2>;
218 #size-cells = <1>;
219
220 ranges = <0 0 0x5 0x80000000 0x08000000
221 2 0 0x5 0x30000000 0x00010000
222 3 0 0x5 0x20000000 0x00010000>;
223 status = "disabled";
224 };
225
226 i2c0: i2c@2000000 {
227 compatible = "fsl,vf610-i2c";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 reg = <0x0 0x2000000 0x0 0x10000>;
231 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&clockgen 4 3>;
233 status = "disabled";
234 };
235
236 i2c1: i2c@2010000 {
237 compatible = "fsl,vf610-i2c";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 reg = <0x0 0x2010000 0x0 0x10000>;
241 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clockgen 4 3>;
243 status = "disabled";
244 };
245
246 i2c2: i2c@2020000 {
247 compatible = "fsl,vf610-i2c";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 reg = <0x0 0x2020000 0x0 0x10000>;
251 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clockgen 4 3>;
253 status = "disabled";
254 };
255
256 i2c3: i2c@2030000 {
257 compatible = "fsl,vf610-i2c";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <0x0 0x2030000 0x0 0x10000>;
261 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clockgen 4 3>;
263 status = "disabled";
264 };
265
266 sata: sata@3200000 {
267 compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
268 reg = <0x0 0x3200000 0x0 0x10000>;
269 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clockgen 4 3>;
271 status = "disabled";
272 };
273 };
274
275};