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authorVineet Gupta2017-01-23 21:32:23 -0600
committerVineet Gupta2017-05-02 17:19:34 -0500
commit7d3d162bbd515070dfa4f422778276aa28f114d4 (patch)
treea55777b7a5b090a9474e9f1aae49986821167d05
parent36b5a5152119cd08760067ca31d8577de993c490 (diff)
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ARC: mm: Move full_page computation into cache version agnostic wrapper
This reduces code duplication in each of cache version specific handlers Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r--arch/arc/mm/cache.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 928562967f3c..18132eb56150 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -28,7 +28,7 @@ unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
28unsigned long perip_end = 0xFFFFFFFF; /* legacy value */ 28unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
29 29
30void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr, 30void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
31 unsigned long sz, const int cacheop); 31 unsigned long sz, const int op, const int full_page);
32 32
33void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz); 33void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
34void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz); 34void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
@@ -233,11 +233,10 @@ slc_chk:
233 233
234static inline 234static inline
235void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr, 235void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
236 unsigned long sz, const int op) 236 unsigned long sz, const int op, const int full_page)
237{ 237{
238 unsigned int aux_cmd; 238 unsigned int aux_cmd;
239 int num_lines; 239 int num_lines;
240 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
241 240
242 if (op == OP_INV_IC) { 241 if (op == OP_INV_IC) {
243 aux_cmd = ARC_REG_IC_IVIL; 242 aux_cmd = ARC_REG_IC_IVIL;
@@ -279,11 +278,10 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
279 */ 278 */
280static inline 279static inline
281void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr, 280void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
282 unsigned long sz, const int op) 281 unsigned long sz, const int op, const int full_page)
283{ 282{
284 unsigned int aux_cmd, aux_tag; 283 unsigned int aux_cmd, aux_tag;
285 int num_lines; 284 int num_lines;
286 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
287 285
288 if (op == OP_INV_IC) { 286 if (op == OP_INV_IC) {
289 aux_cmd = ARC_REG_IC_IVIL; 287 aux_cmd = ARC_REG_IC_IVIL;
@@ -349,17 +347,16 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
349 */ 347 */
350static inline 348static inline
351void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr, 349void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
352 unsigned long sz, const int cacheop) 350 unsigned long sz, const int op, const int full_page)
353{ 351{
354 unsigned int aux_cmd; 352 unsigned int aux_cmd;
355 int num_lines; 353 int num_lines;
356 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
357 354
358 if (cacheop == OP_INV_IC) { 355 if (op == OP_INV_IC) {
359 aux_cmd = ARC_REG_IC_IVIL; 356 aux_cmd = ARC_REG_IC_IVIL;
360 } else { 357 } else {
361 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 358 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
362 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; 359 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
363 } 360 }
364 361
365 /* Ensure we properly floor/ceil the non-line aligned/sized requests 362 /* Ensure we properly floor/ceil the non-line aligned/sized requests
@@ -368,7 +365,7 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
368 * -@paddr will be cache-line aligned already (being page aligned) 365 * -@paddr will be cache-line aligned already (being page aligned)
369 * -@sz will be integral multiple of line size (being page sized). 366 * -@sz will be integral multiple of line size (being page sized).
370 */ 367 */
371 if (!full_page_op) { 368 if (!full_page) {
372 sz += paddr & ~CACHE_LINE_MASK; 369 sz += paddr & ~CACHE_LINE_MASK;
373 paddr &= CACHE_LINE_MASK; 370 paddr &= CACHE_LINE_MASK;
374 } 371 }
@@ -381,7 +378,7 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
381 * - (and needs to be written before the lower 32 bits) 378 * - (and needs to be written before the lower 32 bits)
382 */ 379 */
383 if (is_pae40_enabled()) { 380 if (is_pae40_enabled()) {
384 if (cacheop == OP_INV_IC) 381 if (op == OP_INV_IC)
385 /* 382 /*
386 * Non aliasing I-cache in HS38, 383 * Non aliasing I-cache in HS38,
387 * aliasing I-cache handled in __cache_line_loop_v3() 384 * aliasing I-cache handled in __cache_line_loop_v3()
@@ -486,13 +483,14 @@ static void __dc_enable(void)
486static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr, 483static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr,
487 unsigned long sz, const int op) 484 unsigned long sz, const int op)
488{ 485{
486 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
489 unsigned long flags; 487 unsigned long flags;
490 488
491 local_irq_save(flags); 489 local_irq_save(flags);
492 490
493 __before_dc_op(op); 491 __before_dc_op(op);
494 492
495 __cache_line_loop(paddr, vaddr, sz, op); 493 __cache_line_loop(paddr, vaddr, sz, op, full_page);
496 494
497 __after_dc_op(op); 495 __after_dc_op(op);
498 496
@@ -521,10 +519,11 @@ static inline void
521__ic_line_inv_vaddr_local(phys_addr_t paddr, unsigned long vaddr, 519__ic_line_inv_vaddr_local(phys_addr_t paddr, unsigned long vaddr,
522 unsigned long sz) 520 unsigned long sz)
523{ 521{
522 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
524 unsigned long flags; 523 unsigned long flags;
525 524
526 local_irq_save(flags); 525 local_irq_save(flags);
527 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC); 526 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC, full_page);
528 local_irq_restore(flags); 527 local_irq_restore(flags);
529} 528}
530 529