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authorHoria Geantă2017-03-28 06:46:19 -0500
committerShawn Guo2017-03-28 22:02:32 -0500
commit85b85c56950790f45b10a5a3f436575537ab2c94 (patch)
tree3984b2b26c7f386a3fbbf2e19945553cb886caa7
parent893e2aad4612096c17a51c4fbc7f3897b7e45606 (diff)
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arm64: dts: ls1012a: add crypto node
LS1012A has a SEC v5.4 security engine. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi100
1 files changed, 99 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 60b533144414..b497ac196ccc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -42,7 +42,7 @@
42 * OTHER DEALINGS IN THE SOFTWARE. 42 * OTHER DEALINGS IN THE SOFTWARE.
43 */ 43 */
44 44
45#include <dt-bindings/interrupt-controller/irq.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/thermal/thermal.h> 46#include <dt-bindings/thermal/thermal.h>
47 47
48/ { 48/ {
@@ -51,6 +51,15 @@
51 #address-cells = <2>; 51 #address-cells = <2>;
52 #size-cells = <2>; 52 #size-cells = <2>;
53 53
54 aliases {
55 crypto = &crypto;
56 rtic_a = &rtic_a;
57 rtic_b = &rtic_b;
58 rtic_c = &rtic_c;
59 rtic_d = &rtic_d;
60 sec_mon = &sec_mon;
61 };
62
54 cpus { 63 cpus {
55 #address-cells = <1>; 64 #address-cells = <1>;
56 #size-cells = <0>; 65 #size-cells = <0>;
@@ -114,6 +123,95 @@
114 big-endian; 123 big-endian;
115 }; 124 };
116 125
126 crypto: crypto@1700000 {
127 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
128 "fsl,sec-v4.0";
129 fsl,sec-era = <8>;
130 #address-cells = <1>;
131 #size-cells = <1>;
132 ranges = <0x0 0x00 0x1700000 0x100000>;
133 reg = <0x00 0x1700000 0x0 0x100000>;
134 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
135
136 sec_jr0: jr@10000 {
137 compatible = "fsl,sec-v5.4-job-ring",
138 "fsl,sec-v5.0-job-ring",
139 "fsl,sec-v4.0-job-ring";
140 reg = <0x10000 0x10000>;
141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 };
143
144 sec_jr1: jr@20000 {
145 compatible = "fsl,sec-v5.4-job-ring",
146 "fsl,sec-v5.0-job-ring",
147 "fsl,sec-v4.0-job-ring";
148 reg = <0x20000 0x10000>;
149 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 sec_jr2: jr@30000 {
153 compatible = "fsl,sec-v5.4-job-ring",
154 "fsl,sec-v5.0-job-ring",
155 "fsl,sec-v4.0-job-ring";
156 reg = <0x30000 0x10000>;
157 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
158 };
159
160 sec_jr3: jr@40000 {
161 compatible = "fsl,sec-v5.4-job-ring",
162 "fsl,sec-v5.0-job-ring",
163 "fsl,sec-v4.0-job-ring";
164 reg = <0x40000 0x10000>;
165 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
166 };
167
168 rtic@60000 {
169 compatible = "fsl,sec-v5.4-rtic",
170 "fsl,sec-v5.0-rtic",
171 "fsl,sec-v4.0-rtic";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x60000 0x100 0x60e00 0x18>;
175 ranges = <0x0 0x60100 0x500>;
176
177 rtic_a: rtic-a@0 {
178 compatible = "fsl,sec-v5.4-rtic-memory",
179 "fsl,sec-v5.0-rtic-memory",
180 "fsl,sec-v4.0-rtic-memory";
181 reg = <0x00 0x20 0x100 0x100>;
182 };
183
184 rtic_b: rtic-b@20 {
185 compatible = "fsl,sec-v5.4-rtic-memory",
186 "fsl,sec-v5.0-rtic-memory",
187 "fsl,sec-v4.0-rtic-memory";
188 reg = <0x20 0x20 0x200 0x100>;
189 };
190
191 rtic_c: rtic-c@40 {
192 compatible = "fsl,sec-v5.4-rtic-memory",
193 "fsl,sec-v5.0-rtic-memory",
194 "fsl,sec-v4.0-rtic-memory";
195 reg = <0x40 0x20 0x300 0x100>;
196 };
197
198 rtic_d: rtic-d@60 {
199 compatible = "fsl,sec-v5.4-rtic-memory",
200 "fsl,sec-v5.0-rtic-memory",
201 "fsl,sec-v4.0-rtic-memory";
202 reg = <0x60 0x20 0x400 0x100>;
203 };
204 };
205 };
206
207 sec_mon: sec_mon@1e90000 {
208 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
209 "fsl,sec-v4.0-mon";
210 reg = <0x0 0x1e90000 0x0 0x10000>;
211 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
117 dcfg: dcfg@1ee0000 { 215 dcfg: dcfg@1ee0000 {
118 compatible = "fsl,ls1012a-dcfg", 216 compatible = "fsl,ls1012a-dcfg",
119 "syscon"; 217 "syscon";