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authorLinus Torvalds2017-05-09 11:54:39 -0500
committerLinus Torvalds2017-05-09 11:54:39 -0500
commit85d604902eb28eaea4f9e0f3a655ae986fa4bd2e (patch)
tree3ca4ff0c7e13c09ad006f378fac066790586f391
parent8d648aad05811ccc07df22834de60a7bf8d9e0e6 (diff)
parentb9f34da74e1c4b5f2574333277cd8d8f53bad056 (diff)
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson: "Device-tree continues to see lots of updates. The majority of patches here are smaller changes for new hardware on existing platforms, and there are a few larger changes worth pointing out. Major new platforms: - Gemini has been ported to DT, so a handful of "new" platforms moved over from board files - Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK - A bunch of embedded platforms, several Linksys platforms, Synology DS116, - Motorola Droid4 (really old OMAP-based phone) support is added. Some refactorings, i.e. Allwinner H3/H5 support is commonalized. And lots of smaller changes, cleanups, etc. See shortlog for more description We're adding ability to cross-include DT files between arm and arm64, by creating appropriate links in the dt-include directory, and using arm/ and arm64/ as include prefixes. This will avoid other local hacks such as per-file links between the two arch trees (this broke for external mirroring of DT contents). Now they can just provide their own appropriate dt-include hierarcy per platform" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits) ARM: dts: exynos: Use - instead of @ for DT OPP entries arm: spear6xx: add DT description of the ADC on SPEAr600 arm: spear6xx: remove unneeded pinctrl properties in spear600-evb arm: spear6xx: switch spear600-evb to the new flash partition DT binding arm: spear6xx: fix spaces in spear600-evb.dts arm: spear6xx: use node labels in spear600-evb.dts arm: spear6xx: add labels to various nodes in spear600.dtsi ARM: dts: vexpress: fix few unit address format warnings ARM: dts: at91: sama5d3_xplained: not all ADC channels are available ARM: dts: at91: sama5d3_xplained: fix ADC vref ARM: dts: at91: add envelope detector mux to the Axentia TSE-850 ARM: dts: armada-38x: label USB and SATA nodes ARM: dts: imx6q-utilite-pro: add hpd gpio ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply ARM: dts: imx6qdl-sabresd: Set LDO regulator supply ARM: dts: imx: add Gateworks Ventana GW5903 support ARM: dts: i.MX25: add AIPS control registers ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators ARM: dts: imx7-colibri: remove 1.8V fixed regulator ARM: dts: imx7-colibri: allow to disable Ethernet rail ...
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-rw-r--r--Documentation/devicetree/bindings/arm/rockchip.txt7
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-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt8
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-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socrates.dts8
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sodia.dts23
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_vt.dts2
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts148
-rw-r--r--arch/arm/boot/dts/spear600.dtsi28
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi18
-rw-r--r--arch/arm/boot/dts/stm32429i-eval.dts28
-rw-r--r--arch/arm/boot/dts/stm32746g-eval.dts4
-rw-r--r--arch/arm/boot/dts/stm32f429-disco.dts16
-rw-r--r--arch/arm/boot/dts/stm32f429.dtsi37
-rw-r--r--arch/arm/boot/dts/stm32f469-disco.dts16
-rw-r--r--arch/arm/boot/dts/stm32f746.dtsi96
-rw-r--r--arch/arm/boot/dts/stm32h743-pinctrl.dtsi156
-rw-r--r--arch/arm/boot/dts/stm32h743.dtsi83
-rw-r--r--arch/arm/boot/dts/stm32h743i-eval.dts74
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-inet1.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-marsboard.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mk802.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pcduino.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts1
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi40
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts5
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts3
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi77
-rw-r--r--arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a13-hsg-h702.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a13-licheepi-one.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts1
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi140
-rw-r--r--arch/arm/boot/dts/sun5i-gr8-chip-pro.dts4
-rw-r--r--arch/arm/boot/dts/sun5i-gr8-evb.dts4
-rw-r--r--arch/arm/boot/dts/sun5i-gr8.dtsi618
-rw-r--r--arch/arm/boot/dts/sun5i-r8-chip.dts6
-rw-r--r--arch/arm/boot/dts/sun5i-r8.dtsi40
-rw-r--r--arch/arm/boot/dts/sun5i.dtsi284
-rw-r--r--arch/arm/boot/dts/sun6i-a31-app4-evb1.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31-hummingbird.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31-i7.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31-m9.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi1
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-cs908.dts2
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-primo81.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi1
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-sina31s.dts23
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts57
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-bananapi.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts9
-rw-r--r--arch/arm/boot/dts/sun7i-a20-hummingbird.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-icnova-swac.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-m3.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-mk808c.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts36
-rw-r--r--arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-orangepi.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20-pcduino3.dts1
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi46
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi2
-rw-r--r--arch/arm/boot/dts/sun8i-a23-evb.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-a23-q8-tablet.dts10
-rw-r--r--arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts23
-rw-r--r--arch/arm/boot/dts/sun8i-a33.dtsi155
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi2
-rw-r--r--arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts21
-rw-r--r--arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-h3-beelink-x2.dts11
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts96
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi.dtsi1
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-2.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-one.dts23
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi602
-rw-r--r--arch/arm/boot/dts/sun9i-a80-cubieboard4.dts1
-rw-r--r--arch/arm/boot/dts/sun9i-a80-optimus.dts1
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi2
-rw-r--r--arch/arm/boot/dts/sunxi-common-regulators.dtsi1
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5.dtsi618
-rw-r--r--arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi1
-rw-r--r--arch/arm/boot/dts/uniphier-ld4-ref.dts10
-rw-r--r--arch/arm/boot/dts/uniphier-ld4.dtsi4
-rw-r--r--arch/arm/boot/dts/uniphier-ld6b-ref.dts10
-rw-r--r--arch/arm/boot/dts/uniphier-pinctrl.dtsi2
-rw-r--r--arch/arm/boot/dts/uniphier-pro4-ace.dts11
-rw-r--r--arch/arm/boot/dts/uniphier-pro4-ref.dts10
-rw-r--r--arch/arm/boot/dts/uniphier-pro4-sanji.dts11
-rw-r--r--arch/arm/boot/dts/uniphier-pro4.dtsi4
-rw-r--r--arch/arm/boot/dts/uniphier-pro5.dtsi4
-rw-r--r--arch/arm/boot/dts/uniphier-pxs2-gentil.dts11
-rw-r--r--arch/arm/boot/dts/uniphier-pxs2-vodka.dts10
-rw-r--r--arch/arm/boot/dts/uniphier-pxs2.dtsi4
-rw-r--r--arch/arm/boot/dts/uniphier-ref-daughter.dtsi4
-rw-r--r--arch/arm/boot/dts/uniphier-sld3-ref.dts12
-rw-r--r--arch/arm/boot/dts/uniphier-sld3.dtsi4
-rw-r--r--arch/arm/boot/dts/uniphier-sld8-ref.dts10
-rw-r--r--arch/arm/boot/dts/uniphier-sld8.dtsi4
-rw-r--r--arch/arm/boot/dts/uniphier-support-card.dtsi5
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi24
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi24
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts2
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts18
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts2
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts2
-rw-r--r--arch/arm/boot/dts/vf610-zii-dev-rev-b.dts14
-rw-r--r--arch/arm/boot/dts/vf610-zii-dev-rev-c.dts77
-rw-r--r--arch/arm/boot/dts/vf610-zii-dev.dtsi12
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi43
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2.dts17
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts18
l---------arch/arm64/boot/dts/include/arm1
l---------arch/arm64/boot/dts/include/arm641
-rw-r--r--include/dt-bindings/clock/r7s72100-clock.h9
-rw-r--r--include/dt-bindings/clock/r8a73a4-clock.h1
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h1
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h1
-rw-r--r--include/dt-bindings/clock/r8a7792-clock.h2
-rw-r--r--include/dt-bindings/clock/r8a7793-clock.h5
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h2
-rw-r--r--include/dt-bindings/mfd/stm32f7-rcc.h112
378 files changed, 13121 insertions, 2800 deletions
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 29737b9b616e..799af90dd75b 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -217,7 +217,8 @@ memory, bridge implementations, processor and other functionality not controlled
217elsewhere. 217elsewhere.
218 218
219required properties: 219required properties:
220- compatible: Should be "atmel,<chip>-sfr", "syscon". 220- compatible: Should be "atmel,<chip>-sfr", "syscon" or
221 "atmel,<chip>-sfrbu", "syscon"
221 <chip> can be "sama5d3", "sama5d4" or "sama5d2". 222 <chip> can be "sama5d3", "sama5d4" or "sama5d2".
222- reg: Should contain registers location and length 223- reg: Should contain registers location and length
223 224
diff --git a/Documentation/devicetree/bindings/arm/gemini.txt b/Documentation/devicetree/bindings/arm/gemini.txt
new file mode 100644
index 000000000000..0041eb031116
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gemini.txt
@@ -0,0 +1,86 @@
1Cortina systems Gemini platforms
2
3The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
4produced by Storlink Semiconductor around 2005. The company was renamed
5later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
6It was derived from earlier products from Storm named SL3316 (Centroid) and
7SL3512 (Bulverde).
8
9Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
10produced and used for NAS and similar usecases. In 2014 Cortina Systems was
11in turn acquired by Inphi, who seem to have discontinued this product family.
12
13Many of the IP blocks used in the SoC comes from Faraday Technology.
14
15Required properties (in root node):
16 compatible = "cortina,gemini";
17
18Required nodes:
19
20- soc: the SoC should be represented by a simple bus encompassing all the
21 onchip devices, this is referred to as the soc bus node.
22
23- syscon: the soc bus node must have a system controller node pointing to the
24 global control registers, with the compatible string
25 "cortina,gemini-syscon", "syscon";
26
27- timer: the soc bus node must have a timer node pointing to the SoC timer
28 block, with the compatible string "cortina,gemini-timer"
29 See: clocksource/cortina,gemini-timer.txt
30
31- interrupt-controller: the sob bus node must have an interrupt controller
32 node pointing to the SoC interrupt controller block, with the compatible
33 string "cortina,gemini-interrupt-controller"
34 See interrupt-controller/cortina,gemini-interrupt-controller.txt
35
36Example:
37
38/ {
39 model = "Foo Gemini Machine";
40 compatible = "cortina,gemini";
41 #address-cells = <1>;
42 #size-cells = <1>;
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x8000000>;
47 };
48
49 soc {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53 compatible = "simple-bus";
54 interrupt-parent = <&intcon>;
55
56 syscon: syscon@40000000 {
57 compatible = "cortina,gemini-syscon", "syscon";
58 reg = <0x40000000 0x1000>;
59 };
60
61 uart0: serial@42000000 {
62 compatible = "ns16550a";
63 reg = <0x42000000 0x100>;
64 clock-frequency = <48000000>;
65 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
66 reg-shift = <2>;
67 };
68
69 timer@43000000 {
70 compatible = "cortina,gemini-timer";
71 reg = <0x43000000 0x1000>;
72 interrupt-parent = <&intcon>;
73 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
74 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
75 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
76 syscon = <&syscon>;
77 };
78
79 intcon: interrupt-controller@48000000 {
80 compatible = "cortina,gemini-interrupt-controller";
81 reg = <0x48000000 0x1000>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
84 };
85 };
86};
diff --git a/Documentation/devicetree/bindings/arm/i2se.txt b/Documentation/devicetree/bindings/arm/i2se.txt
new file mode 100644
index 000000000000..dbd54a3aa07d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/i2se.txt
@@ -0,0 +1,22 @@
1I2SE Device Tree Bindings
2-------------------------
3
4Duckbill Board
5Required root node properties:
6 - compatible = "i2se,duckbill", "fsl,imx28";
7
8Duckbill 2 Board
9Required root node properties:
10 - compatible = "i2se,duckbill-2", "fsl,imx28";
11
12Duckbill 2 485 Board
13Required root node properties:
14 - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
15
16Duckbill 2 EnOcean Board
17Required root node properties:
18 - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
19
20Duckbill 2 SPI Board
21Required root node properties:
22 - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28";
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index cc4ace6397ab..6b8d50a0ee78 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -1,5 +1,8 @@
1Rockchip platforms device tree bindings 1Rockchip platforms device tree bindings
2--------------------------------------- 2---------------------------------------
3- Asus Tinker board
4 Required root node properties:
5 - compatible = "asus,rk3288-tinker", "rockchip,rk3288";
3 6
4- Kylin RK3036 board: 7- Kylin RK3036 board:
5 Required root node properties: 8 Required root node properties:
@@ -103,6 +106,10 @@ Rockchip platforms device tree bindings
103 Required root node properties: 106 Required root node properties:
104 - compatible = "mqmaker,miqi", "rockchip,rk3288"; 107 - compatible = "mqmaker,miqi", "rockchip,rk3288";
105 108
109- Phytec phyCORE-RK3288: Rapid Development Kit
110 Required root node properties:
111 - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
112
106- Rockchip PX3 Evaluation board: 113- Rockchip PX3 Evaluation board:
107 Required root node properties: 114 Required root node properties:
108 - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; 115 - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index c9502634316d..170fe0562c63 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -13,8 +13,12 @@ SoCs:
13 compatible = "renesas,r8a73a4" 13 compatible = "renesas,r8a73a4"
14 - R-Mobile A1 (R8A77400) 14 - R-Mobile A1 (R8A77400)
15 compatible = "renesas,r8a7740" 15 compatible = "renesas,r8a7740"
16 - RZ/G1H (R8A77420)
17 compatible = "renesas,r8a7742"
16 - RZ/G1M (R8A77430) 18 - RZ/G1M (R8A77430)
17 compatible = "renesas,r8a7743" 19 compatible = "renesas,r8a7743"
20 - RZ/G1N (R8A77440)
21 compatible = "renesas,r8a7744"
18 - RZ/G1E (R8A77450) 22 - RZ/G1E (R8A77450)
19 compatible = "renesas,r8a7745" 23 compatible = "renesas,r8a7745"
20 - R-Car M1A (R8A77781) 24 - R-Car M1A (R8A77781)
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
index ccf0adddc820..a855c1bffc0f 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -1,7 +1,13 @@
1NVIDIA Tegra Flow Controller 1NVIDIA Tegra Flow Controller
2 2
3Required properties: 3Required properties:
4- compatible: Should be "nvidia,tegra<chip>-flowctrl" 4- compatible: Should contain one of the following:
5 - "nvidia,tegra20-flowctrl": for Tegra20
6 - "nvidia,tegra30-flowctrl": for Tegra30
7 - "nvidia,tegra114-flowctrl": for Tegra114
8 - "nvidia,tegra124-flowctrl": for Tegra124
9 - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
10 - "nvidia,tegra210-flowctrl": for Tegra210
5- reg: Should contain one register range (address and length) 11- reg: Should contain one register range (address and length)
6 12
7Example: 13Example:
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index eb985a633d59..796c260c183d 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x:
31 4 = dclk (SDRAM Interface Clock) 31 4 = dclk (SDRAM Interface Clock)
32 5 = refclk (Reference Clock) 32 5 = refclk (Reference Clock)
33 33
34The following is a list of provided IDs and clock names on 98dx3236:
35 0 = tclk (Internal Bus clock)
36 1 = cpuclk (CPU clock)
37 2 = ddrclk (DDR clock)
38 3 = mpll (MPLL Clock)
39
34The following is a list of provided IDs and clock names on Kirkwood and Dove: 40The following is a list of provided IDs and clock names on Kirkwood and Dove:
35 0 = tclk (Internal Bus clock) 41 0 = tclk (Internal Bus clock)
36 1 = cpuclk (CPU0 clock) 42 1 = cpuclk (CPU0 clock)
@@ -49,6 +55,7 @@ Required properties:
49 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks 55 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
50 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks 56 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
51 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks 57 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
58 "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
52 "marvell,dove-core-clock" - for Dove SoC core clocks 59 "marvell,dove-core-clock" - for Dove SoC core clocks
53 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) 60 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
54 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC 61 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 5142efc8099d..de562da2ae77 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -119,6 +119,16 @@ ID Clock Peripheral
11929 sata1lnk 11929 sata1lnk
12030 sata1 SATA Host 1 12030 sata1 SATA Host 1
121 121
122The following is a list of provided IDs for 98dx3236:
123ID Clock Peripheral
124-----------------------------------
1253 ge1 Gigabit Ethernet 1
1264 ge0 Gigabit Ethernet 0
1275 pex0 PCIe Cntrl 0
12817 sdio SDHCI Host
12918 usb0 USB Host 0
13022 xor0 XOR DMA 0
131
122The following is a list of provided IDs for Dove: 132The following is a list of provided IDs for Dove:
123ID Clock Peripheral 133ID Clock Peripheral
124----------------------------------- 134-----------------------------------
@@ -169,6 +179,7 @@ Required properties:
169 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating 179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
170 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating 180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
171 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating 181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
172 "marvell,dove-gating-clock" - for Dove SoC clock gating 183 "marvell,dove-gating-clock" - for Dove SoC clock gating
173 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating 184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
174- reg : shall be the register address of the Clock Gating Control register 185- reg : shall be the register address of the Clock Gating Control register
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index d085ef90d27c..f8e946471a58 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -202,23 +202,23 @@ Example2 :
202 compatible = "operating-points-v2"; 202 compatible = "operating-points-v2";
203 opp-shared; 203 opp-shared;
204 204
205 opp@50000000 { 205 opp-50000000 {
206 opp-hz = /bits/ 64 <50000000>; 206 opp-hz = /bits/ 64 <50000000>;
207 opp-microvolt = <800000>; 207 opp-microvolt = <800000>;
208 }; 208 };
209 opp@100000000 { 209 opp-100000000 {
210 opp-hz = /bits/ 64 <100000000>; 210 opp-hz = /bits/ 64 <100000000>;
211 opp-microvolt = <800000>; 211 opp-microvolt = <800000>;
212 }; 212 };
213 opp@134000000 { 213 opp-134000000 {
214 opp-hz = /bits/ 64 <134000000>; 214 opp-hz = /bits/ 64 <134000000>;
215 opp-microvolt = <800000>; 215 opp-microvolt = <800000>;
216 }; 216 };
217 opp@200000000 { 217 opp-200000000 {
218 opp-hz = /bits/ 64 <200000000>; 218 opp-hz = /bits/ 64 <200000000>;
219 opp-microvolt = <825000>; 219 opp-microvolt = <825000>;
220 }; 220 };
221 opp@400000000 { 221 opp-400000000 {
222 opp-hz = /bits/ 64 <400000000>; 222 opp-hz = /bits/ 64 <400000000>;
223 opp-microvolt = <875000>; 223 opp-microvolt = <875000>;
224 }; 224 };
@@ -292,23 +292,23 @@ Example2 :
292 compatible = "operating-points-v2"; 292 compatible = "operating-points-v2";
293 opp-shared; 293 opp-shared;
294 294
295 opp@50000000 { 295 opp-50000000 {
296 opp-hz = /bits/ 64 <50000000>; 296 opp-hz = /bits/ 64 <50000000>;
297 opp-microvolt = <900000>; 297 opp-microvolt = <900000>;
298 }; 298 };
299 opp@80000000 { 299 opp-80000000 {
300 opp-hz = /bits/ 64 <80000000>; 300 opp-hz = /bits/ 64 <80000000>;
301 opp-microvolt = <900000>; 301 opp-microvolt = <900000>;
302 }; 302 };
303 opp@100000000 { 303 opp-100000000 {
304 opp-hz = /bits/ 64 <100000000>; 304 opp-hz = /bits/ 64 <100000000>;
305 opp-microvolt = <1000000>; 305 opp-microvolt = <1000000>;
306 }; 306 };
307 opp@134000000 { 307 opp-134000000 {
308 opp-hz = /bits/ 64 <134000000>; 308 opp-hz = /bits/ 64 <134000000>;
309 opp-microvolt = <1000000>; 309 opp-microvolt = <1000000>;
310 }; 310 };
311 opp@200000000 { 311 opp-200000000 {
312 opp-hz = /bits/ 64 <200000000>; 312 opp-hz = /bits/ 64 <200000000>;
313 opp-microvolt = <1000000>; 313 opp-microvolt = <1000000>;
314 }; 314 };
@@ -318,19 +318,19 @@ Example2 :
318 compatible = "operating-points-v2"; 318 compatible = "operating-points-v2";
319 opp-shared; 319 opp-shared;
320 320
321 opp@50000000 { 321 opp-50000000 {
322 opp-hz = /bits/ 64 <50000000>; 322 opp-hz = /bits/ 64 <50000000>;
323 }; 323 };
324 opp@80000000 { 324 opp-80000000 {
325 opp-hz = /bits/ 64 <80000000>; 325 opp-hz = /bits/ 64 <80000000>;
326 }; 326 };
327 opp@100000000 { 327 opp-100000000 {
328 opp-hz = /bits/ 64 <100000000>; 328 opp-hz = /bits/ 64 <100000000>;
329 }; 329 };
330 opp@200000000 { 330 opp-200000000 {
331 opp-hz = /bits/ 64 <200000000>; 331 opp-hz = /bits/ 64 <200000000>;
332 }; 332 };
333 opp@400000000 { 333 opp-400000000 {
334 opp-hz = /bits/ 64 <400000000>; 334 opp-hz = /bits/ 64 <400000000>;
335 }; 335 };
336 }; 336 };
@@ -339,19 +339,19 @@ Example2 :
339 compatible = "operating-points-v2"; 339 compatible = "operating-points-v2";
340 opp-shared; 340 opp-shared;
341 341
342 opp@50000000 { 342 opp-50000000 {
343 opp-hz = /bits/ 64 <50000000>; 343 opp-hz = /bits/ 64 <50000000>;
344 }; 344 };
345 opp@80000000 { 345 opp-80000000 {
346 opp-hz = /bits/ 64 <80000000>; 346 opp-hz = /bits/ 64 <80000000>;
347 }; 347 };
348 opp@100000000 { 348 opp-100000000 {
349 opp-hz = /bits/ 64 <100000000>; 349 opp-hz = /bits/ 64 <100000000>;
350 }; 350 };
351 opp@200000000 { 351 opp-200000000 {
352 opp-hz = /bits/ 64 <200000000>; 352 opp-hz = /bits/ 64 <200000000>;
353 }; 353 };
354 opp@300000000 { 354 opp-300000000 {
355 opp-hz = /bits/ 64 <300000000>; 355 opp-hz = /bits/ 64 <300000000>;
356 }; 356 };
357 }; 357 };
@@ -360,13 +360,13 @@ Example2 :
360 compatible = "operating-points-v2"; 360 compatible = "operating-points-v2";
361 opp-shared; 361 opp-shared;
362 362
363 opp@50000000 { 363 opp-50000000 {
364 opp-hz = /bits/ 64 <50000000>; 364 opp-hz = /bits/ 64 <50000000>;
365 }; 365 };
366 opp@80000000 { 366 opp-80000000 {
367 opp-hz = /bits/ 64 <80000000>; 367 opp-hz = /bits/ 64 <80000000>;
368 }; 368 };
369 opp@100000000 { 369 opp-100000000 {
370 opp-hz = /bits/ 64 <100000000>; 370 opp-hz = /bits/ 64 <100000000>;
371 }; 371 };
372 }; 372 };
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index b82c00449468..57a8d0610062 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -94,6 +94,7 @@ Required properties:
94 * allwinner,sun6i-a31-display-backend 94 * allwinner,sun6i-a31-display-backend
95 * allwinner,sun8i-a33-display-backend 95 * allwinner,sun8i-a33-display-backend
96 - reg: base address and size of the memory-mapped region. 96 - reg: base address and size of the memory-mapped region.
97 - interrupts: interrupt associated to this IP
97 - clocks: phandles to the clocks feeding the frontend and backend 98 - clocks: phandles to the clocks feeding the frontend and backend
98 * ahb: the backend interface clock 99 * ahb: the backend interface clock
99 * mod: the backend module clock 100 * mod: the backend module clock
@@ -265,6 +266,7 @@ fe0: display-frontend@1e00000 {
265be0: display-backend@1e60000 { 266be0: display-backend@1e60000 {
266 compatible = "allwinner,sun5i-a13-display-backend"; 267 compatible = "allwinner,sun5i-a13-display-backend";
267 reg = <0x01e60000 0x10000>; 268 reg = <0x01e60000 0x10000>;
269 interrupts = <47>;
268 clocks = <&ahb_gates 44>, <&de_be_clk>, 270 clocks = <&ahb_gates 44>, <&de_be_clk>,
269 <&dram_gates 26>; 271 <&dram_gates 26>;
270 clock-names = "ahb", "mod", 272 clock-names = "ahb", "mod",
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index 476f5ea6c627..2b6243e730f6 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -35,6 +35,14 @@ Optional properties:
35 - interrupt-names and interrupts: 35 - interrupt-names and interrupts:
36 * pmu: Power Management Unit interrupt, if implemented in hardware 36 * pmu: Power Management Unit interrupt, if implemented in hardware
37 37
38 - memory-region:
39 Memory region to allocate from, as defined in
40 Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
41
42 - operating-points-v2:
43 Operating Points for the GPU, as defined in
44 Documentation/devicetree/bindings/opp/opp.txt
45
38Vendor-specific bindings 46Vendor-specific bindings
39------------------------ 47------------------------
40 48
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index ff3db65e50de..b7e4c7444510 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -5,6 +5,7 @@ Required properties:
5 Currently recognized values: 5 Currently recognized values:
6 - nvidia,gk20a 6 - nvidia,gk20a
7 - nvidia,gm20b 7 - nvidia,gm20b
8 - nvidia,gp10b
8- reg: Physical base address and length of the controller's registers. 9- reg: Physical base address and length of the controller's registers.
9 Must contain two entries: 10 Must contain two entries:
10 - first entry for bar0 11 - first entry for bar0
@@ -14,7 +15,8 @@ Required properties:
14- interrupt-names: Must include the following entries: 15- interrupt-names: Must include the following entries:
15 - stall 16 - stall
16 - nonstall 17 - nonstall
17- vdd-supply: regulator for supply voltage. 18- vdd-supply: regulator for supply voltage. Only required for GPUs not using
19 power domains.
18- clocks: Must contain an entry for each entry in clock-names. 20- clocks: Must contain an entry for each entry in clock-names.
19 See ../clocks/clock-bindings.txt for details. 21 See ../clocks/clock-bindings.txt for details.
20- clock-names: Must include the following entries: 22- clock-names: Must include the following entries:
@@ -27,6 +29,8 @@ is also required:
27 See ../reset/reset.txt for details. 29 See ../reset/reset.txt for details.
28- reset-names: Must include the following entries: 30- reset-names: Must include the following entries:
29 - gpu 31 - gpu
32- power-domains: GPUs that make use of power domains can define this property
33 instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
30 34
31Optional properties: 35Optional properties:
32- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details. 36- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
@@ -68,3 +72,22 @@ Example for GM20B:
68 iommus = <&mc TEGRA_SWGROUP_GPU>; 72 iommus = <&mc TEGRA_SWGROUP_GPU>;
69 status = "disabled"; 73 status = "disabled";
70 }; 74 };
75
76Example for GP10B:
77
78 gpu@17000000 {
79 compatible = "nvidia,gp10b";
80 reg = <0x0 0x17000000 0x0 0x1000000>,
81 <0x0 0x18000000 0x0 0x1000000>;
82 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
83 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "stall", "nonstall";
85 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
86 <&bpmp TEGRA186_CLK_GPU>;
87 clock-names = "gpu", "pwr";
88 resets = <&bpmp TEGRA186_RESET_GPU>;
89 reset-names = "gpu";
90 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
91 iommus = <&smmu TEGRA186_SID_GPU>;
92 status = "disabled";
93 };
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 3e920ec5c4d3..9ce35af8507c 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -40,6 +40,7 @@ Required properties:
40 w25x80 40 w25x80
41 w25x32 41 w25x32
42 w25q32 42 w25q32
43 w25q64
43 w25q32dw 44 w25q32dw
44 w25q80bl 45 w25q80bl
45 w25q128 46 w25q128
diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
index 5fbab29718e8..c329608fa887 100644
--- a/Documentation/devicetree/bindings/net/marvell,prestera.txt
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -32,19 +32,16 @@ DFX Server bindings
32------------------- 32-------------------
33 33
34Required properties: 34Required properties:
35- compatible: must be "marvell,dfx-server" 35- compatible: must be "marvell,dfx-server", "simple-bus"
36- ranges: describes the address mapping of a memory-mapped bus.
36- reg: address and length of the register set for the device. 37- reg: address and length of the register set for the device.
37 38
38Example: 39Example:
39 40
40dfx-registers { 41dfx-server {
41 compatible = "simple-bus"; 42 compatible = "marvell,dfx-server", "simple-bus";
42 #address-cells = <1>; 43 #address-cells = <1>;
43 #size-cells = <1>; 44 #size-cells = <1>;
44 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; 45 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
45 46 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
46 dfx: dfx@0 {
47 compatible = "marvell,dfx-server";
48 reg = <0 0x100000>;
49 };
50}; 47};
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 6c7c2bce6d0c..00bea038639e 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -14,6 +14,10 @@ Required properties:
14 - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; 14 - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
15 - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; 15 - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
16 - snps,dwc2: A generic DWC2 USB controller with default parameters. 16 - snps,dwc2: A generic DWC2 USB controller with default parameters.
17 - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs
18 configured in FS mode;
19 - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs
20 configured in HS mode;
17- reg : Should contain 1 register range (address and length) 21- reg : Should contain 1 register range (address and length)
18- interrupts : Should contain 1 interrupt 22- interrupts : Should contain 1 interrupt
19- clocks: clock provider specifier 23- clocks: clock provider specifier
diff --git a/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt b/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
new file mode 100644
index 000000000000..bc4b865d178b
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
@@ -0,0 +1,17 @@
1Cortina Systems Gemini SoC Watchdog
2
3Required properties:
4- compatible : must be "cortina,gemini-watchdog"
5- reg : shall contain base register location and length
6- interrupts : shall contain the interrupt for the watchdog
7
8Optional properties:
9- timeout-sec : the default watchdog timeout in seconds.
10
11Example:
12
13watchdog@41000000 {
14 compatible = "cortina,gemini-watchdog";
15 reg = <0x41000000 0x1000>;
16 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
17};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 011808490fed..9c5e1d944d1c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
77 bcm4708-asus-rt-ac56u.dtb \ 77 bcm4708-asus-rt-ac56u.dtb \
78 bcm4708-asus-rt-ac68u.dtb \ 78 bcm4708-asus-rt-ac68u.dtb \
79 bcm4708-buffalo-wzr-1750dhp.dtb \ 79 bcm4708-buffalo-wzr-1750dhp.dtb \
80 bcm4708-linksys-ea6300-v1.dtb \
80 bcm4708-luxul-xap-1510.dtb \ 81 bcm4708-luxul-xap-1510.dtb \
81 bcm4708-luxul-xwc-1000.dtb \ 82 bcm4708-luxul-xwc-1000.dtb \
82 bcm4708-netgear-r6250.dtb \ 83 bcm4708-netgear-r6250.dtb \
@@ -87,17 +88,21 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
87 bcm47081-buffalo-wzr-900dhp.dtb \ 88 bcm47081-buffalo-wzr-900dhp.dtb \
88 bcm47081-luxul-xap-1410.dtb \ 89 bcm47081-luxul-xap-1410.dtb \
89 bcm47081-luxul-xwr-1200.dtb \ 90 bcm47081-luxul-xwr-1200.dtb \
91 bcm47081-tplink-archer-c5-v2.dtb \
90 bcm4709-asus-rt-ac87u.dtb \ 92 bcm4709-asus-rt-ac87u.dtb \
91 bcm4709-buffalo-wxr-1900dhp.dtb \ 93 bcm4709-buffalo-wxr-1900dhp.dtb \
94 bcm4709-linksys-ea9200.dtb \
92 bcm4709-netgear-r7000.dtb \ 95 bcm4709-netgear-r7000.dtb \
93 bcm4709-netgear-r8000.dtb \ 96 bcm4709-netgear-r8000.dtb \
94 bcm4709-tplink-archer-c9-v1.dtb \ 97 bcm4709-tplink-archer-c9-v1.dtb \
95 bcm47094-dlink-dir-885l.dtb \ 98 bcm47094-dlink-dir-885l.dtb \
99 bcm47094-linksys-panamera.dtb \
96 bcm47094-luxul-xwr-3100.dtb \ 100 bcm47094-luxul-xwr-3100.dtb \
97 bcm47094-netgear-r8500.dtb \ 101 bcm47094-netgear-r8500.dtb \
98 bcm94708.dtb \ 102 bcm94708.dtb \
99 bcm94709.dtb \ 103 bcm94709.dtb \
100 bcm953012er.dtb \ 104 bcm953012er.dtb \
105 bcm953012hr.dtb \
101 bcm953012k.dtb 106 bcm953012k.dtb
102dtb-$(CONFIG_ARCH_BCM_53573) += \ 107dtb-$(CONFIG_ARCH_BCM_53573) += \
103 bcm47189-tenda-ac9.dtb 108 bcm47189-tenda-ac9.dtb
@@ -173,6 +178,12 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
173 exynos5440-sd5v1.dtb \ 178 exynos5440-sd5v1.dtb \
174 exynos5440-ssdk5440.dtb \ 179 exynos5440-ssdk5440.dtb \
175 exynos5800-peach-pi.dtb 180 exynos5800-peach-pi.dtb
181dtb-$(CONFIG_ARCH_GEMINI) += \
182 gemini-nas4220b.dtb \
183 gemini-rut1xx.dtb \
184 gemini-sq201.dtb \
185 gemini-wbd111.dtb \
186 gemini-wbd222.dtb
176dtb-$(CONFIG_ARCH_HI3xxx) += \ 187dtb-$(CONFIG_ARCH_HI3xxx) += \
177 hi3620-hi4511.dtb 188 hi3620-hi4511.dtb
178dtb-$(CONFIG_ARCH_HIGHBANK) += \ 189dtb-$(CONFIG_ARCH_HIGHBANK) += \
@@ -352,6 +363,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
352 imx6dl-gw551x.dtb \ 363 imx6dl-gw551x.dtb \
353 imx6dl-gw552x.dtb \ 364 imx6dl-gw552x.dtb \
354 imx6dl-gw553x.dtb \ 365 imx6dl-gw553x.dtb \
366 imx6dl-gw5903.dtb \
367 imx6dl-gw5904.dtb \
355 imx6dl-hummingboard.dtb \ 368 imx6dl-hummingboard.dtb \
356 imx6dl-icore.dtb \ 369 imx6dl-icore.dtb \
357 imx6dl-icore-rqs.dtb \ 370 imx6dl-icore-rqs.dtb \
@@ -395,9 +408,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
395 imx6q-gw551x.dtb \ 408 imx6q-gw551x.dtb \
396 imx6q-gw552x.dtb \ 409 imx6q-gw552x.dtb \
397 imx6q-gw553x.dtb \ 410 imx6q-gw553x.dtb \
411 imx6q-gw5903.dtb \
412 imx6q-gw5904.dtb \
398 imx6q-h100.dtb \ 413 imx6q-h100.dtb \
399 imx6q-hummingboard.dtb \ 414 imx6q-hummingboard.dtb \
400 imx6q-icore.dtb \ 415 imx6q-icore.dtb \
416 imx6q-icore-ofcap10.dtb \
417 imx6q-icore-ofcap12.dtb \
401 imx6q-icore-rqs.dtb \ 418 imx6q-icore-rqs.dtb \
402 imx6q-marsboard.dtb \ 419 imx6q-marsboard.dtb \
403 imx6q-mccmon6.dtb \ 420 imx6q-mccmon6.dtb \
@@ -425,9 +442,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
425 imx6q-utilite-pro.dtb \ 442 imx6q-utilite-pro.dtb \
426 imx6q-wandboard.dtb \ 443 imx6q-wandboard.dtb \
427 imx6q-wandboard-revb1.dtb \ 444 imx6q-wandboard-revb1.dtb \
445 imx6q-zii-rdu2.dtb \
428 imx6qp-nitrogen6_max.dtb \ 446 imx6qp-nitrogen6_max.dtb \
447 imx6qp-nitrogen6_som2.dtb \
429 imx6qp-sabreauto.dtb \ 448 imx6qp-sabreauto.dtb \
430 imx6qp-sabresd.dtb 449 imx6qp-sabresd.dtb \
450 imx6qp-zii-rdu2.dtb
431dtb-$(CONFIG_SOC_IMX6SL) += \ 451dtb-$(CONFIG_SOC_IMX6SL) += \
432 imx6sl-evk.dtb \ 452 imx6sl-evk.dtb \
433 imx6sl-warp.dtb 453 imx6sl-warp.dtb
@@ -458,6 +478,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
458 imx7d-nitrogen7.dtb \ 478 imx7d-nitrogen7.dtb \
459 imx7d-sbc-imx7.dtb \ 479 imx7d-sbc-imx7.dtb \
460 imx7d-sdb.dtb \ 480 imx7d-sdb.dtb \
481 imx7d-sdb-sht11.dtb \
461 imx7s-colibri-eval-v3.dtb \ 482 imx7s-colibri-eval-v3.dtb \
462 imx7s-warp.dtb 483 imx7s-warp.dtb
463dtb-$(CONFIG_SOC_LS1021A) += \ 484dtb-$(CONFIG_SOC_LS1021A) += \
@@ -488,6 +509,10 @@ dtb-$(CONFIG_ARCH_MXS) += \
488 imx28-cfa10056.dtb \ 509 imx28-cfa10056.dtb \
489 imx28-cfa10057.dtb \ 510 imx28-cfa10057.dtb \
490 imx28-cfa10058.dtb \ 511 imx28-cfa10058.dtb \
512 imx28-duckbill-2-485.dtb \
513 imx28-duckbill-2.dtb \
514 imx28-duckbill-2-enocean.dtb \
515 imx28-duckbill-2-spi.dtb \
491 imx28-duckbill.dtb \ 516 imx28-duckbill.dtb \
492 imx28-eukrea-mbmx283lc.dtb \ 517 imx28-eukrea-mbmx283lc.dtb \
493 imx28-eukrea-mbmx287lc.dtb \ 518 imx28-eukrea-mbmx287lc.dtb \
@@ -673,6 +698,25 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
673 arm-realview-eb-a9mp-bbrevd.dtb \ 698 arm-realview-eb-a9mp-bbrevd.dtb \
674 arm-realview-pba8.dtb \ 699 arm-realview-pba8.dtb \
675 arm-realview-pbx-a9.dtb 700 arm-realview-pbx-a9.dtb
701dtb-$(CONFIG_ARCH_RENESAS) += \
702 emev2-kzm9d.dtb \
703 r7s72100-genmai.dtb \
704 r7s72100-rskrza1.dtb \
705 r8a73a4-ape6evm.dtb \
706 r8a7740-armadillo800eva.dtb \
707 r8a7743-sk-rzg1m.dtb \
708 r8a7745-sk-rzg1e.dtb \
709 r8a7778-bockw.dtb \
710 r8a7779-marzen.dtb \
711 r8a7790-lager.dtb \
712 r8a7791-koelsch.dtb \
713 r8a7791-porter.dtb \
714 r8a7792-blanche.dtb \
715 r8a7792-wheat.dtb \
716 r8a7793-gose.dtb \
717 r8a7794-alt.dtb \
718 r8a7794-silk.dtb \
719 sh73a0-kzm9g.dtb
676dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 720dtb-$(CONFIG_ARCH_ROCKCHIP) += \
677 rk1108-evb.dtb \ 721 rk1108-evb.dtb \
678 rk3036-evb.dtb \ 722 rk3036-evb.dtb \
@@ -692,9 +736,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
692 rk3288-firefly.dtb \ 736 rk3288-firefly.dtb \
693 rk3288-firefly-reload.dtb \ 737 rk3288-firefly-reload.dtb \
694 rk3288-miqi.dtb \ 738 rk3288-miqi.dtb \
739 rk3288-phycore-rdk.dtb \
695 rk3288-popmetal.dtb \ 740 rk3288-popmetal.dtb \
696 rk3288-r89.dtb \ 741 rk3288-r89.dtb \
697 rk3288-rock2-square.dtb \ 742 rk3288-rock2-square.dtb \
743 rk3288-tinker.dtb \
698 rk3288-veyron-brain.dtb \ 744 rk3288-veyron-brain.dtb \
699 rk3288-veyron-jaq.dtb \ 745 rk3288-veyron-jaq.dtb \
700 rk3288-veyron-jerry.dtb \ 746 rk3288-veyron-jerry.dtb \
@@ -713,25 +759,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
713 s5pv210-smdkc110.dtb \ 759 s5pv210-smdkc110.dtb \
714 s5pv210-smdkv210.dtb \ 760 s5pv210-smdkv210.dtb \
715 s5pv210-torbreck.dtb 761 s5pv210-torbreck.dtb
716dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
717 emev2-kzm9d.dtb \
718 r7s72100-genmai.dtb \
719 r7s72100-rskrza1.dtb \
720 r8a73a4-ape6evm.dtb \
721 r8a7740-armadillo800eva.dtb \
722 r8a7743-sk-rzg1m.dtb \
723 r8a7745-sk-rzg1e.dtb \
724 r8a7778-bockw.dtb \
725 r8a7779-marzen.dtb \
726 r8a7790-lager.dtb \
727 r8a7791-koelsch.dtb \
728 r8a7791-porter.dtb \
729 r8a7792-blanche.dtb \
730 r8a7792-wheat.dtb \
731 r8a7793-gose.dtb \
732 r8a7794-alt.dtb \
733 r8a7794-silk.dtb \
734 sh73a0-kzm9g.dtb
735dtb-$(CONFIG_ARCH_SOCFPGA) += \ 762dtb-$(CONFIG_ARCH_SOCFPGA) += \
736 socfpga_arria5_socdk.dtb \ 763 socfpga_arria5_socdk.dtb \
737 socfpga_arria10_socdk_nand.dtb \ 764 socfpga_arria10_socdk_nand.dtb \
@@ -764,7 +791,8 @@ dtb-$(CONFIG_ARCH_STM32)+= \
764 stm32f429-disco.dtb \ 791 stm32f429-disco.dtb \
765 stm32f469-disco.dtb \ 792 stm32f469-disco.dtb \
766 stm32429i-eval.dtb \ 793 stm32429i-eval.dtb \
767 stm32746g-eval.dtb 794 stm32746g-eval.dtb \
795 stm32h743i-eval.dtb
768dtb-$(CONFIG_MACH_SUN4I) += \ 796dtb-$(CONFIG_MACH_SUN4I) += \
769 sun4i-a10-a1000.dtb \ 797 sun4i-a10-a1000.dtb \
770 sun4i-a10-ba10-tvbox.dtb \ 798 sun4i-a10-ba10-tvbox.dtb \
@@ -868,6 +896,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
868 sun8i-h3-beelink-x2.dtb \ 896 sun8i-h3-beelink-x2.dtb \
869 sun8i-h3-nanopi-m1.dtb \ 897 sun8i-h3-nanopi-m1.dtb \
870 sun8i-h3-nanopi-neo.dtb \ 898 sun8i-h3-nanopi-neo.dtb \
899 sun8i-h3-nanopi-neo-air.dtb \
871 sun8i-h3-orangepi-2.dtb \ 900 sun8i-h3-orangepi-2.dtb \
872 sun8i-h3-orangepi-lite.dtb \ 901 sun8i-h3-orangepi-lite.dtb \
873 sun8i-h3-orangepi-one.dtb \ 902 sun8i-h3-orangepi-one.dtb \
@@ -970,6 +999,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
970 armada-385-db-ap.dtb \ 999 armada-385-db-ap.dtb \
971 armada-385-linksys-caiman.dtb \ 1000 armada-385-linksys-caiman.dtb \
972 armada-385-linksys-cobra.dtb \ 1001 armada-385-linksys-cobra.dtb \
1002 armada-385-linksys-shelby.dtb \
1003 armada-385-synology-ds116.dtb \
973 armada-385-turris-omnia.dtb \ 1004 armada-385-turris-omnia.dtb \
974 armada-388-clearfog.dtb \ 1005 armada-388-clearfog.dtb \
975 armada-388-clearfog-base.dtb \ 1006 armada-388-clearfog-base.dtb \
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index d0eefc3b886c..731df7a8c4e6 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -41,28 +41,28 @@
41 compatible = "arm,cortex-a15"; 41 compatible = "arm,cortex-a15";
42 device_type = "cpu"; 42 device_type = "cpu";
43 reg = <0>; 43 reg = <0>;
44 clock-frequency = <0>; /* Filled by loader */ 44 clock-frequency = <1700000000>;
45 }; 45 };
46 46
47 cpu@1 { 47 cpu@1 {
48 compatible = "arm,cortex-a15"; 48 compatible = "arm,cortex-a15";
49 device_type = "cpu"; 49 device_type = "cpu";
50 reg = <1>; 50 reg = <1>;
51 clock-frequency = <0>; /* Filled by loader */ 51 clock-frequency = <1700000000>;
52 }; 52 };
53 53
54 cpu@2 { 54 cpu@2 {
55 compatible = "arm,cortex-a15"; 55 compatible = "arm,cortex-a15";
56 device_type = "cpu"; 56 device_type = "cpu";
57 reg = <2>; 57 reg = <2>;
58 clock-frequency = <0>; /* Filled by loader */ 58 clock-frequency = <1700000000>;
59 }; 59 };
60 60
61 cpu@3 { 61 cpu@3 {
62 compatible = "arm,cortex-a15"; 62 compatible = "arm,cortex-a15";
63 device_type = "cpu"; 63 device_type = "cpu";
64 reg = <3>; 64 reg = <3>;
65 clock-frequency = <0>; /* Filled by loader */ 65 clock-frequency = <1700000000>;
66 }; 66 };
67 }; 67 };
68 68
@@ -81,7 +81,7 @@
81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
84 clock-frequency = <0>; /* Filled by loader */ 84 clock-frequency = <50000000>;
85 }; 85 };
86 86
87 /* Interrupt Controller */ 87 /* Interrupt Controller */
@@ -120,26 +120,26 @@
120 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 120 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
121 }; 121 };
122 122
123 uart0:uart@fd883000 { 123 uart0: uart@fd883000 {
124 compatible = "ns16550a"; 124 compatible = "ns16550a";
125 reg = <0x0 0xfd883000 0x0 0x1000>; 125 reg = <0x0 0xfd883000 0x0 0x1000>;
126 clock-frequency = <0>; /* Filled by loader */ 126 clock-frequency = <375000000>;
127 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 127 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
128 reg-shift = <2>; 128 reg-shift = <2>;
129 reg-io-width = <4>; 129 reg-io-width = <4>;
130 }; 130 };
131 131
132 uart1:uart@0xfd884000 { 132 uart1: uart@fd884000 {
133 compatible = "ns16550a"; 133 compatible = "ns16550a";
134 reg = <0x0 0xfd884000 0x0 0x1000>; 134 reg = <0x0 0xfd884000 0x0 0x1000>;
135 clock-frequency = <0>; /* Filled by loader */ 135 clock-frequency = <375000000>;
136 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 136 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
137 reg-shift = <2>; 137 reg-shift = <2>;
138 reg-io-width = <4>; 138 reg-io-width = <4>;
139 }; 139 };
140 140
141 /* Internal PCIe Controller */ 141 /* Internal PCIe Controller */
142 pcie-internal@0xfbc00000 { 142 pcie@fbc00000 {
143 compatible = "pci-host-ecam-generic"; 143 compatible = "pci-host-ecam-generic";
144 device_type = "pci"; 144 device_type = "pci";
145 #size-cells = <2>; 145 #size-cells = <2>;
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index 501c7527121b..75de1e723303 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -14,6 +14,7 @@
14/dts-v1/; 14/dts-v1/;
15 15
16#include "am335x-baltos.dtsi" 16#include "am335x-baltos.dtsi"
17#include "am335x-baltos-leds.dtsi"
17 18
18/ { 19/ {
19 model = "OnRISC Baltos iR 2110"; 20 model = "OnRISC Baltos iR 2110";
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index 19f53b8569e1..46df1b22022c 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -14,6 +14,7 @@
14/dts-v1/; 14/dts-v1/;
15 15
16#include "am335x-baltos.dtsi" 16#include "am335x-baltos.dtsi"
17#include "am335x-baltos-leds.dtsi"
17 18
18/ { 19/ {
19 model = "OnRISC Baltos iR 3220"; 20 model = "OnRISC Baltos iR 3220";
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index 2b9d7f4db23f..5d56355ba040 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -14,6 +14,7 @@
14/dts-v1/; 14/dts-v1/;
15 15
16#include "am335x-baltos.dtsi" 16#include "am335x-baltos.dtsi"
17#include "am335x-baltos-leds.dtsi"
17 18
18/ { 19/ {
19 model = "OnRISC Baltos iR 5221"; 20 model = "OnRISC Baltos iR 5221";
diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
new file mode 100644
index 000000000000..3ab1767d5c13
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * VScom OnRISC
11 * http://www.vscom.de
12 */
13
14/*#include "am33xx.dtsi"*/
15
16/ {
17 leds {
18 pinctrl-names = "default";
19 pinctrl-0 = <&user_leds>;
20
21 compatible = "gpio-leds";
22
23 power {
24 label = "onrisc:red:power";
25 linux,default-trigger = "default-on";
26 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
27 default-state = "on";
28 };
29 wlan {
30 label = "onrisc:blue:wlan";
31 gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
32 default-state = "off";
33 };
34 app {
35 label = "onrisc:green:app";
36 gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
37 default-state = "off";
38 };
39 };
40};
41
42&am33xx_pinmux {
43 user_leds: pinmux_user_leds {
44 pinctrl-single,pins = <
45 AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */
46 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */
47 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */
48 >;
49 };
50};
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 77273df1a028..935ed17d22e4 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -15,3 +15,14 @@
15 model = "TI AM335x BeagleBone Black"; 15 model = "TI AM335x BeagleBone Black";
16 compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; 16 compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
17}; 17};
18
19&cpu0_opp_table {
20 /*
21 * All PG 2.0 silicon may not support 1GHz but some of the early
22 * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
23 * to support 1GHz OPP so enable it for PG 2.0 on this board.
24 */
25 oppnitro@1000000000 {
26 opp-supported-hw = <0x06 0x0100>;
27 };
28};
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index a2ad076822db..f2005ecca74f 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -201,6 +201,69 @@
201 AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ 201 AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
202 >; 202 >;
203 }; 203 };
204
205 cpsw_default: cpsw_default {
206 pinctrl-single,pins = <
207 /* Slave 1, RMII mode */
208 AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */
209 AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */
210 AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */
211 AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */
212 AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */
213 AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */
214 AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */
215 AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */
216 /* Slave 2, RMII mode */
217 AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */
218 AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */
219 AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */
220 AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */
221 AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */
222 AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */
223 AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */
224 AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */
225 >;
226 };
227
228 cpsw_sleep: cpsw_sleep {
229 pinctrl-single,pins = <
230 /* Slave 1 reset value */
231 AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
232 AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
233 AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
234 AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
235 AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
236 AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
237 AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
238 AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
239
240 /* Slave 2 reset value */
241 AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
242 AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
243 AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
244 AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
245 AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
246 AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
247 AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
248 AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
249 >;
250 };
251
252 davinci_mdio_default: davinci_mdio_default {
253 pinctrl-single,pins = <
254 /* MDIO */
255 AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */
256 AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */
257 >;
258 };
259
260 davinci_mdio_sleep: davinci_mdio_sleep {
261 pinctrl-single,pins = <
262 /* MDIO reset value */
263 AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
264 AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
265 >;
266 };
204}; 267};
205 268
206&i2c0 { 269&i2c0 {
@@ -245,6 +308,39 @@
245 spi-max-frequency = <1000000>; 308 spi-max-frequency = <1000000>;
246 spi-cpol; 309 spi-cpol;
247 }; 310 };
311
312 spi_nor: flash@0 {
313 #address-cells = <1>;
314 #size-cells = <1>;
315 compatible = "winbond,w25q64", "jedec,spi-nor";
316 spi-max-frequency = <80000000>;
317 m25p,fast-read;
318 reg = <0>;
319
320 partition@0 {
321 label = "u-boot-spl";
322 reg = <0x0 0x80000>;
323 read-only;
324 };
325
326 partition@1 {
327 label = "u-boot";
328 reg = <0x80000 0x100000>;
329 read-only;
330 };
331
332 partition@2 {
333 label = "u-boot-env";
334 reg = <0x180000 0x20000>;
335 read-only;
336 };
337
338 partition@3 {
339 label = "misc";
340 reg = <0x1A0000 0x660000>;
341 };
342 };
343
248}; 344};
249 345
250&tscadc { 346&tscadc {
@@ -350,3 +446,61 @@
350 pinctrl-0 = <&uart3_pins_default>; 446 pinctrl-0 = <&uart3_pins_default>;
351 status = "okay"; 447 status = "okay";
352}; 448};
449
450&gpio3 {
451 p4 {
452 gpio-hog;
453 gpios = <4 GPIO_ACTIVE_HIGH>;
454 output-high;
455 line-name = "PR1_MII_CTRL";
456 };
457
458 p10 {
459 gpio-hog;
460 gpios = <10 GPIO_ACTIVE_HIGH>;
461 /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
462 output-high;
463 line-name = "MUX_MII_CTL1";
464 };
465};
466
467&cpsw_emac0 {
468 phy-handle = <&ethphy0>;
469 phy-mode = "rmii";
470 dual_emac_res_vlan = <1>;
471};
472
473&cpsw_emac1 {
474 phy-handle = <&ethphy1>;
475 phy-mode = "rmii";
476 dual_emac_res_vlan = <2>;
477};
478
479&mac {
480 pinctrl-names = "default", "sleep";
481 pinctrl-0 = <&cpsw_default>;
482 pinctrl-1 = <&cpsw_sleep>;
483 status = "okay";
484 dual_emac;
485};
486
487&phy_sel {
488 rmii-clock-ext;
489};
490
491&davinci_mdio {
492 pinctrl-names = "default", "sleep";
493 pinctrl-0 = <&davinci_mdio_default>;
494 pinctrl-1 = <&davinci_mdio_sleep>;
495 status = "okay";
496 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
497 reset-delay-us = <2>; /* PHY datasheet states 1uS min */
498
499 ethphy0: ethernet-phy@1 {
500 reg = <1>;
501 };
502
503 ethphy1: ethernet-phy@3 {
504 reg = <3>;
505 };
506};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 9e96d60976b7..9e242943dcec 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -46,19 +46,7 @@
46 device_type = "cpu"; 46 device_type = "cpu";
47 reg = <0>; 47 reg = <0>;
48 48
49 /* 49 operating-points-v2 = <&cpu0_opp_table>;
50 * To consider voltage drop between PMIC and SoC,
51 * tolerance value is reduced to 2% from 4% and
52 * voltage value is increased as a precaution.
53 */
54 operating-points = <
55 /* kHz uV */
56 720000 1285000
57 600000 1225000
58 500000 1125000
59 275000 1125000
60 >;
61 voltage-tolerance = <2>; /* 2 percentage */
62 50
63 clocks = <&dpll_mpu_ck>; 51 clocks = <&dpll_mpu_ck>;
64 clock-names = "cpu"; 52 clock-names = "cpu";
@@ -67,6 +55,79 @@
67 }; 55 };
68 }; 56 };
69 57
58 cpu0_opp_table: opp-table {
59 compatible = "operating-points-v2-ti-cpu";
60 syscon = <&scm_conf>;
61
62 /*
63 * The three following nodes are marked with opp-suspend
64 * because the can not be enabled simultaneously on a
65 * single SoC.
66 */
67 opp50@300000000 {
68 opp-hz = /bits/ 64 <300000000>;
69 opp-microvolt = <950000 931000 969000>;
70 opp-supported-hw = <0x06 0x0010>;
71 opp-suspend;
72 };
73
74 opp100@275000000 {
75 opp-hz = /bits/ 64 <275000000>;
76 opp-microvolt = <1100000 1078000 1122000>;
77 opp-supported-hw = <0x01 0x00FF>;
78 opp-suspend;
79 };
80
81 opp100@300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 opp-microvolt = <1100000 1078000 1122000>;
84 opp-supported-hw = <0x06 0x0020>;
85 opp-suspend;
86 };
87
88 opp100@500000000 {
89 opp-hz = /bits/ 64 <500000000>;
90 opp-microvolt = <1100000 1078000 1122000>;
91 opp-supported-hw = <0x01 0xFFFF>;
92 };
93
94 opp100@600000000 {
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <1100000 1078000 1122000>;
97 opp-supported-hw = <0x06 0x0040>;
98 };
99
100 opp120@600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <1200000 1176000 1224000>;
103 opp-supported-hw = <0x01 0xFFFF>;
104 };
105
106 opp120@720000000 {
107 opp-hz = /bits/ 64 <720000000>;
108 opp-microvolt = <1200000 1176000 1224000>;
109 opp-supported-hw = <0x06 0x0080>;
110 };
111
112 oppturbo@720000000 {
113 opp-hz = /bits/ 64 <720000000>;
114 opp-microvolt = <1260000 1234800 1285200>;
115 opp-supported-hw = <0x01 0xFFFF>;
116 };
117
118 oppturbo@800000000 {
119 opp-hz = /bits/ 64 <800000000>;
120 opp-microvolt = <1260000 1234800 1285200>;
121 opp-supported-hw = <0x06 0x0100>;
122 };
123
124 oppnitro@1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1325000 1298500 1351500>;
127 opp-supported-hw = <0x04 0x0200>;
128 };
129 };
130
70 pmu { 131 pmu {
71 compatible = "arm,cortex-a8-pmu"; 132 compatible = "arm,cortex-a8-pmu";
72 interrupts = <3>; 133 interrupts = <3>;
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 9fe545dbfa89..00da3f2c4072 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -13,6 +13,7 @@
13/ { 13/ {
14 aliases { 14 aliases {
15 serial3 = &uart4; 15 serial3 = &uart4;
16 can = &hecc;
16 }; 17 };
17 18
18 ocp@68000000 { 19 ocp@68000000 {
@@ -72,6 +73,17 @@
72 pinctrl-single,register-width = <16>; 73 pinctrl-single,register-width = <16>;
73 pinctrl-single,function-mask = <0xff1f>; 74 pinctrl-single,function-mask = <0xff1f>;
74 }; 75 };
76
77 hecc: can@5c050000 {
78 compatible = "ti,am3517-hecc";
79 status = "disabled";
80 reg = <0x5c050000 0x80>,
81 <0x5c053000 0x180>,
82 <0x5c052000 0x200>;
83 reg-names = "hecc", "hecc-ram", "mbx";
84 interrupts = <24>;
85 clocks = <&hecc_ck>;
86 };
75 }; 87 };
76}; 88};
77 89
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 97fcaf415de1..176e09e9a45e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -50,15 +50,14 @@
50 clock-names = "cpu"; 50 clock-names = "cpu";
51 51
52 operating-points-v2 = <&cpu0_opp_table>; 52 operating-points-v2 = <&cpu0_opp_table>;
53 ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
54 ti,syscon-rev = <&scm_conf 0x600>;
55 53
56 clock-latency = <300000>; /* From omap-cpufreq driver */ 54 clock-latency = <300000>; /* From omap-cpufreq driver */
57 }; 55 };
58 }; 56 };
59 57
60 cpu0_opp_table: opp_table0 { 58 cpu0_opp_table: opp-table {
61 compatible = "operating-points-v2"; 59 compatible = "operating-points-v2-ti-cpu";
60 syscon = <&scm_conf>;
62 61
63 opp50@300000000 { 62 opp50@300000000 {
64 opp-hz = /bits/ 64 <300000000>; 63 opp-hz = /bits/ 64 <300000000>;
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index a4f31739057f..397e98b7e246 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -501,6 +501,21 @@
501 AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ 501 AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
502 >; 502 >;
503 }; 503 };
504
505 uart0_pins_default: uart0_pins_default {
506 pinctrl-single,pins = <
507 AM4372_IOPAD(0x968, PIN_INPUT | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
508 AM4372_IOPAD(0x96C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
509 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
510 AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
511 >;
512 };
513};
514
515&uart0 {
516 status = "okay";
517 pinctrl-names = "default";
518 pinctrl-0 = <&uart0_pins_default>;
504}; 519};
505 520
506&i2c0 { 521&i2c0 {
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index e5ac1d81d15c..c536b2f5389f 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -101,6 +101,22 @@
101 }; 101 };
102}; 102};
103 103
104&dra7_pmx_core {
105 dcan1_pins_default: dcan1_pins_default {
106 pinctrl-single,pins = <
107 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
108 DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */
109 >;
110 };
111
112 dcan1_pins_sleep: dcan1_pins_sleep {
113 pinctrl-single,pins = <
114 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
115 DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
116 >;
117 };
118};
119
104&i2c1 { 120&i2c1 {
105 status = "okay"; 121 status = "okay";
106 clock-frequency = <400000>; 122 clock-frequency = <400000>;
@@ -391,6 +407,14 @@
391 max-frequency = <96000000>; 407 max-frequency = <96000000>;
392}; 408};
393 409
410&dcan1 {
411 status = "okay";
412 pinctrl-names = "default", "sleep", "active";
413 pinctrl-0 = <&dcan1_pins_sleep>;
414 pinctrl-1 = <&dcan1_pins_sleep>;
415 pinctrl-2 = <&dcan1_pins_default>;
416};
417
394&qspi { 418&qspi {
395 status = "okay"; 419 status = "okay";
396 420
diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
new file mode 100644
index 000000000000..c7a8ddd7f9a5
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -0,0 +1,114 @@
1/*
2 * Device Tree file for the Linksys WRT1900ACS (Shelby)
3 *
4 * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
5 *
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without
14 * any warranty of any kind, whether express or implied.
15 *
16 * Or, alternatively,
17 *
18 * b) Permission is hereby granted, free of charge, to any person
19 * obtaining a copy of this software and associated documentation
20 * files (the "Software"), to deal in the Software without
21 * restriction, including without limitation the rights to use,
22 * copy, modify, merge, publish, distribute, sublicense, and/or
23 * sell copies of the Software, and to permit persons to whom the
24 * Software is furnished to do so, subject to the following
25 * conditions:
26 *
27 * The above copyright notice and this permission notice shall be
28 * included in all copies or substantial portions of the Software.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
31 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
32 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
33 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
34 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
35 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
36 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
37 * OTHER DEALINGS IN THE SOFTWARE.
38 */
39
40/dts-v1/;
41#include "armada-385-linksys.dtsi"
42
43/ {
44 model = "Linksys WRT1900ACS";
45 compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
46 "marvell,armada380";
47
48 soc {
49 internal-regs{
50 i2c@11000 {
51
52 pca9635@68 {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 wan_amber@0 {
57 label = "shelby:amber:wan";
58 reg = <0x0>;
59 };
60
61 wan_white@1 {
62 label = "shelby:white:wan";
63 reg = <0x1>;
64 };
65
66 wlan_2g@2 {
67 label = "shelby:white:wlan_2g";
68 reg = <0x2>;
69 };
70
71 wlan_5g@3 {
72 label = "shelby:white:wlan_5g";
73 reg = <0x3>;
74 };
75
76 usb2@5 {
77 label = "shelby:white:usb2";
78 reg = <0x5>;
79 };
80
81 usb3_1@6 {
82 label = "shelby:white:usb3_1";
83 reg = <0x6>;
84 };
85
86 usb3_2@7 {
87 label = "shelby:white:usb3_2";
88 reg = <0x7>;
89 };
90
91 wps_white@8 {
92 label = "shelby:white:wps";
93 reg = <0x8>;
94 };
95
96 wps_amber@9 {
97 label = "shelby:amber:wps";
98 reg = <0x9>;
99 };
100 };
101 };
102 };
103 };
104
105 gpio-leds {
106 power {
107 label = "shelby:white:power";
108 };
109
110 sata {
111 label = "shelby:white:sata";
112 };
113 };
114};
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index df47bf1ea5eb..2306c45685b1 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -59,7 +59,8 @@
59 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 59 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
60 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 60 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
61 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 61 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
62 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; 62 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
63 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
63 64
64 internal-regs { 65 internal-regs {
65 i2c@11000 { 66 i2c@11000 {
@@ -88,6 +89,9 @@
88 ethernet@70000 { 89 ethernet@70000 {
89 status = "okay"; 90 status = "okay";
90 phy-mode = "rgmii-id"; 91 phy-mode = "rgmii-id";
92 buffer-manager = <&bm>;
93 bm,pool-long = <2>;
94 bm,pool-short = <3>;
91 fixed-link { 95 fixed-link {
92 speed = <1000>; 96 speed = <1000>;
93 full-duplex; 97 full-duplex;
@@ -97,6 +101,9 @@
97 ethernet@34000 { 101 ethernet@34000 {
98 status = "okay"; 102 status = "okay";
99 phy-mode = "sgmii"; 103 phy-mode = "sgmii";
104 buffer-manager = <&bm>;
105 bm,pool-long = <0>;
106 bm,pool-short = <1>;
100 fixed-link { 107 fixed-link {
101 speed = <1000>; 108 speed = <1000>;
102 full-duplex; 109 full-duplex;
@@ -159,6 +166,10 @@
159 status = "okay"; 166 status = "okay";
160 }; 167 };
161 168
169 bm@c8000 {
170 status = "okay";
171 };
172
162 /* USB part of the eSATA/USB 2.0 port */ 173 /* USB part of the eSATA/USB 2.0 port */
163 usb@58000 { 174 usb@58000 {
164 status = "okay"; 175 status = "okay";
@@ -241,6 +252,10 @@
241 }; 252 };
242 }; 253 };
243 254
255 bm-bppi {
256 status = "okay";
257 };
258
244 pcie-controller { 259 pcie-controller {
245 status = "okay"; 260 status = "okay";
246 261
@@ -305,6 +320,7 @@
305 sata { 320 sata {
306 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; 321 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
307 default-state = "off"; 322 default-state = "off";
323 linux,default-trigger = "disk-activity";
308 }; 324 };
309 }; 325 };
310 326
diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts
new file mode 100644
index 000000000000..31510eb56f10
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts
@@ -0,0 +1,321 @@
1/*
2 * Device Tree file for Synology DS116 NAS
3 *
4 * Copyright (C) 2017 Willy Tarreau <w@1wt.eu>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without
13 * any warranty of any kind, whether express or implied.
14 *
15 * Or, alternatively,
16 *
17 * b) Permission is hereby granted, free of charge, to any person
18 * obtaining a copy of this software and associated documentation
19 * files (the "Software"), to deal in the Software without
20 * restriction, including without limitation the rights to use,
21 * copy, modify, merge, publish, distribute, sublicense, and/or
22 * sell copies of the Software, and to permit persons to whom the
23 * Software is furnished to do so, subject to the following
24 * conditions:
25 *
26 * The above copyright notice and this permission notice shall be
27 * included in all copies or substantial portions of the Software.
28 *
29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
30 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
31 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
32 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
33 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
34 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
35 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
36 * OTHER DEALINGS IN THE SOFTWARE.
37 */
38
39/dts-v1/;
40#include "armada-385.dtsi"
41#include <dt-bindings/gpio/gpio.h>
42
43/ {
44 model = "Synology DS116";
45 compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
46
47 chosen {
48 stdout-path = "serial0:115200n8";
49 };
50
51 memory {
52 device_type = "memory";
53 reg = <0x00000000 0x40000000>; /* 1 GB */
54 };
55
56 soc {
57 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
58 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
59 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
60 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
61 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
62
63 internal-regs {
64 i2c@11000 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c0_pins>;
67 status = "okay";
68 clock-frequency = <100000>;
69
70 eeprom@57 {
71 compatible = "atmel,24c64";
72 reg = <0x57>;
73 };
74 };
75
76 serial@12000 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&uart0_pins>;
79 status = "okay";
80 };
81
82 serial@12100 {
83 /* A PIC16F1829 is connected to uart1 at 9600 bps,
84 * and takes single-character orders :
85 * "1" : power off // already handled by the poweroff node
86 * "2" : short beep
87 * "3" : long beep
88 * "4" : turn the power LED ON
89 * "5" : flash the power LED
90 * "6" : turn the power LED OFF
91 * "7" : turn the status LED OFF
92 * "8" : turn the status LED ON
93 * "9" : flash the status LED
94 * "A" : flash the motherboard LED (D8)
95 * "B" : turn the motherboard LED OFF
96 * "C" : hard reset
97 */
98 pinctrl-names = "default";
99 pinctrl-0 = <&uart1_pins>;
100 status = "okay";
101 };
102
103 poweroff@12100 {
104 compatible = "synology,power-off";
105 reg = <0x12100 0x100>;
106 clocks = <&coreclk 0>;
107 };
108
109 ethernet@70000 {
110 pinctrl-names = "default";
111 phy = <&phy0>;
112 phy-mode = "sgmii";
113 buffer-manager = <&bm>;
114 bm,pool-long = <0>;
115 status = "okay";
116 };
117
118
119 mdio@72004 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&mdio_pins>;
122
123 phy0: ethernet-phy@1 {
124 reg = <1>;
125 };
126 };
127
128 sata@a8000 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&sata0_pins>;
131 status = "okay";
132 #address-cells = <1>;
133 #size-cells = <0>;
134
135 sata0: sata-port@0 {
136 reg = <0>;
137 target-supply = <&reg_5v_sata0>;
138 };
139 };
140
141 bm@c8000 {
142 status = "okay";
143 };
144
145 usb3@f0000 {
146 usb-phy = <&usb3_0_phy>;
147 status = "okay";
148 };
149
150 usb3@f8000 {
151 usb-phy = <&usb3_1_phy>;
152 status = "okay";
153 };
154 };
155
156 bm-bppi {
157 status = "okay";
158 };
159
160 gpio-fan {
161 compatible = "gpio-fan";
162 gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
163 <&gpio1 17 GPIO_ACTIVE_HIGH>,
164 <&gpio1 16 GPIO_ACTIVE_HIGH>;
165 gpio-fan,speed-map = < 0 0
166 1500 1
167 2500 2
168 3000 3
169 3400 4
170 3700 5
171 3900 6
172 4000 7>;
173 cooling-cells = <2>;
174 };
175
176 gpio-leds {
177 compatible = "gpio-leds";
178
179 /* The green part is on gpio0.20 which is also used by
180 * sata0, and accesses to SATA disk 0 make it blink so it
181 * doesn't need to be declared here.
182 */
183 orange {
184 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
185 label = "ds116:orange:disk";
186 default-state = "off";
187 };
188 };
189 };
190
191 usb3_0_phy: usb3_0_phy {
192 compatible = "usb-nop-xceiv";
193 vcc-supply = <&reg_usb3_0_vbus>;
194 };
195
196 usb3_1_phy: usb3_1_phy {
197 compatible = "usb-nop-xceiv";
198 vcc-supply = <&reg_usb3_1_vbus>;
199 };
200
201 reg_usb3_0_vbus: usb3-vbus0 {
202 compatible = "regulator-fixed";
203 regulator-name = "usb3-vbus0";
204 pinctrl-names = "default";
205 pinctrl-0 = <&xhci0_vbus_pins>;
206 regulator-min-microvolt = <5000000>;
207 regulator-max-microvolt = <5000000>;
208 enable-active-high;
209 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
210 };
211
212 reg_usb3_1_vbus: usb3-vbus1 {
213 compatible = "regulator-fixed";
214 regulator-name = "usb3-vbus1";
215 pinctrl-names = "default";
216 pinctrl-0 = <&xhci1_vbus_pins>;
217 regulator-min-microvolt = <5000000>;
218 regulator-max-microvolt = <5000000>;
219 enable-active-high;
220 gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
221 };
222
223 reg_sata0: pwr-sata0 {
224 compatible = "regulator-fixed";
225 regulator-name = "pwr_en_sata0";
226 regulator-min-microvolt = <12000000>;
227 regulator-max-microvolt = <12000000>;
228 enable-active-high;
229 regulator-boot-on;
230 gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
231 };
232
233 reg_5v_sata0: v5-sata0 {
234 compatible = "regulator-fixed";
235 regulator-name = "v5.0-sata0";
236 regulator-min-microvolt = <5000000>;
237 regulator-max-microvolt = <5000000>;
238 vin-supply = <&reg_sata0>;
239 };
240
241 reg_12v_sata0: v12-sata0 {
242 compatible = "regulator-fixed";
243 regulator-name = "v12.0-sata0";
244 regulator-min-microvolt = <12000000>;
245 regulator-max-microvolt = <12000000>;
246 vin-supply = <&reg_sata0>;
247 };
248};
249
250&spi0 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&spi0_pins>;
253 status = "okay";
254
255 spi-flash@0 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 compatible = "macronix,mx25l6405d", "jedec,spi-nor";
259 reg = <0>; /* Chip select 0 */
260 spi-max-frequency = <50000000>;
261 m25p,fast-read;
262
263 /* Note: there is a redboot partition table despite u-boot
264 * being used. The names presented here are the same as those
265 * found in the FIS directory. There is also a small device
266 * tree in the last 64kB of the RedBoot partition which is not
267 * enumerated. The MAC address and the serial number are listed
268 * in the "vendor" partition.
269 */
270 partition@00000000 {
271 label = "RedBoot";
272 reg = <0x00000000 0x000f0000>;
273 read-only;
274 };
275
276 partition@000c0000 {
277 label = "zImage";
278 reg = <0x000f0000 0x002d0000>;
279 };
280
281 partition@00390000 {
282 label = "rd.gz";
283 reg = <0x003c0000 0x00410000>;
284 };
285
286 partition@007d0000 {
287 label = "vendor";
288 reg = <0x007d0000 0x00010000>;
289 read-only;
290 };
291
292 partition@007e0000 {
293 label = "RedBoot config";
294 reg = <0x007e0000 0x00010000>;
295 read-only;
296 };
297
298 partition@007f0000 {
299 label = "FIS directory";
300 reg = <0x007f0000 0x00010000>;
301 read-only;
302 };
303 };
304};
305
306&pinctrl {
307 /* use only one pin for UART1, as mpp20 is used by sata0 */
308 uart1_pins: uart-pins-1 {
309 marvell,pins = "mpp19";
310 marvell,function = "ua1";
311 };
312
313 xhci0_vbus_pins: xhci0_vbus_pins {
314 marvell,pins = "mpp58";
315 marvell,function = "gpio";
316 };
317 xhci1_vbus_pins: xhci1_vbus_pins {
318 marvell,pins = "mpp59";
319 marvell,function = "gpio";
320 };
321};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 8e63be33472e..7fcc4c4885cf 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -70,13 +70,7 @@
70 }; 70 };
71 71
72 soc { 72 soc {
73 internal-regs { 73 pciec: pcie-controller {
74 pinctrl@18000 {
75 compatible = "marvell,mv88f6820-pinctrl";
76 };
77 };
78
79 pcie-controller {
80 compatible = "marvell,armada-370-pcie"; 74 compatible = "marvell,armada-370-pcie";
81 status = "disabled"; 75 status = "disabled";
82 device_type = "pci"; 76 device_type = "pci";
@@ -106,7 +100,7 @@
106 * configured in x4 by the bootloader, then 100 * configured in x4 by the bootloader, then
107 * pcie@4,0 is not available. 101 * pcie@4,0 is not available.
108 */ 102 */
109 pcie@1,0 { 103 pcie1: pcie@1,0 {
110 device_type = "pci"; 104 device_type = "pci";
111 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 105 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
112 reg = <0x0800 0 0 0 0>; 106 reg = <0x0800 0 0 0 0>;
@@ -124,7 +118,7 @@
124 }; 118 };
125 119
126 /* x1 port */ 120 /* x1 port */
127 pcie@2,0 { 121 pcie2: pcie@2,0 {
128 device_type = "pci"; 122 device_type = "pci";
129 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 123 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
130 reg = <0x1000 0 0 0 0>; 124 reg = <0x1000 0 0 0 0>;
@@ -142,7 +136,7 @@
142 }; 136 };
143 137
144 /* x1 port */ 138 /* x1 port */
145 pcie@3,0 { 139 pcie3: pcie@3,0 {
146 device_type = "pci"; 140 device_type = "pci";
147 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 141 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
148 reg = <0x1800 0 0 0 0>; 142 reg = <0x1800 0 0 0 0>;
@@ -163,7 +157,7 @@
163 * x1 port only available when pcie@1,0 is 157 * x1 port only available when pcie@1,0 is
164 * configured as a x1 port 158 * configured as a x1 port
165 */ 159 */
166 pcie@4,0 { 160 pcie4: pcie@4,0 {
167 device_type = "pci"; 161 device_type = "pci";
168 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 162 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
169 reg = <0x2000 0 0 0 0>; 163 reg = <0x2000 0 0 0 0>;
@@ -182,3 +176,7 @@
182 }; 176 };
183 }; 177 };
184}; 178};
179
180&pinctrl {
181 compatible = "marvell,mv88f6820-pinctrl";
182};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 2745b7416313..0d5f1f062275 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -186,25 +186,6 @@
186 }; 186 };
187}; 187};
188 188
189&pinctrl {
190 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
191 marvell,pins = "mpp46";
192 marvell,function = "ref";
193 };
194 clearfog_dsa0_pins: clearfog-dsa0-pins {
195 marvell,pins = "mpp23", "mpp41";
196 marvell,function = "gpio";
197 };
198 clearfog_spi1_cs_pins: spi1-cs-pins {
199 marvell,pins = "mpp55";
200 marvell,function = "spi1";
201 };
202 rear_button_pins: rear-button-pins {
203 marvell,pins = "mpp34";
204 marvell,function = "gpio";
205 };
206};
207
208&mdio { 189&mdio {
209 status = "okay"; 190 status = "okay";
210 191
@@ -268,6 +249,25 @@
268 }; 249 };
269}; 250};
270 251
252&pinctrl {
253 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
254 marvell,pins = "mpp46";
255 marvell,function = "ref";
256 };
257 clearfog_dsa0_pins: clearfog-dsa0-pins {
258 marvell,pins = "mpp23", "mpp41";
259 marvell,function = "gpio";
260 };
261 clearfog_spi1_cs_pins: spi1-cs-pins {
262 marvell,pins = "mpp55";
263 marvell,function = "spi1";
264 };
265 rear_button_pins: rear-button-pins {
266 marvell,pins = "mpp34";
267 marvell,function = "gpio";
268 };
269};
270
271&spi1 { 271&spi1 {
272 /* 272 /*
273 * Add SPI CS pins for clearfog: 273 * Add SPI CS pins for clearfog:
diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
index 564fa5937e25..1c0d151b2aaa 100644
--- a/arch/arm/boot/dts/armada-388.dtsi
+++ b/arch/arm/boot/dts/armada-388.dtsi
@@ -50,13 +50,8 @@
50 model = "Marvell Armada 388 family SoC"; 50 model = "Marvell Armada 388 family SoC";
51 compatible = "marvell,armada388", "marvell,armada385", 51 compatible = "marvell,armada388", "marvell,armada385",
52 "marvell,armada380"; 52 "marvell,armada380";
53
54 soc { 53 soc {
55 internal-regs { 54 internal-regs {
56 pinctrl@18000 {
57 compatible = "marvell,mv88f6828-pinctrl";
58 };
59
60 sata@e0000 { 55 sata@e0000 {
61 compatible = "marvell,armada-380-ahci"; 56 compatible = "marvell,armada-380-ahci";
62 reg = <0xe0000 0x2000>; 57 reg = <0xe0000 0x2000>;
@@ -68,3 +63,7 @@
68 }; 63 };
69 }; 64 };
70}; 65};
66
67&pinctrl {
68 compatible = "marvell,mv88f6828-pinctrl";
69};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 79b767507eab..8b165c31de1e 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -82,7 +82,7 @@
82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
83 }; 83 };
84 84
85 devbus-bootcs { 85 devbus_bootcs: devbus-bootcs {
86 compatible = "marvell,mvebu-devbus"; 86 compatible = "marvell,mvebu-devbus";
87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -92,7 +92,7 @@
92 status = "disabled"; 92 status = "disabled";
93 }; 93 };
94 94
95 devbus-cs0 { 95 devbus_cs0: devbus-cs0 {
96 compatible = "marvell,mvebu-devbus"; 96 compatible = "marvell,mvebu-devbus";
97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -102,7 +102,7 @@
102 status = "disabled"; 102 status = "disabled";
103 }; 103 };
104 104
105 devbus-cs1 { 105 devbus_cs1: devbus-cs1 {
106 compatible = "marvell,mvebu-devbus"; 106 compatible = "marvell,mvebu-devbus";
107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -112,7 +112,7 @@
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114 114
115 devbus-cs2 { 115 devbus_cs2: devbus-cs2 {
116 compatible = "marvell,mvebu-devbus"; 116 compatible = "marvell,mvebu-devbus";
117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -122,7 +122,7 @@
122 status = "disabled"; 122 status = "disabled";
123 }; 123 };
124 124
125 devbus-cs3 { 125 devbus_cs3: devbus-cs3 {
126 compatible = "marvell,mvebu-devbus"; 126 compatible = "marvell,mvebu-devbus";
127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -339,7 +339,7 @@
339 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 339 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
340 }; 340 };
341 341
342 system-controller@18200 { 342 systemc: system-controller@18200 {
343 compatible = "marvell,armada-380-system-controller", 343 compatible = "marvell,armada-380-system-controller",
344 "marvell,armada-370-xp-system-controller"; 344 "marvell,armada-370-xp-system-controller";
345 reg = <0x18200 0x100>; 345 reg = <0x18200 0x100>;
@@ -360,7 +360,8 @@
360 360
361 mbusc: mbus-controller@20000 { 361 mbusc: mbus-controller@20000 {
362 compatible = "marvell,mbus-controller"; 362 compatible = "marvell,mbus-controller";
363 reg = <0x20000 0x100>, <0x20180 0x20>; 363 reg = <0x20000 0x100>, <0x20180 0x20>,
364 <0x20250 0x8>;
364 }; 365 };
365 366
366 mpic: interrupt-controller@20a00 { 367 mpic: interrupt-controller@20a00 {
@@ -373,7 +374,7 @@
373 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 374 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
374 }; 375 };
375 376
376 timer@20300 { 377 timer: timer@20300 {
377 compatible = "marvell,armada-380-timer", 378 compatible = "marvell,armada-380-timer",
378 "marvell,armada-xp-timer"; 379 "marvell,armada-xp-timer";
379 reg = <0x20300 0x30>, <0x21040 0x30>; 380 reg = <0x20300 0x30>, <0x21040 0x30>;
@@ -387,14 +388,14 @@
387 clock-names = "nbclk", "fixed"; 388 clock-names = "nbclk", "fixed";
388 }; 389 };
389 390
390 watchdog@20300 { 391 watchdog: watchdog@20300 {
391 compatible = "marvell,armada-380-wdt"; 392 compatible = "marvell,armada-380-wdt";
392 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 393 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
393 clocks = <&coreclk 2>, <&refclk>; 394 clocks = <&coreclk 2>, <&refclk>;
394 clock-names = "nbclk", "fixed"; 395 clock-names = "nbclk", "fixed";
395 }; 396 };
396 397
397 cpurst@20800 { 398 cpurst: cpurst@20800 {
398 compatible = "marvell,armada-370-cpu-reset"; 399 compatible = "marvell,armada-370-cpu-reset";
399 reg = <0x20800 0x10>; 400 reg = <0x20800 0x10>;
400 }; 401 };
@@ -404,12 +405,12 @@
404 reg = <0x20d20 0x6c>; 405 reg = <0x20d20 0x6c>;
405 }; 406 };
406 407
407 coherency-fabric@21010 { 408 coherencyfab: coherency-fabric@21010 {
408 compatible = "marvell,armada-380-coherency-fabric"; 409 compatible = "marvell,armada-380-coherency-fabric";
409 reg = <0x21010 0x1c>; 410 reg = <0x21010 0x1c>;
410 }; 411 };
411 412
412 pmsu@22000 { 413 pmsu: pmsu@22000 {
413 compatible = "marvell,armada-380-pmsu"; 414 compatible = "marvell,armada-380-pmsu";
414 reg = <0x22000 0x1000>; 415 reg = <0x22000 0x1000>;
415 }; 416 };
@@ -451,7 +452,7 @@
451 status = "disabled"; 452 status = "disabled";
452 }; 453 };
453 454
454 usb@58000 { 455 usb0: usb@58000 {
455 compatible = "marvell,orion-ehci"; 456 compatible = "marvell,orion-ehci";
456 reg = <0x58000 0x500>; 457 reg = <0x58000 0x500>;
457 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 458 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -459,7 +460,7 @@
459 status = "disabled"; 460 status = "disabled";
460 }; 461 };
461 462
462 xor@60800 { 463 xor0: xor@60800 {
463 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 464 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
464 reg = <0x60800 0x100 465 reg = <0x60800 0x100
465 0x60a00 0x100>; 466 0x60a00 0x100>;
@@ -479,7 +480,7 @@
479 }; 480 };
480 }; 481 };
481 482
482 xor@60900 { 483 xor1: xor@60900 {
483 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 484 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
484 reg = <0x60900 0x100 485 reg = <0x60900 0x100
485 0x60b00 0x100>; 486 0x60b00 0x100>;
@@ -507,7 +508,7 @@
507 clocks = <&gateclk 4>; 508 clocks = <&gateclk 4>;
508 }; 509 };
509 510
510 crypto@90000 { 511 cesa: crypto@90000 {
511 compatible = "marvell,armada-38x-crypto"; 512 compatible = "marvell,armada-38x-crypto";
512 reg = <0x90000 0x10000>; 513 reg = <0x90000 0x10000>;
513 reg-names = "regs"; 514 reg-names = "regs";
@@ -522,14 +523,14 @@
522 marvell,crypto-sram-size = <0x800>; 523 marvell,crypto-sram-size = <0x800>;
523 }; 524 };
524 525
525 rtc@a3800 { 526 rtc: rtc@a3800 {
526 compatible = "marvell,armada-380-rtc"; 527 compatible = "marvell,armada-380-rtc";
527 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 528 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
528 reg-names = "rtc", "rtc-soc"; 529 reg-names = "rtc", "rtc-soc";
529 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 530 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
530 }; 531 };
531 532
532 sata@a8000 { 533 ahci0: sata@a8000 {
533 compatible = "marvell,armada-380-ahci"; 534 compatible = "marvell,armada-380-ahci";
534 reg = <0xa8000 0x2000>; 535 reg = <0xa8000 0x2000>;
535 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 536 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -545,7 +546,7 @@
545 status = "disabled"; 546 status = "disabled";
546 }; 547 };
547 548
548 sata@e0000 { 549 ahci1: sata@e0000 {
549 compatible = "marvell,armada-380-ahci"; 550 compatible = "marvell,armada-380-ahci";
550 reg = <0xe0000 0x2000>; 551 reg = <0xe0000 0x2000>;
551 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 552 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -561,13 +562,13 @@
561 clock-output-names = "nand"; 562 clock-output-names = "nand";
562 }; 563 };
563 564
564 thermal@e8078 { 565 thermal: thermal@e8078 {
565 compatible = "marvell,armada380-thermal"; 566 compatible = "marvell,armada380-thermal";
566 reg = <0xe4078 0x4>, <0xe4074 0x4>; 567 reg = <0xe4078 0x4>, <0xe4074 0x4>;
567 status = "okay"; 568 status = "okay";
568 }; 569 };
569 570
570 flash@d0000 { 571 nand: flash@d0000 {
571 compatible = "marvell,armada370-nand"; 572 compatible = "marvell,armada370-nand";
572 reg = <0xd0000 0x54>; 573 reg = <0xd0000 0x54>;
573 #address-cells = <1>; 574 #address-cells = <1>;
@@ -577,7 +578,7 @@
577 status = "disabled"; 578 status = "disabled";
578 }; 579 };
579 580
580 sdhci@d8000 { 581 sdhci: sdhci@d8000 {
581 compatible = "marvell,armada-380-sdhci"; 582 compatible = "marvell,armada-380-sdhci";
582 reg-names = "sdhci", "mbus", "conf-sdio3"; 583 reg-names = "sdhci", "mbus", "conf-sdio3";
583 reg = <0xd8000 0x1000>, 584 reg = <0xd8000 0x1000>,
@@ -589,7 +590,7 @@
589 status = "disabled"; 590 status = "disabled";
590 }; 591 };
591 592
592 usb3@f0000 { 593 usb3_0: usb3@f0000 {
593 compatible = "marvell,armada-380-xhci"; 594 compatible = "marvell,armada-380-xhci";
594 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 595 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
595 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 596 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -597,7 +598,7 @@
597 status = "disabled"; 598 status = "disabled";
598 }; 599 };
599 600
600 usb3@f8000 { 601 usb3_1: usb3@f8000 {
601 compatible = "marvell,armada-380-xhci"; 602 compatible = "marvell,armada-380-xhci";
602 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 603 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
603 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 604 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index f6a03dcee5ef..84cc232a29e9 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -45,11 +45,14 @@
45 * common to all Armada XP SoCs. 45 * common to all Armada XP SoCs.
46 */ 46 */
47 47
48#include "armada-xp.dtsi" 48#include "armada-370-xp.dtsi"
49 49
50/ { 50/ {
51 #address-cells = <2>;
52 #size-cells = <2>;
53
51 model = "Marvell 98DX3236 SoC"; 54 model = "Marvell 98DX3236 SoC";
52 compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; 55 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
53 56
54 aliases { 57 aliases {
55 gpio0 = &gpio0; 58 gpio0 = &gpio0;
@@ -72,12 +75,19 @@
72 }; 75 };
73 76
74 soc { 77 soc {
78 compatible = "marvell,armadaxp-mbus", "simple-bus";
79
75 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 80 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
76 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 81 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
77 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 82 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
78 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000 83 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
79 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>; 84 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
80 85
86 bootrom {
87 compatible = "marvell,bootrom";
88 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
89 };
90
81 /* 91 /*
82 * 98DX3236 has 1 x1 PCIe unit Gen2.0 92 * 98DX3236 has 1 x1 PCIe unit Gen2.0
83 */ 93 */
@@ -95,8 +105,7 @@
95 ranges = 105 ranges =
96 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 106 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
97 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 107 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
98 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 108 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
99 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
100 109
101 pcie1: pcie@1,0 { 110 pcie1: pcie@1,0 {
102 device_type = "pci"; 111 device_type = "pci";
@@ -117,31 +126,86 @@
117 }; 126 };
118 127
119 internal-regs { 128 internal-regs {
120 coreclk: mvebu-sar@18230 { 129 sdramc@1400 {
121 compatible = "marvell,mv98dx3236-core-clock"; 130 compatible = "marvell,armada-xp-sdram-controller";
131 reg = <0x1400 0x500>;
132 };
133
134 L2: l2-cache@8000 {
135 compatible = "marvell,aurora-system-cache";
136 reg = <0x08000 0x1000>;
137 cache-id-part = <0x100>;
138 cache-level = <2>;
139 cache-unified;
140 wt-override;
141 };
142
143 gpio0: gpio@18100 {
144 compatible = "marvell,orion-gpio";
145 reg = <0x18100 0x40>;
146 ngpios = <32>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 interrupts = <82>, <83>, <84>, <85>;
152 };
153
154 /* does not exist */
155 gpio1: gpio@18140 {
156 compatible = "marvell,orion-gpio";
157 reg = <0x18140 0x40>;
158 status = "disabled";
159 };
160
161 gpio2: gpio@18180 { /* rework some properties */
162 compatible = "marvell,orion-gpio";
163 reg = <0x18180 0x40>;
164 ngpios = <1>; /* only gpio #32 */
165 gpio-controller;
166 #gpio-cells = <2>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
169 interrupts = <87>;
170 };
171
172 systemc: system-controller@18200 {
173 compatible = "marvell,armada-370-xp-system-controller";
174 reg = <0x18200 0x500>;
175 };
176
177 gateclk: clock-gating-control@18220 {
178 compatible = "marvell,mv98dx3236-gating-clock";
179 reg = <0x18220 0x4>;
180 clocks = <&coreclk 0>;
181 #clock-cells = <1>;
122 }; 182 };
123 183
124 cpuclk: clock-complex@18700 { 184 cpuclk: clock-complex@18700 {
185 #clock-cells = <1>;
125 compatible = "marvell,mv98dx3236-cpu-clock"; 186 compatible = "marvell,mv98dx3236-cpu-clock";
187 reg = <0x18700 0x24>, <0x1c054 0x10>;
188 clocks = <&coreclk 1>;
126 }; 189 };
127 190
128 corediv-clock@18740 { 191 corediv-clock@18740 {
129 status = "disabled"; 192 status = "disabled";
130 }; 193 };
131 194
132 xor@60900 { 195 cpu-config@21000 {
133 status = "disabled"; 196 compatible = "marvell,armada-xp-cpu-config";
197 reg = <0x21000 0x8>;
134 }; 198 };
135 199
136 crypto@90000 { 200 ethernet@70000 {
137 status = "disabled"; 201 compatible = "marvell,armada-xp-neta";
138 }; 202 };
139 203
140 xor@f0900 { 204 ethernet@74000 {
141 status = "disabled"; 205 compatible = "marvell,armada-xp-neta";
142 }; 206 };
143 207
144 xor@f0800 { 208 xor1: xor@f0800 {
145 compatible = "marvell,orion-xor"; 209 compatible = "marvell,orion-xor";
146 reg = <0xf0800 0x100 210 reg = <0xf0800 0x100
147 0xf0a00 0x100>; 211 0xf0a00 0x100>;
@@ -161,45 +225,43 @@
161 }; 225 };
162 }; 226 };
163 227
164 gpio0: gpio@18100 { 228 nand: nand@d0000 {
165 compatible = "marvell,orion-gpio"; 229 clocks = <&dfx_coredivclk 0>;
166 reg = <0x18100 0x40>;
167 ngpios = <32>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 interrupts = <82>, <83>, <84>, <85>;
173 };
174
175 /* does not exist */
176 gpio1: gpio@18140 {
177 compatible = "marvell,orion-gpio";
178 reg = <0x18140 0x40>;
179 status = "disabled";
180 }; 230 };
181 231
182 gpio2: gpio@18180 { /* rework some properties */ 232 xor0: xor@f0900 {
183 compatible = "marvell,orion-gpio"; 233 compatible = "marvell,orion-xor";
184 reg = <0x18180 0x40>; 234 reg = <0xF0900 0x100
185 ngpios = <1>; /* only gpio #32 */ 235 0xF0B00 0x100>;
186 gpio-controller; 236 clocks = <&gateclk 28>;
187 #gpio-cells = <2>; 237 status = "okay";
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 interrupts = <87>;
191 };
192 238
193 nand: nand@d0000 { 239 xor00 {
194 clocks = <&dfx_coredivclk 0>; 240 interrupts = <94>;
241 dmacap,memcpy;
242 dmacap,xor;
243 };
244 xor01 {
245 interrupts = <95>;
246 dmacap,memcpy;
247 dmacap,xor;
248 dmacap,memset;
249 };
195 }; 250 };
196 }; 251 };
197 252
198 dfxr: dfx-registers@ac000000 { 253 dfx: dfx-server@ac000000 {
199 compatible = "simple-bus"; 254 compatible = "marvell,dfx-server", "simple-bus";
200 #address-cells = <1>; 255 #address-cells = <1>;
201 #size-cells = <1>; 256 #size-cells = <1>;
202 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; 257 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
258 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
259
260 coreclk: mvebu-sar@f8204 {
261 compatible = "marvell,mv98dx3236-core-clock";
262 reg = <0xf8204 0x4>;
263 #clock-cells = <1>;
264 };
203 265
204 dfx_coredivclk: corediv-clock@f8268 { 266 dfx_coredivclk: corediv-clock@f8268 {
205 compatible = "marvell,mv98dx3236-corediv-clock"; 267 compatible = "marvell,mv98dx3236-corediv-clock";
@@ -208,11 +270,6 @@
208 clocks = <&mainpll>; 270 clocks = <&mainpll>;
209 clock-output-names = "nand"; 271 clock-output-names = "nand";
210 }; 272 };
211
212 dfx: dfx@0 {
213 compatible = "marvell,dfx-server";
214 reg = <0 0x100000>;
215 };
216 }; 273 };
217 274
218 switch: switch@a8000000 { 275 switch: switch@a8000000 {
@@ -229,6 +286,53 @@
229 }; 286 };
230 }; 287 };
231 }; 288 };
289
290 clocks {
291 /* 25 MHz reference crystal */
292 refclk: oscillator {
293 compatible = "fixed-clock";
294 #clock-cells = <0>;
295 clock-frequency = <25000000>;
296 };
297 };
298};
299
300&i2c0 {
301 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
302 reg = <0x11000 0x100>;
303};
304
305&i2c1 {
306 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
307 reg = <0x11100 0x100>;
308};
309
310&mpic {
311 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
312};
313
314&timer {
315 compatible = "marvell,armada-xp-timer";
316 clocks = <&coreclk 2>, <&refclk>;
317 clock-names = "nbclk", "fixed";
318};
319
320&watchdog {
321 compatible = "marvell,armada-xp-wdt";
322 clocks = <&coreclk 2>, <&refclk>;
323 clock-names = "nbclk", "fixed";
324};
325
326&cpurst {
327 reg = <0x20800 0x20>;
328};
329
330&usb0 {
331 clocks = <&gateclk 18>;
332};
333
334&usb1 {
335 clocks = <&gateclk 19>;
232}; 336};
233 337
234&pinctrl { 338&pinctrl {
@@ -241,14 +345,13 @@
241 }; 345 };
242}; 346};
243 347
244&sdio { 348&spi0 {
245 status = "disabled"; 349 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
350 pinctrl-0 = <&spi0_pins>;
351 pinctrl-names = "default";
246}; 352};
247 353
248&crypto_sram0 { 354&sdio {
249 status = "disabled"; 355 status = "disabled";
250}; 356};
251 357
252&crypto_sram1 {
253 status = "disabled";
254};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
index e1580afdc260..a0d81bd7312b 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -49,7 +49,7 @@
49 49
50/ { 50/ {
51 model = "Marvell 98DX3336 SoC"; 51 model = "Marvell 98DX3336 SoC";
52 compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; 52 compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
53 53
54 cpus { 54 cpus {
55 cpu@1 { 55 cpu@1 {
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index b9d9b269efb4..51de91b31a9d 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -49,7 +49,7 @@
49 49
50/ { 50/ {
51 model = "Marvell 98DX4251 SoC"; 51 model = "Marvell 98DX4251 SoC";
52 compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; 52 compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
53 53
54 cpus { 54 cpus {
55 cpu@1 { 55 cpu@1 {
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
index a8130805074e..1b1ff17fdd9c 100644
--- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
+++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
@@ -58,7 +58,7 @@
58 58
59/ { 59/ {
60 model = "Marvell Bobcat2 Evaluation Board"; 60 model = "Marvell Bobcat2 Evaluation Board";
61 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp"; 61 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
62 62
63 chosen { 63 chosen {
64 bootargs = "console=ttyS0,115200 earlyprintk"; 64 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 4e07cb6ed800..06fce35d7491 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -58,7 +58,7 @@
58 58
59/ { 59/ {
60 model = "DB-XC3-24G4XG"; 60 model = "DB-XC3-24G4XG";
61 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp"; 61 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
62 62
63 chosen { 63 chosen {
64 bootargs = "console=ttyS0,115200 earlyprintk"; 64 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 42ea8764814c..9efcf59c9b44 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -71,7 +71,8 @@
71 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 71 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
72 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 72 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
73 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 73 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
74 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; 74 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
75 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
75 76
76 internal-regs { 77 internal-regs {
77 78
@@ -95,6 +96,9 @@
95 pinctrl-names = "default"; 96 pinctrl-names = "default";
96 status = "okay"; 97 status = "okay";
97 phy-mode = "rgmii-id"; 98 phy-mode = "rgmii-id";
99 buffer-manager = <&bm>;
100 bm,pool-long = <0>;
101 bm,pool-short = <1>;
98 fixed-link { 102 fixed-link {
99 speed = <1000>; 103 speed = <1000>;
100 full-duplex; 104 full-duplex;
@@ -106,6 +110,9 @@
106 pinctrl-names = "default"; 110 pinctrl-names = "default";
107 status = "okay"; 111 status = "okay";
108 phy-mode = "rgmii-id"; 112 phy-mode = "rgmii-id";
113 buffer-manager = <&bm>;
114 bm,pool-long = <2>;
115 bm,pool-short = <3>;
109 fixed-link { 116 fixed-link {
110 speed = <1000>; 117 speed = <1000>;
111 full-duplex; 118 full-duplex;
@@ -156,6 +163,7 @@
156 esata@4 { 163 esata@4 {
157 label = "mamba:white:esata"; 164 label = "mamba:white:esata";
158 reg = <0x4>; 165 reg = <0x4>;
166 linux,default-trigger = "disk-activity";
159 }; 167 };
160 168
161 usb2@5 { 169 usb2@5 {
@@ -185,6 +193,10 @@
185 }; 193 };
186 }; 194 };
187 195
196 bm@c8000 {
197 status = "okay";
198 };
199
188 nand@d0000 { 200 nand@d0000 {
189 status = "okay"; 201 status = "okay";
190 num-cs = <1>; 202 num-cs = <1>;
@@ -258,6 +270,10 @@
258 }; 270 };
259 }; 271 };
260 }; 272 };
273
274 bm-bppi {
275 status = "okay";
276 };
261 }; 277 };
262 278
263 gpio_keys { 279 gpio_keys {
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index d967603dade8..7c90dac99822 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -20,6 +20,28 @@
20 }; 20 };
21}; 21};
22 22
23&fmc {
24 status = "okay";
25 flash@0 {
26 status = "okay";
27 m25p,fast-read;
28 label = "bmc";
29 };
30};
31
32&spi1 {
33 status = "okay";
34 flash@0 {
35 status = "okay";
36 m25p,fast-read;
37 label = "pnor";
38 };
39};
40
41&spi2 {
42 status = "okay";
43};
44
23&uart5 { 45&uart5 {
24 status = "okay"; 46 status = "okay";
25}; 47};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 1d2fc1e1dc29..112551766275 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -31,6 +31,24 @@
31 }; 31 };
32}; 32};
33 33
34&fmc {
35 status = "okay";
36 flash@0 {
37 status = "okay";
38 m25p,fast-read;
39 label = "bmc";
40 };
41};
42
43&spi {
44 status = "okay";
45 flash@0 {
46 status = "okay";
47 m25p,fast-read;
48 label = "pnor";
49 };
50};
51
34&uart5 { 52&uart5 {
35 status = "okay"; 53 status = "okay";
36}; 54};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 7a3b2b50c884..1190fec1b5d0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -31,6 +31,42 @@
31 }; 31 };
32}; 32};
33 33
34&fmc {
35 status = "okay";
36 flash@0 {
37 status = "okay";
38 m25p,fast-read;
39 label = "bmc";
40 };
41};
42
43&spi1 {
44 status = "okay";
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_spi1_default>;
47
48 flash@0 {
49 status = "okay";
50 m25p,fast-read;
51 label = "pnor";
52 };
53};
54
55&uart1 {
56 /* Rear RS-232 connector */
57 status = "okay";
58
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_txd1_default
61 &pinctrl_rxd1_default
62 &pinctrl_nrts1_default
63 &pinctrl_ndtr1_default
64 &pinctrl_ndsr1_default
65 &pinctrl_ncts1_default
66 &pinctrl_ndcd1_default
67 &pinctrl_nri1_default>;
68};
69
34&uart5 { 70&uart5 {
35 status = "okay"; 71 status = "okay";
36}; 72};
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index c79c937b0a8a..8c6bc29eb7f6 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -18,21 +18,41 @@
18 }; 18 };
19 }; 19 };
20 20
21 clocks {
22 clk_clkin: clk_clkin {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <48000000>;
26 };
27
28 };
29
30 ahb { 21 ahb {
31 compatible = "simple-bus"; 22 compatible = "simple-bus";
32 #address-cells = <1>; 23 #address-cells = <1>;
33 #size-cells = <1>; 24 #size-cells = <1>;
34 ranges; 25 ranges;
35 26
27 fmc: flash-controller@1e620000 {
28 reg = < 0x1e620000 0x94
29 0x20000000 0x02000000 >;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 compatible = "aspeed,ast2400-fmc";
33 status = "disabled";
34 interrupts = <19>;
35 flash@0 {
36 reg = < 0 >;
37 compatible = "jedec,spi-nor";
38 status = "disabled";
39 };
40 };
41
42 spi: flash-controller@1e630000 {
43 reg = < 0x1e630000 0x18
44 0x30000000 0x02000000 >;
45 #address-cells = <1>;
46 #size-cells = <0>;
47 compatible = "aspeed,ast2400-spi";
48 status = "disabled";
49 flash@0 {
50 reg = < 0 >;
51 compatible = "jedec,spi-nor";
52 status = "disabled";
53 };
54 };
55
36 vic: interrupt-controller@1e6c0080 { 56 vic: interrupt-controller@1e6c0080 {
37 compatible = "aspeed,ast2400-vic"; 57 compatible = "aspeed,ast2400-vic";
38 interrupt-controller; 58 interrupt-controller;
@@ -61,16 +81,48 @@
61 #size-cells = <1>; 81 #size-cells = <1>;
62 ranges; 82 ranges;
63 83
64 clk_hpll: clk_hpll@1e6e2070 {
65 #clock-cells = <0>;
66 compatible = "aspeed,g4-hpll-clock";
67 reg = <0x1e6e2070 0x4>;
68 clocks = <&clk_clkin>;
69 };
70
71 syscon: syscon@1e6e2000 { 84 syscon: syscon@1e6e2000 {
72 compatible = "aspeed,g4-scu", "syscon", "simple-mfd"; 85 compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
73 reg = <0x1e6e2000 0x1a8>; 86 reg = <0x1e6e2000 0x1a8>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 clk_clkin: clk_clkin {
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 clock-frequency = <48000000>;
94 };
95
96 clk_hpll: clk_hpll@70 {
97 #clock-cells = <0>;
98 compatible = "aspeed,g4-hpll-clock", "fixed-clock";
99 reg = <0x70>;
100 clocks = <&clk_clkin>;
101 clock-frequency = <384000000>;
102 };
103
104 clk_ahb: clk_ahb@70 {
105 #clock-cells = <0>;
106 compatible = "aspeed,g4-ahb-clock", "fixed-clock";
107 reg = <0x70>;
108 clocks = <&clk_hpll>;
109 clock-frequency = <192000000>;
110 };
111
112 clk_apb: clk_apb@08 {
113 #clock-cells = <0>;
114 compatible = "aspeed,g4-apb-clock", "fixed-clock";
115 reg = <0x08>;
116 clocks = <&clk_hpll>;
117 clock-frequency = <48000000>;
118