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authorLinus Torvalds2017-05-09 11:49:36 -0500
committerLinus Torvalds2017-05-09 11:49:36 -0500
commit8d648aad05811ccc07df22834de60a7bf8d9e0e6 (patch)
treee742cfec0f9a3727c4ddfc93f6d3b0c380e767b9
parente07e368b27c3470765b70f71279d18992c7d9e03 (diff)
parent17e310b8eef519c998b7ed80f11c212a86785dea (diff)
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson: "SoC platform changes (arch/arm/mach-*). This merge window, the bulk is for a few platforms: Gemini: - Legacy platform that Linus Walleij has converted to multiplatform and DT, so a handful of various tweaks there, removal of some old stale support, etc. Atmel AT91: - Fixup of various power management related pieces - Move of SoC detection to a drivers/soc driver instead ST Micro STM32: - New SoC support: STM32H743 TI platforms: - More driver support for Davinci (SATA in particular) - Removal of some old stale hwmod files (linkspace platform) Misc: - A couple of smaller patches for i.MX, sunxi, hisi" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (57 commits) ARM: davinci: Add clock for CPPI 4.1 DMA engine ARM: mxs: add support for I2SE Duckbill 2 boards MAINTAINERS: Update the Allwinner sunXi entry ARM: i.MX25: globally disable supervisor protect ARM: at91: move SoC detection to its own driver ARM: at91: pm: correct typo ARM: at91: pm: Remove at91_pm_set_standby ARM: at91: pm: Merge all at91sam9*_pm_init ARM: at91: pm: Tie the USB clock mask to the pmc ARM: at91: pm: Tie the memory controller type to the ramc id ARM: at91: pm: Workaround DDRSDRC self-refresh bug with LPDDR1 memories. ARM: at91: pm: Simplify at91rm9200_standby ARM: at91: pm: Use struct at91_pm_data in pm_suspend.S ARM: at91: pm: Move global variables into at91_pm_data ARM: at91: pm: Move at91_ramc_read/write to pm.c ARM: at91: pm: Cleanup headers MAINTAINERS: Add memory drivers to AT91 entry MAINTAINERS: Update AT91 entry ARM: davinci: add pata_bk3710 libata driver support ARM: OMAP2+: mark omap_init_rng as __init ...
-rw-r--r--Documentation/arm/stm32/stm32h743-overview.txt30
-rw-r--r--MAINTAINERS9
-rw-r--r--arch/arm/Kconfig33
-rw-r--r--arch/arm/include/debug/brcmstb.S18
-rw-r--r--arch/arm/mach-at91/Makefile34
-rw-r--r--arch/arm/mach-at91/at91rm9200.c15
-rw-r--r--arch/arm/mach-at91/at91sam9.c91
-rw-r--r--arch/arm/mach-at91/generic.h8
-rw-r--r--arch/arm/mach-at91/pm.c199
-rw-r--r--arch/arm/mach-at91/pm.h24
-rw-r--r--arch/arm/mach-at91/pm_data-offsets.c13
-rw-r--r--arch/arm/mach-at91/pm_suspend.S31
-rw-r--r--arch/arm/mach-at91/sama5.c52
-rw-r--r--arch/arm/mach-at91/soc.c142
-rw-r--r--arch/arm/mach-bcm/Kconfig2
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c4
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c3
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c3
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c3
-rw-r--r--arch/arm/mach-davinci/da830.c6
-rw-r--r--arch/arm/mach-davinci/da850.c6
-rw-r--r--arch/arm/mach-davinci/da8xx-dt.c1
-rw-r--r--arch/arm/mach-davinci/pdata-quirks.c178
-rw-r--r--arch/arm/mach-davinci/pm.c1
-rw-r--r--arch/arm/mach-gemini/Kconfig53
-rw-r--r--arch/arm/mach-gemini/Makefile15
-rw-r--r--arch/arm/mach-gemini/Makefile.boot9
-rw-r--r--arch/arm/mach-gemini/board-dt.c62
-rw-r--r--arch/arm/mach-gemini/board-nas4220b.c106
-rw-r--r--arch/arm/mach-gemini/board-rut1xx.c92
-rw-r--r--arch/arm/mach-gemini/board-wbd111.c133
-rw-r--r--arch/arm/mach-gemini/board-wbd222.c133
-rw-r--r--arch/arm/mach-gemini/common.h33
-rw-r--r--arch/arm/mach-gemini/devices.c118
-rw-r--r--arch/arm/mach-gemini/gpio.c231
-rw-r--r--arch/arm/mach-gemini/idle.c31
-rw-r--r--arch/arm/mach-gemini/include/mach/entry-macro.S33
-rw-r--r--arch/arm/mach-gemini/include/mach/global_reg.h278
-rw-r--r--arch/arm/mach-gemini/include/mach/hardware.h71
-rw-r--r--arch/arm/mach-gemini/include/mach/irqs.h53
-rw-r--r--arch/arm/mach-gemini/include/mach/uncompress.h42
-rw-r--r--arch/arm/mach-gemini/irq.c105
-rw-r--r--arch/arm/mach-gemini/mm.c82
-rw-r--r--arch/arm/mach-gemini/reset.c25
-rw-r--r--arch/arm/mach-gemini/time.c239
-rw-r--r--arch/arm/mach-hisi/platmcpm.c2
-rw-r--r--arch/arm/mach-imx/mach-imx25.c6
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c7
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c4
-rw-r--r--arch/arm/mach-imx/mach-pcm037_eet.c4
-rw-r--r--arch/arm/mach-imx/mmdc.c20
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c3
-rw-r--r--arch/arm/mach-omap1/pm.c1
-rw-r--r--arch/arm/mach-omap2/clockdomains81xx_data.c10
-rw-r--r--arch/arm/mach-omap2/cm81xx.h1
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c208
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h23
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_81xx_data.c34
-rw-r--r--arch/arm/mach-omap2/pm.c1
-rw-r--r--arch/arm/mach-stm32/Kconfig26
-rw-r--r--arch/arm/mach-stm32/board-dt.c1
-rw-r--r--arch/arm/mach-sunxi/Kconfig1
-rw-r--r--drivers/soc/Kconfig1
-rw-r--r--drivers/soc/Makefile1
-rw-r--r--drivers/soc/atmel/Kconfig6
-rw-r--r--drivers/soc/atmel/Makefile1
-rw-r--r--drivers/soc/atmel/soc.c231
-rw-r--r--drivers/soc/atmel/soc.h (renamed from arch/arm/mach-at91/soc.h)0
74 files changed, 887 insertions, 2571 deletions
diff --git a/Documentation/arm/stm32/stm32h743-overview.txt b/Documentation/arm/stm32/stm32h743-overview.txt
new file mode 100644
index 000000000000..3031cbae31a5
--- /dev/null
+++ b/Documentation/arm/stm32/stm32h743-overview.txt
@@ -0,0 +1,30 @@
1 STM32H743 Overview
2 ==================
3
4 Introduction
5 ------------
6 The STM32H743 is a Cortex-M7 MCU aimed at various applications.
7 It features:
8 - Cortex-M7 core running up to @400MHz
9 - 2MB internal flash, 1MBytes internal RAM
10 - FMC controller to connect SDRAM, NOR and NAND memories
11 - Dual mode QSPI
12 - SD/MMC/SDIO support
13 - Ethernet controller
14 - USB OTFG FS & HS controllers
15 - I2C, SPI, CAN busses support
16 - Several 16 & 32 bits general purpose timers
17 - Serial Audio interface
18 - LCD controller
19 - HDMI-CEC
20 - SPDIFRX
21 - DFSDM
22
23 Resources
24 ---------
25 Datasheet and reference manual are publicly available on ST website:
26 - http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
27
28 Document Author
29 ---------------
30 Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 0244bbc76e7f..9d58e9f18705 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1056,8 +1056,13 @@ M: Chen-Yu Tsai <wens@csie.org>
1056L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1056L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1057S: Maintained 1057S: Maintained
1058N: sun[x456789]i 1058N: sun[x456789]i
1059F: arch/arm/boot/dts/ntc-gr8* 1059N: sun50i
1060F: arch/arm/mach-sunxi/
1060F: arch/arm64/boot/dts/allwinner/ 1061F: arch/arm64/boot/dts/allwinner/
1062F: drivers/clk/sunxi-ng/
1063F: drivers/pinctrl/sunxi/
1064F: drivers/soc/sunxi/
1065T: git git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git
1061 1066
1062ARM/Allwinner SoC Clock Support 1067ARM/Allwinner SoC Clock Support
1063M: Emilio López <emilio@elopez.com.ar> 1068M: Emilio López <emilio@elopez.com.ar>
@@ -1110,7 +1115,6 @@ F: drivers/*/*aspeed*
1110ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT 1115ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
1111M: Nicolas Ferre <nicolas.ferre@microchip.com> 1116M: Nicolas Ferre <nicolas.ferre@microchip.com>
1112M: Alexandre Belloni <alexandre.belloni@free-electrons.com> 1117M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
1113M: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
1114L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1118L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1115W: http://www.linux4sam.org 1119W: http://www.linux4sam.org
1116T: git git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git 1120T: git git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
@@ -1122,6 +1126,7 @@ F: arch/arm/boot/dts/at91*.dtsi
1122F: arch/arm/boot/dts/sama*.dts 1126F: arch/arm/boot/dts/sama*.dts
1123F: arch/arm/boot/dts/sama*.dtsi 1127F: arch/arm/boot/dts/sama*.dtsi
1124F: arch/arm/include/debug/at91.S 1128F: arch/arm/include/debug/at91.S
1129F: drivers/memory/atmel*
1125 1130
1126ARM/ATMEL AT91 Clock Support 1131ARM/ATMEL AT91 Clock Support
1127M: Boris Brezillon <boris.brezillon@free-electrons.com> 1132M: Boris Brezillon <boris.brezillon@free-electrons.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4c6816be23a9..4c1a35f15838 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -359,15 +359,6 @@ config ARM_SINGLE_ARMV7M
359 select SPARSE_IRQ 359 select SPARSE_IRQ
360 select USE_OF 360 select USE_OF
361 361
362config ARCH_GEMINI
363 bool "Cortina Systems Gemini"
364 select CLKSRC_MMIO
365 select CPU_FA526
366 select GENERIC_CLOCKEVENTS
367 select GPIOLIB
368 help
369 Support for the Cortina Systems Gemini family SoCs
370
371config ARCH_EBSA110 362config ARCH_EBSA110
372 bool "EBSA-110" 363 bool "EBSA-110"
373 select ARCH_USES_GETTIMEOFFSET 364 select ARCH_USES_GETTIMEOFFSET
@@ -819,6 +810,8 @@ source "arch/arm/mach-spear/Kconfig"
819 810
820source "arch/arm/mach-sti/Kconfig" 811source "arch/arm/mach-sti/Kconfig"
821 812
813source "arch/arm/mach-stm32/Kconfig"
814
822source "arch/arm/mach-s3c24xx/Kconfig" 815source "arch/arm/mach-s3c24xx/Kconfig"
823 816
824source "arch/arm/mach-s3c64xx/Kconfig" 817source "arch/arm/mach-s3c64xx/Kconfig"
@@ -877,28 +870,6 @@ config ARCH_LPC18XX
877 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 870 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
878 high performance microcontrollers. 871 high performance microcontrollers.
879 872
880config ARCH_STM32
881 bool "STMicrolectronics STM32"
882 depends on ARM_SINGLE_ARMV7M
883 select ARCH_HAS_RESET_CONTROLLER
884 select ARMV7M_SYSTICK
885 select CLKSRC_STM32
886 select PINCTRL
887 select RESET_CONTROLLER
888 select STM32_EXTI
889 help
890 Support for STMicroelectronics STM32 processors.
891
892config MACH_STM32F429
893 bool "STMicrolectronics STM32F429"
894 depends on ARCH_STM32
895 default y
896
897config MACH_STM32F746
898 bool "STMicrolectronics STM32F746"
899 depends on ARCH_STM32
900 default y
901
902config ARCH_MPS2 873config ARCH_MPS2
903 bool "ARM MPS2 platform" 874 bool "ARM MPS2 platform"
904 depends on ARM_SINGLE_ARMV7M 875 depends on ARM_SINGLE_ARMV7M
diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S
index 9113d7b33ae0..52aaed2b936f 100644
--- a/arch/arm/include/debug/brcmstb.S
+++ b/arch/arm/include/debug/brcmstb.S
@@ -22,7 +22,8 @@
22 22
23#define UARTA_3390 REG_PHYS_ADDR(0x40a900) 23#define UARTA_3390 REG_PHYS_ADDR(0x40a900)
24#define UARTA_7250 REG_PHYS_ADDR(0x40b400) 24#define UARTA_7250 REG_PHYS_ADDR(0x40b400)
25#define UARTA_7268 REG_PHYS_ADDR(0x40c000) 25#define UARTA_7260 REG_PHYS_ADDR(0x40c000)
26#define UARTA_7268 UARTA_7260
26#define UARTA_7271 UARTA_7268 27#define UARTA_7271 UARTA_7268
27#define UARTA_7364 REG_PHYS_ADDR(0x40b000) 28#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
28#define UARTA_7366 UARTA_7364 29#define UARTA_7366 UARTA_7364
@@ -62,13 +63,14 @@
62 /* Chip specific detection starts here */ 63 /* Chip specific detection starts here */
6320: checkuart(\rp, \rv, 0x33900000, 3390) 6420: checkuart(\rp, \rv, 0x33900000, 3390)
6421: checkuart(\rp, \rv, 0x72500000, 7250) 6521: checkuart(\rp, \rv, 0x72500000, 7250)
6522: checkuart(\rp, \rv, 0x72680000, 7268) 6622: checkuart(\rp, \rv, 0x72600000, 7260)
6623: checkuart(\rp, \rv, 0x72710000, 7271) 6723: checkuart(\rp, \rv, 0x72680000, 7268)
6724: checkuart(\rp, \rv, 0x73640000, 7364) 6824: checkuart(\rp, \rv, 0x72710000, 7271)
6825: checkuart(\rp, \rv, 0x73660000, 7366) 6925: checkuart(\rp, \rv, 0x73640000, 7364)
6926: checkuart(\rp, \rv, 0x07437100, 74371) 7026: checkuart(\rp, \rv, 0x73660000, 7366)
7027: checkuart(\rp, \rv, 0x74390000, 7439) 7127: checkuart(\rp, \rv, 0x07437100, 74371)
7128: checkuart(\rp, \rv, 0x74450000, 7445) 7228: checkuart(\rp, \rv, 0x74390000, 7439)
7329: checkuart(\rp, \rv, 0x74450000, 7445)
72 74
73 /* No valid UART found */ 75 /* No valid UART found */
7490: mov \rp, #0 7690: mov \rp, #0
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c5bbf8bb8c0f..cfd8f60a9268 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,7 +1,6 @@
1# 1#
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4obj-y := soc.o
5 4
6# CPU-specific support 5# CPU-specific support
7obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o 6obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
@@ -18,3 +17,36 @@ endif
18ifeq ($(CONFIG_PM_DEBUG),y) 17ifeq ($(CONFIG_PM_DEBUG),y)
19CFLAGS_pm.o += -DDEBUG 18CFLAGS_pm.o += -DDEBUG
20endif 19endif
20
21# Default sed regexp - multiline due to syntax constraints
22define sed-y
23 "/^->/{s:->#\(.*\):/* \1 */:; \
24 s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
25 s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
26 s:->::; p;}"
27endef
28
29# Use filechk to avoid rebuilds when a header changes, but the resulting file
30# does not
31define filechk_offsets
32 (set -e; \
33 echo "#ifndef $2"; \
34 echo "#define $2"; \
35 echo "/*"; \
36 echo " * DO NOT MODIFY."; \
37 echo " *"; \
38 echo " * This file was generated by Kbuild"; \
39 echo " */"; \
40 echo ""; \
41 sed -ne $(sed-y); \
42 echo ""; \
43 echo "#endif" )
44endef
45
46arch/arm/mach-at91/pm_data-offsets.s: arch/arm/mach-at91/pm_data-offsets.c
47 $(call if_changed_dep,cc_s_c)
48
49include/generated/at91_pm_data-offsets.h: arch/arm/mach-at91/pm_data-offsets.s FORCE
50 $(call filechk,offsets,__PM_DATA_OFFSETS_H__)
51
52arch/arm/mach-at91/pm_suspend.o: include/generated/at91_pm_data-offsets.h
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d068ec3cd1f6..656ad409a253 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -14,23 +14,10 @@
14#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
15 15
16#include "generic.h" 16#include "generic.h"
17#include "soc.h"
18
19static const struct at91_soc rm9200_socs[] = {
20 AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
21 { /* sentinel */ },
22};
23 17
24static void __init at91rm9200_dt_device_init(void) 18static void __init at91rm9200_dt_device_init(void)
25{ 19{
26 struct soc_device *soc; 20 of_platform_default_populate(NULL, NULL, NULL);
27 struct device *soc_dev = NULL;
28
29 soc = at91_soc_init(rm9200_socs);
30 if (soc != NULL)
31 soc_dev = soc_device_to_device(soc);
32
33 of_platform_default_populate(NULL, NULL, soc_dev);
34 21
35 at91rm9200_pm_init(); 22 at91rm9200_pm_init();
36} 23}
diff --git a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c
index ba28e9cc584d..3dbdef4d3cbf 100644
--- a/arch/arm/mach-at91/at91sam9.c
+++ b/arch/arm/mach-at91/at91sam9.c
@@ -14,60 +14,12 @@
14#include <asm/system_misc.h> 14#include <asm/system_misc.h>
15 15
16#include "generic.h" 16#include "generic.h"
17#include "soc.h"
18 17
19static const struct at91_soc at91sam9_socs[] = { 18static void __init at91sam9_init(void)
20 AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
21 AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
22 AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
23 AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
24 AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
25 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
26 "at91sam9m11", "at91sam9g45"),
27 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
28 "at91sam9m10", "at91sam9g45"),
29 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
30 "at91sam9g46", "at91sam9g45"),
31 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
32 "at91sam9g45", "at91sam9g45"),
33 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
34 "at91sam9g15", "at91sam9x5"),
35 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
36 "at91sam9g35", "at91sam9x5"),
37 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
38 "at91sam9x35", "at91sam9x5"),
39 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
40 "at91sam9g25", "at91sam9x5"),
41 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
42 "at91sam9x25", "at91sam9x5"),
43 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
44 "at91sam9cn12", "at91sam9n12"),
45 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
46 "at91sam9n12", "at91sam9n12"),
47 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
48 "at91sam9cn11", "at91sam9n12"),
49 AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
50 AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
51 AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
52 { /* sentinel */ },
53};
54
55static void __init at91sam9_common_init(void)
56{ 19{
57 struct soc_device *soc; 20 of_platform_default_populate(NULL, NULL, NULL);
58 struct device *soc_dev = NULL;
59
60 soc = at91_soc_init(at91sam9_socs);
61 if (soc != NULL)
62 soc_dev = soc_device_to_device(soc);
63 21
64 of_platform_default_populate(NULL, NULL, soc_dev); 22 at91sam9_pm_init();
65}
66
67static void __init at91sam9_dt_device_init(void)
68{
69 at91sam9_common_init();
70 at91sam9260_pm_init();
71} 23}
72 24
73static const char *const at91_dt_board_compat[] __initconst = { 25static const char *const at91_dt_board_compat[] __initconst = {
@@ -77,41 +29,6 @@ static const char *const at91_dt_board_compat[] __initconst = {
77 29
78DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9") 30DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
79 /* Maintainer: Atmel */ 31 /* Maintainer: Atmel */
80 .init_machine = at91sam9_dt_device_init, 32 .init_machine = at91sam9_init,
81 .dt_compat = at91_dt_board_compat, 33 .dt_compat = at91_dt_board_compat,
82MACHINE_END 34MACHINE_END
83
84static void __init at91sam9g45_dt_device_init(void)
85{
86 at91sam9_common_init();
87 at91sam9g45_pm_init();
88}
89
90static const char *const at91sam9g45_board_compat[] __initconst = {
91 "atmel,at91sam9g45",
92 NULL
93};
94
95DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
96 /* Maintainer: Atmel */
97 .init_machine = at91sam9g45_dt_device_init,
98 .dt_compat = at91sam9g45_board_compat,
99MACHINE_END
100
101static void __init at91sam9x5_dt_device_init(void)
102{
103 at91sam9_common_init();
104 at91sam9x5_pm_init();
105}
106
107static const char *const at91sam9x5_board_compat[] __initconst = {
108 "atmel,at91sam9x5",
109 "atmel,at91sam9n12",
110 NULL
111};
112
113DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
114 /* Maintainer: Atmel */
115 .init_machine = at91sam9x5_dt_device_init,
116 .dt_compat = at91sam9x5_board_compat,
117MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 28ca57a2060f..f1ead0f13c19 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -13,15 +13,11 @@
13 13
14#ifdef CONFIG_PM 14#ifdef CONFIG_PM
15extern void __init at91rm9200_pm_init(void); 15extern void __init at91rm9200_pm_init(void);
16extern void __init at91sam9260_pm_init(void); 16extern void __init at91sam9_pm_init(void);
17extern void __init at91sam9g45_pm_init(void);
18extern void __init at91sam9x5_pm_init(void);
19extern void __init sama5_pm_init(void); 17extern void __init sama5_pm_init(void);
20#else 18#else
21static inline void __init at91rm9200_pm_init(void) { } 19static inline void __init at91rm9200_pm_init(void) { }
22static inline void __init at91sam9260_pm_init(void) { } 20static inline void __init at91sam9_pm_init(void) { }
23static inline void __init at91sam9g45_pm_init(void) { }
24static inline void __init at91sam9x5_pm_init(void) { }
25static inline void __init sama5_pm_init(void) { } 21static inline void __init sama5_pm_init(void) { }
26#endif 22#endif
27 23
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index a277981f414d..2cd27c830ab6 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -10,35 +10,22 @@
10 * (at your option) any later version. 10 * (at your option) any later version.
11 */ 11 */
12 12
13#include <linux/gpio.h>
14#include <linux/suspend.h>
15#include <linux/sched.h>
16#include <linux/proc_fs.h>
17#include <linux/genalloc.h> 13#include <linux/genalloc.h>
18#include <linux/interrupt.h> 14#include <linux/io.h>
19#include <linux/sysfs.h> 15#include <linux/of_address.h>
20#include <linux/module.h>
21#include <linux/of.h> 16#include <linux/of.h>
22#include <linux/of_platform.h> 17#include <linux/of_platform.h>
23#include <linux/of_address.h> 18#include <linux/suspend.h>
24#include <linux/platform_device.h> 19
25#include <linux/platform_data/atmel.h>
26#include <linux/io.h>
27#include <linux/clk/at91_pmc.h> 20#include <linux/clk/at91_pmc.h>
28 21
29#include <asm/irq.h>
30#include <linux/atomic.h>
31#include <asm/mach/time.h>
32#include <asm/mach/irq.h>
33#include <asm/fncpy.h>
34#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <asm/fncpy.h>
35#include <asm/system_misc.h> 24#include <asm/system_misc.h>
36 25
37#include "generic.h" 26#include "generic.h"
38#include "pm.h" 27#include "pm.h"
39 28
40static void __iomem *pmc;
41
42/* 29/*
43 * FIXME: this is needed to communicate between the pinctrl driver and 30 * FIXME: this is needed to communicate between the pinctrl driver and
44 * the PM implementation in the machine. Possibly part of the PM 31 * the PM implementation in the machine. Possibly part of the PM
@@ -50,12 +37,13 @@ extern void at91_pinctrl_gpio_suspend(void);
50extern void at91_pinctrl_gpio_resume(void); 37extern void at91_pinctrl_gpio_resume(void);
51#endif 38#endif
52 39
53static struct { 40static struct at91_pm_data pm_data;
54 unsigned long uhp_udp_mask;
55 int memctrl;
56} at91_pm_data;
57 41
58static void __iomem *at91_ramc_base[2]; 42#define at91_ramc_read(id, field) \
43 __raw_readl(pm_data.ramc[id] + field)
44
45#define at91_ramc_write(id, field, value) \
46 __raw_writel(value, pm_data.ramc[id] + field)
59 47
60static int at91_pm_valid_state(suspend_state_t state) 48static int at91_pm_valid_state(suspend_state_t state)
61{ 49{
@@ -91,10 +79,10 @@ static int at91_pm_verify_clocks(void)
91 unsigned long scsr; 79 unsigned long scsr;
92 int i; 80 int i;
93 81
94 scsr = readl(pmc + AT91_PMC_SCSR); 82 scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
95 83
96 /* USB must not be using PLLB */ 84 /* USB must not be using PLLB */
97 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) { 85 if ((scsr & pm_data.uhp_udp_mask) != 0) {
98 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 86 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
99 return 0; 87 return 0;
100 } 88 }
@@ -105,7 +93,7 @@ static int at91_pm_verify_clocks(void)
105 93
106 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 94 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
107 continue; 95 continue;
108 css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 96 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
109 if (css != AT91_PMC_CSS_SLOW) { 97 if (css != AT91_PMC_CSS_SLOW) {
110 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 98 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
111 return 0; 99 return 0;
@@ -131,25 +119,18 @@ int at91_suspend_entering_slow_clock(void)
131} 119}
132EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 120EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
133 121
134static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0, 122static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
135 void __iomem *ramc1, int memctrl); 123extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
136
137extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
138 void __iomem *ramc1, int memctrl);
139extern u32 at91_pm_suspend_in_sram_sz; 124extern u32 at91_pm_suspend_in_sram_sz;
140 125
141static void at91_pm_suspend(suspend_state_t state) 126static void at91_pm_suspend(suspend_state_t state)
142{ 127{
143 unsigned int pm_data = at91_pm_data.memctrl; 128 pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0;
144
145 pm_data |= (state == PM_SUSPEND_MEM) ?
146 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
147 129
148 flush_cache_all(); 130 flush_cache_all();
149 outer_disable(); 131 outer_disable();
150 132
151 at91_suspend_sram_fn(pmc, at91_ramc_base[0], 133 at91_suspend_sram_fn(&pm_data);
152 at91_ramc_base[1], pm_data);
153 134
154 outer_resume(); 135 outer_resume();
155} 136}
@@ -224,12 +205,6 @@ static struct platform_device at91_cpuidle_device = {
224 .name = "cpuidle-at91", 205 .name = "cpuidle-at91",
225}; 206};
226 207
227static void at91_pm_set_standby(void (*at91_standby)(void))
228{
229 if (at91_standby)
230 at91_cpuidle_device.dev.platform_data = at91_standby;
231}
232
233/* 208/*
234 * The AT91RM9200 goes into self-refresh mode with this command, and will 209 * The AT91RM9200 goes into self-refresh mode with this command, and will
235 * terminate self-refresh automatically on the next SDRAM access. 210 * terminate self-refresh automatically on the next SDRAM access.
@@ -241,20 +216,15 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
241 */ 216 */
242static void at91rm9200_standby(void) 217static void at91rm9200_standby(void)
243{ 218{
244 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
245
246 asm volatile( 219 asm volatile(
247 "b 1f\n\t" 220 "b 1f\n\t"
248 ".align 5\n\t" 221 ".align 5\n\t"
249 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 222 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
250 " str %0, [%1, %2]\n\t" 223 " str %2, [%1, %3]\n\t"
251 " str %3, [%1, %4]\n\t"
252 " mcr p15, 0, %0, c7, c0, 4\n\t" 224 " mcr p15, 0, %0, c7, c0, 4\n\t"
253 " str %5, [%1, %2]"
254 : 225 :
255 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR), 226 : "r" (0), "r" (pm_data.ramc[0]),
256 "r" (1), "r" (AT91_MC_SDRAMC_SRR), 227 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
257 "r" (lpr));
258} 228}
259 229
260/* We manage both DDRAM/SDRAM controllers, we need more than one value to 230/* We manage both DDRAM/SDRAM controllers, we need more than one value to
@@ -265,12 +235,27 @@ static void at91_ddr_standby(void)
265 /* Those two values allow us to delay self-refresh activation 235 /* Those two values allow us to delay self-refresh activation
266 * to the maximum. */ 236 * to the maximum. */
267 u32 lpr0, lpr1 = 0; 237 u32 lpr0, lpr1 = 0;
238 u32 mdr, saved_mdr0, saved_mdr1 = 0;
268 u32 saved_lpr0, saved_lpr1 = 0; 239 u32 saved_lpr0, saved_lpr1 = 0;
269 240
270 if (at91_ramc_base[1]) { 241 /* LPDDR1 --> force DDR2 mode during self-refresh */
242 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
243 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
244 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
245 mdr |= AT91_DDRSDRC_MD_DDR2;
246 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
247 }
248
249 if (pm_data.ramc[1]) {
271 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 250 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
272 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 251 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
273 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 252 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
253 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
254 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
255 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
256 mdr |= AT91_DDRSDRC_MD_DDR2;
257 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
258 }
274 } 259 }
275 260
276 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 261 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
@@ -279,14 +264,17 @@ static void at91_ddr_standby(void)
279 264
280 /* self-refresh mode now */ 265 /* self-refresh mode now */
281 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 266 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
282 if (at91_ramc_base[1]) 267 if (pm_data.ramc[1])
283 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 268 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
284 269
285 cpu_do_idle(); 270 cpu_do_idle();
286 271
272 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
287 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 273 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
288 if (at91_ramc_base[1]) 274 if (pm_data.ramc[1]) {
275 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
289 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 276 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
277 }
290} 278}
291 279
292static void sama5d3_ddr_standby(void) 280static void sama5d3_ddr_standby(void)
@@ -313,7 +301,7 @@ static void at91sam9_sdram_standby(void)
313 u32 lpr0, lpr1 = 0; 301 u32 lpr0, lpr1 = 0;
314 u32 saved_lpr0, saved_lpr1 = 0; 302 u32 saved_lpr0, saved_lpr1 = 0;
315 303
316 if (at91_ramc_base[1]) { 304 if (pm_data.ramc[1]) {
317 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 305 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
318 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 306 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
319 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 307 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
@@ -325,21 +313,33 @@ static void at91sam9_sdram_standby(void)
325 313
326 /* self-refresh mode now */ 314 /* self-refresh mode now */
327 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 315 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
328 if (at91_ramc_base[1]) 316 if (pm_data.ramc[1])
329 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 317 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
330 318
331 cpu_do_idle(); 319 cpu_do_idle();
332 320
333 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 321 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
334 if (at91_ramc_base[1]) 322 if (pm_data.ramc[1])
335 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 323 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
336} 324}
337 325
326struct ramc_info {
327 void (*idle)(void);
328 unsigned int memctrl;
329};
330
331static const struct ramc_info ramc_infos[] __initconst = {
332 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
333 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
334 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
335 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
336};
337
338static const struct of_device_id const ramc_ids[] __initconst = { 338static const struct of_device_id const ramc_ids[] __initconst = {
339 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, 339 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
340 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, 340 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
341 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, 341 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
342 { .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby }, 342 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
343 { /*sentinel*/ } 343 { /*sentinel*/ }
344}; 344};
345 345
@@ -348,15 +348,18 @@ static __init void at91_dt_ramc(void)
348 struct device_node *np; 348 struct device_node *np;
349 const struct of_device_id *of_id; 349 const struct of_device_id *of_id;
350 int idx = 0; 350 int idx = 0;
351 const void *standby = NULL; 351 void *standby = NULL;
352 const struct ramc_info *ramc;
352 353
353 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 354 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
354 at91_ramc_base[idx] = of_iomap(np, 0); 355 pm_data.ramc[idx] = of_iomap(np, 0);
355 if (!at91_ramc_base[idx]) 356 if (!pm_data.ramc[idx])
356 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 357 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
357 358
359 ramc = of_id->data;
358 if (!standby) 360 if (!standby)
359 standby = of_id->data; 361 standby = ramc->idle;
362 pm_data.memctrl = ramc->memctrl;
360 363
361 idx++; 364 idx++;
362 } 365 }
@@ -369,7 +372,7 @@ static __init void at91_dt_ramc(void)
369 return; 372 return;
370 } 373 }
371 374
372 at91_pm_set_standby(standby); 375 at91_cpuidle_device.dev.platform_data = standby;
373} 376}
374 377
375static void at91rm9200_idle(void) 378static void at91rm9200_idle(void)
@@ -378,12 +381,12 @@ static void at91rm9200_idle(void)
378 * Disable the processor clock. The processor will be automatically 381 * Disable the processor clock. The processor will be automatically
379 * re-enabled by an interrupt or by a reset. 382 * re-enabled by an interrupt or by a reset.
380 */ 383 */
381 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); 384 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
382} 385}
383 386
384static void at91sam9_idle(void) 387static void at91sam9_idle(void)
385{ 388{
386 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); 389 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
387 cpu_do_idle(); 390 cpu_do_idle();
388} 391}
389 392
@@ -433,31 +436,46 @@ static void __init at91_pm_sram_init(void)
433 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 436 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
434} 437}
435 438
439struct pmc_info {
440 unsigned long uhp_udp_mask;
441};
442
443static const struct pmc_info pmc_infos[] __initconst = {
444 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
445 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
446 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
447};
448
436static const struct of_device_id atmel_pmc_ids[] __initconst = { 449static const struct of_device_id atmel_pmc_ids[] __initconst = {
437 { .compatible = "atmel,at91rm9200-pmc" }, 450 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
438 { .compatible = "atmel,at91sam9260-pmc" }, 451 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
439 { .compatible = "atmel,at91sam9g45-pmc" }, 452 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
440 { .compatible = "atmel,at91sam9n12-pmc" }, 453 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
441 { .compatible = "atmel,at91sam9x5-pmc" }, 454 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
442 { .compatible = "atmel,sama5d3-pmc" }, 455 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
443 { .compatible = "atmel,sama5d2-pmc" }, 456 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
444 { /* sentinel */ }, 457 { /* sentinel */ },
445}; 458};
446 459
447static void __init at91_pm_init(void (*pm_idle)(void)) 460static void __init at91_pm_init(void (*pm_idle)(void))
448{ 461{
449 struct device_node *pmc_np; 462 struct device_node *pmc_np;
463 const struct of_device_id *of_id;
464 const struct pmc_info *pmc;
450 465
451 if (at91_cpuidle_device.dev.platform_data) 466 if (at91_cpuidle_device.dev.platform_data)
452 platform_device_register(&at91_cpuidle_device); 467 platform_device_register(&at91_cpuidle_device);
453 468
454 pmc_np = of_find_matching_node(NULL, atmel_pmc_ids); 469 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
455 pmc = of_iomap(pmc_np, 0); 470 pm_data.pmc = of_iomap(pmc_np, 0);
456 if (!pmc) { 471 if (!pm_data.pmc) {
457 pr_err("AT91: PM not supported, PMC not found\n"); 472 pr_err("AT91: PM not supported, PMC not found\n");
458 return; 473 return;
459 } 474 }
460 475
476 pmc = of_id->data;
477 pm_data.uhp_udp_mask = pmc->uhp_udp_mask;
478
461 if (pm_idle) 479 if (pm_idle)
462 arm_pm_idle = pm_idle; 480 arm_pm_idle = pm_idle;
463 481
@@ -478,40 +496,17 @@ void __init at91rm9200_pm_init(void)
478 */ 496 */
479 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 497 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
480 498
481 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
482 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
483
484 at91_pm_init(at91rm9200_idle); 499 at91_pm_init(at91rm9200_idle);
485} 500}
486 501
487void __init at91sam9260_pm_init(void) 502void __init at91sam9_pm_init(void)
488{
489 at91_dt_ramc();
490 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
491 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
492 at91_pm_init(at91sam9_idle);
493}
494
495void __init at91sam9g45_pm_init(void)
496{
497 at91_dt_ramc();
498 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
499 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
500 at91_pm_init(at91sam9_idle);
501}
502
503void __init at91sam9x5_pm_init(void)
504{ 503{
505 at91_dt_ramc(); 504 at91_dt_ramc();
506 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
507 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
508 at91_pm_init(at91sam9_idle); 505 at91_pm_init(at91sam9_idle);
509} 506}
510 507
511void __init sama5_pm_init(void) 508void __init sama5_pm_init(void)
512{ 509{
513 at91_dt_ramc(); 510 at91_dt_ramc();
514 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
515 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
516 at91_pm_init(NULL); 511 at91_pm_init(NULL);
517} 512}
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index bf980c6ef294..fc0f7d048187 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -17,24 +17,20 @@
17#include <soc/at91/at91sam9_ddrsdr.h> 17#include <soc/at91/at91sam9_ddrsdr.h>
18#include <soc/at91/at91sam9_sdramc.h> 18#include <soc/at91/at91sam9_sdramc.h>
19 19
20#ifndef __ASSEMBLY__
21#define at91_ramc_read(id, field) \
22 __raw_readl(at91_ramc_base[id] + field)
23
24#define at91_ramc_write(id, field, value) \
25 __raw_writel(value, at91_ramc_base[id] + field)
26#endif
27
28#define AT91_MEMCTRL_MC 0 20#define AT91_MEMCTRL_MC 0
29#define AT91_MEMCTRL_SDRAMC 1 21#define AT91_MEMCTRL_SDRAMC 1
30#define AT91_MEMCTRL_DDRSDR 2 22#define AT91_MEMCTRL_DDRSDR 2
31 23
32#define AT91_PM_MEMTYPE_MASK 0x0f
33
34#define AT91_PM_MODE_OFFSET 4
35#define AT91_PM_MODE_MASK 0x01
36#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
37
38#define AT91_PM_SLOW_CLOCK 0x01 24#define AT91_PM_SLOW_CLOCK 0x01
39 25
26#ifndef __ASSEMBLY__
27struct at91_pm_data {
28 void __iomem *pmc;
29 void __iomem *ramc[2];
30 unsigned long uhp_udp_mask;
31 unsigned int memctrl;
32 unsigned int mode;
33};
34#endif
35
40#endif 36#endif
diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
new file mode 100644
index 000000000000..30302cb16df0
--- /dev/null
+++ b/arch/arm/mach-at91/pm_data-offsets.c
@@ -0,0 +1,13 @@
1#include <linux/stddef.h>
2#include <linux/kbuild.h>
3#include "pm.h"
4
5int main(void)
6{
7 DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
8 DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
9 DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
10 DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
11 DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
12 return 0;
13}
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index a25defda3d22..96781daa671a 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -4,7 +4,7 @@
4 * Copyright (C) 2006 Savin Zlobec 4 * Copyright (C) 2006 Savin Zlobec
5 * 5 *
6 * AT91SAM9 support: 6 * AT91SAM9 support:
7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee 7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
@@ -14,6 +14,7 @@
14#include <linux/linkage.h> 14#include <linux/linkage.h>
15#include <linux/clk/at91_pmc.h> 15#include <linux/clk/at91_pmc.h>
16#include "pm.h" 16#include "pm.h"
17#include "generated/at91_pm_data-offsets.h"
17 18
18#define SRAMC_SELF_FRESH_ACTIVE 0x01 19#define SRAMC_SELF_FRESH_ACTIVE 0x01
19#define SRAMC_SELF_FRESH_EXIT 0x00 20#define SRAMC_SELF_FRESH_EXIT 0x00
@@ -72,13 +73,9 @@ tmp2 .req r5
72 .arm 73 .arm
73 74
74/* 75/*
75 * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc, 76 * void at91_suspend_sram_fn(struct at91_pm_data*)
76 * void __iomem *ramc1, int memctrl)
77 * @input param: 77 * @input param:
78 * @r0: base address of AT91_PMC 78 * @r0: base address of struct at91_pm_data
79 * @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
80 * @r2: base address of second SDRAM Controller or 0 if not present
81 * @r3: pm information
82 */ 79 */
83/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ 80/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
84 .align 3 81 .align 3
@@ -90,16 +87,16 @@ ENTRY(at91_pm_suspend_in_sram)
90 mov tmp1, #0 87 mov tmp1, #0
91 mcr p15, 0, tmp1, c7, c10, 4 88 mcr p15, 0, tmp1, c7, c10, 4
92 89
93 str r0, .pmc_base 90 ldr tmp1, [r0, #PM_DATA_PMC]
94 str r1, .sramc_base 91 str tmp1, .pmc_base
95 str r2, .sramc1_base 92 ldr tmp1, [r0, #PM_DATA_RAMC0]
96 93 str tmp1, .sramc_base
97 and r0, r3, #AT91_PM_MEMTYPE_MASK 94 ldr tmp1, [r0, #PM_DATA_RAMC1]
98 str r0, .memtype 95 str tmp1, .sramc1_base
99 96 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
100 lsr r0, r3, #AT91_PM_MODE_OFFSET 97 str tmp1, .memtype
101 and r0, r0, #AT91_PM_MODE_MASK 98 ldr tmp1, [r0, #PM_DATA_MODE]
102 str r0, .pm_mode 99 str tmp1, .pm_mode
103 100
104 /* Active the self-refresh mode */ 101 /* Active the self-refresh mode */
105 mov r0, #SRAMC_SELF_FRESH_ACTIVE 102 mov r0, #SRAMC_SELF_FRESH_ACTIVE
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index b272c45b400f..6d157d0ead8e 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -15,60 +15,10 @@
15#include <asm/system_misc.h> 15#include <asm/system_misc.h>
16 16
17#include "generic.h" 17#include "generic.h"
18#include "soc.h"
19
20static const struct at91_soc sama5_socs[] = {
21 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
22 "sama5d21", "sama5d2"),
23 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
24 "sama5d22", "sama5d2"),
25 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
26 "sama5d23", "sama5d2"),
27 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
28 "sama5d24", "sama5d2"),
29 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
30 "sama5d24", "sama5d2"),
31 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
32 "sama5d26", "sama5d2"),
33 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
34 "sama5d27", "sama5d2"),
35 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
36 "sama5d27", "sama5d2"),
37 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
38 "sama5d28", "sama5d2"),
39 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
40 "sama5d28", "sama5d2"),
41 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
42 "sama5d31", "sama5d3"),
43 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
44 "sama5d33", "sama5d3"),
45 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
46 "sama5d34", "sama5d3"),
47 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
48 "sama5d35", "sama5d3"),
49 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
50 "sama5d36", "sama5d3"),
51 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
52 "sama5d41", "sama5d4"),
53 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
54 "sama5d42", "sama5d4"),
55 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
56 "sama5d43", "sama5d4"),
57 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
58 "sama5d44", "sama5d4"),
59 { /* sentinel */ },
60};
61 18
62static void __init sama5_dt_device_init(void) 19static void __init sama5_dt_device_init(void)
63{ 20{
64 struct soc_device *soc; 21 of_platform_default_populate(NULL, NULL, NULL);
65 struct device *soc_dev = NULL;
66
67 soc = at91_soc_init(sama5_socs);
68 if (soc != NULL)
69 soc_dev = soc_device_to_device(soc);
70
71 of_platform_default_populate(NULL, NULL, soc_dev);
72 sama5_pm_init(); 22 sama5_pm_init();
73} 23}
74 24
diff --git a/arch/arm/mach-at91/soc.c b/arch/arm/mach-at91/soc.c
deleted file mode 100644
index c6fda75ddb89..000000000000
--- a/arch/arm/mach-at91/soc.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 * Copyright (C) 2015 Atmel
3 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com
5 * Boris Brezillon <boris.brezillon@free-electrons.com
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 *
11 */
12
13#define pr_fmt(fmt) "AT91: " fmt
14
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/slab.h>
20#include <linux/sys_soc.h>
21
22#include "soc.h"
23
24#define AT91_DBGU_CIDR 0x40
25#define AT91_DBGU_EXID 0x44
26#define AT91_CHIPID_CIDR 0x00
27#define AT91_CHIPID_EXID 0x04
28#define AT91_CIDR_VERSION(x) ((x) & 0x1f)
29#define AT91_CIDR_EXT BIT(31)
30#define AT91_CIDR_MATCH_MASK 0x7fffffe0
31
32static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
33{
34 struct device_node *np;
35 void __iomem *regs;
36
37 np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
38 if (!np)
39 np = of_find_compatible_node(NULL, NULL,
40 "atmel,at91sam9260-dbgu");
41 if (!np)
42 return -ENODEV;
43
44 regs = of_iomap(np, 0);
45 of_node_put(np);
46
47 if (!regs) {
48 pr_warn("Could not map DBGU iomem range");
49 return -ENXIO;
50 }
51
52 *cidr = readl(regs + AT91_DBGU_CIDR);
53 *exid = readl(regs + AT91_DBGU_EXID);
54
55 iounmap(regs);
56
57 return 0;
58}
59
60static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
61{
62 struct device_node *np;
63 void __iomem *regs;
64
65 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
66 if (!np)
67 return -ENODEV;
68
69 regs = of_iomap(np, 0);
70 of_node_put(np);
71
72 if (!regs) {
73 pr_warn("Could not map DBGU iomem range");
74 return -ENXIO;
75 }
76
77 *cidr = readl(regs + AT91_CHIPID_CIDR);
78 *exid = readl(regs + AT91_CHIPID_EXID);
79
80 iounmap(regs);
81
82 return 0;
83}
84
85struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
86{
87 struct soc_device_attribute *soc_dev_attr;
88 const struct at91_soc *soc;
89 struct soc_device *soc_dev;
90 u32 cidr, exid;
91 int ret;
92
93 /*
94 * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
95 * in the dbgu device but in the chipid device whose purpose is only
96 * to expose these two registers.
97 */
98 ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
99 if (ret)
100 ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
101 if (ret) {
102 if (ret == -ENODEV)
103 pr_warn("Could not find identification node");
104 return NULL;
105 }
106
107 for (soc = socs; soc->name; soc++) {
108 if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
109 continue;
110
111 if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
112 break;
113 }
114
115 if (!soc->name) {
116 pr_warn("Could not find matching SoC description\n");
117 return NULL;
118 }
119
120 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
121 if (!soc_dev_attr)
122 return NULL;
123
124 soc_dev_attr->family = soc->family;
125 soc_dev_attr->soc_id = soc->name;
126 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
127 AT91_CIDR_VERSION(cidr));
128 soc_dev = soc_device_register(soc_dev_attr);
129 if (IS_ERR(soc_dev)) {
130 kfree(soc_dev_attr->revision);
131 kfree(soc_dev_attr);
132 pr_warn("Could not register SoC device\n");
133 return NULL;
134 }
135
136 if (soc->family)
137 pr_info("Detected SoC family: %s\n", soc->family);
138 pr_info("Detected SoC: %s, revision %X\n", soc->name,
139 AT91_CIDR_VERSION(cidr));
140
141 return soc_dev;
142}
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index a0e66d8200c5..f9389c5910e7 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -198,7 +198,9 @@ config ARCH_BRCMSTB
198 select HAVE_ARM_ARCH_TIMER 198 select HAVE_ARM_ARCH_TIMER
199 select BRCMSTB_L2_IRQ 199 select BRCMSTB_L2_IRQ
200 select BCM7120_L2_IRQ 200 select BCM7120_L2_IRQ
201 select ARCH_HAS_HOLES_MEMORYMODEL
201 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 202 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
203 select ZONE_DMA if ARM_LPAE
202 select SOC_BRCMSTB 204 select SOC_BRCMSTB
203 select SOC_BUS 205 select SOC_BUS
204 help 206 help
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6f1e1299cab9..b5625d009288 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -828,6 +828,9 @@ static struct regulator_consumer_supply fixed_supplies[] = {
828 828
829 /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */ 829 /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
830 REGULATOR_SUPPLY("DVDD", "1-0018"), 830 REGULATOR_SUPPLY("DVDD", "1-0018"),
831
832 /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */
833 REGULATOR_SUPPLY("vcc", "1-0020"),
831}; 834};
832 835
833/* TPS65070 voltage regulator support */ 836/* TPS65070 voltage regulator support */
@@ -1213,6 +1216,7 @@ static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
1213static struct vpif_capture_config da850_vpif_capture_config = { 1216static struct vpif_capture_config da850_vpif_capture_config = {
1214 .subdev_info = da850_vpif_capture_sdev_info, 1217 .subdev_info = da850_vpif_capture_sdev_info,
1215 .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info), 1218 .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
1219 .i2c_adapter_id = 1,
1216 .chan_config[0] = { 1220 .chan_config[0] = {
1217 .inputs = da850_ch0_inputs, 1221 .inputs = da850_ch0_inputs,
1218 .input_count = ARRAY_SIZE(da850_ch0_inputs), 1222 .input_count = ARRAY_SIZE(da850_ch0_inputs),
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 023480b75244..20f1874a5657 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -744,7 +744,8 @@ static int davinci_phy_fixup(struct phy_device *phydev)
744 return 0; 744 return 0;
745} 745}
746 746
747#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) 747#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
748 IS_ENABLED(CONFIG_PATA_BK3710))
748 749
749#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP) 750#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
750 751
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index f702d4fc8eb8..cb176826d1cb 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -119,7 +119,8 @@ static struct platform_device davinci_nand_device = {
119 }, 119 },
120}; 120};
121 121
122#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) 122#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
123 IS_ENABLED(CONFIG_PATA_BK3710))
123 124
124#ifdef CONFIG_I2C 125#ifdef CONFIG_I2C
125/* CPLD Register 0 bits to control ATA */ 126/* CPLD Register 0 bits to control ATA */
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 0a7838852649..0c02aaad0539 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -163,7 +163,8 @@ static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
163 .wires = 4, 163 .wires = 4,
164}; 164};
165 165
166#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) 166#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
167 IS_ENABLED(CONFIG_PATA_BK3710))
167 168
168#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI) 169#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
169 170
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 073c458d0c67..bd88470f3e5c 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -304,6 +304,11 @@ static struct clk usb20_clk = {
304 .gpsc = 1, 304 .gpsc = 1,
305}; 305};
306 306
307static struct clk cppi41_clk = {
308 .name = "cppi41",
309 .parent = &usb20_clk,
310};
311
307static struct clk aemif_clk = { 312static struct clk aemif_clk = {
308 .name = "aemif", 313 .name = "aemif",
309 .parent = &pll0_sysclk3, 314 .parent = &pll0_sysclk3,
@@ -413,6 +418,7 @@ static struct clk_lookup da830_clks[] = {
413 CLK("davinci-mcasp.1", NULL, &mcasp1_clk), 418 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
414 CLK("davinci-mcasp.2", NULL, &mcasp2_clk), 419 CLK("davinci-mcasp.2", NULL, &mcasp2_clk),
415 CLK("musb-da8xx", "usb20", &usb20_clk), 420 CLK("musb-da8xx", "usb20", &usb20_clk),
421 CLK("cppi41-dmaengine", NULL, &cppi41_clk),
416 CLK(NULL, "aemif", &aemif_clk), 422 CLK(NULL, "aemif", &aemif_clk),
417 CLK(NULL, "aintc", &aintc_clk), 423 CLK(NULL, "aintc", &aintc_clk),
418 CLK(NULL, "secu_mgr", &secu_mgr_clk), 424 CLK(NULL, "secu_mgr", &secu_mgr_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index ccad2f99dfc9..07d6f0eb8c82 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -401,6 +401,11 @@ static struct clk usb20_clk = {
401 .gpsc = 1, 401 .gpsc = 1,
402}; 402};
403 403
404static struct clk cppi41_clk = {
405 .name = "cppi41",
406 .parent = &usb20_clk,
407};
408
404static struct clk spi0_clk = { 409static struct clk spi0_clk = {
405 .name = "spi0", 410 .name = "spi0",
406 .parent = &pll0_sysclk2, 411 .parent = &pll0_sysclk2,
@@ -560,6 +565,7 @@ static struct clk_lookup da850_clks[] = {
560 CLK("davinci-nand.0", "aemif", &aemif_nand_clk), 565 CLK("davinci-nand.0", "aemif", &aemif_nand_clk),
561 CLK("ohci-da8xx", "usb11", &usb11_clk), 566 CLK("ohci-da8xx", "usb11", &usb11_clk),
562 CLK("musb-da8xx", "usb20", &usb20_clk), 567 CLK("musb-da8xx", "usb20", &usb20_clk),
568 CLK("cppi41-dmaengine", NULL, &cppi41_clk),
563 CLK("spi_davinci.0", NULL, &spi0_clk), 569 CLK("spi_davinci.0", NULL, &spi0_clk),
564 CLK("spi_davinci.1", NULL, &spi1_clk), 570 CLK("spi_davinci.1", NULL, &spi1_clk),
565 CLK("vpif", NULL, &vpif_clk), 571 CLK("vpif", NULL, &vpif_clk),
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index e3cef503cd8f..5699ce39e64f 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -53,6 +53,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
53 OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL), 53 OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL),
54 OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL), 54 OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL),
55 OF_DEV_AUXDATA("ti,da850-ahci", 0x01e18000, "ahci_da850", NULL), 55 OF_DEV_AUXDATA("ti,da850-ahci", 0x01e18000, "ahci_da850", NULL),
56 OF_DEV_AUXDATA("ti,da850-vpif", 0x01e17000, "vpif", NULL),
56 {} 57 {}
57}; 58};
58 59
diff --git a/arch/arm/mach-davinci/pdata-quirks.c b/arch/arm/mach-davinci/pdata-quirks.c
index 5b57da475065..329f5402ad1d 100644
--- a/arch/arm/mach-davinci/pdata-quirks.c
+++ b/arch/arm/mach-davinci/pdata-quirks.c
@@ -10,26 +10,202 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/of_platform.h> 11#include <linux/of_platform.h>
12 12
13#include <media/i2c/tvp514x.h>
14#include <media/i2c/adv7343.h>
15
13#include <mach/common.h> 16#include <mach/common.h>
17#include <mach/da8xx.h>
14 18
15struct pdata_init { 19struct pdata_init {
16 const char *compatible; 20 const char *compatible;
17 void (*fn)(void); 21 void (*fn)(void);
18}; 22};
19 23
24#define TVP5147_CH0 "tvp514x-0"
25#define TVP5147_CH1 "tvp514x-1"
26
27/* VPIF capture configuration */
28static struct tvp514x_platform_data tvp5146_pdata = {
29 .clk_polarity = 0,
30 .hs_polarity = 1,
31 .vs_polarity = 1,
32};
33
34#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
35
36static const struct vpif_input da850_ch0_inputs[] = {
37 {
38 .input = {
39 .index = 0,
40 .name = "Composite",
41 .type = V4L2_INPUT_TYPE_CAMERA,
42 .capabilities = V4L2_IN_CAP_STD,
43 .std = TVP514X_STD_ALL,
44 },
45 .input_route = INPUT_CVBS_VI2B,
46 .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
47 .subdev_name = TVP5147_CH0,
48 },
49};
50
51static const struct vpif_input da850_ch1_inputs[] = {
52 {
53 .input = {
54 .index = 0,
55 .name = "S-Video",
56 .type = V4L2_INPUT_TYPE_CAMERA,
57 .capabilities = V4L2_IN_CAP_STD,
58 .std = TVP514X_STD_ALL,
59 },
60 .input_route = INPUT_SVIDEO_VI2C_VI1C,
61 .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
62 .subdev_name = TVP5147_CH1,
63 },
64};
65
66static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
67 {
68 .name = TVP5147_CH0,
69 .board_info = {
70 I2C_BOARD_INFO("tvp5146", 0x5d),
71 .platform_data = &tvp5146_pdata,
72 },
73 },
74 {
75 .name = TVP5147_CH1,
76 .board_info = {
77 I2C_BOARD_INFO("tvp5146", 0x5c),
78 .platform_data = &tvp5146_pdata,
79 },
80 },
81};
82
83static struct vpif_capture_config da850_vpif_capture_config = {
84 .subdev_info = da850_vpif_capture_sdev_info,
85 .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
86 .chan_config[0] = {
87 .inputs = da850_ch0_inputs,
88 .input_count = ARRAY_SIZE(da850_ch0_inputs),
89 .vpif_if = {
90 .if_type = VPIF_IF_BT656,
91 .hd_pol = 1,
92 .vd_pol = 1,
93 .fid_pol = 0,
94 },
95 },
96 .chan_config[1] = {
97 .inputs = da850_ch1_inputs,
98 .input_count = ARRAY_SIZE(da850_ch1_inputs),
99 .vpif_if = {
100 .if_type = VPIF_IF_BT656,
101 .hd_pol = 1,
102 .vd_pol = 1,
103 .fid_pol = 0,
104 },
105 },
106 .card_name = "DA850/OMAP-L138 Video Capture",
107};
108
109static void __init da850_vpif_legacy_register_capture(void)
110{
111 int ret;
112
113 ret = da850_register_vpif_capture(&da850_vpif_capture_config);
114 if (ret)
115 pr_warn("%s: VPIF capture setup failed: %d\n",
116 __func__, ret);
117}
118
119static void __init da850_vpif_capture_legacy_init_lcdk(void)
120{
121 da850_vpif_capture_config.subdev_count = 1;
122 da850_vpif_legacy_register_capture();
123}
124
125static void __init da850_vpif_capture_legacy_init_evm(void)
126{
127 da850_vpif_legacy_register_capture();
128}
129
130static struct adv7343_platform_data adv7343_pdata = {
131 .mode_config = {
132 .dac = { 1, 1, 1 },
133 },
134 .sd_config = {
135 .sd_dac_out = { 1 },
136 },
137};
138
139static struct vpif_subdev_info da850_vpif_subdev[] = {
140 {
141 .name = "adv7343",
142 .board_info = {
143 I2C_BOARD_INFO("adv7343", 0x2a),
144 .platform_data = &adv7343_pdata,
145 },
146 },
147};
148
149static const struct vpif_output da850_ch0_outputs[] = {
150 {
151 .output = {
152 .index = 0,
153 .name = "Composite",
154 .type = V4L2_OUTPUT_TYPE_ANALOG,
155 .capabilities = V4L2_OUT_CAP_STD,
156 .std = V4L2_STD_ALL,
157 },
158 .subdev_name = "adv7343",
159 .output_route = ADV7343_COMPOSITE_ID,
160 },
161 {
162 .output = {
163 .index = 1,
164 .name = "S-Video",
165 .type = V4L2_OUTPUT_TYPE_ANALOG,
166 .capabilities = V4L2_OUT_CAP_STD,
167 .std = V4L2_STD_ALL,
168 },
169 .subdev_name = "adv7343",
170 .output_route = ADV7343_SVIDEO_ID,
171 },
172};
173
174static struct vpif_display_config da850_vpif_display_config = {
175 .subdevinfo = da850_vpif_subdev,
176 .subdev_count = ARRAY_SIZE(da850_vpif_subdev),
177 .chan_config[0] = {
178 .outputs = da850_ch0_outputs,
179 .output_count = ARRAY_SIZE(da850_ch0_outputs),
180 },
181 .card_name = "DA850/OMAP-L138 Video Display",
182};
183
184static void __init da850_vpif_display_legacy_init_evm(void)
185{
186 int ret;
187
188 ret = da850_register_vpif_display(&da850_vpif_display_config);
189 if (ret)
190 pr_warn("%s: VPIF display setup failed: %d\n",
191 __func__, ret);
192}
193
20static void pdata_quirks_check(struct pdata_init *quirks) 194static void pdata_quirks_check(struct pdata_init *quirks)
21{ 195{
22 while (quirks->compatible) { 196 while (quirks->compatible) {
23 if (of_machine_is_compatible(quirks->compatible)) { 197 if (of_machine_is_compatible(quirks->compatible)) {
24 if (quirks->fn) 198 if (quirks->fn)
25 quirks->fn(); 199 quirks->fn();
26 break;
27 } 200 }
28 quirks++; 201 quirks++;
29 } 202 }
30} 203}
31 204
32static struct pdata_init pdata_quirks[] __initdata = { 205static struct pdata_init pdata_quirks[] __initdata = {
206 { "ti,da850-lcdk", da850_vpif_capture_legacy_init_lcdk, },
207 { "ti,da850-evm", da850_vpif_display_legacy_init_evm, },
208 { "ti,da850-evm", da850_vpif_capture_legacy_init_evm, },
33 { /* sentinel */ }, 209 { /* sentinel */ },
34}; 210};
35 211
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index 0afd201ab980..efb80354f303 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -108,7 +108,6 @@ static int davinci_pm_enter(suspend_state_t state)
108 int ret = 0; 108 int ret = 0;
109 109
110 switch (state) { 110 switch (state) {
111 case PM_SUSPEND_STANDBY:
112 case PM_SUSPEND_MEM: 111 case PM_SUSPEND_MEM:
113 davinci_pm_suspend(); 112 davinci_pm_suspend();
114 break; 113 break;
diff --git a/arch/arm/mach-gemini/Kconfig b/arch/arm/mach-gemini/Kconfig
index 6f066ee4bf24..06c8b095154c 100644
--- a/arch/arm/mach-gemini/Kconfig
+++ b/arch/arm/mach-gemini/Kconfig
@@ -1,40 +1,13 @@
1if ARCH_GEMINI 1menuconfig ARCH_GEMINI
2 2 bool "Cortina Systems Gemini"
3menu "Cortina Systems Gemini Implementations" 3 depends on ARCH_MULTI_V4
4 4 select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
5config MACH_NAS4220B 5 select FARADAY_FTINTC010
6 bool "Raidsonic NAS-4220-B" 6 select FTTMR010_TIMER
7 select GEMINI_MEM_SWAP 7 select GPIO_FTGPIO010
8 help 8 select GPIOLIB
9 Say Y here if you intend to run this kernel on a 9 select POWER_RESET
10 Raidsonic NAS-4220-B. 10 select POWER_RESET_GEMINI_POWEROFF
11 11 select POWER_RESET_SYSCON
12config MACH_RUT100 12 help
13 bool "Teltonika RUT100" 13 Support for the Cortina Systems Gemini family SoCs
14 select GEMINI_MEM_SWAP
15 help
16 Say Y here if you intend to run this kernel on a
17 Teltonika 3G Router RUT100.
18
19config MACH_WBD111
20 bool "Wiliboard WBD-111"
21 select GEMINI_MEM_SWAP
22 help
23 Say Y here if you intend to run this kernel on a
24 Wiliboard WBD-111.
25
26config MACH_WBD222
27 bool "Wiliboard WBD-222"
28 select GEMINI_MEM_SWAP
29 help
30 Say Y here if you intend to run this kernel on a
31 Wiliboard WBD-222.
32
33endmenu
34
35config GEMINI_MEM_SWAP
36 bool "Gemini memory is swapped"
37 help
38 Say Y here if Gemini memory is swapped by bootloader.
39
40endif
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
index 7963a77be637..ca0db5477180 100644
--- a/arch/arm/mach-gemini/Makefile
+++ b/arch/arm/mach-gemini/Makefile
@@ -1,13 +1,2 @@
1# 1# Makefile for Cortina systems Gemini
2# Makefile for the linux kernel. 2obj-y := board-dt.o
3#
4
5# Object file lists.
6
7obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
8
9# Board-specific support
10obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
11obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
12obj-$(CONFIG_MACH_WBD111) += board-wbd111.o
13obj-$(CONFIG_MACH_WBD222) += board-wbd222.o
diff --git a/arch/arm/mach-gemini/Makefile.boot b/arch/arm/mach-gemini/Makefile.boot
deleted file mode 100644
index 683f52b20e3d..000000000000
--- a/arch/arm/mach-gemini/Makefile.boot
+++ /dev/null
@@ -1,9 +0,0 @@
1ifeq ($(CONFIG_GEMINI_MEM_SWAP),y)
2 zreladdr-y += 0x00008000
3params_phys-y := 0x00000100
4initrd_phys-y := 0x00800000
5else
6 zreladdr-y += 0x10008000
7params_phys-y := 0x10000100
8initrd_phys-y := 0x10800000
9endif
diff --git a/arch/arm/mach-gemini/board-dt.c b/arch/arm/mach-gemini/board-dt.c
new file mode 100644
index 000000000000..c0c0ebdd551e
--- /dev/null
+++ b/arch/arm/mach-gemini/board-dt.c
@@ -0,0 +1,62 @@
1/*
2 * Gemini Device Tree boot support
3 */
4#include <linux/kernel.h>
5#include <linux/init.h>
6#include <linux/io.h>
7
8#include <asm/mach/arch.h>
9#include <asm/mach/map.h>
10#include <asm/system_misc.h>
11#include <asm/proc-fns.h>
12
13#ifdef CONFIG_DEBUG_GEMINI
14/* This is needed for LL-debug/earlyprintk/debug-macro.S */
15static struct map_desc gemini_io_desc[] __initdata = {
16 {
17 .virtual = CONFIG_DEBUG_UART_VIRT,
18 .pfn = __phys_to_pfn(CONFIG_DEBUG_UART_PHYS),
19 .length = SZ_4K,
20 .type = MT_DEVICE,
21 },
22};
23
24static void __init gemini_map_io(void)
25{
26 iotable_init(gemini_io_desc, ARRAY_SIZE(gemini_io_desc));
27}
28#else
29#define gemini_map_io NULL
30#endif
31
32static void gemini_idle(void)
33{
34 /*
35 * Because of broken hardware we have to enable interrupts or the CPU
36 * will never wakeup... Acctualy it is not very good to enable
37 * interrupts first since scheduler can miss a tick, but there is
38 * no other way around this. Platforms that needs it for power saving
39 * should enable it in init code, since by default it is
40 * disabled.
41 */
42
43 /* FIXME: Enabling interrupts here is racy! */
44 local_irq_enable();
45 cpu_do_idle();
46}
47
48static void __init gemini_init_machine(void)
49{
50 arm_pm_idle = gemini_idle;
51}
52
53static const char *gemini_board_compat[] = {
54 "cortina,gemini",
55 NULL,
56};
57
58DT_MACHINE_START(GEMINI_DT, "Gemini (Device Tree)")
59 .map_io = gemini_map_io,
60 .init_machine = gemini_init_machine,
61 .dt_compat = gemini_board_compat,
62MACHINE_END
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
deleted file mode 100644
index 18b12796acf9..000000000000
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * Support for Raidsonic NAS-4220-B
3 *
4 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
5 *
6 * based on rut1xx.c
7 * Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/leds.h>
19#include <linux/input.h>
20#include <linux/gpio_keys.h>
21#include <linux/io.h>
22
23#include <asm/setup.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27
28#include <mach/hardware.h>
29#include <mach/global_reg.h>
30
31#include "common.h"
32
33static struct gpio_led ib4220b_leds[] = {
34 {
35 .name = "nas4220b:orange:hdd",
36 .default_trigger = "none",
37 .gpio = 60,
38 },
39 {
40 .name = "nas4220b:green:os",
41 .default_trigger = "heartbeat",
42 .gpio = 62,
43 },
44};
45
46static struct gpio_led_platform_data ib4220b_leds_data = {
47 .num_leds = ARRAY_SIZE(ib4220b_leds),
48 .leds = ib4220b_leds,
49};
50
51static struct platform_device ib4220b_led_device = {
52 .name = "leds-gpio",
53 .id = -1,
54 .dev = {
55 .platform_data = &ib4220b_leds_data,
56 },
57};
58
59static struct gpio_keys_button ib4220b_keys[] = {
60 {
61 .code = KEY_SETUP,
62 .gpio = 61,
63 .active_low = 1,
64 .desc = "Backup Button",
65 .type = EV_KEY,
66 },
67 {
68 .code = KEY_RESTART,
69 .gpio = 63,
70 .active_low = 1,
71 .desc = "Softreset Button",
72 .type = EV_KEY,
73 },
74};
75
76static struct gpio_keys_platform_data ib4220b_keys_data = {
77 .buttons = ib4220b_keys,
78 .nbuttons = ARRAY_SIZE(ib4220b_keys),
79};
80
81static struct platform_device ib4220b_key_device = {
82 .name = "gpio-keys",
83 .id = -1,
84 .dev = {
85 .platform_data = &ib4220b_keys_data,
86 },
87};
88
89static void __init ib4220b_init(void)
90{
91 gemini_gpio_init();
92 platform_register_uart();
93 platform_register_pflash(SZ_16M, NULL, 0);
94 platform_device_register(&ib4220b_led_device);
95 platform_device_register(&ib4220b_key_device);
96 platform_register_rtc();
97}
98
99MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
100 .atag_offset = 0x100,
101 .map_io = gemini_map_io,
102 .init_irq = gemini_init_irq,
103 .init_time = gemini_timer_init,
104 .init_machine = ib4220b_init,
105 .restart = gemini_restart,
106MACHINE_END
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
deleted file mode 100644
index 7a675f88ffd6..000000000000
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Support for Teltonika RUT1xx
3 *
4 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/leds.h>
15#include <linux/input.h>
16#include <linux/gpio_keys.h>
17#include <linux/sizes.h>
18
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21#include <asm/mach/time.h>
22
23#include "common.h"
24
25static struct gpio_keys_button rut1xx_keys[] = {
26 {
27 .code = KEY_SETUP,
28 .gpio = 60,
29 .active_low = 1,
30 .desc = "Reset to defaults",
31 .type = EV_KEY,
32 },
33};
34
35static struct gpio_keys_platform_data rut1xx_keys_data = {
36 .buttons = rut1xx_keys,
37 .nbuttons = ARRAY_SIZE(rut1xx_keys),
38};
39
40static struct platform_device rut1xx_keys_device = {
41 .name = "gpio-keys",
42 .id = -1,
43 .dev = {
44 .platform_data = &rut1xx_keys_data,
45 },
46};
47
48static struct gpio_led rut100_leds[] = {
49 {
50 .name = "Power",
51 .default_trigger = "heartbeat",
52 .gpio = 17,
53 },
54 {
55 .name = "GSM",
56 .default_trigger = "default-on",
57 .gpio = 7,
58 .active_low = 1,
59 },
60};
61
62static struct gpio_led_platform_data rut100_leds_data = {
63 .num_leds = ARRAY_SIZE(rut100_leds),
64 .leds = rut100_leds,
65};
66
67static struct platform_device rut1xx_leds = {
68 .name = "leds-gpio",
69 .id = -1,
70 .dev = {
71 .platform_data = &rut100_leds_data,
72 },
73};
74
75static void __init rut1xx_init(void)
76{
77 gemini_gpio_init();
78 platform_register_uart();
79 platform_register_pflash(SZ_8M, NULL, 0);
80 platform_device_register(&rut1xx_leds);
81 platform_device_register(&rut1xx_keys_device);
82 platform_register_rtc();
83}
84
85MACHINE_START(RUT100, "Teltonika RUT100")
86 .atag_offset = 0x100,
87 .map_io = gemini_map_io,
88 .init_irq = gemini_init_irq,
89 .init_time = gemini_timer_init,
90 .init_machine = rut1xx_init,
91 .restart = gemini_restart,
92MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
deleted file mode 100644
index 14c56f3f0ec2..000000000000
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Support for Wiliboard WBD-111
3 *
4 * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/leds.h>
15#include <linux/input.h>
16#include <linux/skbuff.h>
17#include <linux/gpio_keys.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/partitions.h>
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/time.h>
23
24
25#include "common.h"
26
27static struct gpio_keys_button wbd111_keys[] = {
28 {
29 .code = KEY_SETUP,
30 .gpio = 5,
31 .active_low = 1,
32 .desc = "reset",
33 .type = EV_KEY,
34 },
35};
36
37static struct gpio_keys_platform_data wbd111_keys_data = {
38 .buttons = wbd111_keys,
39 .nbuttons = ARRAY_SIZE(wbd111_keys),
40};
41
42static struct platform_device wbd111_keys_device = {
43 .name = "gpio-keys",
44 .id = -1,
45 .dev = {
46 .platform_data = &wbd111_keys_data,
47 },
48};
49
50static struct gpio_led wbd111_leds[] = {
51 {
52 .name = "L3red",
53 .gpio = 1,
54 },
55 {
56 .name = "L4green",
57 .gpio = 2,
58 },
59 {
60 .name = "L4red",
61 .gpio = 3,
62 },
63 {
64 .name = "L3green",
65 .gpio = 5,
66 },
67};
68
69static struct gpio_led_platform_data wbd111_leds_data = {
70 .num_leds = ARRAY_SIZE(wbd111_leds),
71 .leds = wbd111_leds,
72};
73
74static struct platform_device wbd111_leds_device = {
75 .name = "leds-gpio",
76 .id = -1,
77 .dev = {
78 .platform_data = &wbd111_leds_data,
79 },
80};
81
82static struct mtd_partition wbd111_partitions[] = {
83 {
84 .name = "RedBoot",
85 .offset = 0,
86 .size = 0x020000,
87 .mask_flags = MTD_WRITEABLE,
88 } , {
89 .name = "kernel",
90 .offset = 0x020000,
91 .size = 0x100000,
92 } , {
93 .name = "rootfs",
94 .offset = 0x120000,
95 .size = 0x6a0000,
96 } , {
97 .name = "VCTL",
98 .offset = 0x7c0000,
99 .size = 0x010000,
100 .mask_flags = MTD_WRITEABLE,
101 } , {
102 .name = "cfg",
103 .offset = 0x7d0000,
104 .size = 0x010000,
105 .mask_flags = MTD_WRITEABLE,
106 } , {
107 .name = "FIS",
108 .offset = 0x7e0000,
109 .size = 0x010000,
110 .mask_flags = MTD_WRITEABLE,
111 }
112};
113#define wbd111_num_partitions ARRAY_SIZE(wbd111_partitions)
114
115static void __init wbd111_init(void)
116{
117 gemini_gpio_init();
118 platform_register_uart();
119 platform_register_pflash(SZ_8M, wbd111_partitions,
120 wbd111_num_partitions);
121 platform_device_register(&wbd111_leds_device);
122 platform_device_register(&wbd111_keys_device);
123 platform_register_rtc();
124}
125
126MACHINE_START(WBD111, "Wiliboard WBD-111")
127 .atag_offset = 0x100,
128 .map_io = gemini_map_io,
129 .init_irq = gemini_init_irq,
130 .init_time = gemini_timer_init,
131 .init_machine = wbd111_init,
132 .restart = gemini_restart,
133MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
deleted file mode 100644
index 6070282ce243..000000000000
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Support for Wiliboard WBD-222
3 *
4 * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/leds.h>
15#include <linux/input.h>
16#include <linux/skbuff.h>
17#include <linux/gpio_keys.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/partitions.h>
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/time.h>
23
24
25#include "common.h"
26
27static struct gpio_keys_button wbd222_keys[] = {
28 {
29 .code = KEY_SETUP,
30 .gpio = 5,
31 .active_low = 1,
32 .desc = "reset",
33 .type = EV_KEY,
34 },
35};
36
37static struct gpio_keys_platform_data wbd222_keys_data = {
38 .buttons = wbd222_keys,
39 .nbuttons = ARRAY_SIZE(wbd222_keys),
40};
41
42static struct platform_device wbd222_keys_device = {
43 .name = "gpio-keys",
44 .id = -1,
45 .dev = {
46 .platform_data = &wbd222_keys_data,
47 },
48};
49
50static struct gpio_led wbd222_leds[] = {
51 {
52 .name = "L3red",
53 .gpio = 1,
54 },
55 {
56 .name = "L4green",
57 .gpio = 2,
58 },
59 {
60 .name = "L4red",
61 .gpio = 3,
62 },
63 {
64 .name = "L3green",
65 .gpio = 5,
66 },
67};
68
69static struct gpio_led_platform_data wbd222_leds_data = {
70 .num_leds = ARRAY_SIZE(wbd222_leds),
71 .leds = wbd222_leds,
72};
73
74static struct platform_device wbd222_leds_device = {
75 .name = "leds-gpio",
76 .id = -1,
77 .dev = {
78 .platform_data = &wbd222_leds_data,
79 },
80};
81
82static struct mtd_partition wbd222_partitions[] = {
83 {
84 .name = "RedBoot",
85 .offset = 0,
86 .size = 0x020000,
87 .mask_flags = MTD_WRITEABLE,
88 } , {
89 .name = "kernel",
90 .offset = 0x020000,
91 .size = 0x100000,
92 } , {
93 .name = "rootfs",
94 .offset = 0x120000,
95 .size = 0x6a0000,
96 } , {
97 .name = "VCTL",
98 .offset = 0x7c0000,
99 .size = 0x010000,
100 .mask_flags = MTD_WRITEABLE,
101 } , {
102 .name = "cfg",
103 .offset = 0x7d0000,
104 .size = 0x010000,
105 .mask_flags = MTD_WRITEABLE,
106 } , {
107 .name = "FIS",
108 .offset = 0x7e0000,
109 .size = 0x010000,
110 .mask_flags = MTD_WRITEABLE,
111 }
112};
113#define wbd222_num_partitions ARRAY_SIZE(wbd222_partitions)
114
115static void __init wbd222_init(void)
116{
117 gemini_gpio_init();
118 platform_register_uart();
119 platform_register_pflash(SZ_8M, wbd222_partitions,
120 wbd222_num_partitions);
121 platform_device_register(&wbd222_leds_device);
122 platform_device_register(&wbd222_keys_device);
123 platform_register_rtc();
124}
125
126MACHINE_START(WBD222, "Wiliboard WBD-222")
127 .atag_offset = 0x100,
128 .map_io = gemini_map_io,
129 .init_irq = gemini_init_irq,
130 .init_time = gemini_timer_init,
131 .init_machine = wbd222_init,
132 .restart = gemini_restart,
133MACHINE_END
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
deleted file mode 100644
index dd883698ff7e..000000000000
--- a/arch/arm/mach-gemini/common.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Common Gemini architecture functions
3 *
4 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __GEMINI_COMMON_H__
13#define __GEMINI_COMMON_H__
14
15#include <linux/reboot.h>
16
17struct mtd_partition;
18
19extern void gemini_map_io(void);
20extern void gemini_init_irq(void);
21extern void gemini_timer_init(void);
22extern void gemini_gpio_init(void);
23extern void platform_register_rtc(void);
24
25/* Common platform devices registration functions */
26extern int platform_register_uart(void);
27extern int platform_register_pflash(unsigned int size,
28 struct mtd_partition *parts,
29 unsigned int nr_parts);
30
31extern void gemini_restart(enum reboot_mode mode, const char *cmd);
32
33#endif /* __GEMINI_COMMON_H__ */
diff --git a/arch/arm/mach-gemini/devices.c b/arch/arm/mach-gemini/devices.c
deleted file mode 100644
index 5cff29818b73..000000000000
--- a/arch/arm/mach-gemini/devices.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * Common devices definition for Gemini
3 *
4 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/platform_device.h>
14#include <linux/serial_8250.h>
15#include <linux/mtd/physmap.h>
16
17#include <mach/irqs.h>
18#include <mach/hardware.h>
19#include <mach/global_reg.h>
20
21static struct plat_serial8250_port serial_platform_data[] = {
22 {
23 .membase = (void *)IO_ADDRESS(GEMINI_UART_BASE),
24 .mapbase = GEMINI_UART_BASE,
25 .irq = IRQ_UART,
26 .uartclk = UART_CLK,
27 .regshift = 2,
28 .iotype = UPIO_MEM,
29 .type = PORT_16550A,
30 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_FIXED_TYPE,
31 },
32 {},
33};
34
35static struct platform_device serial_device = {
36 .name = "serial8250",
37 .id = PLAT8250_DEV_PLATFORM,
38 .dev = {
39 .platform_data = serial_platform_data,
40 },
41};
42
43int platform_register_uart(void)
44{
45 return platform_device_register(&serial_device);
46}
47
48static struct resource flash_resource = {
49 .start = GEMINI_FLASH_BASE,
50 .flags = IORESOURCE_MEM,
51};
52
53static struct physmap_flash_data pflash_platform_data = {};
54
55static struct platform_device pflash_device = {
56 .name = "physmap-flash",
57 .id = 0,
58 .dev = {
59 .platform_data = &pflash_platform_data,
60 },
61 .resource = &flash_resource,
62 .num_resources = 1,
63};
64
65int platform_register_pflash(unsigned int size, struct mtd_partition *parts,
66 unsigned int nr_parts)
67{
68 unsigned int reg;
69
70 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_STATUS);
71
72 if ((reg & FLASH_TYPE_MASK) != FLASH_TYPE_PARALLEL)
73 return -ENXIO;
74
75 if (reg & FLASH_WIDTH_16BIT)
76 pflash_platform_data.width = 2;
77 else
78 pflash_platform_data.width = 1;
79
80 /* enable parallel flash pins and disable others */
81 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
82 reg &= ~PFLASH_PADS_DISABLE;
83 reg |= SFLASH_PADS_DISABLE | NAND_PADS_DISABLE;
84 __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
85
86 flash_resource.end = flash_resource.start + size - 1;
87
88 pflash_platform_data.parts = parts;
89 pflash_platform_data.nr_parts = nr_parts;
90
91 return platform_device_register(&pflash_device);
92}
93
94static struct resource gemini_rtc_resources[] = {
95 [0] = {
96 .start = GEMINI_RTC_BASE,
97 .end = GEMINI_RTC_BASE + 0x24,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = IRQ_RTC,
102 .end = IRQ_RTC,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device gemini_rtc_device = {
108 .name = "rtc-gemini",
109 .id = 0,
110 .num_resources = ARRAY_SIZE(gemini_rtc_resources),
111 .resource = gemini_rtc_resources,
112};
113
114int __init platform_register_rtc(void)
115{
116 return platform_device_register(&gemini_rtc_device);
117}
118
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
deleted file mode 100644
index 469a76ea0459..000000000000
--- a/arch/arm/mach-gemini/gpio.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * Gemini gpiochip and interrupt routines
3 *
4 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 *
6 * Based on plat-mxc/gpio.c:
7 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
8 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/gpio/driver.h>
21
22#include <mach/hardware.h>
23#include <mach/irqs.h>
24
25#define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x))
26#define irq_to_gpio(x) ((x) - GPIO_IRQ_BASE)
27
28/* GPIO registers definition */
29#define GPIO_DATA_OUT 0x0
30#define GPIO_DATA_IN 0x4
31#define GPIO_DIR 0x8
32#define GPIO_DATA_SET 0x10
33#define GPIO_DATA_CLR 0x14
34#define GPIO_PULL_EN 0x18
35#define GPIO_PULL_TYPE 0x1C
36#define GPIO_INT_EN 0x20
37#define GPIO_INT_STAT 0x24
38#define GPIO_INT_MASK 0x2C
39#define GPIO_INT_CLR 0x30
40#define GPIO_INT_TYPE 0x34
41#define GPIO_INT_BOTH_EDGE 0x38
42#define GPIO_INT_LEVEL 0x3C
43#define GPIO_DEBOUNCE_EN 0x40
44#define GPIO_DEBOUNCE_PRESCALE 0x44
45
46#define GPIO_PORT_NUM 3
47
48static void _set_gpio_irqenable(void __iomem *base, unsigned int index,
49 int enable)
50{
51 unsigned int reg;
52
53 reg = __raw_readl(base + GPIO_INT_EN);
54 reg = (reg & (~(1 << index))) | (!!enable << index);
55 __raw_writel(reg, base + GPIO_INT_EN);
56}
57
58static void gpio_ack_irq(struct irq_data *d)
59{
60 unsigned int gpio = irq_to_gpio(d->irq);
61 void __iomem *base = GPIO_BASE(gpio / 32);
62
63 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
64}
65
66static void gpio_mask_irq(struct irq_data *d)
67{
68 unsigned int gpio = irq_to_gpio(d->irq);
69 void __iomem *base = GPIO_BASE(gpio / 32);
70
71 _set_gpio_irqenable(base, gpio % 32, 0);
72}
73
74static void gpio_unmask_irq(struct irq_data *d)
75{
76 unsigned int gpio = irq_to_gpio(d->irq);
77 void __iomem *base = GPIO_BASE(gpio / 32);
78
79 _set_gpio_irqenable(base, gpio % 32, 1);
80}
81
82static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
83{
84 unsigned int gpio = irq_to_gpio(d->irq);
85 unsigned int gpio_mask = 1 << (gpio % 32);
86 void __iomem *base = GPIO_BASE(gpio / 32);
87 unsigned int reg_both, reg_level, reg_type;
88
89 reg_type = __raw_readl(base + GPIO_INT_TYPE);
90 reg_level = __raw_readl(base + GPIO_INT_LEVEL);
91 reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
92
93 switch (type) {
94 case IRQ_TYPE_EDGE_BOTH:
95 reg_type &= ~gpio_mask;
96 reg_both |= gpio_mask;
97 break;
98 case IRQ_TYPE_EDGE_RISING:
99 reg_type &= ~gpio_mask;
100 reg_both &= ~gpio_mask;
101 reg_level &= ~gpio_mask;
102 break;
103 case IRQ_TYPE_EDGE_FALLING:
104 reg_type &= ~gpio_mask;
105 reg_both &= ~gpio_mask;
106 reg_level |= gpio_mask;
107 break;
108 case IRQ_TYPE_LEVEL_HIGH:
109 reg_type |= gpio_mask;
110 reg_level &= ~gpio_mask;
111 break;
112 case IRQ_TYPE_LEVEL_LOW:
113 reg_type |= gpio_mask;
114 reg_level |= gpio_mask;
115 break;
116 default:
117 return -EINVAL;
118 }
119
120 __raw_writel(reg_type, base + GPIO_INT_TYPE);
121 __raw_writel(reg_level, base + GPIO_INT_LEVEL);
122 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
123
124 gpio_ack_irq(d);
125
126 return 0;
127}
128
129static void gpio_irq_handler(struct irq_desc *desc)
130{
131 unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
132 unsigned int gpio_irq_no, irq_stat;
133
134 irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
135
136 gpio_irq_no = GPIO_IRQ_BASE + port * 32;
137 for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
138
139 if ((irq_stat & 1) == 0)
140 continue;
141
142 generic_handle_irq(gpio_irq_no);
143 }
144}
145
146static struct irq_chip gpio_irq_chip = {
147 .name = "GPIO",
148 .irq_ack = gpio_ack_irq,
149 .irq_mask = gpio_mask_irq,
150 .irq_unmask = gpio_unmask_irq,
151 .irq_set_type = gpio_set_irq_type,
152};
153
154static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
155 int dir)
156{
157 void __iomem *base = GPIO_BASE(offset / 32);
158 unsigned int reg;
159
160 reg = __raw_readl(base + GPIO_DIR);
161 if (dir)
162 reg |= 1 << (offset % 32);
163 else
164 reg &= ~(1 << (offset % 32));
165 __raw_writel(reg, base + GPIO_DIR);
166}
167
168static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
169{
170 void __iomem *base = GPIO_BASE(offset / 32);
171
172 if (value)
173 __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
174 else
175 __raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR);
176}
177
178static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
179{
180 void __iomem *base = GPIO_BASE(offset / 32);
181
182 return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
183}
184
185static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
186{
187 _set_gpio_direction(chip, offset, 0);
188 return 0;
189}
190
191static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
192 int value)
193{
194 _set_gpio_direction(chip, offset, 1);
195 gemini_gpio_set(chip, offset, value);
196 return 0;
197}
198
199static struct gpio_chip gemini_gpio_chip = {
200 .label = "Gemini",
201 .direction_input = gemini_gpio_direction_input,
202 .get = gemini_gpio_get,
203 .direction_output = gemini_gpio_direction_output,
204 .set = gemini_gpio_set,
205 .base = 0,
206 .ngpio = GPIO_PORT_NUM * 32,
207};
208
209void __init gemini_gpio_init(void)
210{
211 int i, j;
212
213 for (i = 0; i < GPIO_PORT_NUM; i++) {
214 /* disable, unmask and clear all interrupts */
215 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN);
216 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK);
217 __raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR);
218
219 for (j = GPIO_IRQ_BASE + i * 32;
220 j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
221 irq_set_chip_and_handler(j, &gpio_irq_chip,
222 handle_edge_irq);
223 irq_clear_status_flags(j, IRQ_NOREQUEST);
224 }
225
226 irq_set_chained_handler_and_data(IRQ_GPIO(i), gpio_irq_handler,
227 (void *)i);
228 }
229
230 BUG_ON(gpiochip_add_data(&gemini_gpio_chip, NULL));
231}
diff --git a/arch/arm/mach-gemini/idle.c b/arch/arm/mach-gemini/idle.c
deleted file mode 100644
index ddf8ec9d203b..000000000000
--- a/arch/arm/mach-gemini/idle.c
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * arch/arm/mach-gemini/idle.c
3 */
4
5#include <linux/init.h>
6#include <asm/system_misc.h>
7#include <asm/proc-fns.h>
8
9static void gemini_idle(void)
10{
11 /*
12 * Because of broken hardware we have to enable interrupts or the CPU
13 * will never wakeup... Acctualy it is not very good to enable
14 * interrupts first since scheduler can miss a tick, but there is
15 * no other way around this. Platforms that needs it for power saving
16 * should enable it in init code, since by default it is
17 * disabled.
18 */
19
20 /* FIXME: Enabling interrupts here is racy! */
21 local_irq_enable();
22 cpu_do_idle();
23}
24
25static int __init gemini_idle_init(void)
26{
27 arm_pm_idle = gemini_idle;
28 return 0;
29}
30
31arch_initcall(gemini_idle_init);
diff --git a/arch/arm/mach-gemini/include/mach/entry-macro.S b/arch/arm/mach-gemini/include/mach/entry-macro.S
deleted file mode 100644
index f044e430bfa4..000000000000
--- a/arch/arm/mach-gemini/include/mach/entry-macro.S
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Low-level IRQ helper macros for Gemini platform.
3 *
4 * Copyright (C) 2001-2006 Storlink, Corp.
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11#include <mach/hardware.h>
12
13#define IRQ_STATUS 0x14
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 ldr \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS)
20 ldr \irqnr, [\irqstat]
21 cmp \irqnr, #0
22 beq 2313f
23 mov \tmp, \irqnr
24 mov \irqnr, #0
252312:
26 tst \tmp, #1
27 bne 2313f
28 add \irqnr, \irqnr, #1
29 mov \tmp, \tmp, lsr #1
30 cmp \irqnr, #31
31 bcc 2312b
322313:
33 .endm
diff --git a/arch/arm/mach-gemini/include/mach/global_reg.h b/arch/arm/mach-gemini/include/mach/global_reg.h
deleted file mode 100644
index de7ff7e849fc..000000000000
--- a/arch/arm/mach-gemini/include/mach/global_reg.h
+++ /dev/null
@@ -1,278 +0,0 @@
1/*
2 * This file contains the hardware definitions for Gemini.
3 *
4 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef __MACH_GLOBAL_REG_H
12#define __MACH_GLOBAL_REG_H
13
14/* Global Word ID Register*/
15#define GLOBAL_ID 0x00
16
17#define CHIP_ID(reg) ((reg) >> 8)
18#define CHIP_REVISION(reg) ((reg) & 0xFF)
19
20/* Global Status Register */
21#define GLOBAL_STATUS 0x04
22
23#define CPU_BIG_ENDIAN (1 << 31)
24#define PLL_OSC_30M (1 << 30) /* else 60MHz */
25
26#define OPERATION_MODE_MASK (0xF << 26)
27#define OPM_IDDQ (0xF << 26)
28#define OPM_NAND (0xE << 26)
29#define OPM_RING (0xD << 26)
30#define OPM_DIRECT_BOOT (0xC << 26)
31#define OPM_USB1_PHY_TEST (0xB << 26)
32#define OPM_USB0_PHY_TEST (0xA << 26)
33#define OPM_SATA1_PHY_TEST (0x9 << 26)
34#define OPM_SATA0_PHY_TEST (0x8 << 26)
35#define OPM_ICE_ARM (0x7 << 26)
36#define OPM_ICE_FARADAY (0x6 << 26)
37#define OPM_PLL_BYPASS (0x5 << 26)
38#define OPM_DEBUG (0x4 << 26)
39#define OPM_BURN_IN (0x3 << 26)
40#define OPM_MBIST (0x2 << 26)
41#define OPM_SCAN (0x1 << 26)
42#define OPM_REAL (0x0 << 26)
43
44#define FLASH_TYPE_MASK (0x3 << 24)
45#define FLASH_TYPE_NAND_2K (0x3 << 24)
46#define FLASH_TYPE_NAND_512 (0x2 << 24)
47#define FLASH_TYPE_PARALLEL (0x1 << 24)
48#define FLASH_TYPE_SERIAL (0x0 << 24)
49/* if parallel */
50#define FLASH_WIDTH_16BIT (1 << 23) /* else 8 bit */
51/* if serial */
52#define FLASH_ATMEL (1 << 23) /* else STM */
53
54#define FLASH_SIZE_MASK (0x3 << 21)
55#define NAND_256M (0x3 << 21) /* and more */
56#define NAND_128M (0x2 << 21)
57#define NAND_64M (0x1 << 21)
58#define NAND_32M (0x0 << 21)
59#define ATMEL_16M (0x3 << 21) /* and more */
60#define ATMEL_8M (0x2 << 21)
61#define ATMEL_4M_2M (0x1 << 21)
62#define ATMEL_1M (0x0 << 21) /* and less */
63#define STM_32M (1 << 22) /* and more */
64#define STM_16M (0 << 22) /* and less */
65
66#define FLASH_PARALLEL_HIGH_PIN_CNT (1 << 20) /* else low pin cnt */
67
68#define CPU_AHB_RATIO_MASK (0x3 << 18)
69#define CPU_AHB_1_1 (0x0 << 18)
70#define CPU_AHB_3_2 (0x1 << 18)
71#define CPU_AHB_24_13 (0x2 << 18)
72#define CPU_AHB_2_1 (0x3 << 18)
73
74#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130)
75#define AHB_SPEED_TO_REG(x) ((((x - 130)) / 10) << 15)
76
77/* it is posible to override some settings, use >> OVERRIDE_xxxx_SHIFT */
78#define OVERRIDE_FLASH_TYPE_SHIFT 16
79#define OVERRIDE_FLASH_WIDTH_SHIFT 16
80#define OVERRIDE_FLASH_SIZE_SHIFT 16
81#define OVERRIDE_CPU_AHB_RATIO_SHIFT 15
82#define OVERRIDE_AHB_SPEED_SHIFT 15
83
84/* Global PLL Control Register */
85#define GLOBAL_PLL_CTRL 0x08
86
87#define PLL_BYPASS (1 << 31)
88#define PLL_POWER_DOWN (1 << 8)
89#define PLL_CONTROL_Q (0x1F << 0)
90
91/* Global Soft Reset Control Register */
92#define GLOBAL_RESET 0x0C
93
94#define RESET_GLOBAL (1 << 31)
95#define RESET_CPU1 (1 << 30)
96#define RESET_TVE (1 << 28)
97#define RESET_SATA1 (1 << 27)
98#define RESET_SATA0 (1 << 26)
99#define RESET_CIR (1 << 25)
100#define RESET_EXT_DEV (1 << 24)
101#define RESET_WD (1 << 23)
102#define RESET_GPIO2 (1 << 22)
103#define RESET_GPIO1 (1 << 21)
104#define RESET_GPIO0 (1 << 20)
105#define RESET_SSP (1 << 19)
106#define RESET_UART (1 << 18)
107#define RESET_TIMER (1 << 17)
108#define RESET_RTC (1 << 16)
109#define RESET_INT1 (1 << 15)
110#define RESET_INT0 (1 << 14)
111#define RESET_LCD (1 << 13)
112#define RESET_LPC (1 << 12)
113#define RESET_APB (1 << 11)
114#define RESET_DMA (1 << 10)
115#define RESET_USB1 (1 << 9)
116#define RESET_USB0 (1 << 8)
117#define RESET_PCI (1 << 7)
118#define RESET_GMAC1 (1 << 6)
119#define RESET_GMAC0 (1 << 5)
120#define RESET_SECURITY (1 << 4)
121#define RESET_RAID (1 << 3)
122#define RESET_IDE (1 << 2)
123#define RESET_FLASH (1 << 1)
124#define RESET_DRAM (1 << 0)
125
126/* Global IO Pad Driving Capability Control Register */
127#define GLOBAL_IO_DRIVING_CTRL 0x10
128
129#define DRIVING_CURRENT_MASK 0x3
130
131/* here 00-4mA, 01-8mA, 10-12mA, 11-16mA */
132#define GPIO1_PADS_31_28_SHIFT 28
133#define GPIO0_PADS_31_16_SHIFT 26
134#define GPIO0_PADS_15_0_SHIFT 24
135#define PCI_AND_EXT_RESET_PADS_SHIFT 22
136#define IDE_PADS_SHIFT 20
137#define GMAC1_PADS_SHIFT 18
138#define GMAC0_PADS_SHIFT 16
139/* DRAM is not in mA and poorly documented */
140#define DRAM_CLOCK_PADS_SHIFT 8
141#define DRAM_DATA_PADS_SHIFT 4
142#define DRAM_CONTROL_PADS_SHIFT 0
143
144/* Global IO Pad Slew Rate Control Register */
145#define GLOBAL_IO_SLEW_RATE_CTRL 0x14
146
147#define GPIO1_PADS_31_28_SLOW (1 << 10)
148#define GPIO0_PADS_31_16_SLOW (1 << 9)
149#define GPIO0_PADS_15_0_SLOW (1 << 8)
150#define PCI_PADS_SLOW (1 << 7)
151#define IDE_PADS_SLOW (1 << 6)
152#define GMAC1_PADS_SLOW (1 << 5)
153#define GMAC0_PADS_SLOW (1 << 4)
154#define DRAM_CLOCK_PADS_SLOW (1 << 1)
155#define DRAM_IO_PADS_SLOW (1 << 0)
156
157/*
158 * General skew control defines
159 * 16 steps, each step is around 0.2ns
160 */
161#define SKEW_MASK 0xF
162
163/* Global IDE PAD Skew Control Register */
164#define GLOBAL_IDE_SKEW_CTRL 0x18
165
166#define IDE1_HOST_STROBE_DELAY_SHIFT 28
167#define IDE1_DEVICE_STROBE_DELAY_SHIFT 24
168#define IDE1_OUTPUT_IO_SKEW_SHIFT 20
169#define IDE1_INPUT_IO_SKEW_SHIFT 16
170#define IDE0_HOST_STROBE_DELAY_SHIFT 12
171#define IDE0_DEVICE_STROBE_DELAY_SHIFT 8
172#define IDE0_OUTPUT_IO_SKEW_SHIFT 4
173#define IDE0_INPUT_IO_SKEW_SHIFT 0
174
175/* Global GMAC Control Pad Skew Control Register */
176#define GLOBAL_GMAC_CTRL_SKEW_CTRL 0x1C
177
178#define GMAC1_TXC_SKEW_SHIFT 28
179#define GMAC1_TXEN_SKEW_SHIFT 24
180#define GMAC1_RXC_SKEW_SHIFT 20
181#define GMAC1_RXDV_SKEW_SHIFT 16
182#define GMAC0_TXC_SKEW_SHIFT 12
183#define GMAC0_TXEN_SKEW_SHIFT 8
184#define GMAC0_RXC_SKEW_SHIFT 4
185#define GMAC0_RXDV_SKEW_SHIFT 0
186
187/* Global GMAC0 Data PAD Skew Control Register */
188#define GLOBAL_GMAC0_DATA_SKEW_CTRL 0x20
189/* Global GMAC1 Data PAD Skew Control Register */
190#define GLOBAL_GMAC1_DATA_SKEW_CTRL 0x24
191
192#define GMAC_TXD_SKEW_SHIFT(x) (((x) * 4) + 16)
193#define GMAC_RXD_SKEW_SHIFT(x) ((x) * 4)
194
195/* CPU has two AHB busses. */
196
197/* Global Arbitration0 Control Register */
198#define GLOBAL_ARBITRATION0_CTRL 0x28
199
200#define BOOT_CONTROLLER_HIGH_PRIO (1 << 3)
201#define DMA_BUS1_HIGH_PRIO (1 << 2)
202#define CPU0_HIGH_PRIO (1 << 0)
203
204/* Global Arbitration1 Control Register */
205#define GLOBAL_ARBITRATION1_CTRL 0x2C
206
207#define TVE_HIGH_PRIO (1 << 9)
208#define PCI_HIGH_PRIO (1 << 8)
209#define USB1_HIGH_PRIO (1 << 7)
210#define USB0_HIGH_PRIO (1 << 6)
211#define GMAC1_HIGH_PRIO (1 << 5)
212#define GMAC0_HIGH_PRIO (1 << 4)
213#define SECURITY_HIGH_PRIO (1 << 3)
214#define RAID_HIGH_PRIO (1 << 2)
215#define IDE_HIGH_PRIO (1 << 1)
216#define DMA_BUS2_HIGH_PRIO (1 << 0)
217
218/* Common bits for both arbitration registers */
219#define BURST_LENGTH_SHIFT 16
220#define BURST_LENGTH_MASK (0x3F << 16)
221
222/* Miscellaneous Control Register */
223#define GLOBAL_MISC_CTRL 0x30
224
225#define MEMORY_SPACE_SWAP (1 << 31)
226#define USB1_PLUG_MINIB (1 << 30) /* else plug is mini-A */
227#define USB0_PLUG_MINIB (1 << 29)
228#define GMAC_GMII (1 << 28)
229#define GMAC_1_ENABLE (1 << 27)
230/* TODO: define ATA/SATA bits */
231#define USB1_VBUS_ON (1 << 23)
232#define USB0_VBUS_ON (1 << 22)
233#define APB_CLKOUT_ENABLE (1 << 21)
234#define TVC_CLKOUT_ENABLE (1 << 20)
235#define EXT_CLKIN_ENABLE (1 << 19)
236#define PCI_66MHZ (1 << 18) /* else 33 MHz */
237#define PCI_CLKOUT_ENABLE (1 << 17)
238#define LPC_CLKOUT_ENABLE (1 << 16)
239#define USB1_WAKEUP_ON (1 << 15)
240#define USB0_WAKEUP_ON (1 << 14)
241/* TODO: define PCI idle detect bits */
242#define TVC_PADS_ENABLE (1 << 9)
243#define SSP_PADS_ENABLE (1 << 8)
244#define LCD_PADS_ENABLE (1 << 7)
245#define LPC_PADS_ENABLE (1 << 6)
246#define PCI_PADS_ENABLE (1 << 5)
247#define IDE_PADS_ENABLE (1 << 4)
248#define DRAM_PADS_POWER_DOWN (1 << 3)
249#define NAND_PADS_DISABLE (1 << 2)
250#define PFLASH_PADS_DISABLE (1 << 1)
251#define SFLASH_PADS_DISABLE (1 << 0)
252
253/* Global Clock Control Register */
254#define GLOBAL_CLOCK_CTRL 0x34
255
256#define POWER_STATE_G0 (1 << 31)
257#define POWER_STATE_S1 (1 << 30) /* else it is S3/S4 state */
258#define SECURITY_APB_AHB (1 << 29)
259/* else Security APB clk will be 0.75xAHB */
260/* TODO: TVC clock divider */
261#define PCI_CLKRUN_ENABLE (1 << 16)
262#define BOOT_CLK_DISABLE (1 << 13)
263#define TVC_CLK_DISABLE (1 << 12)
264#define FLASH_CLK_DISABLE (1 << 11)
265#define DDR_CLK_DISABLE (1 << 10)
266#define PCI_CLK_DISABLE (1 << 9)
267#define IDE_CLK_DISABLE (1 << 8)
268#define USB1_CLK_DISABLE (1 << 7)
269#define USB0_CLK_DISABLE (1 << 6)
270#define SATA1_CLK_DISABLE (1 << 5)
271#define SATA0_CLK_DISABLE (1 << 4)
272#define GMAC1_CLK_DISABLE (1 << 3)
273#define GMAC0_CLK_DISABLE (1 << 2)
274#define SECURITY_CLK_DISABLE (1 << 1)
275
276/* TODO: other registers definitions if needed */
277
278#endif /* __MACH_GLOBAL_REG_H */
diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h
deleted file mode 100644
index f0390f184742..000000000000
--- a/arch/arm/mach-gemini/include/mach/hardware.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * This file contains the hardware definitions for Gemini.
3 *
4 * Copyright (C) 2001-2006 Storlink, Corp.
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#ifndef __MACH_HARDWARE_H
13#define __MACH_HARDWARE_H
14
15/*
16 * Memory Map definitions
17 */
18#ifdef CONFIG_GEMINI_MEM_SWAP
19# define GEMINI_DRAM_BASE 0x00000000
20# define GEMINI_SRAM_BASE 0x70000000
21#else
22# define GEMINI_SRAM_BASE 0x00000000
23# define GEMINI_DRAM_BASE 0x10000000
24#endif
25#define GEMINI_FLASH_BASE 0x30000000
26#define GEMINI_GLOBAL_BASE 0x40000000
27#define GEMINI_WAQTCHDOG_BASE 0x41000000
28#define GEMINI_UART_BASE 0x42000000
29#define GEMINI_TIMER_BASE 0x43000000
30#define GEMINI_LCD_BASE 0x44000000
31#define GEMINI_RTC_BASE 0x45000000
32#define GEMINI_SATA_BASE 0x46000000
33#define GEMINI_LPC_HOST_BASE 0x47000000
34#define GEMINI_LPC_IO_BASE 0x47800000
35#define GEMINI_INTERRUPT_BASE 0x48000000
36/* TODO: Different interrupt controllers when SMP
37 * #define GEMINI_INTERRUPT0_BASE 0x48000000
38 * #define GEMINI_INTERRUPT1_BASE 0x49000000
39 */
40#define GEMINI_SSP_CTRL_BASE 0x4A000000
41#define GEMINI_POWER_CTRL_BASE 0x4B000000
42#define GEMINI_CIR_BASE 0x4C000000
43#define GEMINI_GPIO_BASE(x) (0x4D000000 + (x) * 0x1000000)
44#define GEMINI_PCI_IO_BASE 0x50000000
45#define GEMINI_PCI_MEM_BASE 0x58000000
46#define GEMINI_TOE_BASE 0x60000000
47#define GEMINI_GMAC0_BASE 0x6000A000
48#define GEMINI_GMAC1_BASE 0x6000E000
49#define GEMINI_SECURITY_BASE 0x62000000
50#define GEMINI_IDE0_BASE 0x63000000
51#define GEMINI_IDE1_BASE 0x63400000
52#define GEMINI_RAID_BASE 0x64000000
53#define GEMINI_FLASH_CTRL_BASE 0x65000000
54#define GEMINI_DRAM_CTRL_BASE 0x66000000
55#define GEMINI_GENERAL_DMA_BASE 0x67000000
56#define GEMINI_USB0_BASE 0x68000000
57#define GEMINI_USB1_BASE 0x69000000
58#define GEMINI_BIG_ENDIAN_BASE 0x80000000
59
60
61/*
62 * UART Clock when System clk is 150MHz
63 */
64#define UART_CLK 48000000
65
66/*
67 * macro to get at IO space when running virtually
68 */
69#define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
70
71#endif
diff --git a/arch/arm/mach-gemini/include/mach/irqs.h b/arch/arm/mach-gemini/include/mach/irqs.h
deleted file mode 100644
index 06bc47e77e8b..000000000000
--- a/arch/arm/mach-gemini/include/mach/irqs.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (C) 2001-2006 Storlink, Corp.
3 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef __MACH_IRQS_H__
12#define __MACH_IRQS_H__
13
14#define IRQ_SERIRQ1 31
15#define IRQ_SERIRQ0 30
16#define IRQ_PCID 29
17#define IRQ_PCIC 28
18#define IRQ_PCIB 27
19#define IRQ_PWR 26
20#define IRQ_CIR 25
21#define IRQ_GPIO(x) (22 + (x))
22#define IRQ_SSP 21
23#define IRQ_LPC 20
24#define IRQ_LCD 19
25#define IRQ_UART 18
26#define IRQ_RTC 17
27#define IRQ_TIMER3 16
28#define IRQ_TIMER2 15
29#define IRQ_TIMER1 14
30#define IRQ_FLASH 12
31#define IRQ_USB1 11
32#define IRQ_USB0 10
33#define IRQ_DMA 9
34#define IRQ_PCI 8
35#define IRQ_IPSEC 7
36#define IRQ_RAID 6
37#define IRQ_IDE1 5
38#define IRQ_IDE0 4
39#define IRQ_WATCHDOG 3
40#define IRQ_GMAC1 2
41#define IRQ_GMAC0 1
42#define IRQ_IPI 0
43
44#define NORMAL_IRQ_NUM 32
45
46#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
47#define GPIO_IRQ_NUM (3 * 32)
48
49#define ARCH_TIMER_IRQ IRQ_TIMER2
50
51#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
52
53#endif /* __MACH_IRQS_H__ */
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
deleted file mode 100644
index 02e225673acb..000000000000
--- a/arch/arm/mach-gemini/include/mach/uncompress.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
3 *
4 * Based on mach-pxa/include/mach/uncompress.h:
5 * Copyright: (C) 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef __MACH_UNCOMPRESS_H
14#define __MACH_UNCOMPRESS_H
15
16#include <linux/serial_reg.h>
17#include <mach/hardware.h>
18
19static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE;
20
21/*
22 * The following code assumes the serial port has already been
23 * initialized by the bootloader. If you didn't setup a port in
24 * your bootloader then nothing will appear (which might be desired).
25 */
26static inline void putc(char c)
27{
28 while (!(UART[UART_LSR] & UART_LSR_THRE))
29 barrier();
30 UART[UART_TX] = c;
31}
32
33static inline void flush(void)
34{
35}
36
37/*
38 * nothing to do
39 */
40#define arch_decomp_setup()
41
42#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
deleted file mode 100644
index d929b3ff18fd..000000000000
--- a/arch/arm/mach-gemini/irq.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Interrupt routines for Gemini
3 *
4 * Copyright (C) 2001-2006 Storlink, Corp.
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/stddef.h>
16#include <linux/list.h>
17#include <linux/sched.h>
18#include <linux/cpu.h>
19
20#include <asm/irq.h>
21#include <asm/mach/irq.h>
22#include <asm/system_misc.h>
23#include <mach/hardware.h>
24
25#define IRQ_SOURCE(base_addr) (base_addr + 0x00)
26#define IRQ_MASK(base_addr) (base_addr + 0x04)
27#define IRQ_CLEAR(base_addr) (base_addr + 0x08)
28#define IRQ_TMODE(base_addr) (base_addr + 0x0C)
29#define IRQ_TLEVEL(base_addr) (base_addr + 0x10)
30#define IRQ_STATUS(base_addr) (base_addr + 0x14)
31#define FIQ_SOURCE(base_addr) (base_addr + 0x20)
32#define FIQ_MASK(base_addr) (base_addr + 0x24)
33#define FIQ_CLEAR(base_addr) (base_addr + 0x28)
34#define FIQ_TMODE(base_addr) (base_addr + 0x2C)
35#define FIQ_LEVEL(base_addr) (base_addr + 0x30)
36#define FIQ_STATUS(base_addr) (base_addr + 0x34)
37
38static void gemini_ack_irq(struct irq_data *d)
39{
40 __raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
41}
42
43static void gemini_mask_irq(struct irq_data *d)
44{
45 unsigned int mask;
46
47 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
48 mask &= ~(1 << d->irq);
49 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
50}
51
52static void gemini_unmask_irq(struct irq_data *d)
53{
54 unsigned int mask;
55
56 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
57 mask |= (1 << d->irq);
58 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
59}
60
61static struct irq_chip gemini_irq_chip = {
62 .name = "INTC",
63 .irq_ack = gemini_ack_irq,
64 .irq_mask = gemini_mask_irq,
65 .irq_unmask = gemini_unmask_irq,
66};
67
68static struct resource irq_resource = {
69 .name = "irq_handler",
70 .start = GEMINI_INTERRUPT_BASE,
71 .end = FIQ_STATUS(GEMINI_INTERRUPT_BASE) + 4,
72};
73
74void __init gemini_init_irq(void)
75{
76 unsigned int i, mode = 0, level = 0;
77
78 /*
79 * Disable the idle handler by default since it is buggy
80 * For more info see arch/arm/mach-gemini/idle.c
81 */
82 cpu_idle_poll_ctrl(true);
83
84 request_resource(&iomem_resource, &irq_resource);
85
86 for (i = 0; i < NR_IRQS; i++) {
87 irq_set_chip(i, &gemini_irq_chip);
88 if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
89 irq_set_handler(i, handle_edge_irq);
90 mode |= 1 << i;
91 level |= 1 << i;
92 } else {
93 irq_set_handler(i, handle_level_irq);
94 }
95 irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
96 }
97
98 /* Disable all interrupts */
99 __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
100 __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
101
102 /* Set interrupt mode */
103 __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
104 __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
105}
diff --git a/arch/arm/mach-gemini/mm.c b/arch/arm/mach-gemini/mm.c
deleted file mode 100644
index 2c2cd284bb6a..000000000000
--- a/arch/arm/mach-gemini/mm.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * Static mappings for Gemini
3 *
4 * Copyright (C) 2001-2006 Storlink, Corp.
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/mm.h>
13#include <linux/init.h>
14
15#include <asm/mach/map.h>
16
17#include <mach/hardware.h>
18
19/* Page table mapping for I/O region */
20static struct map_desc gemini_io_desc[] __initdata = {
21 {
22 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GLOBAL_BASE),
23 .pfn =__phys_to_pfn(GEMINI_GLOBAL_BASE),
24 .length = SZ_512K,
25 .type = MT_DEVICE,
26 }, {
27 .virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
28 .pfn = __phys_to_pfn(GEMINI_UART_BASE),
29 .length = SZ_512K,
30 .type = MT_DEVICE,
31 }, {
32 .virtual = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE),
33 .pfn = __phys_to_pfn(GEMINI_TIMER_BASE),
34 .length = SZ_512K,
35 .type = MT_DEVICE,
36 }, {
37 .virtual = (unsigned long)IO_ADDRESS(GEMINI_INTERRUPT_BASE),
38 .pfn = __phys_to_pfn(GEMINI_INTERRUPT_BASE),
39 .length = SZ_512K,
40 .type = MT_DEVICE,
41 }, {
42 .virtual = (unsigned long)IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
43 .pfn = __phys_to_pfn(GEMINI_POWER_CTRL_BASE),
44 .length = SZ_512K,
45 .type = MT_DEVICE,
46 }, {
47 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(0)),
48 .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(0)),
49 .length = SZ_512K,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(1)),
53 .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(1)),
54 .length = SZ_512K,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(2)),
58 .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(2)),
59 .length = SZ_512K,
60 .type = MT_DEVICE,
61 }, {
62 .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
63 .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
64 .length = SZ_512K,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = (unsigned long)IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
68 .pfn = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE),
69 .length = SZ_512K,
70 .type = MT_DEVICE,
71 }, {
72 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
73 .pfn = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE),
74 .length = SZ_512K,
75 .type = MT_DEVICE,
76 },
77};
78
79void __init gemini_map_io(void)
80{
81 iotable_init(gemini_io_desc, ARRAY_SIZE(gemini_io_desc));
82}
diff --git a/arch/arm/mach-gemini/reset.c b/arch/arm/mach-gemini/reset.c
deleted file mode 100644
index 21a6d6d4f9c4..000000000000
--- a/arch/arm/mach-gemini/reset.c
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2001-2006 Storlink, Corp.
3 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10#ifndef __MACH_SYSTEM_H
11#define __MACH_SYSTEM_H
12
13#include <linux/io.h>
14#include <mach/hardware.h>
15#include <mach/global_reg.h>
16
17#include "common.h"
18
19void gemini_restart(enum reboot_mode mode, const char *cmd)
20{
21 __raw_writel(RESET_GLOBAL | RESET_CPU1,
22 IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
23}
24
25#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
deleted file mode 100644
index f5f18df5aacd..000000000000
--- a/arch/arm/mach-gemini/time.c
+++ /dev/null
@@ -1,239 +0,0 @@
1/*
2 * Copyright (C) 2001-2006 Storlink, Corp.
3 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <linux/io.h>
13#include <mach/hardware.h>
14#include <mach/global_reg.h>
15#include <asm/mach/time.h>
16#include <linux/clockchips.h>
17#include <linux/clocksource.h>
18#include <linux/sched_clock.h>
19
20/*
21 * Register definitions for the timers
22 */
23
24#define TIMER1_BASE GEMINI_TIMER_BASE
25#define TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
26#define TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
27
28#define TIMER_COUNT(BASE) (IO_ADDRESS(BASE) + 0x00)
29#define TIMER_LOAD(BASE) (IO_ADDRESS(BASE) + 0x04)
30#define TIMER_MATCH1(BASE) (IO_ADDRESS(BASE) + 0x08)
31#define TIMER_MATCH2(BASE) (IO_ADDRESS(BASE) + 0x0C)
32#define TIMER_CR (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x30)
33#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34)
34#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38)
35
36#define TIMER_1_CR_ENABLE (1 << 0)
37#define TIMER_1_CR_CLOCK (1 << 1)
38#define TIMER_1_CR_INT (1 << 2)
39#define TIMER_2_CR_ENABLE (1 << 3)
40#define TIMER_2_CR_CLOCK (1 << 4)
41#define TIMER_2_CR_INT (1 << 5)
42#define TIMER_3_CR_ENABLE (1 << 6)
43#define TIMER_3_CR_CLOCK (1 << 7)
44#define TIMER_3_CR_INT (1 << 8)
45#define TIMER_1_CR_UPDOWN (1 << 9)
46#define TIMER_2_CR_UPDOWN (1 << 10)
47#define TIMER_3_CR_UPDOWN (1 << 11)
48#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
49 TIMER_3_CR_ENABLE | \
50 TIMER_3_CR_UPDOWN)
51
52#define TIMER_1_INT_MATCH1 (1 << 0)
53#define TIMER_1_INT_MATCH2 (1 << 1)
54#define TIMER_1_INT_OVERFLOW (1 << 2)
55#define TIMER_2_INT_MATCH1 (1 << 3)
56#define TIMER_2_INT_MATCH2 (1 << 4)
57#define TIMER_2_INT_OVERFLOW (1 << 5)
58#define TIMER_3_INT_MATCH1 (1 << 6)
59#define TIMER_3_INT_MATCH2 (1 << 7)
60#define TIMER_3_INT_OVERFLOW (1 << 8)
61#define TIMER_INT_ALL_MASK 0x1ff
62
63
64static unsigned int tick_rate;
65
66static u64 notrace gemini_read_sched_clock(void)
67{
68 return readl(TIMER_COUNT(TIMER3_BASE));
69}
70
71static int gemini_timer_set_next_event(unsigned long cycles,
72 struct clock_event_device *evt)
73{
74 u32 cr;
75
76 /* Setup the match register */
77 cr = readl(TIMER_COUNT(TIMER1_BASE));
78 writel(cr + cycles, TIMER_MATCH1(TIMER1_BASE));
79 if (readl(TIMER_COUNT(TIMER1_BASE)) - cr > cycles)
80 return -ETIME;
81
82 return 0;
83}
84
85static int gemini_timer_shutdown(struct clock_event_device *evt)
86{
87 u32 cr;
88
89 /*
90 * Disable also for oneshot: the set_next() call will arm the timer
91 * instead.
92 */
93 /* Stop timer and interrupt. */
94 cr = readl(TIMER_CR);
95 cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
96 writel(cr, TIMER_CR);
97
98 /* Setup counter start from 0 */
99 writel(0, TIMER_COUNT(TIMER1_BASE));
100 writel(0, TIMER_LOAD(TIMER1_BASE));
101
102 /* enable interrupt */
103 cr = readl(TIMER_INTR_MASK);
104 cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
105 cr |= TIMER_1_INT_MATCH1;
106 writel(cr, TIMER_INTR_MASK);
107
108 /* start the timer */
109 cr = readl(TIMER_CR);
110 cr |= TIMER_1_CR_ENABLE;
111 writel(cr, TIMER_CR);
112
113 return 0;
114}
115
116static int gemini_timer_set_periodic(struct clock_event_device *evt)
117{
118 u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
119 u32 cr;
120
121 /* Stop timer and interrupt */
122 cr = readl(TIMER_CR);
123 cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
124 writel(cr, TIMER_CR);
125
126 /* Setup timer to fire at 1/HT intervals. */
127 cr = 0xffffffff - (period - 1);
128 writel(cr, TIMER_COUNT(TIMER1_BASE));
129 writel(cr, TIMER_LOAD(TIMER1_BASE));
130
131 /* enable interrupt on overflow */
132 cr = readl(TIMER_INTR_MASK);
133 cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
134 cr |= TIMER_1_INT_OVERFLOW;
135 writel(cr, TIMER_INTR_MASK);
136
137 /* Start the timer */
138 cr = readl(TIMER_CR);
139 cr |= TIMER_1_CR_ENABLE;
140 cr |= TIMER_1_CR_INT;
141 writel(cr, TIMER_CR);
142
143 return 0;
144}
145
146/* Use TIMER1 as clock event */
147static struct clock_event_device gemini_clockevent = {
148 .name = "TIMER1",
149 /* Reasonably fast and accurate clock event */
150 .rating = 300,
151 .shift = 32,
152 .features = CLOCK_EVT_FEAT_PERIODIC |
153 CLOCK_EVT_FEAT_ONESHOT,
154 .set_next_event = gemini_timer_set_next_event,
155 .set_state_shutdown = gemini_timer_shutdown,
156 .set_state_periodic = gemini_timer_set_periodic,
157 .set_state_oneshot = gemini_timer_shutdown,
158 .tick_resume = gemini_timer_shutdown,
159};
160
161/*
162 * IRQ handler for the timer
163 */
164static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
165{
166 struct clock_event_device *evt = &gemini_clockevent;
167
168 evt->event_handler(evt);
169 return IRQ_HANDLED;
170}
171
172static struct irqaction gemini_timer_irq = {
173 .name = "Gemini Timer Tick",
174 .flags = IRQF_TIMER,
175 .handler = gemini_timer_interrupt,
176};
177
178/*
179 * Set up timer interrupt, and return the current time in seconds.
180 */
181void __init gemini_timer_init(void)
182{
183 u32 reg_v;
184
185 reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS));
186 tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000;
187
188 printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000);
189
190 tick_rate /= 6; /* APB bus run AHB*(1/6) */
191
192 switch(reg_v & CPU_AHB_RATIO_MASK) {
193 case CPU_AHB_1_1:
194 printk(KERN_CONT "(1/1)\n");
195 break;
196 case CPU_AHB_3_2:
197 printk(KERN_CONT "(3/2)\n");
198 break;
199 case CPU_AHB_24_13:
200 printk(KERN_CONT "(24/13)\n");
201 break;
202 case CPU_AHB_2_1:
203 printk(KERN_CONT "(2/1)\n");
204 break;
205 }
206
207 /*
208 * Reset the interrupt mask and status
209 */
210 writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK);
211 writel(0, TIMER_INTR_STATE);
212 writel(TIMER_DEFAULT_FLAGS, TIMER_CR);
213
214 /*
215 * Setup free-running clocksource timer (interrupts
216 * disabled.)
217 */
218 writel(0, TIMER_COUNT(TIMER3_BASE));
219 writel(0, TIMER_LOAD(TIMER3_BASE));
220 writel(0, TIMER_MATCH1(TIMER3_BASE));
221 writel(0, TIMER_MATCH2(TIMER3_BASE));
222 clocksource_mmio_init(TIMER_COUNT(TIMER3_BASE),
223 "gemini_clocksource", tick_rate,
224 300, 32, clocksource_mmio_readl_up);
225 sched_clock_register(gemini_read_sched_clock, 32, tick_rate);
226
227 /*
228 * Setup clockevent timer (interrupt-driven.)
229 */
230 writel(0, TIMER_COUNT(TIMER1_BASE));
231 writel(0, TIMER_LOAD(TIMER1_BASE));
232 writel(0, TIMER_MATCH1(TIMER1_BASE));
233 writel(0, TIMER_MATCH2(TIMER1_BASE));
234 setup_irq(IRQ_TIMER1, &gemini_timer_irq);
235 gemini_clockevent.cpumask = cpumask_of(0);
236 clockevents_config_and_register(&gemini_clockevent, tick_rate,
237 1, 0xffffffff);
238
239}
diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
index a6c117622d67..f66815c3dd07 100644
--- a/arch/arm/mach-hisi/platmcpm.c
+++ b/arch/arm/mach-hisi/platmcpm.c
@@ -279,6 +279,8 @@ static int __init hip04_smp_init(void)
279 &hip04_boot_method[0], 4); 279 &hip04_boot_method[0], 4);
280 if (ret) 280 if (ret)
281 goto err; 281 goto err;
282
283 ret = -ENODEV;
282 np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); 284 np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
283 if (!np_sctl) 285 if (!np_sctl)
284 goto err; 286 goto err;
diff --git a/arch/arm/mach-imx/mach-imx25.c b/arch/arm/mach-imx/mach-imx25.c
index 32dcb5e99e23..353b86e3808f 100644
--- a/arch/arm/mach-imx/mach-imx25.c
+++ b/arch/arm/mach-imx/mach-imx25.c
@@ -23,6 +23,11 @@ static void __init imx25_init_early(void)
23 mxc_set_cpu_type(MXC_CPU_MX25); 23 mxc_set_cpu_type(MXC_CPU_MX25);
24} 24}
25 25
26static void __init imx25_dt_init(void)
27{
28 imx_aips_allow_unprivileged_access("fsl,imx25-aips");
29}
30
26static void __init mx25_init_irq(void) 31static void __init mx25_init_irq(void)
27{ 32{
28 struct device_node *np; 33 struct device_node *np;
@@ -41,6 +46,7 @@ static const char * const imx25_dt_board_compat[] __initconst = {
41 46
42DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") 47DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
43 .init_early = imx25_init_early, 48 .init_early = imx25_init_early,
49 .init_machine = imx25_dt_init,
44 .init_late = imx25_pm_init, 50 .init_late = imx25_pm_init,
45 .init_irq = mx25_init_irq, 51 .init_irq = mx25_init_irq,
46 .dt_compat = imx25_dt_board_compat, 52 .dt_compat = imx25_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 558e5f8589cb..68c3f0799d5b 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -375,6 +375,8 @@ static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
375 375
376/* SPI */ 376/* SPI */
377static int spi0_internal_chipselect[] = { 377static int spi0_internal_chipselect[] = {
378 MXC_SPI_CS(0),
379 MXC_SPI_CS(1),
378 MXC_SPI_CS(2), 380 MXC_SPI_CS(2),
379}; 381};
380 382
@@ -385,6 +387,7 @@ static const struct spi_imx_master spi0_pdata __initconst = {
385 387
386static int spi1_internal_chipselect[] = { 388static int spi1_internal_chipselect[] = {
387 MXC_SPI_CS(0), 389 MXC_SPI_CS(0),
390 MXC_SPI_CS(1),
388 MXC_SPI_CS(2), 391 MXC_SPI_CS(2),
389}; 392};
390 393
@@ -398,7 +401,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
398 .modalias = "mc13783", 401 .modalias = "mc13783",
399 .max_speed_hz = 1000000, 402 .max_speed_hz = 1000000,
400 .bus_num = 1, 403 .bus_num = 1,
401 .chip_select = 1, /* SS2 */ 404 .chip_select = 2, /* SS2 */
402 .platform_data = &mc13783_pdata, 405 .platform_data = &mc13783_pdata,
403 /* irq number is run-time assigned */ 406 /* irq number is run-time assigned */
404 .mode = SPI_CS_HIGH, 407 .mode = SPI_CS_HIGH,
@@ -406,7 +409,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
406 .modalias = "l4f00242t03", 409 .modalias = "l4f00242t03",
407 .max_speed_hz = 5000000, 410 .max_speed_hz = 5000000,
408 .bus_num = 0, 411 .bus_num = 0,
409 .chip_select = 0, /* SS2 */ 412 .chip_select = 2, /* SS2 */
410 .platform_data = &mx31_3ds_l4f00242t03_pdata, 413 .platform_data = &mx31_3ds_l4f00242t03_pdata,
411 }, 414 },
412}; 415};
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index cc867682520e..bde9a9af6714 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -296,14 +296,14 @@ static struct spi_board_info moboard_spi_board_info[] __initdata = {
296 /* irq number is run-time assigned */ 296 /* irq number is run-time assigned */
297 .max_speed_hz = 300000, 297 .max_speed_hz = 300000,
298 .bus_num = 1, 298 .bus_num = 1,
299 .chip_select = 0, 299 .chip_select = 1,
300 .platform_data = &moboard_pmic, 300 .platform_data = &moboard_pmic,
301 .mode = SPI_CS_HIGH, 301 .mode = SPI_CS_HIGH,
302 }, 302 },
303}; 303};
304 304
305static int moboard_spi2_cs[] = { 305static int moboard_spi2_cs[] = {
306 MXC_SPI_CS(1), 306 MXC_SPI_CS(0), MXC_SPI_CS(1),
307}; 307};
308 308
309static const struct spi_imx_master moboard_spi2_pdata __initconst = { 309static const struct spi_imx_master moboard_spi2_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index 8fd8255068ee..95bd97710494 100644
--- a/arch/arm/mach-imx/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -50,13 +50,13 @@ static struct spi_board_info pcm037_spi_dev[] = {
50 .modalias = "dac124s085", 50 .modalias = "dac124s085",
51 .max_speed_hz = 400000, 51 .max_speed_hz = 400000,
52 .bus_num = 0, 52 .bus_num = 0,
53 .chip_select = 0, /* Index in pcm037_spi1_cs[] */ 53 .chip_select = 1, /* Index in pcm037_spi1_cs[] */
54 .mode = SPI_CPHA, 54 .mode = SPI_CPHA,
55 }, 55 },
56}; 56};
57 57
58/* Platform Data for MXC CSPI */ 58/* Platform Data for MXC CSPI */
59static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)}; 59static int pcm037_spi1_cs[] = { MXC_SPI_CS(0), MXC_SPI_CS(1), };
60 60
61static const struct spi_imx_master pcm037_spi1_pdata __initconst = { 61static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
62 .chipselect = pcm037_spi1_cs, 62 .chipselect = pcm037_spi1_cs,
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index c03bf28d8bbc..78262899a590 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -1,4 +1,5 @@
1/* 1/*
2 * Copyright 2017 NXP
2 * Copyright 2011,2016 Freescale Semiconductor, Inc. 3 * Copyright 2011,2016 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 4 * Copyright 2011 Linaro Ltd.
4 * 5 *
@@ -47,6 +48,7 @@
47#define PROFILE_SEL 0x10 48#define PROFILE_SEL 0x10
48 49
49#define MMDC_MADPCR0 0x410 50#define MMDC_MADPCR0 0x410
51#define MMDC_MADPCR1 0x414
50#define MMDC_MADPSR0 0x418 52#define MMDC_MADPSR0 0x418
51#define MMDC_MADPSR1 0x41C 53#define MMDC_MADPSR1 0x41C
52#define MMDC_MADPSR2 0x420 54#define MMDC_MADPSR2 0x420
@@ -57,6 +59,7 @@
57#define MMDC_NUM_COUNTERS 6 59#define MMDC_NUM_COUNTERS 6
58 60
59#define MMDC_FLAG_PROFILE_SEL 0x1 61#define MMDC_FLAG_PROFILE_SEL 0x1
62#define MMDC_PRF_AXI_ID_CLEAR 0x0
60 63
61#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) 64#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
62 65
@@ -87,7 +90,7 @@ static DEFINE_IDA(mmdc_ida);
87PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00") 90PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
88PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01") 91PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
89PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02") 92PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
90PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "config=0x03") 93PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
91PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04") 94PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
92PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB"); 95PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
93PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001"); 96PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
@@ -161,8 +164,11 @@ static struct attribute_group mmdc_pmu_events_attr_group = {
161}; 164};
162 165
163PMU_FORMAT_ATTR(event, "config:0-63"); 166PMU_FORMAT_ATTR(event, "config:0-63");
167PMU_FORMAT_ATTR(axi_id, "config1:0-63");
168
164static struct attribute *mmdc_pmu_format_attrs[] = { 169static struct attribute *mmdc_pmu_format_attrs[] = {
165 &format_attr_event.attr, 170 &format_attr_event.attr,
171 &format_attr_axi_id.attr,
166 NULL, 172 NULL,
167}; 173};
168 174
@@ -345,6 +351,14 @@ static void mmdc_pmu_event_start(struct perf_event *event, int flags)
345 351
346 writel(DBG_RST, reg); 352 writel(DBG_RST, reg);
347 353
354 /*
355 * Write the AXI id parameter to MADPCR1.
356 */
357 val = event->attr.config1;
358 reg = mmdc_base + MMDC_MADPCR1;
359 writel(val, reg);
360
361 reg = mmdc_base + MMDC_MADPCR0;
348 val = DBG_EN; 362 val = DBG_EN;
349 if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL) 363 if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)
350 val |= PROFILE_SEL; 364 val |= PROFILE_SEL;
@@ -382,6 +396,10 @@ static void mmdc_pmu_event_stop(struct perf_event *event, int flags)
382 reg = mmdc_base + MMDC_MADPCR0; 396 reg = mmdc_base + MMDC_MADPCR0;
383 397
384 writel(PRF_FRZ, reg); 398 writel(PRF_FRZ, reg);
399
400 reg = mmdc_base + MMDC_MADPCR1;
401 writel(MMDC_PRF_AXI_ID_CLEAR, reg);
402
385 mmdc_pmu_event_update(event); 403 mmdc_pmu_event_update(event);
386} 404}
387 405
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index e4f21086b42b..1c6062d240c8 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -419,7 +419,8 @@ static void __init mxs_machine_init(void)
419 crystalfontz_init(); 419 crystalfontz_init();
420 else if (of_machine_is_compatible("eukrea,mbmx283lc")) 420 else if (of_machine_is_compatible("eukrea,mbmx283lc"))
421 eukrea_mbmx283lc_init(); 421 eukrea_mbmx283lc_init();
422 else if (of_machine_is_compatible("i2se,duckbill")) 422 else if (of_machine_is_compatible("i2se,duckbill") ||
423 of_machine_is_compatible("i2se,duckbill-2"))
423 duckbill_init(); 424 duckbill_init();
424 else if (of_machine_is_compatible("msr,m28cu3")) 425 else if (of_machine_is_compatible("msr,m28cu3"))
425 m28cu3_init(); 426 m28cu3_init();
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index ee5460b8ec2e..f1135bf8940e 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -581,7 +581,6 @@ static int omap_pm_enter(suspend_state_t state)
581{ 581{
582 switch (state) 582 switch (state)
583 { 583 {
584 case PM_SUSPEND_STANDBY:
585 case PM_SUSPEND_MEM: 584 case PM_SUSPEND_MEM:
586 omap1_pm_suspend(); 585 omap1_pm_suspend();
587 break; 586 break;
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 3b5fb05ae701..65fbd136b20c 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -91,6 +91,14 @@ static struct clockdomain default_l3_slow_81xx_clkdm = {
91 .flags = CLKDM_CAN_SWSUP, 91 .flags = CLKDM_CAN_SWSUP,
92}; 92};
93 93
94static struct clockdomain default_sata_81xx_clkdm = {
95 .name = "default_clkdm",
96 .pwrdm = { .name = "default_pwrdm" },