aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson2017-04-19 08:33:14 -0500
committerOlof Johansson2017-04-19 08:33:14 -0500
commitb42f45558e77724cb53e8885b26596ffa4f71434 (patch)
tree545d098bf5ca38d967c132506922c54d9810eff2
parent13ed63b6cbdf3b99abf47fd92325a18dc6282152 (diff)
parentf006aaf7b11230e38a35f09d706e751fa77eb799 (diff)
downloadkernel-b42f45558e77724cb53e8885b26596ffa4f71434.tar.gz
kernel-b42f45558e77724cb53e8885b26596ffa4f71434.tar.xz
kernel-b42f45558e77724cb53e8885b26596ffa4f71434.zip
Merge tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
ZTE arm64 device tree updates for 4.12: - Add mmc devices for ZX296718 SoC and enable those available on zx296718-evb board. - Add VOU controller device, output devices HDMI and TVENC, and enable display support for zx296718-evb board. - Remove pll_vga clock from ZX296718 device tree, as it's not a fixed rate clock. * tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: zte: add tvenc device for zx296718 arm64: dts: zte: add vou and hdmi devices for zx296718 arm64: dts: zte: add mmc devices for zx296718 arm64: dts: zte: remove zx296718 pll_vga clock Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm64/boot/dts/zte/zx296718-evb.dts28
-rw-r--r--arch/arm64/boot/dts/zte/zx296718.dtsi126
2 files changed, 147 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts
index e164ff6de5fc..bb900d2bbcfb 100644
--- a/arch/arm64/boot/dts/zte/zx296718-evb.dts
+++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts
@@ -57,6 +57,34 @@
57 reg = <0x40000000 0x40000000>; 57 reg = <0x40000000 0x40000000>;
58 }; 58 };
59 59
60 sound0 {
61 compatible = "simple-audio-card";
62 simple-audio-card,name = "zx_snd_spdif0";
63
64 simple-audio-card,cpu {
65 sound-dai = <&spdif0>;
66 };
67
68 simple-audio-card,codec {
69 sound-dai = <&hdmi>;
70 };
71 };
72};
73
74&emmc {
75 status = "okay";
76};
77
78&hdmi {
79 status = "okay";
80};
81
82&sd1 {
83 status = "okay";
84};
85
86&spdif0 {
87 status = "okay";
60}; 88};
61 89
62&uart0 { 90&uart0 {
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index b850b2cd0adc..316dc713268c 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -235,13 +235,6 @@
235 clock-output-names = "pll_mac"; 235 clock-output-names = "pll_mac";
236 }; 236 };
237 237
238 pll_vga: clk-pll-1073m {
239 compatible = "fixed-clock";
240 #clock-cells = <0>;
241 clock-frequency = <1073000000>;
242 clock-output-names = "pll_vga";
243 };
244
245 pll_mm0: clk-pll-1188m { 238 pll_mm0: clk-pll-1188m {
246 compatible = "fixed-clock"; 239 compatible = "fixed-clock";
247 #clock-cells = <0>; 240 #clock-cells = <0>;
@@ -305,6 +298,51 @@
305 status = "disabled"; 298 status = "disabled";
306 }; 299 };
307 300
301 sd0: mmc@1110000 {
302 compatible = "zte,zx296718-dw-mshc";
303 #address-cells = <1>;
304 #size-cells = <0>;
305 reg = <0x01110000 0x1000>;
306 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
307 fifo-depth = <32>;
308 data-addr = <0x200>;
309 fifo-watermark-aligned;
310 bus-width = <4>;
311 clock-frequency = <50000000>;
312 clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
313 clock-names = "biu", "ciu";
314 num-slots = <1>;
315 max-frequency = <50000000>;
316 cap-sdio-irq;
317 cap-sd-highspeed;
318 sd-uhs-sdr12;
319 sd-uhs-sdr25;
320 sd-uhs-sdr50;
321 sd-uhs-sdr104;
322 sd-uhs-ddr50;
323 status = "disabled";
324 };
325
326 sd1: mmc@1111000 {
327 compatible = "zte,zx296718-dw-mshc";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 reg = <0x01111000 0x1000>;
331 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
332 fifo-depth = <32>;
333 data-addr = <0x200>;
334 fifo-watermark-aligned;
335 bus-width = <4>;
336 clock-frequency = <167000000>;
337 clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
338 clock-names = "biu", "ciu";
339 num-slots = <1>;
340 max-frequency = <167000000>;
341 cap-sdio-irq;
342 cap-sd-highspeed;
343 status = "disabled";
344 };
345
308 dma: dma-controller@1460000 { 346 dma: dma-controller@1460000 {
309 compatible = "zte,zx296702-dma"; 347 compatible = "zte,zx296702-dma";
310 reg = <0x01460000 0x1000>; 348 reg = <0x01460000 0x1000>;
@@ -328,6 +366,47 @@
328 #clock-cells = <1>; 366 #clock-cells = <1>;
329 }; 367 };
330 368
369 vou: vou@1440000 {
370 compatible = "zte,zx296718-vou";
371 #address-cells = <1>;
372 #size-cells = <1>;
373 ranges = <0 0x1440000 0x10000>;
374
375 dpc: dpc@0 {
376 compatible = "zte,zx296718-dpc";
377 reg = <0x0000 0x1000>, <0x1000 0x1000>,
378 <0x5000 0x1000>, <0x6000 0x1000>,
379 <0xa000 0x1000>;
380 reg-names = "osd", "timing_ctrl",
381 "dtrc", "vou_ctrl",
382 "otfppu";
383 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
385 <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
386 clock-names = "aclk", "ppu_wclk",
387 "main_wclk", "aux_wclk";
388 };
389
390 hdmi: hdmi@c000 {
391 compatible = "zte,zx296718-hdmi";
392 reg = <0xc000 0x4000>;
393 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
394 clocks = <&topcrm HDMI_OSC_CEC>,
395 <&topcrm HDMI_OSC_CLK>,
396 <&topcrm HDMI_XCLK>;
397 clock-names = "osc_cec", "osc_clk", "xclk";
398 #sound-dai-cells = <0>;
399 status = "disabled";
400 };
401
402 tvenc: tvenc@2000 {
403 compatible = "zte,zx296718-tvenc";
404 reg = <0x2000 0x1000>;
405 zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
406 status = "disabled";
407 };
408 };
409
331 topcrm: clock-controller@1461000 { 410 topcrm: clock-controller@1461000 {
332 compatible = "zte,zx296718-topcrm"; 411 compatible = "zte,zx296718-topcrm";
333 reg = <0x01461000 0x1000>; 412 reg = <0x01461000 0x1000>;
@@ -339,10 +418,43 @@
339 reg = <0x1463000 0x1000>; 418 reg = <0x1463000 0x1000>;
340 }; 419 };
341 420
421 emmc: mmc@1470000{
422 compatible = "zte,zx296718-dw-mshc";
423 reg = <0x01470000 0x1000>;
424 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
425 zte,aon-syscon = <&aon_sysctrl>;
426 bus-width = <8>;
427 fifo-depth = <128>;
428 data-addr = <0x200>;
429 fifo-watermark-aligned;
430 clock-frequency = <167000000>;
431 clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
432 clock-names = "biu", "ciu";
433 max-frequency = <167000000>;
434 cap-mmc-highspeed;
435 mmc-ddr-1_8v;
436 mmc-hs200-1_8v;
437 non-removable;
438 disable-wp;
439 status = "disabled";
440 };
441
342 audiocrm: clock-controller@1480000 { 442 audiocrm: clock-controller@1480000 {
343 compatible = "zte,zx296718-audiocrm"; 443 compatible = "zte,zx296718-audiocrm";
344 reg = <0x01480000 0x1000>; 444 reg = <0x01480000 0x1000>;
345 #clock-cells = <1>; 445 #clock-cells = <1>;
346 }; 446 };
447
448 spdif0: spdif@1488000 {
449 compatible = "zte,zx296702-spdif";
450 reg = <0x1488000 0x1000>;
451 clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
452 clock-names = "tx";
453 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
454 #sound-dai-cells = <0>;
455 dmas = <&dma 30>;
456 dma-names = "tx";
457 status = "disabled";
458 };
347 }; 459 };
348}; 460};