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author | Wei Xu | 2017-03-28 10:40:40 -0500 |
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committer | Wei Xu | 2017-04-08 00:43:45 -0500 |
commit | 86d67897f937000dd13ca9e81e3130adecdf45a0 (patch) | |
tree | 1d35511459b430b6011f0e6b8cd66470581a2cca /arch | |
parent | 0f57c6c9cda8e593d6cbdd0fc93ea51084024f2d (diff) | |
download | kernel-86d67897f937000dd13ca9e81e3130adecdf45a0.tar.gz kernel-86d67897f937000dd13ca9e81e3130adecdf45a0.tar.xz kernel-86d67897f937000dd13ca9e81e3130adecdf45a0.zip |
arm64: dts: hisi: add SAS nodes for the hip07 SoC
Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip07.dtsi | 129 |
1 files changed, 129 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index bc54b61e52c7..283d7b532e16 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi | |||
@@ -1127,6 +1127,11 @@ | |||
1127 | reg = <0x0 0xc0000000 0x0 0x10000>; | 1127 | reg = <0x0 0xc0000000 0x0 0x10000>; |
1128 | }; | 1128 | }; |
1129 | 1129 | ||
1130 | pcie_subctl: pcie_subctl@a0000000 { | ||
1131 | compatible = "hisilicon,pcie-sas-subctrl", "syscon"; | ||
1132 | reg = <0x0 0xa0000000 0x0 0x10000>; | ||
1133 | }; | ||
1134 | |||
1130 | serdes_ctrl: sds_ctrl@c2200000 { | 1135 | serdes_ctrl: sds_ctrl@c2200000 { |
1131 | compatible = "syscon"; | 1136 | compatible = "syscon"; |
1132 | reg = <0 0xc2200000 0x0 0x80000>; | 1137 | reg = <0 0xc2200000 0x0 0x80000>; |
@@ -1405,5 +1410,129 @@ | |||
1405 | "hns-roce-async", | 1410 | "hns-roce-async", |
1406 | "hns-roce-common"; | 1411 | "hns-roce-common"; |
1407 | }; | 1412 | }; |
1413 | |||
1414 | sas0: sas@c3000000 { | ||
1415 | compatible = "hisilicon,hip07-sas-v2"; | ||
1416 | reg = <0 0xc3000000 0 0x10000>; | ||
1417 | sas-addr = [50 01 88 20 16 00 00 00]; | ||
1418 | hisilicon,sas-syscon = <&dsa_subctrl>; | ||
1419 | ctrl-reset-reg = <0xa60>; | ||
1420 | ctrl-reset-sts-reg = <0x5a30>; | ||
1421 | ctrl-clock-ena-reg = <0x338>; | ||
1422 | queue-count = <16>; | ||
1423 | phy-count = <8>; | ||
1424 | dma-coherent; | ||
1425 | interrupt-parent = <&mbigen_sas0>; | ||
1426 | interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, | ||
1427 | <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, | ||
1428 | <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, | ||
1429 | <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, | ||
1430 | <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, | ||
1431 | <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, | ||
1432 | <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, | ||
1433 | <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, | ||
1434 | <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, | ||
1435 | <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, | ||
1436 | <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, | ||
1437 | <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, | ||
1438 | <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, | ||
1439 | <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, | ||
1440 | <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, | ||
1441 | <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, | ||
1442 | <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, | ||
1443 | <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, | ||
1444 | <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, | ||
1445 | <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, | ||
1446 | <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, | ||
1447 | <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, | ||
1448 | <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, | ||
1449 | <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, | ||
1450 | <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, | ||
1451 | <630 1>,<631 1>,<632 1>; | ||
1452 | status = "disabled"; | ||
1453 | }; | ||
1454 | |||
1455 | sas1: sas@a2000000 { | ||
1456 | compatible = "hisilicon,hip07-sas-v2"; | ||
1457 | reg = <0 0xa2000000 0 0x10000>; | ||
1458 | sas-addr = [50 01 88 20 16 00 00 00]; | ||
1459 | hisilicon,sas-syscon = <&pcie_subctl>; | ||
1460 | hip06-sas-v2-quirk-amt; | ||
1461 | ctrl-reset-reg = <0xa18>; | ||
1462 | ctrl-reset-sts-reg = <0x5a0c>; | ||
1463 | ctrl-clock-ena-reg = <0x318>; | ||
1464 | queue-count = <16>; | ||
1465 | phy-count = <8>; | ||
1466 | dma-coherent; | ||
1467 | interrupt-parent = <&mbigen_sas1>; | ||
1468 | interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, | ||
1469 | <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, | ||
1470 | <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, | ||
1471 | <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, | ||
1472 | <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, | ||
1473 | <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, | ||
1474 | <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, | ||
1475 | <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, | ||
1476 | <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, | ||
1477 | <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, | ||
1478 | <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, | ||
1479 | <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, | ||
1480 | <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, | ||
1481 | <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, | ||
1482 | <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, | ||
1483 | <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, | ||
1484 | <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, | ||
1485 | <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, | ||
1486 | <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, | ||
1487 | <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, | ||
1488 | <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, | ||
1489 | <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, | ||
1490 | <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, | ||
1491 | <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, | ||
1492 | <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, | ||
1493 | <605 1>,<606 1>,<607 1>; | ||
1494 | status = "disabled"; | ||
1495 | }; | ||
1496 | |||
1497 | sas2: sas@a3000000 { | ||
1498 | compatible = "hisilicon,hip07-sas-v2"; | ||
1499 | reg = <0 0xa3000000 0 0x10000>; | ||
1500 | sas-addr = [50 01 88 20 16 00 00 00]; | ||
1501 | hisilicon,sas-syscon = <&pcie_subctl>; | ||
1502 | ctrl-reset-reg = <0xae0>; | ||
1503 | ctrl-reset-sts-reg = <0x5a70>; | ||
1504 | ctrl-clock-ena-reg = <0x3a8>; | ||
1505 | queue-count = <16>; | ||
1506 | phy-count = <9>; | ||
1507 | dma-coherent; | ||
1508 | interrupt-parent = <&mbigen_sas2>; | ||
1509 | interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, | ||
1510 | <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, | ||
1511 | <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, | ||
1512 | <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, | ||
1513 | <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, | ||
1514 | <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, | ||
1515 | <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, | ||
1516 | <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, | ||
1517 | <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, | ||
1518 | <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, | ||
1519 | <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, | ||
1520 | <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, | ||
1521 | <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, | ||
1522 | <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, | ||
1523 | <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, | ||
1524 | <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, | ||
1525 | <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, | ||
1526 | <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, | ||
1527 | <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, | ||
1528 | <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, | ||
1529 | <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, | ||
1530 | <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, | ||
1531 | <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, | ||
1532 | <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, | ||
1533 | <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, | ||
1534 | <637 1>,<638 1>,<639 1>; | ||
1535 | status = "disabled"; | ||
1536 | }; | ||
1408 | }; | 1537 | }; |
1409 | }; | 1538 | }; |