Merge tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux into next/drivers

Reset controller changes for v4.12

- make reset drivers with bool Kconfig options explicitly non-modular
- fix uniphier non-static symbol warnings
- fix socfpga nr_resets property
- new drivers for the Arria10 and i.MX7 system reset controllers
- fix sunxi 64-bit compilation

* tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux:
  reset: sunxi: fix for 64-bit compilation
  reset: Add Altera Arria10 SR Reset Controller
  dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets
  reset: Add i.MX7 SRC reset driver
  reset-socfpga: Fix nr_resets property
  reset: uniphier: fix non static symbol warnings
  reset: pistachio: make it explicitly non-modular
  reset: ath79: make it explicitly non-modular
  reset: oxnas: make it explicitly non-modular
  reset: meson: make it explicitly non-modular

Signed-off-by: Olof Johansson <olof@lixom.net>

2 files changed, 95 insertions, 0 deletions

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10sr.h b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h
new file mode 100644
index 000000000000..9855925e5256
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h
@@ -0,0 +1,33 @@
+/*
+ *  Copyright Intel Corporation (C) 2017. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from altr,rst-mgr-a10.h
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
+
+/* Peripheral PHY resets */
+#define A10SR_RESET_ENET_HPS    0
+#define A10SR_RESET_PCIE        1
+#define A10SR_RESET_FILE        2
+#define A10SR_RESET_BQSPI       3
+#define A10SR_RESET_USB         4
+
+#define A10SR_RESET_NUM         5
+
+#endif
diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h
new file mode 100644
index 000000000000..63948170c7b2
--- /dev/null
+++ b/include/dt-bindings/reset/imx7-reset.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2017 Impinj, Inc.
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_BINDING_RESET_IMX7_H
+#define DT_BINDING_RESET_IMX7_H
+
+#define IMX7_RESET_A7_CORE_POR_RESET0   0
+#define IMX7_RESET_A7_CORE_POR_RESET1   1
+#define IMX7_RESET_A7_CORE_RESET0       2
+#define IMX7_RESET_A7_CORE_RESET1       3
+#define IMX7_RESET_A7_DBG_RESET0        4
+#define IMX7_RESET_A7_DBG_RESET1        5
+#define IMX7_RESET_A7_ETM_RESET0        6
+#define IMX7_RESET_A7_ETM_RESET1        7
+#define IMX7_RESET_A7_SOC_DBG_RESET     8
+#define IMX7_RESET_A7_L2RESET           9
+#define IMX7_RESET_SW_M4C_RST           10
+#define IMX7_RESET_SW_M4P_RST           11
+#define IMX7_RESET_EIM_RST              12
+#define IMX7_RESET_HSICPHY_PORT_RST     13
+#define IMX7_RESET_USBPHY1_POR          14
+#define IMX7_RESET_USBPHY1_PORT_RST     15
+#define IMX7_RESET_USBPHY2_POR          16
+#define IMX7_RESET_USBPHY2_PORT_RST     17
+#define IMX7_RESET_MIPI_PHY_MRST        18
+#define IMX7_RESET_MIPI_PHY_SRST        19
+
+/*
+ * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
+ * and PCIEPHY_G_RST
+ */
+#define IMX7_RESET_PCIEPHY              20
+#define IMX7_RESET_PCIEPHY_PERST        21
+
+/*
+ * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
+ * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
+ * of as one
+ */
+#define IMX7_RESET_PCIE_CTRL_APPS_EN    22
+#define IMX7_RESET_DDRC_PRST            23
+#define IMX7_RESET_DDRC_CORE_RST        24
+
+#define IMX7_RESET_NUM                  25
+
+#endif
+