diff options
-rw-r--r-- | Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 8 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/Makefile | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts | 162 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 411 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 407 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 20 | ||||
-rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip07.dtsi | 479 | ||||
-rw-r--r-- | include/dt-bindings/pinctrl/hisi.h | 15 |
10 files changed, 1507 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index f1c1e21a8110..2e732152064b 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | |||
@@ -4,6 +4,14 @@ Hi3660 SoC | |||
4 | Required root node properties: | 4 | Required root node properties: |
5 | - compatible = "hisilicon,hi3660"; | 5 | - compatible = "hisilicon,hi3660"; |
6 | 6 | ||
7 | Hi3798cv200 SoC | ||
8 | Required root node properties: | ||
9 | - compatible = "hisilicon,hi3798cv200"; | ||
10 | |||
11 | Hi3798cv200 Poplar Board | ||
12 | Required root node properties: | ||
13 | - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; | ||
14 | |||
7 | Hi4511 Board | 15 | Hi4511 Board |
8 | Required root node properties: | 16 | Required root node properties: |
9 | - compatible = "hisilicon,hi3620-hi4511"; | 17 | - compatible = "hisilicon,hi3620-hi4511"; |
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index c3a6c1943038..8960ecafd37d 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile | |||
@@ -1,4 +1,5 @@ | |||
1 | dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb | 1 | dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb |
2 | dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb | ||
2 | dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb | 3 | dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb |
3 | dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb | 4 | dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb |
4 | dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb | 5 | dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb |
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index ff37f0a0aa93..186251ffc6b2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | |||
@@ -8,6 +8,7 @@ | |||
8 | /dts-v1/; | 8 | /dts-v1/; |
9 | 9 | ||
10 | #include "hi3660.dtsi" | 10 | #include "hi3660.dtsi" |
11 | #include "hikey960-pinctrl.dtsi" | ||
11 | 12 | ||
12 | / { | 13 | / { |
13 | model = "HiKey960"; | 14 | model = "HiKey960"; |
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts new file mode 100644 index 000000000000..b9142871d6fe --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts | |||
@@ -0,0 +1,162 @@ | |||
1 | /* | ||
2 | * DTS File for HiSilicon Poplar Development Board | ||
3 | * | ||
4 | * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. | ||
5 | * | ||
6 | * Released under the GPLv2 only. | ||
7 | * SPDX-License-Identifier: GPL-2.0 | ||
8 | */ | ||
9 | |||
10 | /dts-v1/; | ||
11 | |||
12 | #include <dt-bindings/gpio/gpio.h> | ||
13 | #include "hi3798cv200.dtsi" | ||
14 | |||
15 | / { | ||
16 | model = "HiSilicon Poplar Development Board"; | ||
17 | compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; | ||
18 | |||
19 | aliases { | ||
20 | serial0 = &uart0; | ||
21 | serial2 = &uart2; | ||
22 | }; | ||
23 | |||
24 | chosen { | ||
25 | stdout-path = "serial0:115200n8"; | ||
26 | }; | ||
27 | |||
28 | memory@0 { | ||
29 | device_type = "memory"; | ||
30 | reg = <0x0 0x0 0x0 0x80000000>; | ||
31 | }; | ||
32 | |||
33 | leds { | ||
34 | compatible = "gpio-leds"; | ||
35 | |||
36 | user-led0 { | ||
37 | label = "USER-LED0"; | ||
38 | gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; | ||
39 | linux,default-trigger = "heartbeat"; | ||
40 | default-state = "off"; | ||
41 | }; | ||
42 | |||
43 | user-led1 { | ||
44 | label = "USER-LED1"; | ||
45 | gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; | ||
46 | linux,default-trigger = "mmc0"; | ||
47 | default-state = "off"; | ||
48 | }; | ||
49 | |||
50 | user-led2 { | ||
51 | label = "USER-LED2"; | ||
52 | gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; | ||
53 | linux,default-trigger = "none"; | ||
54 | default-state = "off"; | ||
55 | }; | ||
56 | |||
57 | user-led3 { | ||
58 | label = "USER-LED3"; | ||
59 | gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; | ||
60 | linux,default-trigger = "cpu0"; | ||
61 | default-state = "off"; | ||
62 | }; | ||
63 | }; | ||
64 | }; | ||
65 | |||
66 | &gmac1 { | ||
67 | status = "okay"; | ||
68 | #address-cells = <1>; | ||
69 | #size-cells = <0>; | ||
70 | phy-handle = <ð_phy1>; | ||
71 | phy-mode = "rgmii"; | ||
72 | hisilicon,phy-reset-delays-us = <10000 10000 30000>; | ||
73 | |||
74 | eth_phy1: phy@3 { | ||
75 | reg = <3>; | ||
76 | }; | ||
77 | }; | ||
78 | |||
79 | &gpio1 { | ||
80 | status = "okay"; | ||
81 | gpio-line-names = "LS-GPIO-E", "", | ||
82 | "", "", | ||
83 | "", "LS-GPIO-F", | ||
84 | "", "LS-GPIO-J"; | ||
85 | }; | ||
86 | |||
87 | &gpio2 { | ||
88 | status = "okay"; | ||
89 | gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", | ||
90 | "LS-GPIO-L", "LS-GPIO-G", | ||
91 | "LS-GPIO-K", "", | ||
92 | "", ""; | ||
93 | }; | ||
94 | |||
95 | &gpio3 { | ||
96 | status = "okay"; | ||
97 | gpio-line-names = "", "", | ||
98 | "", "", | ||
99 | "LS-GPIO-C", "", | ||
100 | "", "LS-GPIO-B"; | ||
101 | }; | ||
102 | |||
103 | &gpio4 { | ||
104 | status = "okay"; | ||
105 | gpio-line-names = "", "", | ||
106 | "", "", | ||
107 | "", "LS-GPIO-D", | ||
108 | "", ""; | ||
109 | }; | ||
110 | |||
111 | &gpio5 { | ||
112 | status = "okay"; | ||
113 | gpio-line-names = "", "USER-LED-1", | ||
114 | "USER-LED-2", "", | ||
115 | "", "LS-GPIO-A", | ||
116 | "", ""; | ||
117 | }; | ||
118 | |||
119 | &gpio6 { | ||
120 | status = "okay"; | ||
121 | gpio-line-names = "", "", | ||
122 | "", "USER-LED-0", | ||
123 | "", "", | ||
124 | "", ""; | ||
125 | }; | ||
126 | |||
127 | &gpio10 { | ||
128 | status = "okay"; | ||
129 | gpio-line-names = "", "", | ||
130 | "", "", | ||
131 | "", "", | ||
132 | "USER-LED-3", ""; | ||
133 | }; | ||
134 | |||
135 | &i2c0 { | ||
136 | status = "okay"; | ||
137 | label = "LS-I2C0"; | ||
138 | }; | ||
139 | |||
140 | &i2c2 { | ||
141 | status = "okay"; | ||
142 | label = "LS-I2C1"; | ||
143 | }; | ||
144 | |||
145 | &ir { | ||
146 | status = "okay"; | ||
147 | }; | ||
148 | |||
149 | &spi0 { | ||
150 | status = "okay"; | ||
151 | label = "LS-SPI0"; | ||
152 | }; | ||
153 | |||
154 | &uart0 { | ||
155 | status = "okay"; | ||
156 | }; | ||
157 | |||
158 | &uart2 { | ||
159 | status = "okay"; | ||
160 | label = "LS-UART0"; | ||
161 | }; | ||
162 | /* No optional LS-UART1 on Low Speed Expansion Connector. */ | ||
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi new file mode 100644 index 000000000000..75865f8a862a --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | |||
@@ -0,0 +1,411 @@ | |||
1 | /* | ||
2 | * DTS File for HiSilicon Hi3798cv200 SoC. | ||
3 | * | ||
4 | * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. | ||
5 | * | ||
6 | * Released under the GPLv2 only. | ||
7 | * SPDX-License-Identifier: GPL-2.0 | ||
8 | */ | ||
9 | |||
10 | #include <dt-bindings/clock/histb-clock.h> | ||
11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
12 | #include <dt-bindings/reset/ti-syscon.h> | ||
13 | |||
14 | / { | ||
15 | compatible = "hisilicon,hi3798cv200"; | ||
16 | interrupt-parent = <&gic>; | ||
17 | #address-cells = <2>; | ||
18 | #size-cells = <2>; | ||
19 | |||
20 | psci { | ||
21 | compatible = "arm,psci-0.2"; | ||
22 | method = "smc"; | ||
23 | }; | ||
24 | |||
25 | cpus { | ||
26 | #address-cells = <2>; | ||
27 | #size-cells = <0>; | ||
28 | |||
29 | cpu@0 { | ||
30 | compatible = "arm,cortex-a53"; | ||
31 | device_type = "cpu"; | ||
32 | reg = <0x0 0x0>; | ||
33 | enable-method = "psci"; | ||
34 | }; | ||
35 | |||
36 | cpu@1 { | ||
37 | compatible = "arm,cortex-a53"; | ||
38 | device_type = "cpu"; | ||
39 | reg = <0x0 0x1>; | ||
40 | enable-method = "psci"; | ||
41 | }; | ||
42 | |||
43 | cpu@2 { | ||
44 | compatible = "arm,cortex-a53"; | ||
45 | device_type = "cpu"; | ||
46 | reg = <0x0 0x2>; | ||
47 | enable-method = "psci"; | ||
48 | }; | ||
49 | |||
50 | cpu@3 { | ||
51 | compatible = "arm,cortex-a53"; | ||
52 | device_type = "cpu"; | ||
53 | reg = <0x0 0x3>; | ||
54 | enable-method = "psci"; | ||
55 | }; | ||
56 | }; | ||
57 | |||
58 | gic: interrupt-controller@f1001000 { | ||
59 | compatible = "arm,gic-400"; | ||
60 | reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ | ||
61 | <0x0 0xf1002000 0x0 0x100>; /* GICC */ | ||
62 | #address-cells = <0>; | ||
63 | #interrupt-cells = <3>; | ||
64 | interrupt-controller; | ||
65 | }; | ||
66 | |||
67 | timer { | ||
68 | compatible = "arm,armv8-timer"; | ||
69 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | | ||
70 | IRQ_TYPE_LEVEL_LOW)>, | ||
71 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | | ||
72 | IRQ_TYPE_LEVEL_LOW)>, | ||
73 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | | ||
74 | IRQ_TYPE_LEVEL_LOW)>, | ||
75 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | | ||
76 | IRQ_TYPE_LEVEL_LOW)>; | ||
77 | }; | ||
78 | |||
79 | soc: soc@f0000000 { | ||
80 | compatible = "simple-bus"; | ||
81 | #address-cells = <1>; | ||
82 | #size-cells = <1>; | ||
83 | ranges = <0x0 0x0 0xf0000000 0x10000000>; | ||
84 | |||
85 | crg: clock-reset-controller@8a22000 { | ||
86 | compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; | ||
87 | reg = <0x8a22000 0x1000>; | ||
88 | #clock-cells = <1>; | ||
89 | #reset-cells = <2>; | ||
90 | |||
91 | gmacphyrst: reset-controller { | ||
92 | compatible = "ti,syscon-reset"; | ||
93 | #reset-cells = <1>; | ||
94 | ti,reset-bits = | ||
95 | <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | | ||
96 | DEASSERT_SET|STATUS_NONE)>, | ||
97 | <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | | ||
98 | DEASSERT_SET|STATUS_NONE)>; | ||
99 | }; | ||
100 | }; | ||
101 | |||
102 | sysctrl: system-controller@8000000 { | ||
103 | compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; | ||
104 | reg = <0x8000000 0x1000>; | ||
105 | #clock-cells = <1>; | ||
106 | #reset-cells = <2>; | ||
107 | }; | ||
108 | |||
109 | uart0: serial@8b00000 { | ||
110 | compatible = "arm,pl011", "arm,primecell"; | ||
111 | reg = <0x8b00000 0x1000>; | ||
112 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | ||
113 | clocks = <&sysctrl HISTB_UART0_CLK>; | ||
114 | clock-names = "apb_pclk"; | ||
115 | status = "disabled"; | ||
116 | }; | ||
117 | |||
118 | uart2: serial@8b02000 { | ||
119 | compatible = "arm,pl011", "arm,primecell"; | ||
120 | reg = <0x8b02000 0x1000>; | ||
121 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | ||
122 | clocks = <&crg HISTB_UART2_CLK>; | ||
123 | clock-names = "apb_pclk"; | ||
124 | status = "disabled"; | ||
125 | }; | ||
126 | |||
127 | i2c0: i2c@8b10000 { | ||
128 | compatible = "hisilicon,hix5hd2-i2c"; | ||
129 | reg = <0x8b10000 0x1000>; | ||
130 | #address-cells = <1>; | ||
131 | #size-cells = <0>; | ||
132 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | ||
133 | clock-frequency = <400000>; | ||
134 | clocks = <&crg HISTB_I2C0_CLK>; | ||
135 | status = "disabled"; | ||
136 | }; | ||
137 | |||
138 | i2c1: i2c@8b11000 { | ||
139 | compatible = "hisilicon,hix5hd2-i2c"; | ||
140 | reg = <0x8b11000 0x1000>; | ||
141 | #address-cells = <1>; | ||
142 | #size-cells = <0>; | ||
143 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | ||
144 | clock-frequency = <400000>; | ||
145 | clocks = <&crg HISTB_I2C1_CLK>; | ||
146 | status = "disabled"; | ||
147 | }; | ||
148 | |||
149 | i2c2: i2c@8b12000 { | ||
150 | compatible = "hisilicon,hix5hd2-i2c"; | ||
151 | reg = <0x8b12000 0x1000>; | ||
152 | #address-cells = <1>; | ||
153 | #size-cells = <0>; | ||
154 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | ||
155 | clock-frequency = <400000>; | ||
156 | clocks = <&crg HISTB_I2C2_CLK>; | ||
157 | status = "disabled"; | ||
158 | }; | ||
159 | |||
160 | i2c3: i2c@8b13000 { | ||
161 | compatible = "hisilicon,hix5hd2-i2c"; | ||
162 | reg = <0x8b13000 0x1000>; | ||
163 | #address-cells = <1>; | ||
164 | #size-cells = <0>; | ||
165 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | ||
166 | clock-frequency = <400000>; | ||
167 | clocks = <&crg HISTB_I2C3_CLK>; | ||
168 | status = "disabled"; | ||
169 | }; | ||
170 | |||
171 | i2c4: i2c@8b14000 { | ||
172 | compatible = "hisilicon,hix5hd2-i2c"; | ||
173 | reg = <0x8b14000 0x1000>; | ||
174 | #address-cells = <1>; | ||
175 | #size-cells = <0>; | ||
176 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | ||
177 | clock-frequency = <400000>; | ||
178 | clocks = <&crg HISTB_I2C4_CLK>; | ||
179 | status = "disabled"; | ||
180 | }; | ||
181 | |||
182 | spi0: spi@8b1a000 { | ||
183 | compatible = "arm,pl022", "arm,primecell"; | ||
184 | reg = <0x8b1a000 0x1000>; | ||
185 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | ||
186 | num-cs = <1>; | ||
187 | cs-gpios = <&gpio7 1 0>; | ||
188 | clocks = <&crg HISTB_SPI0_CLK>; | ||
189 | clock-names = "apb_pclk"; | ||
190 | #address-cells = <1>; | ||
191 | #size-cells = <0>; | ||
192 | status = "disabled"; | ||
193 | }; | ||
194 | |||
195 | emmc: mmc@9830000 { | ||
196 | compatible = "snps,dw-mshc"; | ||
197 | reg = <0x9830000 0x10000>; | ||
198 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | ||
199 | clocks = <&crg HISTB_MMC_CIU_CLK>, | ||
200 | <&crg HISTB_MMC_BIU_CLK>; | ||
201 | clock-names = "ciu", "biu"; | ||
202 | }; | ||
203 | |||
204 | gpio0: gpio@8b20000 { | ||
205 | compatible = "arm,pl061", "arm,primecell"; | ||
206 | reg = <0x8b20000 0x1000>; | ||
207 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | ||
208 | gpio-controller; | ||
209 | #gpio-cells = <2>; | ||
210 | interrupt-controller; | ||
211 | #interrupt-cells = <2>; | ||
212 | clocks = <&crg HISTB_APB_CLK>; | ||
213 | clock-names = "apb_pclk"; | ||
214 | status = "disabled"; | ||
215 | }; | ||
216 | |||
217 | gpio1: gpio@8b21000 { | ||
218 | compatible = "arm,pl061", "arm,primecell"; | ||
219 | reg = <0x8b21000 0x1000>; | ||
220 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | ||
221 | gpio-controller; | ||
222 | #gpio-cells = <2>; | ||
223 | interrupt-controller; | ||
224 | #interrupt-cells = <2>; | ||
225 | clocks = <&crg HISTB_APB_CLK>; | ||
226 | clock-names = "apb_pclk"; | ||
227 | status = "disabled"; | ||
228 | }; | ||
229 | |||
230 | gpio2: gpio@8b22000 { | ||
231 | compatible = "arm,pl061", "arm,primecell"; | ||
232 | reg = <0x8b22000 0x1000>; | ||
233 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | ||
234 | gpio-controller; | ||
235 | #gpio-cells = <2>; | ||
236 | interrupt-controller; | ||
237 | #interrupt-cells = <2>; | ||
238 | clocks = <&crg HISTB_APB_CLK>; | ||
239 | clock-names = "apb_pclk"; | ||
240 | status = "disabled"; | ||
241 | }; | ||
242 | |||
243 | gpio3: gpio@8b23000 { | ||
244 | compatible = "arm,pl061", "arm,primecell"; | ||
245 | reg = <0x8b23000 0x1000>; | ||
246 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | ||
247 | gpio-controller; | ||
248 | #gpio-cells = <2>; | ||
249 | interrupt-controller; | ||
250 | #interrupt-cells = <2>; | ||
251 | clocks = <&crg HISTB_APB_CLK>; | ||
252 | clock-names = "apb_pclk"; | ||
253 | status = "disabled"; | ||
254 | }; | ||
255 | |||
256 | gpio4: gpio@8b24000 { | ||
257 | compatible = "arm,pl061", "arm,primecell"; | ||
258 | reg = <0x8b24000 0x1000>; | ||
259 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | ||
260 | gpio-controller; | ||
261 | #gpio-cells = <2>; | ||
262 | interrupt-controller; | ||
263 | #interrupt-cells = <2>; | ||
264 | clocks = <&crg HISTB_APB_CLK>; | ||
265 | clock-names = "apb_pclk"; | ||
266 | status = "disabled"; | ||
267 | }; | ||
268 | |||
269 | gpio5: gpio@8004000 { | ||
270 | compatible = "arm,pl061", "arm,primecell"; | ||
271 | reg = <0x8004000 0x1000>; | ||
272 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | ||
273 | gpio-controller; | ||
274 | #gpio-cells = <2>; | ||
275 | interrupt-controller; | ||
276 | #interrupt-cells = <2>; | ||
277 | clocks = <&crg HISTB_APB_CLK>; | ||
278 | clock-names = "apb_pclk"; | ||
279 | status = "disabled"; | ||
280 | }; | ||
281 | |||
282 | gpio6: gpio@8b26000 { | ||
283 | compatible = "arm,pl061", "arm,primecell"; | ||
284 | reg = <0x8b26000 0x1000>; | ||
285 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | ||
286 | gpio-controller; | ||
287 | #gpio-cells = <2>; | ||
288 | interrupt-controller; | ||
289 | #interrupt-cells = <2>; | ||
290 | clocks = <&crg HISTB_APB_CLK>; | ||
291 | clock-names = "apb_pclk"; | ||
292 | status = "disabled"; | ||
293 | }; | ||
294 | |||
295 | gpio7: gpio@8b27000 { | ||
296 | compatible = "arm,pl061", "arm,primecell"; | ||
297 | reg = <0x8b27000 0x1000>; | ||
298 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | ||
299 | gpio-controller; | ||
300 | #gpio-cells = <2>; | ||
301 | interrupt-controller; | ||
302 | #interrupt-cells = <2>; | ||
303 | clocks = <&crg HISTB_APB_CLK>; | ||
304 | clock-names = "apb_pclk"; | ||
305 | status = "disabled"; | ||
306 | }; | ||
307 | |||
308 | gpio8: gpio@8b28000 { | ||
309 | compatible = "arm,pl061", "arm,primecell"; | ||
310 | reg = <0x8b28000 0x1000>; | ||
311 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | ||
312 | gpio-controller; | ||
313 | #gpio-cells = <2>; | ||
314 | interrupt-controller; | ||
315 | #interrupt-cells = <2>; | ||
316 | clocks = <&crg HISTB_APB_CLK>; | ||
317 | clock-names = "apb_pclk"; | ||
318 | status = "disabled"; | ||
319 | }; | ||
320 | |||
321 | gpio9: gpio@8b29000 { | ||
322 | compatible = "arm,pl061", "arm,primecell"; | ||
323 | reg = <0x8b29000 0x1000>; | ||
324 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | ||
325 | gpio-controller; | ||
326 | #gpio-cells = <2>; | ||
327 | interrupt-controller; | ||
328 | #interrupt-cells = <2>; | ||
329 | clocks = <&crg HISTB_APB_CLK>; | ||
330 | clock-names = "apb_pclk"; | ||
331 | status = "disabled"; | ||
332 | }; | ||
333 | |||
334 | gpio10: gpio@8b2a000 { | ||
335 | compatible = "arm,pl061", "arm,primecell"; | ||
336 | reg = <0x8b2a000 0x1000>; | ||
337 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | ||
338 | gpio-controller; | ||
339 | #gpio-cells = <2>; | ||
340 | interrupt-controller; | ||
341 | #interrupt-cells = <2>; | ||
342 | clocks = <&crg HISTB_APB_CLK>; | ||
343 | clock-names = "apb_pclk"; | ||
344 | status = "disabled"; | ||
345 | }; | ||
346 | |||
347 | gpio11: gpio@8b2b000 { | ||
348 | compatible = "arm,pl061", "arm,primecell"; | ||
349 | reg = <0x8b2b000 0x1000>; | ||
350 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | ||
351 | gpio-controller; | ||
352 | #gpio-cells = <2>; | ||
353 | interrupt-controller; | ||
354 | #interrupt-cells = <2>; | ||
355 | clocks = <&crg HISTB_APB_CLK>; | ||
356 | clock-names = "apb_pclk"; | ||
357 | status = "disabled"; | ||
358 | }; | ||
359 | |||
360 | gpio12: gpio@8b2c000 { | ||
361 | compatible = "arm,pl061", "arm,primecell"; | ||
362 | reg = <0x8b2c000 0x1000>; | ||
363 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | ||
364 | gpio-controller; | ||
365 | #gpio-cells = <2>; | ||
366 | interrupt-controller; | ||
367 | #interrupt-cells = <2>; | ||
368 | clocks = <&crg HISTB_APB_CLK>; | ||
369 | clock-names = "apb_pclk"; | ||
370 | status = "disabled"; | ||
371 | }; | ||
372 | |||
373 | gmac0: ethernet@9840000 { | ||
374 | compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; | ||
375 | reg = <0x9840000 0x1000>, | ||
376 | <0x984300c 0x4>; | ||
377 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | ||
378 | clocks = <&crg HISTB_ETH0_MAC_CLK>, | ||
379 | <&crg HISTB_ETH0_MACIF_CLK>; | ||
380 | clock-names = "mac_core", "mac_ifc"; | ||
381 | resets = <&crg 0xcc 8>, | ||
382 | <&crg 0xcc 10>, | ||
383 | <&gmacphyrst 0>; | ||
384 | reset-names = "mac_core", "mac_ifc", "phy"; | ||
385 | status = "disabled"; | ||
386 | }; | ||
387 | |||
388 | gmac1: ethernet@9841000 { | ||
389 | compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; | ||
390 | reg = <0x9841000 0x1000>, | ||
391 | <0x9843010 0x4>; | ||
392 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | ||
393 | clocks = <&crg HISTB_ETH1_MAC_CLK>, | ||
394 | <&crg HISTB_ETH1_MACIF_CLK>; | ||
395 | clock-names = "mac_core", "mac_ifc"; | ||
396 | resets = <&crg 0xcc 9>, | ||
397 | <&crg 0xcc 11>, | ||
398 | <&gmacphyrst 1>; | ||
399 | reset-names = "mac_core", "mac_ifc", "phy"; | ||
400 | status = "disabled"; | ||
401 | }; | ||
402 | |||
403 | ir: ir@8001000 { | ||
404 | compatible = "hisilicon,hix5hd2-ir"; | ||
405 | reg = <0x8001000 0x1000>; | ||
406 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | ||
407 | clocks = <&sysctrl HISTB_IR_CLK>; | ||
408 | status = "disabled"; | ||
409 | }; | ||
410 | }; | ||
411 | }; | ||
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 470461ddd427..1e5129b19280 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi | |||
@@ -774,6 +774,7 @@ | |||
774 | clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; | 774 | clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; |
775 | clock-names = "ciu", "biu"; | 775 | clock-names = "ciu", "biu"; |
776 | resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; | 776 | resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; |
777 | reset-names = "reset"; | ||
777 | bus-width = <0x8>; | 778 | bus-width = <0x8>; |
778 | vmmc-supply = <&ldo19>; | 779 | vmmc-supply = <&ldo19>; |
779 | pinctrl-names = "default"; | 780 | pinctrl-names = "default"; |
@@ -797,6 +798,7 @@ | |||
797 | clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; | 798 | clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; |
798 | clock-names = "ciu", "biu"; | 799 | clock-names = "ciu", "biu"; |
799 | resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; | 800 | resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; |
801 | reset-names = "reset"; | ||
800 | vqmmc-supply = <&ldo7>; | 802 | vqmmc-supply = <&ldo7>; |
801 | vmmc-supply = <&ldo10>; | 803 | vmmc-supply = <&ldo10>; |
802 | bus-width = <0x4>; | 804 | bus-width = <0x4>; |
@@ -815,6 +817,7 @@ | |||
815 | clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; | 817 | clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; |
816 | clock-names = "ciu", "biu"; | 818 | clock-names = "ciu", "biu"; |
817 | resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; | 819 | resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; |
820 | reset-names = "reset"; | ||
818 | bus-width = <0x4>; | 821 | bus-width = <0x4>; |
819 | broken-cd; | 822 | broken-cd; |
820 | pinctrl-names = "default", "idle"; | 823 | pinctrl-names = "default", "idle"; |
diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi new file mode 100644 index 000000000000..719c4bc937a4 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | |||
@@ -0,0 +1,407 @@ | |||
1 | /* | ||
2 | * pinctrl dts fils for Hislicon HiKey960 development board | ||
3 | * | ||
4 | */ | ||
5 | |||
6 | #include <dt-bindings/pinctrl/hisi.h> | ||
7 | |||
8 | / { | ||
9 | soc { | ||
10 | /* [IOMG_000, IOMG_123] */ | ||
11 | range: gpio-range { | ||
12 | #pinctrl-single,gpio-range-cells = <3>; | ||
13 | }; | ||
14 | |||
15 | pmx0: pinmux@e896c000 { | ||
16 | compatible = "pinctrl-single"; | ||
17 | reg = <0x0 0xe896c000 0x0 0x1f0>; | ||
18 | #pinctrl-cells = <1>; | ||
19 | #gpio-range-cells = <0x3>; | ||
20 | pinctrl-single,register-width = <0x20>; | ||
21 | pinctrl-single,function-mask = <0x7>; | ||
22 | /* pin base, nr pins & gpio function */ | ||
23 | pinctrl-single,gpio-range = < | ||
24 | &range 0 7 0 | ||
25 | &range 8 116 0>; | ||
26 | |||
27 | isp0_pmx_func: isp0_pmx_func { | ||
28 | pinctrl-single,pins = < | ||
29 | 0x058 MUX_M1 /* ISP_CLK0 */ | ||
30 | 0x064 MUX_M1 /* ISP_SCL0 */ | ||
31 | 0x068 MUX_M1 /* ISP_SDA0 */ | ||
32 | >; | ||
33 | }; | ||
34 | |||
35 | isp1_pmx_func: isp1_pmx_func { | ||
36 | pinctrl-single,pins = < | ||
37 | 0x05c MUX_M1 /* ISP_CLK1 */ | ||
38 | 0x06c MUX_M1 /* ISP_SCL1 */ | ||
39 | 0x070 MUX_M1 /* ISP_SDA1 */ | ||
40 | >; | ||
41 | }; | ||
42 | |||
43 | i2c3_pmx_func: i2c3_pmx_func { | ||
44 | pinctrl-single,pins = < | ||
45 | 0x02c MUX_M1 /* I2C3_SCL */ | ||
46 | 0x030 MUX_M1 /* I2C3_SDA */ | ||
47 | >; | ||
48 | }; | ||
49 | |||
50 | i2c4_pmx_func: i2c4_pmx_func { | ||
51 | pinctrl-single,pins = < | ||
52 | 0x090 MUX_M1 /* I2C4_SCL */ | ||
53 | 0x094 MUX_M1 /* I2C4_SDA */ | ||
54 | >; | ||
55 | }; | ||
56 | |||
57 | pcie_perstn_pmx_func: pcie_perstn_pmx_func { | ||
58 | pinctrl-single,pins = < | ||
59 | 0x15c MUX_M1 /* PCIE_PERST_N */ | ||
60 | >; | ||
61 | }; | ||
62 | |||
63 | usbhub5734_pmx_func: usbhub5734_pmx_func { | ||
64 | pinctrl-single,pins = < | ||
65 | 0x11c MUX_M0 /* GPIO_073 */ | ||
66 | 0x120 MUX_M0 /* GPIO_074 */ | ||
67 | >; | ||
68 | }; | ||
69 | |||
70 | spi1_pmx_func: spi1_pmx_func { | ||
71 | pinctrl-single,pins = < | ||
72 | 0x034 MUX_M1 /* SPI1_CLK */ | ||
73 | 0x038 MUX_M1 /* SPI1_DI */ | ||
74 | 0x03c MUX_M1 /* SPI1_DO */ | ||
75 | 0x040 MUX_M1 /* SPI1_CS_N */ | ||
76 | >; | ||
77 | }; | ||
78 | |||
79 | uart0_pmx_func: uart0_pmx_func { | ||
80 | pinctrl-single,pins = < | ||
81 | 0x0cc MUX_M2 /* UART0_RXD */ | ||
82 | 0x0d0 MUX_M2 /* UART0_TXD */ | ||
83 | 0x0d4 MUX_M2 /* UART0_RXD_M */ | ||
84 | 0x0d8 MUX_M2 /* UART0_TXD_M */ | ||
85 | >; | ||
86 | }; | ||
87 | |||
88 | uart1_pmx_func: uart1_pmx_func { | ||
89 | pinctrl-single,pins = < | ||
90 | 0x0b0 MUX_M2 /* UART1_CTS_N */ | ||
91 | 0x0b4 MUX_M2 /* UART1_RTS_N */ | ||
92 | 0x0a8 MUX_M2 /* UART1_RXD */ | ||
93 | 0x0ac MUX_M2 /* UART1_TXD */ | ||
94 | >; | ||
95 | }; | ||
96 | |||
97 | uart2_pmx_func: uart2_pmx_func { | ||
98 | pinctrl-single,pins = < | ||
99 | 0x0bc MUX_M2 /* UART2_CTS_N */ | ||
100 | 0x0c0 MUX_M2 /* UART2_RTS_N */ | ||
101 | 0x0c8 MUX_M2 /* UART2_RXD */ | ||
102 | 0x0c4 MUX_M2 /* UART2_TXD */ | ||
103 | >; | ||
104 | }; | ||
105 | |||
106 | uart3_pmx_func: uart3_pmx_func { | ||
107 | pinctrl-single,pins = < | ||
108 | 0x0dc MUX_M1 /* UART3_CTS_N */ | ||
109 | 0x0e0 MUX_M1 /* UART3_RTS_N */ | ||
110 | 0x0e4 MUX_M1 /* UART3_RXD */ | ||
111 | 0x0e8 MUX_M1 /* UART3_TXD */ | ||
112 | >; | ||
113 | }; | ||
114 | |||
115 | uart4_pmx_func: uart4_pmx_func { | ||
116 | pinctrl-single,pins = < | ||
117 | 0x0ec MUX_M1 /* UART4_CTS_N */ | ||
118 | 0x0f0 MUX_M1 /* UART4_RTS_N */ | ||
119 | 0x0f4 MUX_M1 /* UART4_RXD */ | ||
120 | 0x0f8 MUX_M1 /* UART4_TXD */ | ||
121 | >; | ||
122 | }; | ||
123 | |||
124 | uart5_pmx_func: uart5_pmx_func { | ||
125 | pinctrl-single,pins = < | ||
126 | 0x0c4 MUX_M3 /* UART5_CTS_N */ | ||
127 | 0x0c8 MUX_M3 /* UART5_RTS_N */ | ||
128 | 0x0bc MUX_M3 /* UART5_RXD */ | ||
129 | 0x0c0 MUX_M3 /* UART5_TXD */ | ||
130 | >; | ||
131 | }; | ||
132 | |||
133 | uart6_pmx_func: uart6_pmx_func { | ||
134 | pinctrl-single,pins = < | ||
135 | 0x0cc MUX_M1 /* UART6_CTS_N */ | ||
136 | 0x0d0 MUX_M1 /* UART6_RTS_N */ | ||
137 | 0x0d4 MUX_M1 /* UART6_RXD */ | ||
138 | 0x0d8 MUX_M1 /* UART6_TXD */ | ||
139 | >; | ||
140 | }; | ||
141 | }; | ||
142 | |||
143 | /* [IOMG_MMC0_000, IOMG_MMC0_005] */ | ||
144 | pmx1: pinmux@ff37e000 { | ||
145 | compatible = "pinctrl-single"; | ||
146 | reg = <0x0 0xff37e000 0x0 0x18>; | ||
147 | #gpio-range-cells = <0x3>; | ||
148 | #pinctrl-cells = <1>; | ||
149 | pinctrl-single,register-width = <0x20>; | ||
150 | pinctrl-single,function-mask = <0x7>; | ||
151 | /* pin base, nr pins & gpio function */ | ||
152 | pinctrl-single,gpio-range = <&range 0 6 0>; | ||
153 | |||
154 | sd_pmx_func: sd_pmx_func { | ||
155 | pinctrl-single,pins = < | ||
156 | 0x000 MUX_M1 /* SD_CLK */ | ||
157 | 0x004 MUX_M1 /* SD_CMD */ | ||
158 | 0x008 MUX_M1 /* SD_DATA0 */ | ||
159 | 0x00c MUX_M1 /* SD_DATA1 */ | ||
160 | 0x010 MUX_M1 /* SD_DATA2 */ | ||
161 | 0x014 MUX_M1 /* SD_DATA3 */ | ||
162 | >; | ||
163 | }; | ||
164 | }; | ||
165 | |||
166 | /* [IOMG_FIX_000, IOMG_FIX_011] */ | ||
167 | pmx2: pinmux@ff3b6000 { | ||
168 | compatible = "pinctrl-single"; | ||
169 | reg = <0x0 0xff3b6000 0x0 0x30>; | ||
170 | #pinctrl-cells = <1>; | ||
171 | #gpio-range-cells = <0x3>; | ||
172 | pinctrl-single,register-width = <0x20>; | ||
173 | pinctrl-single,function-mask = <0x7>; | ||
174 | /* pin base, nr pins & gpio function */ | ||
175 | pinctrl-single,gpio-range = <&range 0 12 0>; | ||
176 | |||
177 | spi3_pmx_func: spi3_pmx_func { | ||
178 | pinctrl-single,pins = < | ||
179 | 0x008 MUX_M1 /* SPI3_CLK */ | ||
180 | 0x00c MUX_M1 /* SPI3_DI */ | ||
181 | 0x010 MUX_M1 /* SPI3_DO */ | ||
182 | 0x014 MUX_M1 /* SPI3_CS0_N */ | ||
183 | >; | ||
184 | }; | ||
185 | }; | ||
186 | |||
187 | /* [IOMG_MMC1_000, IOMG_MMC1_005] */ | ||
188 | pmx3: pinmux@ff3fd000 { | ||
189 | compatible = "pinctrl-single"; | ||
190 | reg = <0x0 0xff3fd000 0x0 0x18>; | ||
191 | #pinctrl-cells = <1>; | ||
192 | #gpio-range-cells = <0x3>; | ||
193 | pinctrl-single,register-width = <0x20>; | ||
194 | pinctrl-single,function-mask = <0x7>; | ||
195 | /* pin base, nr pins & gpio function */ | ||
196 | pinctrl-single,gpio-range = <&range 0 6 0>; | ||
197 | |||
198 | sdio_pmx_func: sdio_pmx_func { | ||
199 | pinctrl-single,pins = < | ||
200 | 0x000 MUX_M1 /* SDIO_CLK */ | ||
201 | 0x004 MUX_M1 /* SDIO_CMD */ | ||
202 | 0x008 MUX_M1 /* SDIO_DATA0 */ | ||
203 | 0x00c MUX_M1 /* SDIO_DATA1 */ | ||
204 | 0x010 MUX_M1 /* SDIO_DATA2 */ | ||
205 | 0x014 MUX_M1 /* SDIO_DATA3 */ | ||
206 | >; | ||
207 | }; | ||
208 | }; | ||
209 | |||
210 | /* [IOMG_AO_000, IOMG_AO_041] */ | ||
211 | pmx4: pinmux@fff11000 { | ||
212 | compatible = "pinctrl-single"; | ||
213 | reg = <0x0 0xfff11000 0x0 0xa8>; | ||
214 | #pinctrl-cells = <1>; | ||
215 | #gpio-range-cells = <0x3>; | ||
216 | pinctrl-single,register-width = <0x20>; | ||
217 | pinctrl-single,function-mask = <0x7>; | ||
218 | /* pin base in node, nr pins & gpio function */ | ||
219 | pinctrl-single,gpio-range = <&range 0 42 0>; | ||
220 | |||
221 | i2s2_pmx_func: i2s2_pmx_func { | ||
222 | pinctrl-single,pins = < | ||
223 | 0x044 MUX_M1 /* I2S2_DI */ | ||
224 | 0x048 MUX_M1 /* I2S2_DO */ | ||
225 | 0x04c MUX_M1 /* I2S2_XCLK */ | ||
226 | 0x050 MUX_M1 /* I2S2_XFS */ | ||
227 | >; | ||
228 | }; | ||
229 | |||
230 | slimbus_pmx_func: slimbus_pmx_func { | ||
231 | pinctrl-single,pins = < | ||
232 | 0x02c MUX_M1 /* SLIMBUS_CLK */ | ||
233 | 0x030 MUX_M1 /* SLIMBUS_DATA */ | ||
234 | >; | ||
235 | }; | ||
236 | |||
237 | i2c0_pmx_func: i2c0_pmx_func { | ||
238 | pinctrl-single,pins = < | ||
239 | 0x014 MUX_M1 /* I2C0_SCL */ | ||
240 | 0x018 MUX_M1 /* I2C0_SDA */ | ||
241 | >; | ||
242 | }; | ||
243 | |||
244 | i2c1_pmx_func: i2c1_pmx_func { | ||
245 | pinctrl-single,pins = < | ||
246 | 0x01c MUX_M1 /* I2C1_SCL */ | ||
247 | 0x020 MUX_M1 /* I2C1_SDA */ | ||
248 | >; | ||
249 | }; | ||
250 | |||
251 | i2c2_pmx_func: i2c2_pmx_func { | ||
252 | pinctrl-single,pins = < | ||
253 | 0x024 MUX_M1 /* I2C2_SCL */ | ||
254 | 0x028 MUX_M1 /* I2C2_SDA */ | ||
255 | >; | ||
256 | }; | ||
257 | |||
258 | i2c7_pmx_func: i2c7_pmx_func { | ||
259 | pinctrl-single,pins = < | ||
260 | 0x024 MUX_M3 /* I2C7_SCL */ | ||
261 | 0x028 MUX_M3 /* I2C7_SDA */ | ||
262 | >; | ||
263 | }; | ||
264 | |||
265 | spi2_pmx_func: spi2_pmx_func { | ||
266 | pinctrl-single,pins = < | ||
267 | 0x08c MUX_M1 /* SPI2_CLK */ | ||
268 | 0x090 MUX_M1 /* SPI2_DI */ | ||
269 | 0x094 MUX_M1 /* SPI2_DO */ | ||
270 | 0x098 MUX_M1 /* SPI2_CS0_N */ | ||
271 | >; | ||
272 | }; | ||
273 | |||
274 | spi4_pmx_func: spi4_pmx_func { | ||
275 | pinctrl-single,pins = < | ||
276 | 0x08c MUX_M4 /* SPI4_CLK */ | ||
277 | 0x090 MUX_M4 /* SPI4_DI */ | ||
278 | 0x094 MUX_M4 /* SPI4_DO */ | ||
279 | 0x098 MUX_M4 /* SPI4_CS0_N */ | ||
280 | >; | ||
281 | }; | ||
282 | |||
283 | i2s0_pmx_func: i2s0_pmx_func { | ||
284 | pinctrl-single,pins = < | ||
285 | 0x034 MUX_M1 /* I2S0_DI */ | ||
286 | 0x038 MUX_M1 /* I2S0_DO */ | ||
287 | 0x03c MUX_M1 /* I2S0_XCLK */ | ||
288 | 0x040 MUX_M1 /* I2S0_XFS */ | ||
289 | >; | ||
290 | }; | ||
291 | }; | ||
292 | |||
293 | pmx5: pinmux@ff3fd800 { | ||
294 | compatible = "pinconf-single"; | ||
295 | reg = <0x0 0xff3fd800 0x0 0x18>; | ||
296 | #pinctrl-cells = <1>; | ||
297 | #address-cells = <1>; | ||
298 | #size-cells = <1>; | ||
299 | pinctrl-single,register-width = <32>; | ||
300 | |||
301 | sdio_clk_cfg_func: sdio_clk_cfg_func { | ||
302 | pinctrl-single,pins = < | ||
303 | 0x000 0x0 /* SDIO_CLK */ | ||
304 | >; | ||
305 | pinctrl-single,bias-pulldown = < | ||
306 | PULL_DIS | ||
307 | PULL_DOWN | ||
308 | PULL_DIS | ||
309 | PULL_DOWN | ||
310 | >; | ||
311 | pinctrl-single,bias-pullup = < | ||
312 | PULL_DIS | ||
313 | PULL_UP | ||
314 | PULL_DIS | ||
315 | PULL_UP | ||
316 | >; | ||
317 | pinctrl-single,drive-strength = < | ||
318 | DRIVE6_32MA | ||
319 | DRIVE6_MASK | ||
320 | >; | ||
321 | }; | ||
322 | |||
323 | sdio_cfg_func: sdio_cfg_func { | ||
324 | pinctrl-single,pins = < | ||
325 | 0x004 0x0 /* SDIO_CMD */ | ||
326 | 0x008 0x0 /* SDIO_DATA0 */ | ||
327 | 0x00c 0x0 /* SDIO_DATA1 */ | ||
328 | 0x010 0x0 /* SDIO_DATA2 */ | ||
329 | 0x014 0x0 /* SDIO_DATA3 */ | ||
330 | >; | ||
331 | pinctrl-single,bias-pulldown = < | ||
332 | PULL_DIS | ||
333 | PULL_DOWN | ||
334 | PULL_DIS | ||
335 | PULL_DOWN | ||
336 | >; | ||
337 | pinctrl-single,bias-pullup = < | ||
338 | PULL_UP | ||
339 | PULL_UP | ||
340 | PULL_DIS | ||
341 | PULL_UP | ||
342 | >; | ||
343 | pinctrl-single,drive-strength = < | ||
344 | DRIVE6_19MA | ||
345 | DRIVE6_MASK | ||
346 | >; | ||
347 | }; | ||
348 | }; | ||
349 | |||
350 | pmx6: pinmux@ff37e800 { | ||
351 | compatible = "pinconf-single"; | ||
352 | reg = <0x0 0xff37e800 0x0 0x18>; | ||
353 | #pinctrl-cells = <1>; | ||
354 | #address-cells = <1>; | ||
355 | #size-cells = <1>; | ||
356 | pinctrl-single,register-width = <32>; | ||
357 | |||
358 | sd_clk_cfg_func: sd_clk_cfg_func { | ||
359 | pinctrl-single,pins = < | ||
360 | 0x000 0x0 /* SD_CLK */ | ||
361 | >; | ||
362 | pinctrl-single,bias-pulldown = < | ||
363 | PULL_DIS | ||
364 | PULL_DOWN | ||
365 | PULL_DIS | ||
366 | PULL_DOWN | ||
367 | >; | ||
368 | pinctrl-single,bias-pullup = < | ||
369 | PULL_DIS | ||
370 | PULL_UP | ||
371 | PULL_DIS | ||
372 | PULL_UP | ||
373 | >; | ||
374 | pinctrl-single,drive-strength = < | ||
375 | DRIVE6_32MA | ||
376 | DRIVE6_MASK | ||
377 | >; | ||
378 | }; | ||
379 | |||
380 | sd_cfg_func: sd_cfg_func { | ||
381 | pinctrl-single,pins = < | ||
382 | 0x004 0x0 /* SD_CMD */ | ||
383 | 0x008 0x0 /* SD_DATA0 */ | ||
384 | 0x00c 0x0 /* SD_DATA1 */ | ||
385 | 0x010 0x0 /* SD_DATA2 */ | ||
386 | 0x014 0x0 /* SD_DATA3 */ | ||
387 | >; | ||
388 | pinctrl-single,bias-pulldown = < | ||
389 | PULL_DIS | ||
390 | PULL_DOWN | ||
391 | PULL_DIS | ||
392 | PULL_DOWN | ||
393 | >; | ||
394 | pinctrl-single,bias-pullup = < | ||
395 | PULL_UP | ||
396 | PULL_UP | ||
397 | PULL_DIS | ||
398 | PULL_UP | ||
399 | >; | ||
400 | pinctrl-single,drive-strength = < | ||
401 | DRIVE6_19MA | ||
402 | DRIVE6_MASK | ||
403 | >; | ||
404 | }; | ||
405 | }; | ||
406 | }; | ||
407 | }; | ||
diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts index e05844230583..f5d7f0889b41 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts | |||
@@ -64,3 +64,23 @@ | |||
64 | &usb_ehci { | 64 | &usb_ehci { |
65 | status = "ok"; | 65 | status = "ok"; |
66 | }; | 66 | }; |
67 | |||
68 | ð0 { | ||
69 | status = "ok"; | ||
70 | }; | ||
71 | |||
72 | ð1 { | ||
73 | status = "ok"; | ||
74 | }; | ||
75 | |||
76 | ð2 { | ||
77 | status = "ok"; | ||
78 | }; | ||
79 | |||
80 | ð3 { | ||
81 | status = "ok"; | ||
82 | }; | ||
83 | |||
84 | &sas1 { | ||
85 | status = "ok"; | ||
86 | }; | ||
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 5144eb1c179d..283d7b532e16 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi | |||
@@ -1014,6 +1014,34 @@ | |||
1014 | compatible = "hisilicon,mbigen-v2"; | 1014 | compatible = "hisilicon,mbigen-v2"; |
1015 | reg = <0x0 0xa0080000 0x0 0x10000>; | 1015 | reg = <0x0 0xa0080000 0x0 0x10000>; |
1016 | 1016 | ||
1017 | mbigen_pcie2_a: intc_pcie2_a { | ||
1018 | msi-parent = <&p0_its_dsa_a 0x40087>; | ||
1019 | interrupt-controller; | ||
1020 | #interrupt-cells = <2>; | ||
1021 | num-pins = <10>; | ||
1022 | }; | ||
1023 | |||
1024 | mbigen_sas1: intc_sas1 { | ||
1025 | msi-parent = <&p0_its_dsa_a 0x40000>; | ||
1026 | interrupt-controller; | ||
1027 | #interrupt-cells = <2>; | ||
1028 | num-pins = <128>; | ||
1029 | }; | ||
1030 | |||
1031 | mbigen_sas2: intc_sas2 { | ||
1032 | msi-parent = <&p0_its_dsa_a 0x40040>; | ||
1033 | interrupt-controller; | ||
1034 | #interrupt-cells = <2>; | ||
1035 | num-pins = <128>; | ||
1036 | }; | ||
1037 | |||
1038 | mbigen_smmu_pcie: intc_smmu_pcie { | ||
1039 | msi-parent = <&p0_its_dsa_a 0x40b0c>; | ||
1040 | interrupt-controller; | ||
1041 | #interrupt-cells = <2>; | ||
1042 | num-pins = <3>; | ||
1043 | }; | ||
1044 | |||
1017 | mbigen_usb: intc_usb { | 1045 | mbigen_usb: intc_usb { |
1018 | msi-parent = <&p0_its_dsa_a 0x40080>; | 1046 | msi-parent = <&p0_its_dsa_a 0x40080>; |
1019 | interrupt-controller; | 1047 | interrupt-controller; |
@@ -1022,6 +1050,39 @@ | |||
1022 | }; | 1050 | }; |
1023 | }; | 1051 | }; |
1024 | 1052 | ||
1053 | p0_mbigen_dsa_a: interrupt-controller@c0080000 { | ||
1054 | compatible = "hisilicon,mbigen-v2"; | ||
1055 | reg = <0x0 0xc0080000 0x0 0x10000>; | ||
1056 | |||
1057 | mbigen_dsaf0: intc_dsaf0 { | ||
1058 | msi-parent = <&p0_its_dsa_a 0x40800>; | ||
1059 | interrupt-controller; | ||
1060 | #interrupt-cells = <2>; | ||
1061 | num-pins = <409>; | ||
1062 | }; | ||
1063 | |||
1064 | mbigen_dsa_roce: intc-roce { | ||
1065 | msi-parent = <&p0_its_dsa_a 0x40B1E>; | ||
1066 | interrupt-controller; | ||
1067 | #interrupt-cells = <2>; | ||
1068 | num-pins = <34>; | ||
1069 | }; | ||
1070 | |||
1071 | mbigen_sas0: intc-sas0 { | ||
1072 | msi-parent = <&p0_its_dsa_a 0x40900>; | ||
1073 | interrupt-controller; | ||
1074 | #interrupt-cells = <2>; | ||
1075 | num-pins = <128>; | ||
1076 | }; | ||
1077 | |||
1078 | mbigen_smmu_dsa: intc_smmu_dsa { | ||
1079 | msi-parent = <&p0_its_dsa_a 0x40b20>; | ||
1080 | interrupt-controller; | ||
1081 | #interrupt-cells = <2>; | ||
1082 | num-pins = <3>; | ||
1083 | }; | ||
1084 | }; | ||
1085 | |||
1025 | soc { | 1086 | soc { |
1026 | compatible = "simple-bus"; | 1087 | compatible = "simple-bus"; |
1027 | #address-cells = <2>; | 1088 | #address-cells = <2>; |
@@ -1055,5 +1116,423 @@ | |||
1055 | dma-coherent; | 1116 | dma-coherent; |
1056 | status = "disabled"; | 1117 | status = "disabled"; |
1057 | }; | 1118 | }; |
1119 | |||
1120 | peri_c_subctrl: sub_ctrl_c@60000000 { | ||
1121 | compatible = "hisilicon,peri-subctrl","syscon"; | ||
1122 | reg = <0 0x60000000 0x0 0x10000>; | ||
1123 | }; | ||
1124 | |||
1125 | dsa_subctrl: dsa_subctrl@c0000000 { | ||
1126 | compatible = "hisilicon,dsa-subctrl", "syscon"; | ||
1127 | reg = <0x0 0xc0000000 0x0 0x10000>; | ||
1128 | }; | ||
1129 | |||
1130 | pcie_subctl: pcie_subctl@a0000000 { | ||
1131 | compatible = "hisilicon,pcie-sas-subctrl", "syscon"; | ||
1132 | reg = <0x0 0xa0000000 0x0 0x10000>; | ||
1133 | }; | ||
1134 | |||
1135 | serdes_ctrl: sds_ctrl@c2200000 { | ||
1136 | compatible = "syscon"; | ||
1137 | reg = <0 0xc2200000 0x0 0x80000>; | ||
1138 | }; | ||
1139 | |||
1140 | mdio@603c0000 { | ||
1141 | compatible = "hisilicon,hns-mdio"; | ||
1142 | reg = <0x0 0x603c0000 0x0 0x1000>; | ||
1143 | subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 | ||
1144 | 0x531c 0x5a1c>; | ||
1145 | #address-cells = <1>; | ||
1146 | #size-cells = <0>; | ||
1147 | |||
1148 | phy0: ethernet-phy@0 { | ||
1149 | compatible = "ethernet-phy-ieee802.3-c22"; | ||
1150 | reg = <0>; | ||
1151 | }; | ||
1152 | |||
1153 | phy1: ethernet-phy@1 { | ||
1154 | compatible = "ethernet-phy-ieee802.3-c22"; | ||
1155 | reg = <1>; | ||
1156 | }; | ||
1157 | }; | ||
1158 | |||
1159 | dsaf0: dsa@c7000000 { | ||
1160 | #address-cells = <1>; | ||
1161 | #size-cells = <0>; | ||
1162 | compatible = "hisilicon,hns-dsaf-v2"; | ||
1163 | mode = "6port-16rss"; | ||
1164 | reg = <0x0 0xc5000000 0x0 0x890000 | ||
1165 | 0x0 0xc7000000 0x0 0x600000>; | ||
1166 | reg-names = "ppe-base", "dsaf-base"; | ||
1167 | interrupt-parent = <&mbigen_dsaf0>; | ||
1168 | subctrl-syscon = <&dsa_subctrl>; | ||
1169 | reset-field-offset = <0>; | ||
1170 | interrupts = | ||
1171 | <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, | ||
1172 | <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, | ||
1173 | <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, | ||
1174 | <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, | ||
1175 | <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, | ||
1176 | <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, | ||
1177 | <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, | ||
1178 | <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, | ||
1179 | <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, | ||
1180 | <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, | ||
1181 | <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, | ||
1182 | <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, | ||
1183 | <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, | ||
1184 | <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, | ||
1185 | <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, | ||
1186 | <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, | ||
1187 | <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, | ||
1188 | <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, | ||
1189 | <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, | ||
1190 | <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, | ||
1191 | <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, | ||
1192 | <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, | ||
1193 | <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, | ||
1194 | <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, | ||
1195 | <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, | ||
1196 | <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, | ||
1197 | <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, | ||
1198 | <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, | ||
1199 | <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, | ||
1200 | <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, | ||
1201 | <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, | ||
1202 | <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, | ||
1203 | <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, | ||
1204 | <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, | ||
1205 | <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, | ||
1206 | <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, | ||
1207 | <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, | ||
1208 | <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, | ||
1209 | <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, | ||
1210 | <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, | ||
1211 | <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, | ||
1212 | <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, | ||
1213 | <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, | ||
1214 | <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, | ||
1215 | <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, | ||
1216 | <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, | ||
1217 | <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, | ||
1218 | <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, | ||
1219 | <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, | ||
1220 | <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, | ||
1221 | <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, | ||
1222 | <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, | ||
1223 | <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, | ||
1224 | <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, | ||
1225 | <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, | ||
1226 | <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, | ||
1227 | <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, | ||
1228 | <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, | ||
1229 | <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, | ||
1230 | <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, | ||
1231 | <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, | ||
1232 | <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, | ||
1233 | <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, | ||
1234 | <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, | ||
1235 | <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, | ||
1236 | <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, | ||
1237 | <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, | ||
1238 | <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, | ||
1239 | <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, | ||
1240 | <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, | ||
1241 | <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, | ||
1242 | <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, | ||
1243 | <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, | ||
1244 | <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, | ||
1245 | <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, | ||
1246 | <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, | ||
1247 | <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, | ||
1248 | <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, | ||
1249 | <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, | ||
1250 | <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, | ||
1251 | <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, | ||
1252 | <1340 1>, <1341 1>, <1342 1>, <1343 1>; | ||
1253 | |||
1254 | desc-num = <0x400>; | ||
1255 | buf-size = <0x1000>; | ||
1256 | dma-coherent; | ||
1257 | |||
1258 | port@0 { | ||
1259 | reg = <0>; | ||
1260 | serdes-syscon = <&serdes_ctrl>; | ||
1261 | port-rst-offset = <0>; | ||
1262 | port-mode-offset = <0>; | ||
1263 | mc-mac-mask = [ff f0 00 00 00 00]; | ||
1264 | media-type = "fiber"; | ||
1265 | }; | ||
1266 | |||
1267 | port@1 { | ||
1268 | reg = <1>; | ||
1269 | serdes-syscon= <&serdes_ctrl>; | ||
1270 | port-rst-offset = <1>; | ||
1271 | port-mode-offset = <1>; | ||
1272 | mc-mac-mask = [ff f0 00 00 00 00]; | ||
1273 | media-type = "fiber"; | ||
1274 | }; | ||
1275 | |||
1276 | port@4 { | ||
1277 | reg = <4>; | ||
1278 | phy-handle = <&phy0>; | ||
1279 | serdes-syscon= <&serdes_ctrl>; | ||
1280 | port-rst-offset = <4>; | ||
1281 | port-mode-offset = <2>; | ||
1282 | mc-mac-mask = [ff f0 00 00 00 00]; | ||
1283 | media-type = "copper"; | ||
1284 | }; | ||
1285 | |||
1286 | port@5 { | ||
1287 | reg = <5>; | ||
1288 | phy-handle = <&phy1>; | ||
1289 | serdes-syscon= <&serdes_ctrl>; | ||
1290 | port-rst-offset = <5>; | ||
1291 | port-mode-offset = <3>; | ||
1292 | mc-mac-mask = [ff f0 00 00 00 00]; | ||
1293 | media-type = "copper"; | ||
1294 | }; | ||
1295 | }; | ||
1296 | |||
1297 | eth0: ethernet@4{ | ||
1298 | compatible = "hisilicon,hns-nic-v2"; | ||
1299 | ae-handle = <&dsaf0>; | ||
1300 | port-idx-in-ae = <4>; | ||
1301 | local-mac-address = [00 00 00 00 00 00]; | ||
1302 | status = "disabled"; | ||
1303 | dma-coherent; | ||
1304 | }; | ||
1305 | |||
1306 | eth1: ethernet@5{ | ||
1307 | compatible = "hisilicon,hns-nic-v2"; | ||
1308 | ae-handle = <&dsaf0>; | ||
1309 | port-idx-in-ae = <5>; | ||
1310 | local-mac-address = [00 00 00 00 00 00]; | ||
1311 | status = "disabled"; | ||
1312 | dma-coherent; | ||
1313 | }; | ||
1314 | |||
1315 | eth2: ethernet@0{ | ||
1316 | compatible = "hisilicon,hns-nic-v2"; | ||
1317 | ae-handle = <&dsaf0>; | ||
1318 | port-idx-in-ae = <0>; | ||
1319 | local-mac-address = [00 00 00 00 00 00]; | ||
1320 | status = "disabled"; | ||
1321 | dma-coherent; | ||
1322 | }; | ||
1323 | |||
1324 | eth3: ethernet@1{ | ||
1325 | compatible = "hisilicon,hns-nic-v2"; | ||
1326 | ae-handle = <&dsaf0>; | ||
1327 | port-idx-in-ae = <1>; | ||
1328 | local-mac-address = [00 00 00 00 00 00]; | ||
1329 | status = "disabled"; | ||
1330 | dma-coherent; | ||
1331 | }; | ||
1332 | |||
1333 | infiniband@c4000000 { | ||
1334 | compatible = "hisilicon,hns-roce-v1"; | ||
1335 | reg = <0x0 0xc4000000 0x0 0x100000>; | ||
1336 | dma-coherent; | ||
1337 | eth-handle = <ð2 ð3 0 0 ð0 ð1>; | ||
1338 | dsaf-handle = <&dsaf0>; | ||
1339 | node-guid = [00 9A CD 00 00 01 02 03]; | ||
1340 | #address-cells = <2>; | ||
1341 | #size-cells = <2>; | ||
1342 | interrupt-parent = <&mbigen_dsa_roce>; | ||
1343 | interrupts = <722 1>, | ||
1344 | <723 1>, | ||
1345 | <724 1>, | ||
1346 | <725 1>, | ||
1347 | <726 1>, | ||
1348 | <727 1>, | ||
1349 | <728 1>, | ||
1350 | <729 1>, | ||
1351 | <730 1>, | ||
1352 | <731 1>, | ||
1353 | <732 1>, | ||
1354 | <733 1>, | ||
1355 | <734 1>, | ||
1356 | <735 1>, | ||
1357 | <736 1>, | ||
1358 | <737 1>, | ||
1359 | <738 1>, | ||
1360 | <739 1>, | ||
1361 | <740 1>, | ||
1362 | <741 1>, | ||
1363 | <742 1>, | ||
1364 | <743 1>, | ||
1365 | <744 1>, | ||
1366 | <745 1>, | ||
1367 | <746 1>, | ||
1368 | <747 1>, | ||
1369 | <748 1>, | ||
1370 | <749 1>, | ||
1371 | <750 1>, | ||
1372 | <751 1>, | ||
1373 | <752 1>, | ||
1374 | <753 1>, | ||
1375 | <785 1>, | ||
1376 | <754 4>; | ||
1377 | |||
1378 | interrupt-names = "hns-roce-comp-0", | ||
1379 | "hns-roce-comp-1", | ||
1380 | "hns-roce-comp-2", | ||
1381 | "hns-roce-comp-3", | ||
1382 | "hns-roce-comp-4", | ||
1383 | "hns-roce-comp-5", | ||
1384 | "hns-roce-comp-6", | ||
1385 | "hns-roce-comp-7", | ||
1386 | "hns-roce-comp-8", | ||
1387 | "hns-roce-comp-9", | ||
1388 | "hns-roce-comp-10", | ||
1389 | "hns-roce-comp-11", | ||
1390 | "hns-roce-comp-12", | ||
1391 | "hns-roce-comp-13", | ||
1392 | "hns-roce-comp-14", | ||
1393 | "hns-roce-comp-15", | ||
1394 | "hns-roce-comp-16", | ||
1395 | "hns-roce-comp-17", | ||
1396 | "hns-roce-comp-18", | ||
1397 | "hns-roce-comp-19", | ||
1398 | "hns-roce-comp-20", | ||
1399 | "hns-roce-comp-21", | ||
1400 | "hns-roce-comp-22", | ||
1401 | "hns-roce-comp-23", | ||
1402 | "hns-roce-comp-24", | ||
1403 | "hns-roce-comp-25", | ||
1404 | "hns-roce-comp-26", | ||
1405 | "hns-roce-comp-27", | ||
1406 | "hns-roce-comp-28", | ||
1407 | "hns-roce-comp-29", | ||
1408 | "hns-roce-comp-30", | ||
1409 | "hns-roce-comp-31", | ||
1410 | "hns-roce-async", | ||
1411 | "hns-roce-common"; | ||
1412 | }; | ||
1413 | |||
1414 | sas0: sas@c3000000 { | ||
1415 | compatible = "hisilicon,hip07-sas-v2"; | ||
1416 | reg = <0 0xc3000000 0 0x10000>; | ||
1417 | sas-addr = [50 01 88 20 16 00 00 00]; | ||
1418 | hisilicon,sas-syscon = <&dsa_subctrl>; | ||
1419 | ctrl-reset-reg = <0xa60>; | ||
1420 | ctrl-reset-sts-reg = <0x5a30>; | ||
1421 | ctrl-clock-ena-reg = <0x338>; | ||
1422 | queue-count = <16>; | ||
1423 | phy-count = <8>; | ||
1424 | dma-coherent; | ||
1425 | interrupt-parent = <&mbigen_sas0>; | ||
1426 | interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, | ||
1427 | <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, | ||
1428 | <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, | ||
1429 | <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, | ||
1430 | <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, | ||
1431 | <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, | ||
1432 | <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, | ||
1433 | <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, | ||
1434 | <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, | ||
1435 | <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, | ||
1436 | <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, | ||
1437 | <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, | ||
1438 | <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, | ||
1439 | <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, | ||
1440 | <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, | ||
1441 | <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, | ||
1442 | <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, | ||
1443 | <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, | ||
1444 | <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, | ||
1445 | <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, | ||
1446 | <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, | ||
1447 | <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, | ||
1448 | <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, | ||
1449 | <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, | ||
1450 | <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, | ||
1451 | <630 1>,<631 1>,<632 1>; | ||
1452 | status = "disabled"; | ||
1453 | }; | ||
1454 | |||
1455 | sas1: sas@a2000000 { | ||
1456 | compatible = "hisilicon,hip07-sas-v2"; | ||
1457 | reg = <0 0xa2000000 0 0x10000>; | ||
1458 | sas-addr = [50 01 88 20 16 00 00 00]; | ||
1459 | hisilicon,sas-syscon = <&pcie_subctl>; | ||
1460 | hip06-sas-v2-quirk-amt; | ||
1461 | ctrl-reset-reg = <0xa18>; | ||
1462 | ctrl-reset-sts-reg = <0x5a0c>; | ||
1463 | ctrl-clock-ena-reg = <0x318>; | ||
1464 | queue-count = <16>; | ||
1465 | phy-count = <8>; | ||
1466 | dma-coherent; | ||
1467 | interrupt-parent = <&mbigen_sas1>; | ||
1468 | interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, | ||
1469 | <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, | ||
1470 | <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, | ||
1471 | <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, | ||
1472 | <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, | ||
1473 | <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, | ||
1474 | <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, | ||
1475 | <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, | ||
1476 | <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, | ||
1477 | <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, | ||
1478 | <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, | ||
1479 | <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, | ||
1480 | <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, | ||
1481 | <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, | ||
1482 | <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, | ||
1483 | <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, | ||
1484 | <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, | ||
1485 | <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, | ||
1486 | <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, | ||
1487 | <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, | ||
1488 | <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, | ||
1489 | <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, | ||
1490 | <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, | ||
1491 | <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, | ||
1492 | <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, | ||
1493 | <605 1>,<606 1>,<607 1>; | ||
1494 | status = "disabled"; | ||
1495 | }; | ||
1496 | |||
1497 | sas2: sas@a3000000 { | ||
1498 | compatible = "hisilicon,hip07-sas-v2"; | ||
1499 | reg = <0 0xa3000000 0 0x10000>; | ||
1500 | sas-addr = [50 01 88 20 16 00 00 00]; | ||
1501 | hisilicon,sas-syscon = <&pcie_subctl>; | ||
1502 | ctrl-reset-reg = <0xae0>; | ||
1503 | ctrl-reset-sts-reg = <0x5a70>; | ||
1504 | ctrl-clock-ena-reg = <0x3a8>; | ||
1505 | queue-count = <16>; | ||
1506 | phy-count = <9>; | ||
1507 | dma-coherent; | ||
1508 | interrupt-parent = <&mbigen_sas2>; | ||
1509 | interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, | ||
1510 | <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, | ||
1511 | <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, | ||
1512 | <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, | ||
1513 | <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, | ||
1514 | <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, | ||
1515 | <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, | ||
1516 | <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, | ||
1517 | <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, | ||
1518 | <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, | ||
1519 | <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, | ||
1520 | <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, | ||
1521 | <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, | ||
1522 | <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, | ||
1523 | <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, | ||
1524 | <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, | ||
1525 | <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, | ||
1526 | <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, | ||
1527 | <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, | ||
1528 | <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, | ||
1529 | <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, | ||
1530 | <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, | ||
1531 | <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, | ||
1532 | <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, | ||
1533 | <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, | ||
1534 | <637 1>,<638 1>,<639 1>; | ||
1535 | status = "disabled"; | ||
1536 | }; | ||
1058 | }; | 1537 | }; |
1059 | }; | 1538 | }; |
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h index 38f1ea879ea1..0359bfdc9119 100644 --- a/include/dt-bindings/pinctrl/hisi.h +++ b/include/dt-bindings/pinctrl/hisi.h | |||
@@ -56,4 +56,19 @@ | |||
56 | #define DRIVE4_08MA (4 << 4) | 56 | #define DRIVE4_08MA (4 << 4) |
57 | #define DRIVE4_10MA (6 << 4) | 57 | #define DRIVE4_10MA (6 << 4) |
58 | 58 | ||
59 | /* drive strength definition for hi3660 */ | ||
60 | #define DRIVE6_MASK (15 << 4) | ||
61 | #define DRIVE6_04MA (0 << 4) | ||
62 | #define DRIVE6_12MA (4 << 4) | ||
63 | #define DRIVE6_19MA (8 << 4) | ||
64 | #define DRIVE6_27MA (10 << 4) | ||
65 | #define DRIVE6_32MA (15 << 4) | ||
66 | #define DRIVE7_02MA (0 << 4) | ||
67 | #define DRIVE7_04MA (1 << 4) | ||
68 | #define DRIVE7_06MA (2 << 4) | ||
69 | #define DRIVE7_08MA (3 << 4) | ||
70 | #define DRIVE7_10MA (4 << 4) | ||
71 | #define DRIVE7_12MA (5 << 4) | ||
72 | #define DRIVE7_14MA (6 << 4) | ||
73 | #define DRIVE7_16MA (7 << 4) | ||
59 | #endif | 74 | #endif |