diff options
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c')
-rw-r--r-- | drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 6ac04fc303f5..e4e9bf04b736 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | |||
@@ -559,6 +559,7 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) | |||
559 | struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; | 559 | struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; |
560 | void __iomem *phy_base = pll_10nm->phy_cmn_mmio; | 560 | void __iomem *phy_base = pll_10nm->phy_cmn_mmio; |
561 | u32 val; | 561 | u32 val; |
562 | int ret; | ||
562 | 563 | ||
563 | val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); | 564 | val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); |
564 | val &= ~0x3; | 565 | val &= ~0x3; |
@@ -573,6 +574,13 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) | |||
573 | val |= cached->pll_mux; | 574 | val |= cached->pll_mux; |
574 | pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); | 575 | pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); |
575 | 576 | ||
577 | ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); | ||
578 | if (ret) { | ||
579 | DRM_DEV_ERROR(&pll_10nm->pdev->dev, | ||
580 | "restore vco rate failed. ret=%d\n", ret); | ||
581 | return ret; | ||
582 | } | ||
583 | |||
576 | DBG("DSI PLL%d", pll_10nm->id); | 584 | DBG("DSI PLL%d", pll_10nm->id); |
577 | 585 | ||
578 | return 0; | 586 | return 0; |