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Diffstat (limited to 'drivers/nvmem/imx-ocotp.c')
-rw-r--r--drivers/nvmem/imx-ocotp.c39
1 files changed, 34 insertions, 5 deletions
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 926d9cc080cf..09281aca86c2 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -50,7 +50,9 @@
50#define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 50#define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
51#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 51#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
52 52
53#define DEF_RELAX 20 /* > 16.5ns */ 53#define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */
54#define TIMING_STROBE_READ_NS 37 /* Min time before read */
55#define TIMING_RELAX_NS 17
54#define DEF_FSOURCE 1001 /* > 1000 ns */ 56#define DEF_FSOURCE 1001 /* > 1000 ns */
55#define DEF_STROBE_PROG 10000 /* IPG clocks */ 57#define DEF_STROBE_PROG 10000 /* IPG clocks */
56#define IMX_OCOTP_WR_UNLOCK 0x3E770000 58#define IMX_OCOTP_WR_UNLOCK 0x3E770000
@@ -182,14 +184,41 @@ static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
182 * fields with timing values to match the current frequency of the 184 * fields with timing values to match the current frequency of the
183 * ipg_clk. OTP writes will work at maximum bus frequencies as long 185 * ipg_clk. OTP writes will work at maximum bus frequencies as long
184 * as the HW_OCOTP_TIMING parameters are set correctly. 186 * as the HW_OCOTP_TIMING parameters are set correctly.
187 *
188 * Note: there are minimum timings required to ensure an OTP fuse burns
189 * correctly that are independent of the ipg_clk. Those values are not
190 * formally documented anywhere however, working from the minimum
191 * timings given in u-boot we can say:
192 *
193 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
194 * microseconds feels about right as representative of a minimum time
195 * to physically burn out a fuse.
196 *
197 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
198 * performing another read is 37 nanoseconds
199 *
200 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
201 * timing is not entirely clear the documentation says "This
202 * count value specifies the time to add to all default timing
203 * parameters other than the Tpgm and Trd. It is given in number
204 * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
205 * and STROBE_READ respectively. What the other timing parameters
206 * are though, is not specified. Experience shows a zero RELAX
207 * value will mess up a re-load of the shadow registers post OTP
208 * burn.
185 */ 209 */
186 clk_rate = clk_get_rate(priv->clk); 210 clk_rate = clk_get_rate(priv->clk);
187 211
188 relax = clk_rate / (1000000000 / DEF_RELAX) - 1; 212 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
189 strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; 213 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
190 strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; 214 1000000000);
215 strobe_read += 2 * (relax + 1) - 1;
216 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
217 1000000);
218 strobe_prog += 2 * (relax + 1) - 1;
191 219
192 timing = strobe_prog & 0x00000FFF; 220 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
221 timing |= strobe_prog & 0x00000FFF;
193 timing |= (relax << 12) & 0x0000F000; 222 timing |= (relax << 12) & 0x0000F000;
194 timing |= (strobe_read << 16) & 0x003F0000; 223 timing |= (strobe_read << 16) & 0x003F0000;
195 224