1 files changed, 15 insertions, 1 deletions

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 1bdac298a943..33e510393976 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -108,6 +108,7 @@ struct qcom_pcie_resources_2_1_0 {
         struct reset_control *ahb_reset;
         struct reset_control *por_reset;
         struct reset_control *phy_reset;
+        struct reset_control *ext_reset;
         struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
 };
 
@@ -269,6 +270,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
         if (IS_ERR(res->por_reset))
                 return PTR_ERR(res->por_reset);
 
+        res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
+        if (IS_ERR(res->ext_reset))
+                return PTR_ERR(res->ext_reset);
+
         res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
         return PTR_ERR_OR_ZERO(res->phy_reset);
 }
@@ -281,6 +286,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
         reset_control_assert(res->axi_reset);
         reset_control_assert(res->ahb_reset);
         reset_control_assert(res->por_reset);
+        reset_control_assert(res->ext_reset);
         reset_control_assert(res->pci_reset);
         clk_disable_unprepare(res->iface_clk);
         clk_disable_unprepare(res->core_clk);
@@ -333,6 +339,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
                 goto err_deassert_ahb;
         }
 
+        ret = reset_control_deassert(res->ext_reset);
+        if (ret) {
+                dev_err(dev, "cannot deassert ext reset\n");
+                goto err_deassert_ahb;
+        }
+
         /* enable PCIe clocks and resets */
         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
         val &= ~BIT(0);
@@ -359,7 +371,9 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 
         /* enable external reference clock */
         val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
-        val &= ~PHY_REFCLK_USE_PAD;
+        /* USE_PAD is required only for ipq806x */
+        if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
+                val &= ~PHY_REFCLK_USE_PAD;
         val |= PHY_REFCLK_SSP_EN;
         writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);