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* Merge tag 'arc-4.12-rc1' of ↵HEADmasterLinus Torvalds2017-05-0910-25/+197
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - AXS10x platform clk updates for I2S, PGU - add region based cache flush operation for ARCv2 cores - enforce PAE40 dependency on HIGHMEM - ptrace support for additional regs in ARCv2 cores - fix build failure in linux-next dut to a header include ordering change * tag 'arc-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: Revert "ARCv2: Allow enabling PAE40 w/o HIGHMEM" ARC: mm: fix build failure in linux-next for UP builds ARCv2: ptrace: provide regset for accumulator/r30 regs elf: Add ARCv2 specific core note section ARCv2: mm: micro-optimize region flush generated code ARCv2: mm: Merge 2 updates to DC_CTRL for region flush ARCv2: mm: Implement cache region flush operations ARC: mm: Move full_page computation into cache version agnostic wrapper arc: axs10x: Fix ARC PGU default clock frequency arc: axs10x: Add DT bindings for I2S audio playback
| * Revert "ARCv2: Allow enabling PAE40 w/o HIGHMEM"Alexey Brodkin2017-05-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7cab91b87dd8eeee5911ec34be8bb0288ebba18b. Now when we have a real hardware platform with PAE40 enabled (here I mean axs103 with firmware v1.2) and 1 Gb of DDR mapped to 0x1_a000_0000-0x1_ffff_ffff we're really targeting memory above 4Gb when PAE40 is enabled. This in its turn requires HIGHMEM to be enabled otherwise user won't see any difference with enabling PAE in kernel configuration as only lowmem will be used anyways. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: mm: fix build failure in linux-next for UP buildsVineet Gupta2017-05-052-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kisskb build service reported ARC defconfig build failures in linux-next | arch/arc/include/asm/mmu.h:75:21: error: 'NR_CPUS' undeclared here (not in a function) | make[3]: *** [arch/arc/mm/ioremap.o] Error 1 | make[2]: *** [arch/arc/mm] Error 2 | make[1]: *** [arch/arc] Error 2 which I bisected to a subtle side-effect of a totally benign mm patch ("mm, vmalloc: properly track vmalloc users") which caused a header include chain deviation - asm/mmu.h using NR_CPUS before including linux/threads.h Fix that by adding the dependnet header and while it at fix a related header to include linux headers aheads of asm headers as sometimes that slso triggers such issues ! Reported-by: noreply@ellerman.id.au Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARCv2: ptrace: provide regset for accumulator/r30 regsVineet Gupta2017-05-033-3/+65
| | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * elf: Add ARCv2 specific core note sectionVineet Gupta2017-05-031-1/+1
| | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARCv2: mm: micro-optimize region flush generated codeVineet Gupta2017-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DC_CTRL.RGN_OP is 3 bits wide, however only 1 bit is used in current programming model (0: flush, 1: invalidate) The current code targetting 3 bits leads to additional 8 byte AND operation which can be elided given that only 1 bit is ever set by software and/or looked at by hardware before ------ | 80b63324 <__dma_cache_wback_inv_l1>: | 80b63324: clri r3 | 80b63328: lr r2,[dc_ctrl] | 80b6332c: and r2,r2,0xfffff1ff <--- 8 bytes insn | 80b63334: or r2,r2,576 | 80b63338: sr r2,[dc_ctrl] | ... | ... | 80b63360 <__dma_cache_inv_l1>: | 80b63360: clri r3 | 80b63364: lr r2,[dc_ctrl] | 80b63368: and r2,r2,0xfffff1ff <--- 8 bytes insn | 80b63370: bset_s r2,r2,0x9 | 80b63372: sr r2,[dc_ctrl] | ... | ... | 80b6338c <__dma_cache_wback_l1>: | 80b6338c: clri r3 | 80b63390: lr r2,[dc_ctrl] | 80b63394: and r2,r2,0xfffff1ff <--- 8 bytes insn | 80b6339c: sr r2,[dc_ctrl] after (AND elided totally in 2 cases, replaced with 2 byte BCLR in 3rd) ----- | 80b63324 <__dma_cache_wback_inv_l1>: | 80b63324: clri r3 | 80b63328: lr r2,[dc_ctrl] | 80b6332c: or r2,r2,576 | 80b63330: sr r2,[dc_ctrl] | ... | ... | 80b63358 <__dma_cache_inv_l1>: | 80b63358: clri r3 | 80b6335c: lr r2,[dc_ctrl] | 80b63360: bset_s r2,r2,0x9 | 80b63362: sr r2,[dc_ctrl] | ... | ... | 80b6337c <__dma_cache_wback_l1>: | 80b6337c: clri r3 | 80b63380: lr r2,[dc_ctrl] | 80b63384: bclr_s r2,r2,0x9 | 80b63386: sr r2,[dc_ctrl] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARCv2: mm: Merge 2 updates to DC_CTRL for region flushVineet Gupta2017-05-021-14/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Region Flush has a weird programming model. 1. Flush or Invalidate is selected by DC_CTRL.RGN_OP 2 Flush-n-Invalidate is done by DC_CTRL.IM Given the code structuring before, case #2 above was generating two seperate updates to DC_CTRL which was pointless. | 80a342b0 <__dma_cache_wback_inv_l1>: | 80a342b0: clri r4 | 80a342b4: lr r2,[dc_ctrl] | 80a342b8: bset_s r2,r2,0x6 | 80a342ba: sr r2,[dc_ctrl] <-- FIRST | | 80a342be: bmskn r3,r0,0x5 | | 80a342c2: lr r2,[dc_ctrl] | 80a342c6: and r2,r2,0xfffff1ff | 80a342ce: bset_s r2,r2,0x9 | 80a342d0: sr r2,[dc_ctrl] <-- SECOND | | 80a342d4: add_s r1,r1,0x3f | 80a342d6: bmsk_s r0,r0,0x5 | 80a342d8: add_s r0,r0,r1 | 80a342da: add_s r0,r0,r3 | 80a342dc: sr r0,[78] | 80a342e0: sr r3,[77] |... |... So move setting of DC_CTRL.RGN_OP into __before_dc_op() and combine with any other update. | 80b63324 <__dma_cache_wback_inv_l1>: | 80b63324: clri r3 | 80b63328: lr r2,[dc_ctrl] | 80b6332c: and r2,r2,0xfffff1ff | 80b63334: or r2,r2,576 | 80b63338: sr r2,[dc_ctrl] | | 80b6333c: add_s r1,r1,0x3f | 80b6333e: bmskn r2,r0,0x5 | 80b63342: add_s r0,r0,r1 | 80b63344: sr r0,[78] | 80b63348: sr r2,[77] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARCv2: mm: Implement cache region flush operationsVineet Gupta2017-05-022-0/+74
| | | | | | | | | | | | These are more efficient than the per-line ops Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * ARC: mm: Move full_page computation into cache version agnostic wrapperVineet Gupta2017-05-021-13/+12
| | | | | | | | | | | | This reduces code duplication in each of cache version specific handlers Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * arc: axs10x: Fix ARC PGU default clock frequencyJose Abreu2017-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Default clock frequency for ARC PGU does not match any existing HDMI mode, instead the default value matches a DVI mode. Change the clock frequency to 74.25MHz so that it matches HDMI mode 1280x720@60Hz Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: Carlos Palminha <palminha@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: devicetree@vger.kernel.org Cc: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * arc: axs10x: Add DT bindings for I2S audio playbackJose Abreu2017-04-271-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary DT bindings to get HDMI audio output in ARC AXS10x SDP. The bindings for I2S controller were added as well as the bindings for simple audio card. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: Carlos Palminha <palminha@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: devicetree@vger.kernel.org Cc: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* | Merge tag 'armsoc-dt64' of ↵Linus Torvalds2017-05-09130-1401/+11043
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Olof Johansson: "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller changes, but also some new platforms that are worth mentioning: - Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook Plus (Kevin) - Orange Pi PC2 (Allwinner H5) - Freescale LS2088A and LS1088A SoCs - Expanded support for Nvidia Tegra186 (and Jetson TX2)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits) arm64: dts: Add basic DT to support Spreadtrum's SP9860G arm64: dts: exynos: Use - instead of @ for DT OPP entries arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board arm64: dts: juno: add information about L1 and L2 caches arm64: dts: juno: fix few unit address format warnings arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB arm64: marvell: dts: add crypto engine description for 7k/8k arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: rockchip: fix the memory size of PX5 Evaluation board arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board ...
| * | arm64: dts: Add basic DT to support Spreadtrum's SP9860GOrson Zhai2017-04-274-1/+698
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum. According to regular hierarchy of sprd dts, whale2.dtsi contains SoC peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff and sp9860g dts is for the board level. Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | Merge tag 'samsung-dt64-4.12-3' of ↵Arnd Bergmann2017-04-273-49/+60
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64 Pull "Second update of Samsung DeviceTree ARM64 for v4.12" from Krzysztof Kozłowski: - Fix DTC warnings in Exynos ARM64 Device Tree sources. - Add panel node to TM2E board. * tag 'samsung-dt64-4.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Use - instead of @ for DT OPP entries arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
| | * | arm64: dts: exynos: Use - instead of @ for DT OPP entriesViresh Kumar2017-04-242-49/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Rob Herring <robh@kernel.org> [k.kozlowski: Split patch per ARM and ARM64] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| | * | arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e boardHoegeun Kwon2017-04-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the panel device tree node for s6e3hf2 display controller to TM2e dts. Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * | | Merge tag 'juno-fixes-4.12' of ↵Arnd Bergmann2017-04-275-8/+134
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64 Pull "ARMv8 Juno DT fixes for v4.12" from Sudeep Holla: 1. Couple of fixes to remove device tree warnings introduced with recently added checks in DTC 2. Add information about L1 and L2 caches to Juno device trees as CCSIDR-based cacheinfo probing is now removed * tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: add information about L1 and L2 caches arm64: dts: juno: fix few unit address format warnings arm64: dts: juno: fix PCI bus dtc warnings
| | * | | arm64: dts: juno: add information about L1 and L2 cachesSudeep Holla2017-04-193-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing") removed mechanism to extract cache information based on CCSIDR register as the architecture explicitly states no inference about the actual sizes of caches based on CCSIDR registers. Commit 9a802431c527 ("arm64: cacheinfo: add support to override cache levels via device tree") had already provided options to override cache information from the device tree. This patch adds the information about L1 and L2 caches on all variants of Juno platform. Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| | * | | arm64: dts: juno: fix few unit address format warningsSudeep Holla2017-04-192-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following set of warnings on juno. smb@08000000 unit name should not have leading 0s sysctl@020000 simple-bus unit address format error, expected "20000" apbregs@010000 simple-bus unit address format error, expected "10000" mmci@050000 simple-bus unit address format error, expected "50000" kmi@060000 simple-bus unit address format error, expected "60000" kmi@070000 simple-bus unit address format error, expected "70000" wdt@0f0000 simple-bus unit address format error, expected "f0000" Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| | * | | arm64: dts: juno: fix PCI bus dtc warningsRob Herring2017-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * | | | Merge tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson2017-04-197-0/+107
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt64 mvebu dt64 for 4.12 (part 2) - crypto engine description for the Armada 7k/8k SoCs and the boards using it - SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards using it * tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu: arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB arm64: marvell: dts: add crypto engine description for 7k/8k arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: dts: marvell: add eMMC support for Armada 37xx Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | arm64: marvell: dts: enable the crypto engine on the Armada 8040 DBAntoine Tenart2017-04-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the cryptographic engine available in the CP110 master on the Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we do not support multiple cryptographic engines yet. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | | | arm64: marvell: dts: enable the crypto engine on the Armada 7040 DBAntoine Tenart2017-04-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the cryptographic engine available in the CP110 master on the Armada 7040 DB. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | | | arm64: marvell: dts: add crypto engine description for 7k/8kAntoine Tenart2017-04-122-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the description of the crypto engine hardware block for the Marvell Armada 7k and Armada 8k processors; for both the CP110 slave and master. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | | | arm64: dts: marvell: add sdhci support for Armada 7K/8KGregory CLEMENT2017-04-114-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also enable it on the Armada 7040 DB and Armada 8040 DB boards. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | | | arm64: dts: marvell: add eMMC support for Armada 37xxGregory CLEMENT2017-04-112-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * | | | | Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi ↵Olof Johansson2017-04-1910-0/+1507
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/dt64 ARM64: DT: Hisilicon SoC DT updates for 4.12 - Reset the hi6220 mmc hosts to avoid hang - Add the binding for the hi3798cv200 SoC and the poplar board - Add basic dts files to support the hi3798cv200 poplar board - Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board - Add driver strength MACRO for the hi3660 SoC - Add the pinctrl dtsi file for hikey960 board to configure the pins * tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board arm64: dts: hi6220: Reset the mmc hosts Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development boardWang Xiaoyin2017-04-102-0/+408
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl dtsi file for HiKey960 development board, enable 5 pinmux devices and 1 pinconf device, also include some nodes of configurations for pins. Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoCWang Xiaoyin2017-04-101-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend drive strength levels of the pins for Hi3660 Soc. Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 boardWei Xu2017-04-101-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the NIC and SAS nodes for the hip07-d05 board to support related functions. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hisi: add SAS nodes for the hip07 SoCWei Xu2017-04-081-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 3 SAS host controller nodes and the dependent subctrl node to enable the SAS and SATA function for the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hisi: add RoCE nodes for the hip07 SoCWei Xu2017-04-071-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the infiniband node to support the RoCE function on the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hisi: add network related nodes for the hip07 SoCWei Xu2017-04-071-0/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MDIO, SerDes, Port and realted HNS nodes to support the network on the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hisi: add mbigen nodes for the hip07 SoCWei Xu2017-04-071-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mbigen nodes for the hip07 SoC those will be used for the SAS, XGE and PCIe host controllers. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hisilicon: add dts files for hi3798cv200-poplar boardJiancheng Xue2017-04-063-0/+574
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic dts files for hi3798cv200-poplar board. Poplar is the first development board compliant with the 96Boards Enterprise Edition TV Platform specification. The board features the Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53 processor and high performance Mali T720 GPU. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar boardJiancheng Xue2017-04-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bindings for HiSilicon hi3798cv200 SoC and Poplar Board. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| | * | | | | arm64: dts: hi6220: Reset the mmc hostsDaniel Lezcano2017-04-051-0/+3
| | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC hosts could be left in an unconsistent or uninitialized state from the firmware. Instead of assuming, the firmware did the right things, let's reset the host controllers. This change fixes a bug when the mmc2/sdio is initialized leading to a hung task: [ 242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds. [ 242.711129] Not tainted 4.9.0-rc8-00017-gcf0251f #3 [ 242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 242.724435] kworker/7:1 D 0 675 2 0x00000000 [ 242.729973] Workqueue: events_freezable mmc_rescan [ 242.734796] Call trace: [ 242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4 [ 242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c [ 242.747689] [<ffff000008d08254>] schedule+0x40/0xa0 [ 242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c [ 242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c [ 242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34 [ 242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124 [ 242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8 [ 242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84 [ 242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114 [ 242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c [ 242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360 [ ... ] Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | | | | Merge tag 'zte-dt64-4.12' of ↵Olof Johansson2017-04-192-7/+147
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 ZTE arm64 device tree updates for 4.12: - Add mmc devices for ZX296718 SoC and enable those available on zx296718-evb board. - Add VOU controller device, output devices HDMI and TVENC, and enable display support for zx296718-evb board. - Remove pll_vga clock from ZX296718 device tree, as it's not a fixed rate clock. * tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: zte: add tvenc device for zx296718 arm64: dts: zte: add vou and hdmi devices for zx296718 arm64: dts: zte: add mmc devices for zx296718 arm64: dts: zte: remove zx296718 pll_vga clock Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | arm64: dts: zte: add tvenc device for zx296718Shawn Guo2017-03-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds VOU tvenc device in zx296718.dtsi, so that boards with TV connector can enable the support by changing 'status' in board DTS file. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | arm64: dts: zte: add vou and hdmi devices for zx296718Shawn Guo2017-03-242-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds VOU DPC device and enables HDMI support, which includes both display and audio through SPDIF interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | arm64: dts: zte: add mmc devices for zx296718Jun Nie2017-03-242-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add three mmc devices for zx296718 SoC, and enable the SD and eMMMC on zx296718-evb board. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | arm64: dts: zte: remove zx296718 pll_vga clockShawn Guo2017-03-241-7/+0
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than a fixed rate clock, pll_vga is a PLL can be programmed into different freqencies. Let's drop it from device tree and get it registered from clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | Merge tag 'imx-dt64-4.12' of ↵Olof Johansson2017-04-1921-1034/+2206
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Freescale arm64 device tree updates for 4.12: - Add support of LS2088A SoC, which is a derivative of existing LS2080A SoC, and the major difference is on ARM cores. - Add support of LS1088A SoC which includes eight Cortex-A53 cores with 32 KB L1 D-cache and I-cache respectively. - Add crypto and thermal device support for LS1012A platform. - Add ECC register region for SATA device on LS1012A, LS1043A and LS1046A platforms. * tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards dt-bindings: clockgen: Add compatible string for LS1088A arm64: dts: Add support for FSL's LS1088A SoC arm64: dts: ls1012a: add crypto node arm64: dts: ls1012a: add thermal monitor node arm64: dts: updated sata node on ls1012a platform arm64: dts: added ecc register address to sata node on ls1046a arm64: dts: added ecc register address to sata node on ls1043a arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC arm64: dts: freescale: ls2080a: Split devicetree for code resuability dt-bindings: Add compatible for LS2088A QDS and RDB board Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boardsHarninder Rai2017-04-041-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | | dt-bindings: clockgen: Add compatible string for LS1088AHarninder Rai2017-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | | arm64: dts: Add support for FSL's LS1088A SoCHarninder Rai2017-03-284-0/+507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1088A contains eight ARM v8 CortexA53 processor cores with 32 KB L1-D cache and 32 KB L1-I cache Features summary Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Arranged as two clusters of four cores sharing a 1 MB L2 cache - Speed Up to 1.5 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 700 MHz One 64-bit DDR4 SDRAM memory controller with ECC Data path acceleration architecture 2.0 (DPAA2) Three PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Three high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1088A SoC family: - fsl-ls1088a.dtsi: DTS-Include file for NXP LS1088A SoC. - fsl-ls1088a-qds.dts: DTS file for NXP LS1088A QDS board. - fsl-ls1088a-rdb.dts: DTS file for NXP LS1088A RDB board Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>` Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | | arm64: dts: ls1012a: add crypto nodeHoria Geantă2017-03-281-1/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1012A has a SEC v5.4 security engine. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | | arm64: dts: ls1012a: add thermal monitor nodeYuantian Tang2017-03-151-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a thermal monitoring unit on ls1012a soc which can monitor and record the temperature of cores so that appropriate actions can be taken or alarm the user when the temperature exceeds a programmed temperature threshold. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | | arm64: dts: updated sata node on ls1012a platformYuantian Tang2017-03-144-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | | arm64: dts: added ecc register address to sata node on ls1046aTang Yuantian2017-03-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ls1046 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>