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authorMiodrag Dinic2017-11-03 08:39:08 -0500
committerMiodrag Dinic2017-11-06 09:38:49 -0600
commitcc599273b4d67fceb0fdcd715d2d18b7eefcdd8d (patch)
tree49c7cadb685f14608a8959128747db22bc5d0ebd /libpixelflinger
parentebcfa449375fb809b266383d0036a7be3ecdac01 (diff)
downloadplatform-system-core-cc599273b4d67fceb0fdcd715d2d18b7eefcdd8d.tar.gz
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MIPS[64]: codeflinger: Fix build due to unused variable warnings
Change-Id: Ie31d44ee74a218c83774df855be496ca862af8c5 Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com>
Diffstat (limited to 'libpixelflinger')
-rw-r--r--libpixelflinger/codeflinger/MIPS64Assembler.cpp139
-rw-r--r--libpixelflinger/codeflinger/MIPSAssembler.cpp136
-rw-r--r--libpixelflinger/codeflinger/mips64_disassem.c6
-rw-r--r--libpixelflinger/codeflinger/mips_disassem.c3
4 files changed, 148 insertions, 136 deletions
diff --git a/libpixelflinger/codeflinger/MIPS64Assembler.cpp b/libpixelflinger/codeflinger/MIPS64Assembler.cpp
index d5e4cea89..d6d215679 100644
--- a/libpixelflinger/codeflinger/MIPS64Assembler.cpp
+++ b/libpixelflinger/codeflinger/MIPS64Assembler.cpp
@@ -39,6 +39,7 @@
39#include "mips64_disassem.h" 39#include "mips64_disassem.h"
40 40
41#define NOT_IMPLEMENTED() LOG_ALWAYS_FATAL("Arm instruction %s not yet implemented\n", __func__) 41#define NOT_IMPLEMENTED() LOG_ALWAYS_FATAL("Arm instruction %s not yet implemented\n", __func__)
42#define __unused __attribute__((__unused__))
42 43
43// ---------------------------------------------------------------------------- 44// ----------------------------------------------------------------------------
44 45
@@ -146,7 +147,7 @@ void ArmToMips64Assembler::prolog()
146 mMips->MOVE(R_v0, R_a0); // move context * passed in a0 to v0 (arm r0) 147 mMips->MOVE(R_v0, R_a0); // move context * passed in a0 to v0 (arm r0)
147} 148}
148 149
149void ArmToMips64Assembler::epilog(uint32_t touched) 150void ArmToMips64Assembler::epilog(uint32_t touched __unused)
150{ 151{
151 mArmPC[mInum++] = pc(); // save starting PC for this instr 152 mArmPC[mInum++] = pc(); // save starting PC for this instr
152 153
@@ -205,7 +206,7 @@ int ArmToMips64Assembler::buildImmediate(
205 206
206// shifters... 207// shifters...
207 208
208bool ArmToMips64Assembler::isValidImmediate(uint32_t immediate) 209bool ArmToMips64Assembler::isValidImmediate(uint32_t immediate __unused)
209{ 210{
210 // for MIPS, any 32-bit immediate is OK 211 // for MIPS, any 32-bit immediate is OK
211 return true; 212 return true;
@@ -225,13 +226,14 @@ uint32_t ArmToMips64Assembler::reg_imm(int Rm, int type, uint32_t shift)
225 return AMODE_REG_IMM; 226 return AMODE_REG_IMM;
226} 227}
227 228
228uint32_t ArmToMips64Assembler::reg_rrx(int Rm) 229uint32_t ArmToMips64Assembler::reg_rrx(int Rm __unused)
229{ 230{
230 // reg_rrx mode is not used in the GLLAssember code at this time 231 // reg_rrx mode is not used in the GLLAssember code at this time
231 return AMODE_UNSUPPORTED; 232 return AMODE_UNSUPPORTED;
232} 233}
233 234
234uint32_t ArmToMips64Assembler::reg_reg(int Rm, int type, int Rs) 235uint32_t ArmToMips64Assembler::reg_reg(int Rm __unused, int type __unused,
236 int Rs __unused)
235{ 237{
236 // reg_reg mode is not used in the GLLAssember code at this time 238 // reg_reg mode is not used in the GLLAssember code at this time
237 return AMODE_UNSUPPORTED; 239 return AMODE_UNSUPPORTED;
@@ -272,14 +274,15 @@ uint32_t ArmToMips64Assembler::reg_scale_pre(int Rm, int type,
272 return AMODE_REG_SCALE_PRE; 274 return AMODE_REG_SCALE_PRE;
273} 275}
274 276
275uint32_t ArmToMips64Assembler::reg_scale_post(int Rm, int type, uint32_t shift) 277uint32_t ArmToMips64Assembler::reg_scale_post(int Rm __unused, int type __unused,
278 uint32_t shift __unused)
276{ 279{
277 LOG_ALWAYS_FATAL("adr mode reg_scale_post not yet implemented\n"); 280 LOG_ALWAYS_FATAL("adr mode reg_scale_post not yet implemented\n");
278 return AMODE_UNSUPPORTED; 281 return AMODE_UNSUPPORTED;
279} 282}
280 283
281// LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0) 284// LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
282uint32_t ArmToMips64Assembler::immed8_pre(int32_t immed8, int W) 285uint32_t ArmToMips64Assembler::immed8_pre(int32_t immed8, int W __unused)
283{ 286{
284 LOG_ALWAYS_FATAL("adr mode immed8_pre not yet implemented\n"); 287 LOG_ALWAYS_FATAL("adr mode immed8_pre not yet implemented\n");
285 288
@@ -305,7 +308,7 @@ uint32_t ArmToMips64Assembler::reg_pre(int Rm, int W)
305 return AMODE_REG_PRE; 308 return AMODE_REG_PRE;
306} 309}
307 310
308uint32_t ArmToMips64Assembler::reg_post(int Rm) 311uint32_t ArmToMips64Assembler::reg_post(int Rm __unused)
309{ 312{
310 LOG_ALWAYS_FATAL("adr mode reg_post not yet implemented\n"); 313 LOG_ALWAYS_FATAL("adr mode reg_post not yet implemented\n");
311 return AMODE_UNSUPPORTED; 314 return AMODE_UNSUPPORTED;
@@ -320,12 +323,6 @@ uint32_t ArmToMips64Assembler::reg_post(int Rm)
320#pragma mark Data Processing... 323#pragma mark Data Processing...
321#endif 324#endif
322 325
323
324static const char * const dpOpNames[] = {
325 "AND", "EOR", "SUB", "RSB", "ADD", "ADC", "SBC", "RSC",
326 "TST", "TEQ", "CMP", "CMN", "ORR", "MOV", "BIC", "MVN"
327};
328
329// check if the operand registers from a previous CMP or S-bit instruction 326// check if the operand registers from a previous CMP or S-bit instruction
330// would be overwritten by this instruction. If so, move the value to a 327// would be overwritten by this instruction. If so, move the value to a
331// safe register. 328// safe register.
@@ -594,7 +591,7 @@ void ArmToMips64Assembler::dataProcessing(int opcode, int cc,
594#endif 591#endif
595 592
596// multiply, accumulate 593// multiply, accumulate
597void ArmToMips64Assembler::MLA(int cc, int s, 594void ArmToMips64Assembler::MLA(int cc __unused, int s,
598 int Rd, int Rm, int Rs, int Rn) { 595 int Rd, int Rm, int Rs, int Rn) {
599 596
600 //ALOGW("MLA"); 597 //ALOGW("MLA");
@@ -608,7 +605,7 @@ void ArmToMips64Assembler::MLA(int cc, int s,
608 } 605 }
609} 606}
610 607
611void ArmToMips64Assembler::MUL(int cc, int s, 608void ArmToMips64Assembler::MUL(int cc __unused, int s,
612 int Rd, int Rm, int Rs) { 609 int Rd, int Rm, int Rs) {
613 mArmPC[mInum++] = pc(); 610 mArmPC[mInum++] = pc();
614 mMips->MUL(Rd, Rm, Rs); 611 mMips->MUL(Rd, Rm, Rs);
@@ -618,7 +615,7 @@ void ArmToMips64Assembler::MUL(int cc, int s,
618 } 615 }
619} 616}
620 617
621void ArmToMips64Assembler::UMULL(int cc, int s, 618void ArmToMips64Assembler::UMULL(int cc __unused, int s,
622 int RdLo, int RdHi, int Rm, int Rs) { 619 int RdLo, int RdHi, int Rm, int Rs) {
623 mArmPC[mInum++] = pc(); 620 mArmPC[mInum++] = pc();
624 mMips->MUH(RdHi, Rm, Rs); 621 mMips->MUH(RdHi, Rm, Rs);
@@ -631,8 +628,8 @@ void ArmToMips64Assembler::UMULL(int cc, int s,
631 } 628 }
632} 629}
633 630
634void ArmToMips64Assembler::UMUAL(int cc, int s, 631void ArmToMips64Assembler::UMUAL(int cc __unused, int s,
635 int RdLo, int RdHi, int Rm, int Rs) { 632 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
636 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi, 633 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
637 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs); 634 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
638 // *mPC++ = (cc<<28) | (1<<23) | (1<<21) | (s<<20) | 635 // *mPC++ = (cc<<28) | (1<<23) | (1<<21) | (s<<20) |
@@ -647,8 +644,8 @@ void ArmToMips64Assembler::UMUAL(int cc, int s,
647 } 644 }
648} 645}
649 646
650void ArmToMips64Assembler::SMULL(int cc, int s, 647void ArmToMips64Assembler::SMULL(int cc __unused, int s,
651 int RdLo, int RdHi, int Rm, int Rs) { 648 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
652 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi, 649 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
653 "SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs); 650 "SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
654 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (s<<20) | 651 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (s<<20) |
@@ -662,8 +659,8 @@ void ArmToMips64Assembler::SMULL(int cc, int s,
662 LOG_ALWAYS_FATAL("Condition on SMULL must be on 64-bit result\n"); 659 LOG_ALWAYS_FATAL("Condition on SMULL must be on 64-bit result\n");
663 } 660 }
664} 661}
665void ArmToMips64Assembler::SMUAL(int cc, int s, 662void ArmToMips64Assembler::SMUAL(int cc __unused, int s,
666 int RdLo, int RdHi, int Rm, int Rs) { 663 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
667 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi, 664 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
668 "SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs); 665 "SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
669 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (1<<21) | (s<<20) | 666 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (1<<21) | (s<<20) |
@@ -717,26 +714,26 @@ void ArmToMips64Assembler::B(int cc, const char* label)
717 } 714 }
718} 715}
719 716
720void ArmToMips64Assembler::BL(int cc, const char* label) 717void ArmToMips64Assembler::BL(int cc __unused, const char* label __unused)
721{ 718{
722 LOG_ALWAYS_FATAL("branch-and-link not supported yet\n"); 719 LOG_ALWAYS_FATAL("branch-and-link not supported yet\n");
723 mArmPC[mInum++] = pc(); 720 mArmPC[mInum++] = pc();
724} 721}
725 722
726// no use for Branches with integer PC, but they're in the Interface class .... 723// no use for Branches with integer PC, but they're in the Interface class ....
727void ArmToMips64Assembler::B(int cc, uint32_t* to_pc) 724void ArmToMips64Assembler::B(int cc __unused, uint32_t* to_pc __unused)
728{ 725{
729 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n"); 726 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
730 mArmPC[mInum++] = pc(); 727 mArmPC[mInum++] = pc();
731} 728}
732 729
733void ArmToMips64Assembler::BL(int cc, uint32_t* to_pc) 730void ArmToMips64Assembler::BL(int cc __unused, uint32_t* to_pc __unused)
734{ 731{
735 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n"); 732 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
736 mArmPC[mInum++] = pc(); 733 mArmPC[mInum++] = pc();
737} 734}
738 735
739void ArmToMips64Assembler::BX(int cc, int Rn) 736void ArmToMips64Assembler::BX(int cc __unused, int Rn __unused)
740{ 737{
741 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n"); 738 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
742 mArmPC[mInum++] = pc(); 739 mArmPC[mInum++] = pc();
@@ -750,7 +747,7 @@ void ArmToMips64Assembler::BX(int cc, int Rn)
750#endif 747#endif
751 748
752// data transfer... 749// data transfer...
753void ArmToMips64Assembler::LDR(int cc, int Rd, int Rn, uint32_t offset) 750void ArmToMips64Assembler::LDR(int cc __unused, int Rd, int Rn, uint32_t offset)
754{ 751{
755 mArmPC[mInum++] = pc(); 752 mArmPC[mInum++] = pc();
756 // work-around for ARM default address mode of immed12_pre(0) 753 // work-around for ARM default address mode of immed12_pre(0)
@@ -784,7 +781,7 @@ void ArmToMips64Assembler::LDR(int cc, int Rd, int Rn, uint32_t offset)
784 } 781 }
785} 782}
786 783
787void ArmToMips64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t offset) 784void ArmToMips64Assembler::LDRB(int cc __unused, int Rd, int Rn, uint32_t offset)
788{ 785{
789 mArmPC[mInum++] = pc(); 786 mArmPC[mInum++] = pc();
790 // work-around for ARM default address mode of immed12_pre(0) 787 // work-around for ARM default address mode of immed12_pre(0)
@@ -813,7 +810,7 @@ void ArmToMips64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
813 810
814} 811}
815 812
816void ArmToMips64Assembler::STR(int cc, int Rd, int Rn, uint32_t offset) 813void ArmToMips64Assembler::STR(int cc __unused, int Rd, int Rn, uint32_t offset)
817{ 814{
818 mArmPC[mInum++] = pc(); 815 mArmPC[mInum++] = pc();
819 // work-around for ARM default address mode of immed12_pre(0) 816 // work-around for ARM default address mode of immed12_pre(0)
@@ -849,7 +846,7 @@ void ArmToMips64Assembler::STR(int cc, int Rd, int Rn, uint32_t offset)
849 } 846 }
850} 847}
851 848
852void ArmToMips64Assembler::STRB(int cc, int Rd, int Rn, uint32_t offset) 849void ArmToMips64Assembler::STRB(int cc __unused, int Rd, int Rn, uint32_t offset)
853{ 850{
854 mArmPC[mInum++] = pc(); 851 mArmPC[mInum++] = pc();
855 // work-around for ARM default address mode of immed12_pre(0) 852 // work-around for ARM default address mode of immed12_pre(0)
@@ -877,7 +874,7 @@ void ArmToMips64Assembler::STRB(int cc, int Rd, int Rn, uint32_t offset)
877 } 874 }
878} 875}
879 876
880void ArmToMips64Assembler::LDRH(int cc, int Rd, int Rn, uint32_t offset) 877void ArmToMips64Assembler::LDRH(int cc __unused, int Rd, int Rn, uint32_t offset)
881{ 878{
882 mArmPC[mInum++] = pc(); 879 mArmPC[mInum++] = pc();
883 // work-around for ARM default address mode of immed8_pre(0) 880 // work-around for ARM default address mode of immed8_pre(0)
@@ -905,21 +902,23 @@ void ArmToMips64Assembler::LDRH(int cc, int Rd, int Rn, uint32_t offset)
905 } 902 }
906} 903}
907 904
908void ArmToMips64Assembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset) 905void ArmToMips64Assembler::LDRSB(int cc __unused, int Rd __unused,
906 int Rn __unused, uint32_t offset __unused)
909{ 907{
910 mArmPC[mInum++] = pc(); 908 mArmPC[mInum++] = pc();
911 mMips->NOP2(); 909 mMips->NOP2();
912 NOT_IMPLEMENTED(); 910 NOT_IMPLEMENTED();
913} 911}
914 912
915void ArmToMips64Assembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset) 913void ArmToMips64Assembler::LDRSH(int cc __unused, int Rd __unused,
914 int Rn __unused, uint32_t offset __unused)
916{ 915{
917 mArmPC[mInum++] = pc(); 916 mArmPC[mInum++] = pc();
918 mMips->NOP2(); 917 mMips->NOP2();
919 NOT_IMPLEMENTED(); 918 NOT_IMPLEMENTED();
920} 919}
921 920
922void ArmToMips64Assembler::STRH(int cc, int Rd, int Rn, uint32_t offset) 921void ArmToMips64Assembler::STRH(int cc __unused, int Rd, int Rn, uint32_t offset)
923{ 922{
924 mArmPC[mInum++] = pc(); 923 mArmPC[mInum++] = pc();
925 // work-around for ARM default address mode of immed8_pre(0) 924 // work-around for ARM default address mode of immed8_pre(0)
@@ -955,8 +954,8 @@ void ArmToMips64Assembler::STRH(int cc, int Rd, int Rn, uint32_t offset)
955#endif 954#endif
956 955
957// block data transfer... 956// block data transfer...
958void ArmToMips64Assembler::LDM(int cc, int dir, 957void ArmToMips64Assembler::LDM(int cc __unused, int dir __unused,
959 int Rn, int W, uint32_t reg_list) 958 int Rn __unused, int W __unused, uint32_t reg_list __unused)
960{ // ED FD EA FA IB IA DB DA 959{ // ED FD EA FA IB IA DB DA
961 // const uint8_t P[8] = { 1, 0, 1, 0, 1, 0, 1, 0 }; 960 // const uint8_t P[8] = { 1, 0, 1, 0, 1, 0, 1, 0 };
962 // const uint8_t U[8] = { 1, 1, 0, 0, 1, 1, 0, 0 }; 961 // const uint8_t U[8] = { 1, 1, 0, 0, 1, 1, 0, 0 };
@@ -967,8 +966,8 @@ void ArmToMips64Assembler::LDM(int cc, int dir,
967 NOT_IMPLEMENTED(); 966 NOT_IMPLEMENTED();
968} 967}
969 968
970void ArmToMips64Assembler::STM(int cc, int dir, 969void ArmToMips64Assembler::STM(int cc __unused, int dir __unused,
971 int Rn, int W, uint32_t reg_list) 970 int Rn __unused, int W __unused, uint32_t reg_list __unused)
972{ // FA EA FD ED IB IA DB DA 971{ // FA EA FD ED IB IA DB DA
973 // const uint8_t P[8] = { 0, 1, 0, 1, 1, 0, 1, 0 }; 972 // const uint8_t P[8] = { 0, 1, 0, 1, 1, 0, 1, 0 };
974 // const uint8_t U[8] = { 0, 0, 1, 1, 1, 1, 0, 0 }; 973 // const uint8_t U[8] = { 0, 0, 1, 1, 1, 1, 0, 0 };
@@ -987,21 +986,23 @@ void ArmToMips64Assembler::STM(int cc, int dir,
987#endif 986#endif
988 987
989// special... 988// special...
990void ArmToMips64Assembler::SWP(int cc, int Rn, int Rd, int Rm) { 989void ArmToMips64Assembler::SWP(int cc __unused, int Rn __unused,
990 int Rd __unused, int Rm __unused) {
991 // *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm; 991 // *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
992 mArmPC[mInum++] = pc(); 992 mArmPC[mInum++] = pc();
993 mMips->NOP2(); 993 mMips->NOP2();
994 NOT_IMPLEMENTED(); 994 NOT_IMPLEMENTED();
995} 995}
996 996
997void ArmToMips64Assembler::SWPB(int cc, int Rn, int Rd, int Rm) { 997void ArmToMips64Assembler::SWPB(int cc __unused, int Rn __unused,
998 int Rd __unused, int Rm __unused) {
998 // *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm; 999 // *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
999 mArmPC[mInum++] = pc(); 1000 mArmPC[mInum++] = pc();
1000 mMips->NOP2(); 1001 mMips->NOP2();
1001 NOT_IMPLEMENTED(); 1002 NOT_IMPLEMENTED();
1002} 1003}
1003 1004
1004void ArmToMips64Assembler::SWI(int cc, uint32_t comment) { 1005void ArmToMips64Assembler::SWI(int cc __unused, uint32_t comment __unused) {
1005 // *mPC++ = (cc<<28) | (0xF<<24) | comment; 1006 // *mPC++ = (cc<<28) | (0xF<<24) | comment;
1006 mArmPC[mInum++] = pc(); 1007 mArmPC[mInum++] = pc();
1007 mMips->NOP2(); 1008 mMips->NOP2();
@@ -1015,7 +1016,7 @@ void ArmToMips64Assembler::SWI(int cc, uint32_t comment) {
1015#endif 1016#endif
1016 1017
1017// DSP instructions... 1018// DSP instructions...
1018void ArmToMips64Assembler::PLD(int Rn, uint32_t offset) { 1019void ArmToMips64Assembler::PLD(int Rn __unused, uint32_t offset) {
1019 LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))), 1020 LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))),
1020 "PLD only P=1, W=0"); 1021 "PLD only P=1, W=0");
1021 // *mPC++ = 0xF550F000 | (Rn<<16) | offset; 1022 // *mPC++ = 0xF550F000 | (Rn<<16) | offset;
@@ -1024,13 +1025,14 @@ void ArmToMips64Assembler::PLD(int Rn, uint32_t offset) {
1024 NOT_IMPLEMENTED(); 1025 NOT_IMPLEMENTED();
1025} 1026}
1026 1027
1027void ArmToMips64Assembler::CLZ(int cc, int Rd, int Rm) 1028void ArmToMips64Assembler::CLZ(int cc __unused, int Rd, int Rm)
1028{ 1029{
1029 mArmPC[mInum++] = pc(); 1030 mArmPC[mInum++] = pc();
1030 mMips->CLZ(Rd, Rm); 1031 mMips->CLZ(Rd, Rm);
1031} 1032}
1032 1033
1033void ArmToMips64Assembler::QADD(int cc, int Rd, int Rm, int Rn) 1034void ArmToMips64Assembler::QADD(int cc __unused, int Rd __unused,
1035 int Rm __unused, int Rn __unused)
1034{ 1036{
1035 // *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm; 1037 // *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
1036 mArmPC[mInum++] = pc(); 1038 mArmPC[mInum++] = pc();
@@ -1038,7 +1040,8 @@ void ArmToMips64Assembler::QADD(int cc, int Rd, int Rm, int Rn)
1038 NOT_IMPLEMENTED(); 1040 NOT_IMPLEMENTED();
1039} 1041}
1040 1042
1041void ArmToMips64Assembler::QDADD(int cc, int Rd, int Rm, int Rn) 1043void ArmToMips64Assembler::QDADD(int cc __unused, int Rd __unused,
1044 int Rm __unused, int Rn __unused)
1042{ 1045{
1043 // *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm; 1046 // *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
1044 mArmPC[mInum++] = pc(); 1047 mArmPC[mInum++] = pc();
@@ -1046,7 +1049,8 @@ void ArmToMips64Assembler::QDADD(int cc, int Rd, int Rm, int Rn)
1046 NOT_IMPLEMENTED(); 1049 NOT_IMPLEMENTED();
1047} 1050}
1048 1051
1049void ArmToMips64Assembler::QSUB(int cc, int Rd, int Rm, int Rn) 1052void ArmToMips64Assembler::QSUB(int cc __unused, int Rd __unused,
1053 int Rm __unused, int Rn __unused)
1050{ 1054{
1051 // *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm; 1055 // *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
1052 mArmPC[mInum++] = pc(); 1056 mArmPC[mInum++] = pc();
@@ -1054,7 +1058,8 @@ void ArmToMips64Assembler::QSUB(int cc, int Rd, int Rm, int Rn)
1054 NOT_IMPLEMENTED(); 1058 NOT_IMPLEMENTED();
1055} 1059}
1056 1060
1057void ArmToMips64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn) 1061void ArmToMips64Assembler::QDSUB(int cc __unused, int Rd __unused,
1062 int Rm __unused, int Rn __unused)
1058{ 1063{
1059 // *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm; 1064 // *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
1060 mArmPC[mInum++] = pc(); 1065 mArmPC[mInum++] = pc();
@@ -1063,7 +1068,7 @@ void ArmToMips64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn)
1063} 1068}
1064 1069
1065// 16 x 16 signed multiply (like SMLAxx without the accumulate) 1070// 16 x 16 signed multiply (like SMLAxx without the accumulate)
1066void ArmToMips64Assembler::SMUL(int cc, int xy, 1071void ArmToMips64Assembler::SMUL(int cc __unused, int xy,
1067 int Rd, int Rm, int Rs) 1072 int Rd, int Rm, int Rs)
1068{ 1073{
1069 mArmPC[mInum++] = pc(); 1074 mArmPC[mInum++] = pc();
@@ -1092,7 +1097,7 @@ void ArmToMips64Assembler::SMUL(int cc, int xy,
1092} 1097}
1093 1098
1094// signed 32b x 16b multiple, save top 32-bits of 48-bit result 1099// signed 32b x 16b multiple, save top 32-bits of 48-bit result
1095void ArmToMips64Assembler::SMULW(int cc, int y, 1100void ArmToMips64Assembler::SMULW(int cc __unused, int y,
1096 int Rd, int Rm, int Rs) 1101 int Rd, int Rm, int Rs)
1097{ 1102{
1098 mArmPC[mInum++] = pc(); 1103 mArmPC[mInum++] = pc();
@@ -1111,7 +1116,7 @@ void ArmToMips64Assembler::SMULW(int cc, int y,
1111} 1116}
1112 1117
1113// 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn 1118// 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
1114void ArmToMips64Assembler::SMLA(int cc, int xy, 1119void ArmToMips64Assembler::SMLA(int cc __unused, int xy,
1115 int Rd, int Rm, int Rs, int Rn) 1120 int Rd, int Rm, int Rs, int Rn)
1116{ 1121{
1117 mArmPC[mInum++] = pc(); 1122 mArmPC[mInum++] = pc();
@@ -1141,8 +1146,9 @@ void ArmToMips64Assembler::SMLA(int cc, int xy,
1141 mMips->ADDU(Rd, R_at, Rn); 1146 mMips->ADDU(Rd, R_at, Rn);
1142} 1147}
1143 1148
1144void ArmToMips64Assembler::SMLAL(int cc, int xy, 1149void ArmToMips64Assembler::SMLAL(int cc __unused, int xy __unused,
1145 int RdHi, int RdLo, int Rs, int Rm) 1150 int RdHi __unused, int RdLo __unused,
1151 int Rs __unused, int Rm __unused)
1146{ 1152{
1147 // *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm; 1153 // *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm;
1148 mArmPC[mInum++] = pc(); 1154 mArmPC[mInum++] = pc();
@@ -1150,8 +1156,9 @@ void ArmToMips64Assembler::SMLAL(int cc, int xy,
1150 NOT_IMPLEMENTED(); 1156 NOT_IMPLEMENTED();
1151} 1157}
1152 1158
1153void ArmToMips64Assembler::SMLAW(int cc, int y, 1159void ArmToMips64Assembler::SMLAW(int cc __unused, int y __unused,
1154 int Rd, int Rm, int Rs, int Rn) 1160 int Rd __unused, int Rm __unused,
1161 int Rs __unused, int Rn __unused)
1155{ 1162{
1156 // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm; 1163 // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
1157 mArmPC[mInum++] = pc(); 1164 mArmPC[mInum++] = pc();
@@ -1160,7 +1167,7 @@ void ArmToMips64Assembler::SMLAW(int cc, int y,
1160} 1167}
1161 1168
1162// used by ARMv6 version of GGLAssembler::filter32 1169// used by ARMv6 version of GGLAssembler::filter32
1163void ArmToMips64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate) 1170void ArmToMips64Assembler::UXTB16(int cc __unused, int Rd, int Rm, int rotate)
1164{ 1171{
1165 mArmPC[mInum++] = pc(); 1172 mArmPC[mInum++] = pc();
1166 1173
@@ -1173,7 +1180,8 @@ void ArmToMips64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate)
1173 mMips->AND(Rd, R_at2, R_at); 1180 mMips->AND(Rd, R_at2, R_at);
1174} 1181}
1175 1182
1176void ArmToMips64Assembler::UBFX(int cc, int Rd, int Rn, int lsb, int width) 1183void ArmToMips64Assembler::UBFX(int cc __unused, int Rd __unused, int Rn __unused,
1184 int lsb __unused, int width __unused)
1177{ 1185{
1178 /* Placeholder for UBFX */ 1186 /* Placeholder for UBFX */
1179 mArmPC[mInum++] = pc(); 1187 mArmPC[mInum++] = pc();
@@ -1202,7 +1210,8 @@ void ArmToMips64Assembler::ADDR_SUB(int cc,
1202 dataProcessing(opSUB64, cc, s, Rd, Rn, Op2); 1210 dataProcessing(opSUB64, cc, s, Rd, Rn, Op2);
1203} 1211}
1204 1212
1205void ArmToMips64Assembler::ADDR_LDR(int cc, int Rd, int Rn, uint32_t offset) { 1213void ArmToMips64Assembler::ADDR_LDR(int cc __unused, int Rd,
1214 int Rn, uint32_t offset) {
1206 mArmPC[mInum++] = pc(); 1215 mArmPC[mInum++] = pc();
1207 // work-around for ARM default address mode of immed12_pre(0) 1216 // work-around for ARM default address mode of immed12_pre(0)
1208 if (offset > AMODE_UNSUPPORTED) offset = 0; 1217 if (offset > AMODE_UNSUPPORTED) offset = 0;
@@ -1235,7 +1244,8 @@ void ArmToMips64Assembler::ADDR_LDR(int cc, int Rd, int Rn, uint32_t offset) {
1235 } 1244 }
1236} 1245}
1237 1246
1238void ArmToMips64Assembler::ADDR_STR(int cc, int Rd, int Rn, uint32_t offset) { 1247void ArmToMips64Assembler::ADDR_STR(int cc __unused, int Rd,
1248 int Rn, uint32_t offset) {
1239 mArmPC[mInum++] = pc(); 1249 mArmPC[mInum++] = pc();
1240 // work-around for ARM default address mode of immed12_pre(0) 1250 // work-around for ARM default address mode of immed12_pre(0)
1241 if (offset > AMODE_UNSUPPORTED) offset = 0; 1251 if (offset > AMODE_UNSUPPORTED) offset = 0;
@@ -1290,14 +1300,12 @@ void ArmToMips64Assembler::ADDR_STR(int cc, int Rd, int Rn, uint32_t offset) {
1290*/ 1300*/
1291 1301
1292MIPS64Assembler::MIPS64Assembler(const sp<Assembly>& assembly, ArmToMips64Assembler *parent) 1302MIPS64Assembler::MIPS64Assembler(const sp<Assembly>& assembly, ArmToMips64Assembler *parent)
1293 : mParent(parent), 1303 : MIPSAssembler::MIPSAssembler(assembly, NULL), mParent(parent)
1294 MIPSAssembler::MIPSAssembler(assembly, NULL)
1295{ 1304{
1296} 1305}
1297 1306
1298MIPS64Assembler::MIPS64Assembler(void* assembly, ArmToMips64Assembler *parent) 1307MIPS64Assembler::MIPS64Assembler(void* assembly, ArmToMips64Assembler *parent)
1299 : mParent(parent), 1308 : MIPSAssembler::MIPSAssembler(assembly), mParent(parent)
1300 MIPSAssembler::MIPSAssembler(assembly)
1301{ 1309{
1302} 1310}
1303 1311
@@ -1319,7 +1327,7 @@ void MIPS64Assembler::reset()
1319} 1327}
1320 1328
1321 1329
1322void MIPS64Assembler::disassemble(const char* name) 1330void MIPS64Assembler::disassemble(const char* name __unused)
1323{ 1331{
1324 char di_buf[140]; 1332 char di_buf[140];
1325 1333
@@ -1334,11 +1342,6 @@ void MIPS64Assembler::disassemble(const char* name)
1334 } 1342 }
1335 } 1343 }
1336 1344
1337 // iArm is an index to Arm instructions 1...n for this assembly sequence
1338 // mArmPC[iArm] holds the value of the Mips-PC for the first MIPS
1339 // instruction corresponding to that Arm instruction number
1340
1341 int iArm = 0;
1342 size_t count = pc()-base(); 1345 size_t count = pc()-base();
1343 uint32_t* mipsPC = base(); 1346 uint32_t* mipsPC = base();
1344 1347
diff --git a/libpixelflinger/codeflinger/MIPSAssembler.cpp b/libpixelflinger/codeflinger/MIPSAssembler.cpp
index 865a5683c..039a72504 100644
--- a/libpixelflinger/codeflinger/MIPSAssembler.cpp
+++ b/libpixelflinger/codeflinger/MIPSAssembler.cpp
@@ -51,6 +51,7 @@
51 51
52#include <stdio.h> 52#include <stdio.h>
53#include <stdlib.h> 53#include <stdlib.h>
54#include <inttypes.h>
54 55
55#include <cutils/properties.h> 56#include <cutils/properties.h>
56#include <log/log.h> 57#include <log/log.h>
@@ -60,6 +61,8 @@
60#include "MIPSAssembler.h" 61#include "MIPSAssembler.h"
61#include "mips_disassem.h" 62#include "mips_disassem.h"
62 63
64#define __unused __attribute__((__unused__))
65
63// Choose MIPS arch variant following gcc flags 66// Choose MIPS arch variant following gcc flags
64#if defined(__mips__) && __mips==32 && __mips_isa_rev>=2 67#if defined(__mips__) && __mips==32 && __mips_isa_rev>=2
65#define mips32r2 1 68#define mips32r2 1
@@ -167,7 +170,7 @@ void ArmToMipsAssembler::prolog()
167 mMips->MOVE(R_v0, R_a0); // move context * passed in a0 to v0 (arm r0) 170 mMips->MOVE(R_v0, R_a0); // move context * passed in a0 to v0 (arm r0)
168} 171}
169 172
170void ArmToMipsAssembler::epilog(uint32_t touched) 173void ArmToMipsAssembler::epilog(uint32_t touched __unused)
171{ 174{
172 mArmPC[mInum++] = pc(); // save starting PC for this instr 175 mArmPC[mInum++] = pc(); // save starting PC for this instr
173 176
@@ -213,7 +216,7 @@ int ArmToMipsAssembler::buildImmediate(
213 216
214// shifters... 217// shifters...
215 218
216bool ArmToMipsAssembler::isValidImmediate(uint32_t immediate) 219bool ArmToMipsAssembler::isValidImmediate(uint32_t immediate __unused)
217{ 220{
218 // for MIPS, any 32-bit immediate is OK 221 // for MIPS, any 32-bit immediate is OK
219 return true; 222 return true;
@@ -234,13 +237,14 @@ uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift)
234 return AMODE_REG_IMM; 237 return AMODE_REG_IMM;
235} 238}
236 239
237uint32_t ArmToMipsAssembler::reg_rrx(int Rm) 240uint32_t ArmToMipsAssembler::reg_rrx(int Rm __unused)
238{ 241{
239 // reg_rrx mode is not used in the GLLAssember code at this time 242 // reg_rrx mode is not used in the GLLAssember code at this time
240 return AMODE_UNSUPPORTED; 243 return AMODE_UNSUPPORTED;
241} 244}
242 245
243uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs) 246uint32_t ArmToMipsAssembler::reg_reg(int Rm __unused, int type __unused,
247 int Rs __unused)
244{ 248{
245 // reg_reg mode is not used in the GLLAssember code at this time 249 // reg_reg mode is not used in the GLLAssember code at this time
246 return AMODE_UNSUPPORTED; 250 return AMODE_UNSUPPORTED;
@@ -281,14 +285,15 @@ uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type,
281 return AMODE_REG_SCALE_PRE; 285 return AMODE_REG_SCALE_PRE;
282} 286}
283 287
284uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift) 288uint32_t ArmToMipsAssembler::reg_scale_post(int Rm __unused, int type __unused,
289 uint32_t shift __unused)
285{ 290{
286 LOG_ALWAYS_FATAL("adr mode reg_scale_post not yet implemented\n"); 291 LOG_ALWAYS_FATAL("adr mode reg_scale_post not yet implemented\n");
287 return AMODE_UNSUPPORTED; 292 return AMODE_UNSUPPORTED;
288} 293}
289 294
290// LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0) 295// LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
291uint32_t ArmToMipsAssembler::immed8_pre(int32_t immed8, int W) 296uint32_t ArmToMipsAssembler::immed8_pre(int32_t immed8, int W __unused)
292{ 297{
293 // uint32_t offset = abs(immed8); 298 // uint32_t offset = abs(immed8);
294 299
@@ -318,7 +323,7 @@ uint32_t ArmToMipsAssembler::reg_pre(int Rm, int W)
318 return AMODE_REG_PRE; 323 return AMODE_REG_PRE;
319} 324}
320 325
321uint32_t ArmToMipsAssembler::reg_post(int Rm) 326uint32_t ArmToMipsAssembler::reg_post(int Rm __unused)
322{ 327{
323 LOG_ALWAYS_FATAL("adr mode reg_post not yet implemented\n"); 328 LOG_ALWAYS_FATAL("adr mode reg_post not yet implemented\n");
324 return AMODE_UNSUPPORTED; 329 return AMODE_UNSUPPORTED;
@@ -333,12 +338,6 @@ uint32_t ArmToMipsAssembler::reg_post(int Rm)
333#pragma mark Data Processing... 338#pragma mark Data Processing...
334#endif 339#endif
335 340
336
337static const char * const dpOpNames[] = {
338 "AND", "EOR", "SUB", "RSB", "ADD", "ADC", "SBC", "RSC",
339 "TST", "TEQ", "CMP", "CMN", "ORR", "MOV", "BIC", "MVN"
340};
341
342// check if the operand registers from a previous CMP or S-bit instruction 341// check if the operand registers from a previous CMP or S-bit instruction
343// would be overwritten by this instruction. If so, move the value to a 342// would be overwritten by this instruction. If so, move the value to a
344// safe register. 343// safe register.
@@ -605,7 +604,7 @@ void ArmToMipsAssembler::dataProcessing(int opcode, int cc,
605#endif 604#endif
606 605
607// multiply, accumulate 606// multiply, accumulate
608void ArmToMipsAssembler::MLA(int cc, int s, 607void ArmToMipsAssembler::MLA(int cc __unused, int s,
609 int Rd, int Rm, int Rs, int Rn) { 608 int Rd, int Rm, int Rs, int Rn) {
610 609
611 mArmPC[mInum++] = pc(); // save starting PC for this instr 610 mArmPC[mInum++] = pc(); // save starting PC for this instr
@@ -618,7 +617,7 @@ void ArmToMipsAssembler::MLA(int cc, int s,
618 } 617 }
619} 618}
620 619
621void ArmToMipsAssembler::MUL(int cc, int s, 620void ArmToMipsAssembler::MUL(int cc __unused, int s,
622 int Rd, int Rm, int Rs) { 621 int Rd, int Rm, int Rs) {
623 mArmPC[mInum++] = pc(); 622 mArmPC[mInum++] = pc();
624 mMips->MUL(Rd, Rm, Rs); 623 mMips->MUL(Rd, Rm, Rs);
@@ -628,7 +627,7 @@ void ArmToMipsAssembler::MUL(int cc, int s,
628 } 627 }
629} 628}
630 629
631void ArmToMipsAssembler::UMULL(int cc, int s, 630void ArmToMipsAssembler::UMULL(int cc __unused, int s,
632 int RdLo, int RdHi, int Rm, int Rs) { 631 int RdLo, int RdHi, int Rm, int Rs) {
633 mArmPC[mInum++] = pc(); 632 mArmPC[mInum++] = pc();
634 mMips->MULT(Rm, Rs); 633 mMips->MULT(Rm, Rs);
@@ -641,8 +640,8 @@ void ArmToMipsAssembler::UMULL(int cc, int s,
641 } 640 }
642} 641}
643 642
644void ArmToMipsAssembler::UMUAL(int cc, int s, 643void ArmToMipsAssembler::UMUAL(int cc __unused, int s,
645 int RdLo, int RdHi, int Rm, int Rs) { 644 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
646 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi, 645 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
647 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs); 646 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
648 // *mPC++ = (cc<<28) | (1<<23) | (1<<21) | (s<<20) | 647 // *mPC++ = (cc<<28) | (1<<23) | (1<<21) | (s<<20) |
@@ -657,8 +656,8 @@ void ArmToMipsAssembler::UMUAL(int cc, int s,
657 } 656 }
658} 657}
659 658
660void ArmToMipsAssembler::SMULL(int cc, int s, 659void ArmToMipsAssembler::SMULL(int cc __unused, int s,
661 int RdLo, int RdHi, int Rm, int Rs) { 660 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
662 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi, 661 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
663 "SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs); 662 "SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
664 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (s<<20) | 663 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (s<<20) |
@@ -672,8 +671,8 @@ void ArmToMipsAssembler::SMULL(int cc, int s,
672 LOG_ALWAYS_FATAL("Condition on SMULL must be on 64-bit result\n"); 671 LOG_ALWAYS_FATAL("Condition on SMULL must be on 64-bit result\n");
673 } 672 }
674} 673}
675void ArmToMipsAssembler::SMUAL(int cc, int s, 674void ArmToMipsAssembler::SMUAL(int cc __unused, int s,
676 int RdLo, int RdHi, int Rm, int Rs) { 675 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
677 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi, 676 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
678 "SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs); 677 "SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
679 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (1<<21) | (s<<20) | 678 // *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (1<<21) | (s<<20) |
@@ -727,26 +726,26 @@ void ArmToMipsAssembler::B(int cc, const char* label)
727 } 726 }
728} 727}
729 728
730void ArmToMipsAssembler::BL(int cc, const char* label) 729void ArmToMipsAssembler::BL(int cc __unused, const char* label __unused)
731{ 730{
732 LOG_ALWAYS_FATAL("branch-and-link not supported yet\n"); 731 LOG_ALWAYS_FATAL("branch-and-link not supported yet\n");
733 mArmPC[mInum++] = pc(); 732 mArmPC[mInum++] = pc();
734} 733}
735 734
736// no use for Branches with integer PC, but they're in the Interface class .... 735// no use for Branches with integer PC, but they're in the Interface class ....
737void ArmToMipsAssembler::B(int cc, uint32_t* to_pc) 736void ArmToMipsAssembler::B(int cc __unused, uint32_t* to_pc __unused)
738{ 737{
739 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n"); 738 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
740 mArmPC[mInum++] = pc(); 739 mArmPC[mInum++] = pc();
741} 740}
742 741
743void ArmToMipsAssembler::BL(int cc, uint32_t* to_pc) 742void ArmToMipsAssembler::BL(int cc __unused, uint32_t* to_pc __unused)
744{ 743{
745 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n"); 744 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
746 mArmPC[mInum++] = pc(); 745 mArmPC[mInum++] = pc();
747} 746}
748 747
749void ArmToMipsAssembler::BX(int cc, int Rn) 748void ArmToMipsAssembler::BX(int cc __unused, int Rn __unused)
750{ 749{
751 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n"); 750 LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
752 mArmPC[mInum++] = pc(); 751 mArmPC[mInum++] = pc();
@@ -760,7 +759,7 @@ void ArmToMipsAssembler::BX(int cc, int Rn)
760#endif 759#endif
761 760
762// data transfer... 761// data transfer...
763void ArmToMipsAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) 762void ArmToMipsAssembler::LDR(int cc __unused, int Rd, int Rn, uint32_t offset)
764{ 763{
765 mArmPC[mInum++] = pc(); 764 mArmPC[mInum++] = pc();
766 // work-around for ARM default address mode of immed12_pre(0) 765 // work-around for ARM default address mode of immed12_pre(0)
@@ -794,7 +793,7 @@ void ArmToMipsAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset)
794 } 793 }
795} 794}
796 795
797void ArmToMipsAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset) 796void ArmToMipsAssembler::LDRB(int cc __unused, int Rd, int Rn, uint32_t offset)
798{ 797{
799 mArmPC[mInum++] = pc(); 798 mArmPC[mInum++] = pc();
800 // work-around for ARM default address mode of immed12_pre(0) 799 // work-around for ARM default address mode of immed12_pre(0)
@@ -823,7 +822,7 @@ void ArmToMipsAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
823 822
824} 823}
825 824
826void ArmToMipsAssembler::STR(int cc, int Rd, int Rn, uint32_t offset) 825void ArmToMipsAssembler::STR(int cc __unused, int Rd, int Rn, uint32_t offset)
827{ 826{
828 mArmPC[mInum++] = pc(); 827 mArmPC[mInum++] = pc();
829 // work-around for ARM default address mode of immed12_pre(0) 828 // work-around for ARM default address mode of immed12_pre(0)
@@ -859,7 +858,7 @@ void ArmToMipsAssembler::STR(int cc, int Rd, int Rn, uint32_t offset)
859 } 858 }
860} 859}
861 860
862void ArmToMipsAssembler::STRB(int cc, int Rd, int Rn, uint32_t offset) 861void ArmToMipsAssembler::STRB(int cc __unused, int Rd, int Rn, uint32_t offset)
863{ 862{
864 mArmPC[mInum++] = pc(); 863 mArmPC[mInum++] = pc();
865 // work-around for ARM default address mode of immed12_pre(0) 864 // work-around for ARM default address mode of immed12_pre(0)
@@ -887,7 +886,7 @@ void ArmToMipsAssembler::STRB(int cc, int Rd, int Rn, uint32_t offset)
887 } 886 }
888} 887}
889 888
890void ArmToMipsAssembler::LDRH(int cc, int Rd, int Rn, uint32_t offset) 889void ArmToMipsAssembler::LDRH(int cc __unused, int Rd, int Rn, uint32_t offset)
891{ 890{
892 mArmPC[mInum++] = pc(); 891 mArmPC[mInum++] = pc();
893 // work-around for ARM default address mode of immed8_pre(0) 892 // work-around for ARM default address mode of immed8_pre(0)
@@ -915,21 +914,23 @@ void ArmToMipsAssembler::LDRH(int cc, int Rd, int Rn, uint32_t offset)
915 } 914 }
916} 915}
917 916
918void ArmToMipsAssembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset) 917void ArmToMipsAssembler::LDRSB(int cc __unused, int Rd __unused,
918 int Rn __unused, uint32_t offset __unused)
919{ 919{
920 mArmPC[mInum++] = pc(); 920 mArmPC[mInum++] = pc();
921 mMips->NOP2(); 921 mMips->NOP2();
922 NOT_IMPLEMENTED(); 922 NOT_IMPLEMENTED();
923} 923}
924 924
925void ArmToMipsAssembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset) 925void ArmToMipsAssembler::LDRSH(int cc __unused, int Rd __unused,
926 int Rn __unused, uint32_t offset __unused)
926{ 927{
927 mArmPC[mInum++] = pc(); 928 mArmPC[mInum++] = pc();
928 mMips->NOP2(); 929 mMips->NOP2();
929 NOT_IMPLEMENTED(); 930 NOT_IMPLEMENTED();
930} 931}
931 932
932void ArmToMipsAssembler::STRH(int cc, int Rd, int Rn, uint32_t offset) 933void ArmToMipsAssembler::STRH(int cc __unused, int Rd, int Rn, uint32_t offset)
933{ 934{
934 mArmPC[mInum++] = pc(); 935 mArmPC[mInum++] = pc();
935 // work-around for ARM default address mode of immed8_pre(0) 936 // work-around for ARM default address mode of immed8_pre(0)
@@ -965,8 +966,8 @@ void ArmToMipsAssembler::STRH(int cc, int Rd, int Rn, uint32_t offset)
965#endif 966#endif
966 967
967// block data transfer... 968// block data transfer...
968void ArmToMipsAssembler::LDM(int cc, int dir, 969void ArmToMipsAssembler::LDM(int cc __unused, int dir __unused,
969 int Rn, int W, uint32_t reg_list) 970 int Rn __unused, int W __unused, uint32_t reg_list __unused)
970{ // ED FD EA FA IB IA DB DA 971{ // ED FD EA FA IB IA DB DA
971 // const uint8_t P[8] = { 1, 0, 1, 0, 1, 0, 1, 0 }; 972 // const uint8_t P[8] = { 1, 0, 1, 0, 1, 0, 1, 0 };
972 // const uint8_t U[8] = { 1, 1, 0, 0, 1, 1, 0, 0 }; 973 // const uint8_t U[8] = { 1, 1, 0, 0, 1, 1, 0, 0 };
@@ -977,8 +978,8 @@ void ArmToMipsAssembler::LDM(int cc, int dir,
977 NOT_IMPLEMENTED(); 978 NOT_IMPLEMENTED();
978} 979}
979 980
980void ArmToMipsAssembler::STM(int cc, int dir, 981void ArmToMipsAssembler::STM(int cc __unused, int dir __unused,
981 int Rn, int W, uint32_t reg_list) 982 int Rn __unused, int W __unused, uint32_t reg_list __unused)
982{ // FA EA FD ED IB IA DB DA 983{ // FA EA FD ED IB IA DB DA
983 // const uint8_t P[8] = { 0, 1, 0, 1, 1, 0, 1, 0 }; 984 // const uint8_t P[8] = { 0, 1, 0, 1, 1, 0, 1, 0 };
984 // const uint8_t U[8] = { 0, 0, 1, 1, 1, 1, 0, 0 }; 985 // const uint8_t U[8] = { 0, 0, 1, 1, 1, 1, 0, 0 };
@@ -997,21 +998,23 @@ void ArmToMipsAssembler::STM(int cc, int dir,
997#endif 998#endif
998 999
999// special... 1000// special...
1000void ArmToMipsAssembler::SWP(int cc, int Rn, int Rd, int Rm) { 1001void ArmToMipsAssembler::SWP(int cc __unused, int Rn __unused,
1002 int Rd __unused, int Rm __unused) {
1001 // *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm; 1003 // *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1002 mArmPC[mInum++] = pc(); 1004 mArmPC[mInum++] = pc();
1003 mMips->NOP2(); 1005 mMips->NOP2();
1004 NOT_IMPLEMENTED(); 1006 NOT_IMPLEMENTED();
1005} 1007}
1006 1008
1007void ArmToMipsAssembler::SWPB(int cc, int Rn, int Rd, int Rm) { 1009void ArmToMipsAssembler::SWPB(int cc __unused, int Rn __unused,
1010 int Rd __unused, int Rm __unused) {
1008 // *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm; 1011 // *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1009 mArmPC[mInum++] = pc(); 1012 mArmPC[mInum++] = pc();
1010 mMips->NOP2(); 1013 mMips->NOP2();
1011 NOT_IMPLEMENTED(); 1014 NOT_IMPLEMENTED();
1012} 1015}
1013 1016
1014void ArmToMipsAssembler::SWI(int cc, uint32_t comment) { 1017void ArmToMipsAssembler::SWI(int cc __unused, uint32_t comment __unused) {
1015 // *mPC++ = (cc<<28) | (0xF<<24) | comment; 1018 // *mPC++ = (cc<<28) | (0xF<<24) | comment;
1016 mArmPC[mInum++] = pc(); 1019 mArmPC[mInum++] = pc();
1017 mMips->NOP2(); 1020 mMips->NOP2();
@@ -1025,7 +1028,7 @@ void ArmToMipsAssembler::SWI(int cc, uint32_t comment) {
1025#endif 1028#endif
1026 1029
1027// DSP instructions... 1030// DSP instructions...
1028void ArmToMipsAssembler::PLD(int Rn, uint32_t offset) { 1031void ArmToMipsAssembler::PLD(int Rn __unused, uint32_t offset) {
1029 LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))), 1032 LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))),
1030 "PLD only P=1, W=0"); 1033 "PLD only P=1, W=0");
1031 // *mPC++ = 0xF550F000 | (Rn<<16) | offset; 1034 // *mPC++ = 0xF550F000 | (Rn<<16) | offset;
@@ -1034,13 +1037,14 @@ void ArmToMipsAssembler::PLD(int Rn, uint32_t offset) {
1034 NOT_IMPLEMENTED(); 1037 NOT_IMPLEMENTED();
1035} 1038}
1036 1039
1037void ArmToMipsAssembler::CLZ(int cc, int Rd, int Rm) 1040void ArmToMipsAssembler::CLZ(int cc __unused, int Rd, int Rm)
1038{ 1041{
1039 mArmPC[mInum++] = pc(); 1042 mArmPC[mInum++] = pc();
1040 mMips->CLZ(Rd, Rm); 1043 mMips->CLZ(Rd, Rm);
1041} 1044}
1042 1045
1043void ArmToMipsAssembler::QADD(int cc, int Rd, int Rm, int Rn) 1046void ArmToMipsAssembler::QADD(int cc __unused, int Rd __unused,
1047 int Rm __unused, int Rn __unused)
1044{ 1048{
1045 // *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm; 1049 // *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
1046 mArmPC[mInum++] = pc(); 1050 mArmPC[mInum++] = pc();
@@ -1048,7 +1052,8 @@ void ArmToMipsAssembler::QADD(int cc, int Rd, int Rm, int Rn)
1048 NOT_IMPLEMENTED(); 1052 NOT_IMPLEMENTED();
1049} 1053}
1050 1054
1051void ArmToMipsAssembler::QDADD(int cc, int Rd, int Rm, int Rn) 1055void ArmToMipsAssembler::QDADD(int cc __unused, int Rd __unused,
1056 int Rm __unused, int Rn __unused)
1052{ 1057{
1053 // *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm; 1058 // *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
1054 mArmPC[mInum++] = pc(); 1059 mArmPC[mInum++] = pc();
@@ -1056,7 +1061,8 @@ void ArmToMipsAssembler::QDADD(int cc, int Rd, int Rm, int Rn)
1056 NOT_IMPLEMENTED(); 1061 NOT_IMPLEMENTED();
1057} 1062}
1058 1063
1059void ArmToMipsAssembler::QSUB(int cc, int Rd, int Rm, int Rn) 1064void ArmToMipsAssembler::QSUB(int cc __unused, int Rd __unused,
1065 int Rm __unused, int Rn __unused)
1060{ 1066{
1061 // *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm; 1067 // *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
1062 mArmPC[mInum++] = pc(); 1068 mArmPC[mInum++] = pc();
@@ -1064,7 +1070,8 @@ void ArmToMipsAssembler::QSUB(int cc, int Rd, int Rm, int Rn)
1064 NOT_IMPLEMENTED(); 1070 NOT_IMPLEMENTED();
1065} 1071}
1066 1072
1067void ArmToMipsAssembler::QDSUB(int cc, int Rd, int Rm, int Rn) 1073void ArmToMipsAssembler::QDSUB(int cc __unused, int Rd __unused,
1074 int Rm __unused, int Rn __unused)
1068{ 1075{
1069 // *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm; 1076 // *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
1070 mArmPC[mInum++] = pc(); 1077 mArmPC[mInum++] = pc();
@@ -1073,7 +1080,7 @@ void ArmToMipsAssembler::QDSUB(int cc, int Rd, int Rm, int Rn)
1073} 1080}
1074 1081
1075// 16 x 16 signed multiply (like SMLAxx without the accumulate) 1082// 16 x 16 signed multiply (like SMLAxx without the accumulate)
1076void ArmToMipsAssembler::SMUL(int cc, int xy, 1083void ArmToMipsAssembler::SMUL(int cc __unused, int xy,
1077 int Rd, int Rm, int Rs) 1084 int Rd, int Rm, int Rs)
1078{ 1085{
1079 mArmPC[mInum++] = pc(); 1086 mArmPC[mInum++] = pc();
@@ -1112,7 +1119,7 @@ void ArmToMipsAssembler::SMUL(int cc, int xy,
1112} 1119}
1113 1120
1114// signed 32b x 16b multiple, save top 32-bits of 48-bit result 1121// signed 32b x 16b multiple, save top 32-bits of 48-bit result
1115void ArmToMipsAssembler::SMULW(int cc, int y, 1122void ArmToMipsAssembler::SMULW(int cc __unused, int y,
1116 int Rd, int Rm, int Rs) 1123 int Rd, int Rm, int Rs)
1117{ 1124{
1118 mArmPC[mInum++] = pc(); 1125 mArmPC[mInum++] = pc();
@@ -1132,7 +1139,7 @@ void ArmToMipsAssembler::SMULW(int cc, int y,
1132} 1139}
1133 1140
1134// 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn 1141// 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
1135void ArmToMipsAssembler::SMLA(int cc, int xy, 1142void ArmToMipsAssembler::SMLA(int cc __unused, int xy,
1136 int Rd, int Rm, int Rs, int Rn) 1143 int Rd, int Rm, int Rs, int Rn)
1137{ 1144{
1138 mArmPC[mInum++] = pc(); 1145 mArmPC[mInum++] = pc();
@@ -1172,8 +1179,9 @@ void ArmToMipsAssembler::SMLA(int cc, int xy,
1172 mMips->ADDU(Rd, R_at, Rn); 1179 mMips->ADDU(Rd, R_at, Rn);
1173} 1180}
1174 1181
1175void ArmToMipsAssembler::SMLAL(int cc, int xy, 1182void ArmToMipsAssembler::SMLAL(int cc __unused, int xy __unused,
1176 int RdHi, int RdLo, int Rs, int Rm) 1183 int RdHi __unused, int RdLo __unused,
1184 int Rs __unused, int Rm __unused)
1177{ 1185{
1178 // *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm; 1186 // *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm;
1179 mArmPC[mInum++] = pc(); 1187 mArmPC[mInum++] = pc();
@@ -1181,8 +1189,9 @@ void ArmToMipsAssembler::SMLAL(int cc, int xy,
1181 NOT_IMPLEMENTED(); 1189 NOT_IMPLEMENTED();
1182} 1190}
1183 1191
1184void ArmToMipsAssembler::SMLAW(int cc, int y, 1192void ArmToMipsAssembler::SMLAW(int cc __unused, int y __unused,
1185 int Rd, int Rm, int Rs, int Rn) 1193 int Rd __unused, int Rm __unused,
1194 int Rs __unused, int Rn __unused)
1186{ 1195{
1187 // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm; 1196 // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
1188 mArmPC[mInum++] = pc(); 1197 mArmPC[mInum++] = pc();
@@ -1191,7 +1200,7 @@ void ArmToMipsAssembler::SMLAW(int cc, int y,
1191} 1200}
1192 1201
1193// used by ARMv6 version of GGLAssembler::filter32 1202// used by ARMv6 version of GGLAssembler::filter32
1194void ArmToMipsAssembler::UXTB16(int cc, int Rd, int Rm, int rotate) 1203void ArmToMipsAssembler::UXTB16(int cc __unused, int Rd, int Rm, int rotate)
1195{ 1204{
1196 mArmPC[mInum++] = pc(); 1205 mArmPC[mInum++] = pc();
1197 1206
@@ -1202,7 +1211,9 @@ void ArmToMipsAssembler::UXTB16(int cc, int Rd, int Rm, int rotate)
1202 mMips->AND(Rd, Rm, 0x00FF00FF); 1211 mMips->AND(Rd, Rm, 0x00FF00FF);
1203} 1212}
1204 1213
1205void ArmToMipsAssembler::UBFX(int cc, int Rd, int Rn, int lsb, int width) 1214void ArmToMipsAssembler::UBFX(int cc __unused, int Rd __unused,
1215 int Rn __unused, int lsb __unused,
1216 int width __unused)
1206{ 1217{
1207 /* Placeholder for UBFX */ 1218 /* Placeholder for UBFX */
1208 mArmPC[mInum++] = pc(); 1219 mArmPC[mInum++] = pc();
@@ -1339,11 +1350,6 @@ void MIPSAssembler::disassemble(const char* name)
1339 } 1350 }
1340 } 1351 }
1341 1352
1342 // iArm is an index to Arm instructions 1...n for this assembly sequence
1343 // mArmPC[iArm] holds the value of the Mips-PC for the first MIPS
1344 // instruction corresponding to that Arm instruction number
1345
1346 int iArm = 0;
1347 size_t count = pc()-base(); 1353 size_t count = pc()-base();
1348 uint32_t* mipsPC = base(); 1354 uint32_t* mipsPC = base();
1349 while (count--) { 1355 while (count--) {
@@ -1359,7 +1365,7 @@ void MIPSAssembler::disassemble(const char* name)
1359 ::mips_disassem(mipsPC, di_buf, arm_disasm_fmt); 1365 ::mips_disassem(mipsPC, di_buf, arm_disasm_fmt);
1360 string_detab(di_buf); 1366 string_detab(di_buf);
1361 string_pad(di_buf, 30); 1367 string_pad(di_buf, 30);
1362 ALOGW("%08x: %08x %s", uintptr_t(mipsPC), uint32_t(*mipsPC), di_buf); 1368 ALOGW("0x%p: %08x %s", mipsPC, uint32_t(*mipsPC), di_buf);
1363 mipsPC++; 1369 mipsPC++;
1364 } 1370 }
1365} 1371}
@@ -1381,7 +1387,7 @@ void MIPSAssembler::prolog()
1381 // empty - done in ArmToMipsAssembler 1387 // empty - done in ArmToMipsAssembler
1382} 1388}
1383 1389
1384void MIPSAssembler::epilog(uint32_t touched) 1390void MIPSAssembler::epilog(uint32_t touched __unused)
1385{ 1391{
1386 // empty - done in ArmToMipsAssembler 1392 // empty - done in ArmToMipsAssembler
1387} 1393}
@@ -1403,7 +1409,7 @@ int MIPSAssembler::generate(const char* name)
1403 1409
1404 // the instruction & data caches are flushed by CodeCache 1410 // the instruction & data caches are flushed by CodeCache
1405 const int64_t duration = ggl_system_time() - mDuration; 1411 const int64_t duration = ggl_system_time() - mDuration;
1406 const char * const format = "generated %s (%d ins) at [%p:%p] in %lld ns\n"; 1412 const char * const format = "generated %s (%d ins) at [%p:%p] in %" PRId64 " ns\n";
1407 ALOGI(format, name, int(pc()-base()), base(), pc(), duration); 1413 ALOGI(format, name, int(pc()-base()), base(), pc(), duration);
1408 1414
1409 char value[PROPERTY_VALUE_MAX]; 1415 char value[PROPERTY_VALUE_MAX];
@@ -1864,7 +1870,7 @@ void MIPSAssembler::BEQZ(int Rs, const char* label)
1864 BEQ(Rs, R_zero, label); 1870 BEQ(Rs, R_zero, label);
1865} 1871}
1866 1872
1867void MIPSAssembler::BNEZ(int Rs, const char* label) 1873void MIPSAssembler::BNEZ(int Rs __unused, const char* label)
1868{ 1874{
1869 BNE(R_at, R_zero, label); 1875 BNE(R_at, R_zero, label);
1870} 1876}
diff --git a/libpixelflinger/codeflinger/mips64_disassem.c b/libpixelflinger/codeflinger/mips64_disassem.c
index 1856e5c0e..852829984 100644
--- a/libpixelflinger/codeflinger/mips64_disassem.c
+++ b/libpixelflinger/codeflinger/mips64_disassem.c
@@ -45,6 +45,8 @@
45 45
46#include "mips_opcode.h" 46#include "mips_opcode.h"
47 47
48#define __unused __attribute__((__unused__))
49
48static char *sprintf_buffer; 50static char *sprintf_buffer;
49static int sprintf_buf_len; 51static int sprintf_buf_len;
50 52
@@ -114,7 +116,7 @@ static char * alt_arm_reg_name[32] = { // hacked names for comparison with ARM
114 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 116 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
115}; 117};
116 118
117static char ** reg_name = &mips_reg_name[0]; 119static char * const * reg_name = &mips_reg_name[0];
118 120
119static const char * const c0_opname[64] = { 121static const char * const c0_opname[64] = {
120 "c0op00","tlbr", "tlbwi", "c0op03","c0op04","c0op05","tlbwr", "c0op07", 122 "c0op00","tlbr", "tlbwi", "c0op03","c0op04","c0op05","tlbwr", "c0op07",
@@ -147,7 +149,7 @@ db_addr_t mips_disassem(db_addr_t loc, char *di_buffer, int alt_dis_format);
147 * 'loc' may in fact contain a breakpoint instruction. 149 * 'loc' may in fact contain a breakpoint instruction.
148 */ 150 */
149static db_addr_t 151static db_addr_t
150db_disasm_insn(int insn, db_addr_t loc, bool altfmt) 152db_disasm_insn(int insn, db_addr_t loc, bool altfmt __unused)
151{ 153{
152 bool bdslot = false; 154 bool bdslot = false;
153 InstFmt i; 155 InstFmt i;
diff --git a/libpixelflinger/codeflinger/mips_disassem.c b/libpixelflinger/codeflinger/mips_disassem.c
index 83a9740ed..1fe680675 100644
--- a/libpixelflinger/codeflinger/mips_disassem.c
+++ b/libpixelflinger/codeflinger/mips_disassem.c
@@ -57,6 +57,7 @@
57// #include <ddb/db_extern.h> 57// #include <ddb/db_extern.h>
58// #include <ddb/db_sym.h> 58// #include <ddb/db_sym.h>
59 59
60#define __unused __attribute__((__unused__))
60 61
61static char *sprintf_buffer; 62static char *sprintf_buffer;
62static int sprintf_buf_len; 63static int sprintf_buf_len;
@@ -183,7 +184,7 @@ db_addr_t mips_disassem(db_addr_t loc, char *di_buffer, int alt_dis_format);
183 * 'loc' may in fact contain a breakpoint instruction. 184 * 'loc' may in fact contain a breakpoint instruction.
184 */ 185 */
185static db_addr_t 186static db_addr_t
186db_disasm_insn(int insn, db_addr_t loc, bool altfmt) 187db_disasm_insn(int insn, db_addr_t loc, bool altfmt __unused)
187{ 188{
188 bool bdslot = false; 189 bool bdslot = false;
189 InstFmt i; 190 InstFmt i;