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Diffstat (limited to 'libpixelflinger/codeflinger/disassem.c')
-rw-r--r-- | libpixelflinger/codeflinger/disassem.c | 702 |
1 files changed, 702 insertions, 0 deletions
diff --git a/libpixelflinger/codeflinger/disassem.c b/libpixelflinger/codeflinger/disassem.c new file mode 100644 index 000000000..4676da0d8 --- /dev/null +++ b/libpixelflinger/codeflinger/disassem.c | |||
@@ -0,0 +1,702 @@ | |||
1 | /* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */ | ||
2 | |||
3 | /*- | ||
4 | * Copyright (c) 1996 Mark Brinicombe. | ||
5 | * Copyright (c) 1996 Brini. | ||
6 | * | ||
7 | * All rights reserved. | ||
8 | * | ||
9 | * Redistribution and use in source and binary forms, with or without | ||
10 | * modification, are permitted provided that the following conditions | ||
11 | * are met: | ||
12 | * 1. Redistributions of source code must retain the above copyright | ||
13 | * notice, this list of conditions and the following disclaimer. | ||
14 | * 2. Redistributions in binary form must reproduce the above copyright | ||
15 | * notice, this list of conditions and the following disclaimer in the | ||
16 | * documentation and/or other materials provided with the distribution. | ||
17 | * 3. All advertising materials mentioning features or use of this software | ||
18 | * must display the following acknowledgement: | ||
19 | * This product includes software developed by Brini. | ||
20 | * 4. The name of the company nor the name of the author may be used to | ||
21 | * endorse or promote products derived from this software without specific | ||
22 | * prior written permission. | ||
23 | * | ||
24 | * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | ||
27 | * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, | ||
28 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | ||
29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | ||
30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | ||
33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | ||
34 | * SUCH DAMAGE. | ||
35 | * | ||
36 | * RiscBSD kernel project | ||
37 | * | ||
38 | * db_disasm.c | ||
39 | * | ||
40 | * Kernel disassembler | ||
41 | * | ||
42 | * Created : 10/02/96 | ||
43 | * | ||
44 | * Structured after the sparc/sparc/db_disasm.c by David S. Miller & | ||
45 | * Paul Kranenburg | ||
46 | * | ||
47 | * This code is not complete. Not all instructions are disassembled. | ||
48 | */ | ||
49 | |||
50 | #include <sys/cdefs.h> | ||
51 | //__FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/arm/arm/disassem.c,v 1.2 2005/01/05 21:58:47 imp Exp $"); | ||
52 | #include <sys/param.h> | ||
53 | #include <stdio.h> | ||
54 | |||
55 | #include "disassem.h" | ||
56 | #include "armreg.h" | ||
57 | //#include <ddb/ddb.h> | ||
58 | |||
59 | /* | ||
60 | * General instruction format | ||
61 | * | ||
62 | * insn[cc][mod] [operands] | ||
63 | * | ||
64 | * Those fields with an uppercase format code indicate that the field | ||
65 | * follows directly after the instruction before the separator i.e. | ||
66 | * they modify the instruction rather than just being an operand to | ||
67 | * the instruction. The only exception is the writeback flag which | ||
68 | * follows a operand. | ||
69 | * | ||
70 | * | ||
71 | * 2 - print Operand 2 of a data processing instruction | ||
72 | * d - destination register (bits 12-15) | ||
73 | * n - n register (bits 16-19) | ||
74 | * s - s register (bits 8-11) | ||
75 | * o - indirect register rn (bits 16-19) (used by swap) | ||
76 | * m - m register (bits 0-3) | ||
77 | * a - address operand of ldr/str instruction | ||
78 | * e - address operand of ldrh/strh instruction | ||
79 | * l - register list for ldm/stm instruction | ||
80 | * f - 1st fp operand (register) (bits 12-14) | ||
81 | * g - 2nd fp operand (register) (bits 16-18) | ||
82 | * h - 3rd fp operand (register/immediate) (bits 0-4) | ||
83 | * b - branch address | ||
84 | * t - thumb branch address (bits 24, 0-23) | ||
85 | * k - breakpoint comment (bits 0-3, 8-19) | ||
86 | * X - block transfer type | ||
87 | * Y - block transfer type (r13 base) | ||
88 | * c - comment field bits(0-23) | ||
89 | * p - saved or current status register | ||
90 | * F - PSR transfer fields | ||
91 | * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN | ||
92 | * L - co-processor transfer size | ||
93 | * S - set status flag | ||
94 | * P - fp precision | ||
95 | * Q - fp precision (for ldf/stf) | ||
96 | * R - fp rounding | ||
97 | * v - co-processor data transfer registers + addressing mode | ||
98 | * W - writeback flag | ||
99 | * x - instruction in hex | ||
100 | * # - co-processor number | ||
101 | * y - co-processor data processing registers | ||
102 | * z - co-processor register transfer registers | ||
103 | */ | ||
104 | |||
105 | struct arm32_insn { | ||
106 | u_int mask; | ||
107 | u_int pattern; | ||
108 | char* name; | ||
109 | char* format; | ||
110 | }; | ||
111 | |||
112 | static const struct arm32_insn arm32_i[] = { | ||
113 | { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ | ||
114 | { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ | ||
115 | { 0x0f000000, 0x0f000000, "swi", "c" }, | ||
116 | { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ | ||
117 | { 0x0f000000, 0x0a000000, "b", "b" }, | ||
118 | { 0x0f000000, 0x0b000000, "bl", "b" }, | ||
119 | { 0x0fe000f0, 0x00000090, "mul", "Snms" }, | ||
120 | { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, | ||
121 | { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, | ||
122 | { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, | ||
123 | { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, | ||
124 | { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, | ||
125 | { 0x0d700000, 0x04200000, "strt", "daW" }, | ||
126 | { 0x0d700000, 0x04300000, "ldrt", "daW" }, | ||
127 | { 0x0d700000, 0x04600000, "strbt", "daW" }, | ||
128 | { 0x0d700000, 0x04700000, "ldrbt", "daW" }, | ||
129 | { 0x0c500000, 0x04000000, "str", "daW" }, | ||
130 | { 0x0c500000, 0x04100000, "ldr", "daW" }, | ||
131 | { 0x0c500000, 0x04400000, "strb", "daW" }, | ||
132 | { 0x0c500000, 0x04500000, "ldrb", "daW" }, | ||
133 | { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ | ||
134 | { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ | ||
135 | { 0x0e100000, 0x08000000, "stm", "XnWl" }, | ||
136 | { 0x0e100000, 0x08100000, "ldm", "XnWl" }, | ||
137 | { 0x0e1000f0, 0x00100090, "ldrb", "deW" }, | ||
138 | { 0x0e1000f0, 0x00000090, "strb", "deW" }, | ||
139 | { 0x0e1000f0, 0x001000d0, "ldrsb", "deW" }, | ||
140 | { 0x0e1000f0, 0x001000b0, "ldrh", "deW" }, | ||
141 | { 0x0e1000f0, 0x000000b0, "strh", "deW" }, | ||
142 | { 0x0e1000f0, 0x001000f0, "ldrsh", "deW" }, | ||
143 | { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ | ||
144 | { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ | ||
145 | { 0x0ff00ff0, 0x01000090, "swp", "dmo" }, | ||
146 | { 0x0ff00ff0, 0x01400090, "swpb", "dmo" }, | ||
147 | { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ | ||
148 | { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ | ||
149 | { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ | ||
150 | { 0x0ffffff0, 0x012fff10, "bx", "m" }, | ||
151 | { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, | ||
152 | { 0x0ffffff0, 0x012fff30, "blx", "m" }, | ||
153 | { 0xfff000f0, 0xe1200070, "bkpt", "k" }, | ||
154 | { 0x0de00000, 0x00000000, "and", "Sdn2" }, | ||
155 | { 0x0de00000, 0x00200000, "eor", "Sdn2" }, | ||
156 | { 0x0de00000, 0x00400000, "sub", "Sdn2" }, | ||
157 | { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, | ||
158 | { 0x0de00000, 0x00800000, "add", "Sdn2" }, | ||
159 | { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, | ||
160 | { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, | ||
161 | { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, | ||
162 | { 0x0df00000, 0x01100000, "tst", "Dn2" }, | ||
163 | { 0x0df00000, 0x01300000, "teq", "Dn2" }, | ||
164 | { 0x0df00000, 0x01500000, "cmp", "Dn2" }, | ||
165 | { 0x0df00000, 0x01700000, "cmn", "Dn2" }, | ||
166 | { 0x0de00000, 0x01800000, "orr", "Sdn2" }, | ||
167 | { 0x0de00000, 0x01a00000, "mov", "Sd2" }, | ||
168 | { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, | ||
169 | { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, | ||
170 | { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, | ||
171 | { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, | ||
172 | { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, | ||
173 | { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, | ||
174 | { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, | ||
175 | { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, | ||
176 | { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, | ||
177 | { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, | ||
178 | { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, | ||
179 | { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, | ||
180 | { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, | ||
181 | { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, | ||
182 | { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, | ||
183 | { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, | ||
184 | { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, | ||
185 | { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, | ||
186 | { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, | ||
187 | { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, | ||
188 | { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, | ||
189 | { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, | ||
190 | { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, | ||
191 | { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, | ||
192 | { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, | ||
193 | { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, | ||
194 | { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, | ||
195 | { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, | ||
196 | { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, | ||
197 | { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, | ||
198 | { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, | ||
199 | { 0x0e100f00, 0x0c000100, "stf", "QLv" }, | ||
200 | { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, | ||
201 | { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, | ||
202 | { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, | ||
203 | { 0x0ff00f10, 0x0e200110, "wfs", "d" }, | ||
204 | { 0x0ff00f10, 0x0e300110, "rfs", "d" }, | ||
205 | { 0x0ff00f10, 0x0e400110, "wfc", "d" }, | ||
206 | { 0x0ff00f10, 0x0e500110, "rfc", "d" }, | ||
207 | { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, | ||
208 | { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, | ||
209 | { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, | ||
210 | { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, | ||
211 | { 0xff100010, 0xfe000010, "mcr2", "#z" }, | ||
212 | { 0x0f100010, 0x0e000010, "mcr", "#z" }, | ||
213 | { 0xff100010, 0xfe100010, "mrc2", "#z" }, | ||
214 | { 0x0f100010, 0x0e100010, "mrc", "#z" }, | ||
215 | { 0xff000010, 0xfe000000, "cdp2", "#y" }, | ||
216 | { 0x0f000010, 0x0e000000, "cdp", "#y" }, | ||
217 | { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, | ||
218 | { 0x0e100090, 0x0c100000, "ldc", "L#v" }, | ||
219 | { 0xfe100090, 0xfc000000, "stc2", "L#v" }, | ||
220 | { 0x0e100090, 0x0c000000, "stc", "L#v" }, | ||
221 | { 0xf550f000, 0xf550f000, "pld", "ne" }, | ||
222 | { 0x0ff00ff0, 0x01000050, "qaad", "dmn" }, | ||
223 | { 0x0ff00ff0, 0x01400050, "qdaad", "dmn" }, | ||
224 | { 0x0ff00ff0, 0x01600050, "qdsub", "dmn" }, | ||
225 | { 0x0ff00ff0, 0x01200050, "dsub", "dmn" }, | ||
226 | { 0x0ff000f0, 0x01000080, "smlabb", "nmsd" }, // d & n inverted!! | ||
227 | { 0x0ff000f0, 0x010000a0, "smlatb", "nmsd" }, // d & n inverted!! | ||
228 | { 0x0ff000f0, 0x010000c0, "smlabt", "nmsd" }, // d & n inverted!! | ||
229 | { 0x0ff000f0, 0x010000e0, "smlatt", "nmsd" }, // d & n inverted!! | ||
230 | { 0x0ff000f0, 0x01400080, "smlalbb","ndms" }, // d & n inverted!! | ||
231 | { 0x0ff000f0, 0x014000a0, "smlaltb","ndms" }, // d & n inverted!! | ||
232 | { 0x0ff000f0, 0x014000c0, "smlalbt","ndms" }, // d & n inverted!! | ||
233 | { 0x0ff000f0, 0x014000e0, "smlaltt","ndms" }, // d & n inverted!! | ||
234 | { 0x0ff000f0, 0x01200080, "smlawb", "nmsd" }, // d & n inverted!! | ||
235 | { 0x0ff0f0f0, 0x012000a0, "smulwb","nms" }, // d & n inverted!! | ||
236 | { 0x0ff000f0, 0x012000c0, "smlawt", "nmsd" }, // d & n inverted!! | ||
237 | { 0x0ff0f0f0, 0x012000e0, "smulwt","nms" }, // d & n inverted!! | ||
238 | { 0x0ff0f0f0, 0x01600080, "smulbb","nms" }, // d & n inverted!! | ||
239 | { 0x0ff0f0f0, 0x016000a0, "smultb","nms" }, // d & n inverted!! | ||
240 | { 0x0ff0f0f0, 0x016000c0, "smulbt","nms" }, // d & n inverted!! | ||
241 | { 0x0ff0f0f0, 0x016000e0, "smultt","nms" }, // d & n inverted!! | ||
242 | { 0x00000000, 0x00000000, NULL, NULL } | ||
243 | }; | ||
244 | |||
245 | static char const arm32_insn_conditions[][4] = { | ||
246 | "eq", "ne", "cs", "cc", | ||
247 | "mi", "pl", "vs", "vc", | ||
248 | "hi", "ls", "ge", "lt", | ||
249 | "gt", "le", "", "nv" | ||
250 | }; | ||
251 | |||
252 | static char const insn_block_transfers[][4] = { | ||
253 | "da", "ia", "db", "ib" | ||
254 | }; | ||
255 | |||
256 | static char const insn_stack_block_transfers[][4] = { | ||
257 | "ed", "ea", "fd", "fa" | ||
258 | }; | ||
259 | |||
260 | static char const op_shifts[][4] = { | ||
261 | "lsl", "lsr", "asr", "ror" | ||
262 | }; | ||
263 | |||
264 | static char const insn_fpa_rounding[][2] = { | ||
265 | "", "p", "m", "z" | ||
266 | }; | ||
267 | |||
268 | static char const insn_fpa_precision[][2] = { | ||
269 | "s", "d", "e", "p" | ||
270 | }; | ||
271 | |||
272 | static char const insn_fpaconstants[][8] = { | ||
273 | "0.0", "1.0", "2.0", "3.0", | ||
274 | "4.0", "5.0", "0.5", "10.0" | ||
275 | }; | ||
276 | |||
277 | #define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] | ||
278 | #define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] | ||
279 | #define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3] | ||
280 | #define op2_shift(x) op_shifts[(x >> 5) & 3] | ||
281 | #define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] | ||
282 | #define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] | ||
283 | #define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] | ||
284 | #define insn_fpaimm(x) insn_fpaconstants[x & 0x07] | ||
285 | |||
286 | /* Local prototypes */ | ||
287 | static void disasm_register_shift(const disasm_interface_t *di, u_int insn); | ||
288 | static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); | ||
289 | static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, | ||
290 | u_int loc); | ||
291 | static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, | ||
292 | u_int loc); | ||
293 | static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, | ||
294 | u_int loc); | ||
295 | static u_int disassemble_readword(u_int address); | ||
296 | static void disassemble_printaddr(u_int address); | ||
297 | |||
298 | u_int | ||
299 | disasm(const disasm_interface_t *di, u_int loc, int altfmt) | ||
300 | { | ||
301 | const struct arm32_insn *i_ptr = &arm32_i[0]; | ||
302 | |||
303 | u_int insn; | ||
304 | int matchp; | ||
305 | int branch; | ||
306 | char* f_ptr; | ||
307 | int fmt; | ||
308 | |||
309 | fmt = 0; | ||
310 | matchp = 0; | ||
311 | insn = di->di_readword(loc); | ||
312 | |||
313 | /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ | ||
314 | |||
315 | while (i_ptr->name) { | ||
316 | if ((insn & i_ptr->mask) == i_ptr->pattern) { | ||
317 | matchp = 1; | ||
318 | break; | ||
319 | } | ||
320 | i_ptr++; | ||
321 | } | ||
322 | |||
323 | if (!matchp) { | ||
324 | di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); | ||
325 | return(loc + INSN_SIZE); | ||
326 | } | ||
327 | |||
328 | /* If instruction forces condition code, don't print it. */ | ||
329 | if ((i_ptr->mask & 0xf0000000) == 0xf0000000) | ||
330 | di->di_printf("%s", i_ptr->name); | ||
331 | else | ||
332 | di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); | ||
333 | |||
334 | f_ptr = i_ptr->format; | ||
335 | |||
336 | /* Insert tab if there are no instruction modifiers */ | ||
337 | |||
338 | if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { | ||
339 | ++fmt; | ||
340 | di->di_printf("\t"); | ||
341 | } | ||
342 | |||
343 | while (*f_ptr) { | ||
344 | switch (*f_ptr) { | ||
345 | /* 2 - print Operand 2 of a data processing instruction */ | ||
346 | case '2': | ||
347 | if (insn & 0x02000000) { | ||
348 | int rotate= ((insn >> 7) & 0x1e); | ||
349 | |||
350 | di->di_printf("#0x%08x", | ||
351 | (insn & 0xff) << (32 - rotate) | | ||
352 | (insn & 0xff) >> rotate); | ||
353 | } else { | ||
354 | disasm_register_shift(di, insn); | ||
355 | } | ||
356 | break; | ||
357 | /* d - destination register (bits 12-15) */ | ||
358 | case 'd': | ||
359 | di->di_printf("r%d", ((insn >> 12) & 0x0f)); | ||
360 | break; | ||
361 | /* D - insert 'p' if Rd is R15 */ | ||
362 | case 'D': | ||
363 | if (((insn >> 12) & 0x0f) == 15) | ||
364 | di->di_printf("p"); | ||
365 | break; | ||
366 | /* n - n register (bits 16-19) */ | ||
367 | case 'n': | ||
368 | di->di_printf("r%d", ((insn >> 16) & 0x0f)); | ||
369 | break; | ||
370 | /* s - s register (bits 8-11) */ | ||
371 | case 's': | ||
372 | di->di_printf("r%d", ((insn >> 8) & 0x0f)); | ||
373 | break; | ||
374 | /* o - indirect register rn (bits 16-19) (used by swap) */ | ||
375 | case 'o': | ||
376 | di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); | ||
377 | break; | ||
378 | /* m - m register (bits 0-4) */ | ||
379 | case 'm': | ||
380 | di->di_printf("r%d", ((insn >> 0) & 0x0f)); | ||
381 | break; | ||
382 | /* a - address operand of ldr/str instruction */ | ||
383 | case 'a': | ||
384 | disasm_insn_ldrstr(di, insn, loc); | ||
385 | break; | ||
386 | /* e - address operand of ldrh/strh instruction */ | ||
387 | case 'e': | ||
388 | disasm_insn_ldrhstrh(di, insn, loc); | ||
389 | break; | ||
390 | /* l - register list for ldm/stm instruction */ | ||
391 | case 'l': | ||
392 | disasm_print_reglist(di, insn); | ||
393 | break; | ||
394 | /* f - 1st fp operand (register) (bits 12-14) */ | ||
395 | case 'f': | ||
396 | di->di_printf("f%d", (insn >> 12) & 7); | ||
397 | break; | ||
398 | /* g - 2nd fp operand (register) (bits 16-18) */ | ||
399 | case 'g': | ||
400 | di->di_printf("f%d", (insn >> 16) & 7); | ||
401 | break; | ||
402 | /* h - 3rd fp operand (register/immediate) (bits 0-4) */ | ||
403 | case 'h': | ||
404 | if (insn & (1 << 3)) | ||
405 | di->di_printf("#%s", insn_fpaimm(insn)); | ||
406 | else | ||
407 | di->di_printf("f%d", insn & 7); | ||
408 | break; | ||
409 | /* b - branch address */ | ||
410 | case 'b': | ||
411 | branch = ((insn << 2) & 0x03ffffff); | ||
412 | if (branch & 0x02000000) | ||
413 | branch |= 0xfc000000; | ||
414 | di->di_printaddr(loc + 8 + branch); | ||
415 | break; | ||
416 | /* t - blx address */ | ||
417 | case 't': | ||
418 | branch = ((insn << 2) & 0x03ffffff) | | ||
419 | (insn >> 23 & 0x00000002); | ||
420 | if (branch & 0x02000000) | ||
421 | branch |= 0xfc000000; | ||
422 | di->di_printaddr(loc + 8 + branch); | ||
423 | break; | ||
424 | /* X - block transfer type */ | ||
425 | case 'X': | ||
426 | di->di_printf("%s", insn_blktrans(insn)); | ||
427 | break; | ||
428 | /* Y - block transfer type (r13 base) */ | ||
429 | case 'Y': | ||
430 | di->di_printf("%s", insn_stkblktrans(insn)); | ||
431 | break; | ||
432 | /* c - comment field bits(0-23) */ | ||
433 | case 'c': | ||
434 | di->di_printf("0x%08x", (insn & 0x00ffffff)); | ||
435 | break; | ||
436 | /* k - breakpoint comment (bits 0-3, 8-19) */ | ||
437 | case 'k': | ||
438 | di->di_printf("0x%04x", | ||
439 | (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); | ||
440 | break; | ||
441 | /* p - saved or current status register */ | ||
442 | case 'p': | ||
443 | if (insn & 0x00400000) | ||
444 | di->di_printf("spsr"); | ||
445 | else | ||
446 | di->di_printf("cpsr"); | ||
447 | break; | ||
448 | /* F - PSR transfer fields */ | ||
449 | case 'F': | ||
450 | di->di_printf("_"); | ||
451 | if (insn & (1 << 16)) | ||
452 | di->di_printf("c"); | ||
453 | if (insn & (1 << 17)) | ||
454 | di->di_printf("x"); | ||
455 | if (insn & (1 << 18)) | ||
456 | di->di_printf("s"); | ||
457 | if (insn & (1 << 19)) | ||
458 | di->di_printf("f"); | ||
459 | break; | ||
460 | /* B - byte transfer flag */ | ||
461 | case 'B': | ||
462 | if (insn & 0x00400000) | ||
463 | di->di_printf("b"); | ||
464 | break; | ||
465 | /* L - co-processor transfer size */ | ||
466 | case 'L': | ||
467 | if (insn & (1 << 22)) | ||
468 | di->di_printf("l"); | ||
469 | break; | ||
470 | /* S - set status flag */ | ||
471 | case 'S': | ||
472 | if (insn & 0x00100000) | ||
473 | di->di_printf("s"); | ||
474 | break; | ||
475 | /* P - fp precision */ | ||
476 | case 'P': | ||
477 | di->di_printf("%s", insn_fpaprec(insn)); | ||
478 | break; | ||
479 | /* Q - fp precision (for ldf/stf) */ | ||
480 | case 'Q': | ||
481 | break; | ||
482 | /* R - fp rounding */ | ||
483 | case 'R': | ||
484 | di->di_printf("%s", insn_fparnd(insn)); | ||
485 | break; | ||
486 | /* W - writeback flag */ | ||
487 | case 'W': | ||
488 | if (insn & (1 << 21)) | ||
489 | di->di_printf("!"); | ||
490 | break; | ||
491 | /* # - co-processor number */ | ||
492 | case '#': | ||
493 | di->di_printf("p%d", (insn >> 8) & 0x0f); | ||
494 | break; | ||
495 | /* v - co-processor data transfer registers+addressing mode */ | ||
496 | case 'v': | ||
497 | disasm_insn_ldcstc(di, insn, loc); | ||
498 | break; | ||
499 | /* x - instruction in hex */ | ||
500 | case 'x': | ||
501 | di->di_printf("0x%08x", insn); | ||
502 | break; | ||
503 | /* y - co-processor data processing registers */ | ||
504 | case 'y': | ||
505 | di->di_printf("%d, ", (insn >> 20) & 0x0f); | ||
506 | |||
507 | di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, | ||
508 | (insn >> 16) & 0x0f, insn & 0x0f); | ||
509 | |||
510 | di->di_printf(", %d", (insn >> 5) & 0x07); | ||
511 | break; | ||
512 | /* z - co-processor register transfer registers */ | ||
513 | case 'z': | ||
514 | di->di_printf("%d, ", (insn >> 21) & 0x07); | ||
515 | di->di_printf("r%d, c%d, c%d, %d", | ||
516 | (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, | ||
517 | insn & 0x0f, (insn >> 5) & 0x07); | ||
518 | |||
519 | /* if (((insn >> 5) & 0x07) != 0) | ||
520 | di->di_printf(", %d", (insn >> 5) & 0x07);*/ | ||
521 | break; | ||
522 | default: | ||
523 | di->di_printf("[%c - unknown]", *f_ptr); | ||
524 | break; | ||
525 | } | ||
526 | if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') | ||
527 | ++f_ptr; | ||
528 | else if (*(++f_ptr)) { | ||
529 | ++fmt; | ||
530 | if (fmt == 1) | ||
531 | di->di_printf("\t"); | ||
532 | else | ||
533 | di->di_printf(", "); | ||
534 | } | ||
535 | }; | ||
536 | |||
537 | di->di_printf("\n"); | ||
538 | |||
539 | return(loc + INSN_SIZE); | ||
540 | } | ||
541 | |||
542 | |||
543 | static void | ||
544 | disasm_register_shift(const disasm_interface_t *di, u_int insn) | ||
545 | { | ||
546 | di->di_printf("r%d", (insn & 0x0f)); | ||
547 | if ((insn & 0x00000ff0) == 0) | ||
548 | ; | ||
549 | else if ((insn & 0x00000ff0) == 0x00000060) | ||
550 | di->di_printf(", rrx"); | ||
551 | else { | ||
552 | if (insn & 0x10) | ||
553 | di->di_printf(", %s r%d", op2_shift(insn), | ||
554 | (insn >> 8) & 0x0f); | ||
555 | else | ||
556 | di->di_printf(", %s #%d", op2_shift(insn), | ||
557 | (insn >> 7) & 0x1f); | ||
558 | } | ||
559 | } | ||
560 | |||
561 | |||
562 | static void | ||
563 | disasm_print_reglist(const disasm_interface_t *di, u_int insn) | ||
564 | { | ||
565 | int loop; | ||
566 | int start; | ||
567 | int comma; | ||
568 | |||
569 | di->di_printf("{"); | ||
570 | start = -1; | ||
571 | comma = 0; | ||
572 | |||
573 | for (loop = 0; loop < 17; ++loop) { | ||
574 | if (start != -1) { | ||
575 | if (loop == 16 || !(insn & (1 << loop))) { | ||
576 | if (comma) | ||
577 | di->di_printf(", "); | ||
578 | else | ||
579 | comma = 1; | ||
580 | if (start == loop - 1) | ||
581 | di->di_printf("r%d", start); | ||
582 | else | ||
583 | di->di_printf("r%d-r%d", start, loop - 1); | ||
584 | start = -1; | ||
585 | } | ||
586 | } else { | ||
587 | if (insn & (1 << loop)) | ||
588 | start = loop; | ||
589 | } | ||
590 | } | ||
591 | di->di_printf("}"); | ||
592 | |||
593 | if (insn & (1 << 22)) | ||
594 | di->di_printf("^"); | ||
595 | } | ||
596 | |||
597 | static void | ||
598 | disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) | ||
599 | { | ||
600 | int offset; | ||
601 | |||
602 | offset = insn & 0xfff; | ||
603 | if ((insn & 0x032f0000) == 0x010f0000) { | ||
604 | /* rA = pc, immediate index */ | ||
605 | if (insn & 0x00800000) | ||
606 | loc += offset; | ||
607 | else | ||
608 | loc -= offset; | ||
609 | di->di_printaddr(loc + 8); | ||
610 | } else { | ||
611 | di->di_printf("[r%d", (insn >> 16) & 0x0f); | ||
612 | if ((insn & 0x03000fff) != 0x01000000) { | ||
613 | di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); | ||
614 | if (!(insn & 0x00800000)) | ||
615 | di->di_printf("-"); | ||
616 | if (insn & (1 << 25)) | ||
617 | disasm_register_shift(di, insn); | ||
618 | else | ||
619 | di->di_printf("#0x%03x", offset); | ||
620 | } | ||
621 | if (insn & (1 << 24)) | ||
622 | di->di_printf("]"); | ||
623 | } | ||
624 | } | ||
625 | |||
626 | static void | ||
627 | disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc) | ||
628 | { | ||
629 | int offset; | ||
630 | |||
631 | offset = ((insn & 0xf00) >> 4) | (insn & 0xf); | ||
632 | if ((insn & 0x004f0000) == 0x004f0000) { | ||
633 | /* rA = pc, immediate index */ | ||
634 | if (insn & 0x00800000) | ||
635 | loc += offset; | ||
636 | else | ||
637 | loc -= offset; | ||
638 | di->di_printaddr(loc + 8); | ||
639 | } else { | ||
640 | di->di_printf("[r%d", (insn >> 16) & 0x0f); | ||
641 | if ((insn & 0x01400f0f) != 0x01400000) { | ||
642 | di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); | ||
643 | if (!(insn & 0x00800000)) | ||
644 | di->di_printf("-"); | ||
645 | if (insn & (1 << 22)) | ||
646 | di->di_printf("#0x%02x", offset); | ||
647 | else | ||
648 | di->di_printf("r%d", (insn & 0x0f)); | ||
649 | } | ||
650 | if (insn & (1 << 24)) | ||
651 | di->di_printf("]"); | ||
652 | } | ||
653 | } | ||
654 | |||
655 | static void | ||
656 | disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) | ||
657 | { | ||
658 | if (((insn >> 8) & 0xf) == 1) | ||
659 | di->di_printf("f%d, ", (insn >> 12) & 0x07); | ||
660 | else | ||
661 | di->di_printf("c%d, ", (insn >> 12) & 0x0f); | ||
662 | |||
663 | di->di_printf("[r%d", (insn >> 16) & 0x0f); | ||
664 | |||
665 | di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); | ||
666 | |||
667 | if (!(insn & (1 << 23))) | ||
668 | di->di_printf("-"); | ||
669 | |||
670 | di->di_printf("#0x%03x", (insn & 0xff) << 2); | ||
671 | |||
672 | if (insn & (1 << 24)) | ||
673 | di->di_printf("]"); | ||
674 | |||
675 | if (insn & (1 << 21)) | ||
676 | di->di_printf("!"); | ||
677 | } | ||
678 | |||
679 | static u_int | ||
680 | disassemble_readword(u_int address) | ||
681 | { | ||
682 | return(*((u_int *)address)); | ||
683 | } | ||
684 | |||
685 | static void | ||
686 | disassemble_printaddr(u_int address) | ||
687 | { | ||
688 | printf("0x%08x", address); | ||
689 | } | ||
690 | |||
691 | static const disasm_interface_t disassemble_di = { | ||
692 | disassemble_readword, disassemble_printaddr, printf | ||
693 | }; | ||
694 | |||
695 | void | ||
696 | disassemble(u_int address) | ||
697 | { | ||
698 | |||
699 | (void)disasm(&disassemble_di, address, 0); | ||
700 | } | ||
701 | |||
702 | /* End of disassem.c */ | ||