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authorAlistair Strachan2019-01-15 12:20:28 -0600
committerAlistair Strachan2019-01-15 12:51:13 -0600
commitb64db842f7c8bdb8e1946216de67c4dc00042abb (patch)
tree7861e2f1eac3d986bd8141f9871c059bc3c8c0a3
parent9e020547bedb6c7188de6278f4e28aff6369dc7a (diff)
parentd3689267f92c5956e09cc7d1baa4700141662bff (diff)
downloadu-boot-aosp-master.tar.gz
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Merge v2019.01 from aosp/upstream-master into masteraosp-master
Change-Id: I0ec59133084ed919c953c651561522c8ccc81863 Signed-off-by: Alistair Strachan <astrachan@google.com>
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-rw-r--r--drivers/spi/sun4i_spi.c3
-rw-r--r--drivers/timer/Kconfig7
-rw-r--r--drivers/timer/Makefile1
-rw-r--r--drivers/timer/riscv_timer.c56
-rw-r--r--drivers/usb/gadget/Makefile2
-rw-r--r--drivers/usb/gadget/udc/Makefile3
-rw-r--r--drivers/usb/gadget/udc/udc-uclass.c7
-rw-r--r--drivers/usb/host/xhci-mem.c3
-rw-r--r--drivers/video/fonts/Kconfig1
-rw-r--r--drivers/w1/Kconfig14
-rw-r--r--drivers/w1/Makefile1
-rw-r--r--drivers/w1/mxc_w1.c232
-rw-r--r--drivers/watchdog/Kconfig6
-rw-r--r--drivers/watchdog/Makefile2
-rw-r--r--drivers/watchdog/imx_watchdog.c9
-rw-r--r--env/env.c3
-rw-r--r--env/sata.c2
-rw-r--r--fs/cbfs/cbfs.c7
-rw-r--r--fs/fat/fat.c5
-rw-r--r--include/altera.h8
-rw-r--r--include/bootm.h2
-rw-r--r--include/cbfs.h14
-rw-r--r--include/configs/bmips_common.h6
-rw-r--r--include/configs/ci20.h72
-rw-r--r--include/configs/edison.h10
-rw-r--r--include/configs/embestmx6boards.h13
-rw-r--r--include/configs/helios4.h2
-rw-r--r--include/configs/imx8mq_evk.h246
-rw-r--r--include/configs/m53menlo.h3
-rw-r--r--include/configs/mt7623.h2
-rw-r--r--include/configs/odroid.h4
-rw-r--r--include/configs/odroid_xu3.h5
-rw-r--r--include/configs/omap3_igep00x0.h4
-rw-r--r--include/configs/pcm058.h1
-rw-r--r--include/configs/pico-imx7d.h14
-rw-r--r--include/configs/poplar.h6
-rw-r--r--include/configs/s5p_goni.h4
-rw-r--r--include/configs/s5pc210_universal.h4
-rw-r--r--include/configs/tbs2910.h2
-rw-r--r--include/configs/trats.h4
-rw-r--r--include/configs/trats2.h4
-rw-r--r--include/configs/uniphier.h26
-rw-r--r--include/configs/vcoreiii.h82
-rw-r--r--include/cpu.h3
-rw-r--r--include/dm/pinctrl.h12
-rw-r--r--include/dt-bindings/clock/bcm6318-clock.h11
-rw-r--r--include/dt-bindings/clock/jz4780-cgu.h89
-rw-r--r--include/dt-bindings/dma/bcm6318-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm63268-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6328-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6338-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6348-dma.h16
-rw-r--r--include/dt-bindings/dma/bcm6358-dma.h16
-rw-r--r--include/dt-bindings/dma/bcm6362-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6368-dma.h14
-rw-r--r--include/environment/ti/boot.h7
-rw-r--r--include/imximage.h17
-rw-r--r--include/linux/kernel.h12
-rw-r--r--include/spl.h13
-rw-r--r--include/vxworks.h1
-rw-r--r--lib/crc32.c3
-rw-r--r--lib/efi_loader/efi_runtime.c34
-rw-r--r--lib/efi_selftest/efi_selftest_block_device.c10
-rw-r--r--scripts/Makefile.spl2
-rwxr-xr-xscripts/check-config.sh9
-rw-r--r--scripts/config_whitelist.txt10
-rw-r--r--test/dm/video.c6
-rw-r--r--test/overlay/Kconfig7
-rw-r--r--tools/Makefile1
-rw-r--r--tools/imagetool.h1
-rw-r--r--tools/imx8image.c2
-rwxr-xr-xtools/imx8m_image.sh43
-rw-r--r--tools/imx8mimage.c623
-rwxr-xr-xtools/imx_cntr_image.sh2
-rw-r--r--tools/mkimage.c7
724 files changed, 21969 insertions, 1767 deletions
diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
new file mode 100644
index 0000000000..23599b97c0
--- /dev/null
+++ b/.github/pull_request_template.md
@@ -0,0 +1,3 @@
1Please do not submit a Pull Request via github. Our project makes use of
2mailing lists for patch submission and review. For more details please
3see https://www.denx.de/wiki/U-Boot/Patches
diff --git a/Android.bp b/Android.bp
index 5bb58e7ae5..25c6d9af5a 100644
--- a/Android.bp
+++ b/Android.bp
@@ -57,6 +57,7 @@ cc_binary_host {
57 "tools/image-host.c", 57 "tools/image-host.c",
58 "tools/imagetool.c", 58 "tools/imagetool.c",
59 "tools/imx8image.c", 59 "tools/imx8image.c",
60 "tools/imx8mimage.c",
60 "tools/imximage.c", 61 "tools/imximage.c",
61 "tools/kwbimage.c", 62 "tools/kwbimage.c",
62 "tools/libfdt/fdt.c", 63 "tools/libfdt/fdt.c",
diff --git a/Kconfig b/Kconfig
index 9e0b8af40a..aff7b2e00a 100644
--- a/Kconfig
+++ b/Kconfig
@@ -251,6 +251,16 @@ config FIT
251 251
252if FIT 252if FIT
253 253
254config FIT_EXTERNAL_OFFSET
255 hex "Text Base"
256 default 0x0
257 help
258 This specifies a data offset in fit image.
259 The offset is from data payload offset to the beginning of
260 fit image header. When specifies a offset, specific data
261 could be put in the hole between data payload and fit image
262 header, such as CSF data on i.MX platform.
263
254config FIT_ENABLE_SHA256_SUPPORT 264config FIT_ENABLE_SHA256_SUPPORT
255 bool "Support SHA256 checksum of FIT image contents" 265 bool "Support SHA256 checksum of FIT image contents"
256 default y 266 default y
diff --git a/MAINTAINERS b/MAINTAINERS
index 0fb089807c..f86fdf9c33 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -123,7 +123,7 @@ F: drivers/spi/bcmstb_spi.c
123ARM FREESCALE IMX 123ARM FREESCALE IMX
124M: Stefano Babic <sbabic@denx.de> 124M: Stefano Babic <sbabic@denx.de>
125M: Fabio Estevam <fabio.estevam@nxp.com> 125M: Fabio Estevam <fabio.estevam@nxp.com>
126R: NXP Linux Team <linux-imx@nxp.com> 126R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
127S: Maintained 127S: Maintained
128T: git git://git.denx.de/u-boot-imx.git 128T: git git://git.denx.de/u-boot-imx.git
129F: arch/arm/cpu/arm1136/mx*/ 129F: arch/arm/cpu/arm1136/mx*/
@@ -512,6 +512,24 @@ S: Maintained
512T: git git://git.denx.de/u-boot-mips.git 512T: git git://git.denx.de/u-boot-mips.git
513F: arch/mips/ 513F: arch/mips/
514 514
515MIPS MSCC
516M: Gregory CLEMENT <gregory.clement@bootlin.com>
517M: Lars Povlsen <lars.povlsen@microchip.com>
518M: Horatiu Vultur <horatiu.vultur@microchip.com>
519S: Maintained
520F: arch/mips/mach-mscc/
521F: arch/mips/dts/luton*
522F: arch/mips/dts/mscc*
523F: arch/mips/dts/ocelot*
524F: board/mscc/
525F: configs/mscc*
526F: include/configs/vcoreiii.h
527
528MIPS JZ4780
529M: Ezequiel Garcia <ezequiel@collabora.com>
530S: Maintained
531F: arch/mips/mach-jz47xx/
532
515MMC 533MMC
516M: Jaehoon Chung <jh80.chung@samsung.com> 534M: Jaehoon Chung <jh80.chung@samsung.com>
517S: Maintained 535S: Maintained
diff --git a/Makefile b/Makefile
index a8461dd611..6aa08964ff 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
3VERSION = 2019 3VERSION = 2019
4PATCHLEVEL = 01 4PATCHLEVEL = 01
5SUBLEVEL = 5SUBLEVEL =
6EXTRAVERSION = -rc2 6EXTRAVERSION =
7NAME = 7NAME =
8 8
9# *DOCUMENTATION* 9# *DOCUMENTATION*
@@ -712,8 +712,8 @@ libs-y += drivers/usb/dwc3/
712libs-y += drivers/usb/common/ 712libs-y += drivers/usb/common/
713libs-y += drivers/usb/emul/ 713libs-y += drivers/usb/emul/
714libs-y += drivers/usb/eth/ 714libs-y += drivers/usb/eth/
715libs-y += drivers/usb/gadget/ 715libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
716libs-y += drivers/usb/gadget/udc/ 716libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
717libs-y += drivers/usb/host/ 717libs-y += drivers/usb/host/
718libs-y += drivers/usb/musb/ 718libs-y += drivers/usb/musb/
719libs-y += drivers/usb/musb-new/ 719libs-y += drivers/usb/musb-new/
@@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
893 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) 893 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
894 894
895quiet_cmd_mkfitimage = MKIMAGE $@ 895quiet_cmd_mkfitimage = MKIMAGE $@
896cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \ 896cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
897 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) 897 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
898 898
899quiet_cmd_cat = CAT $@ 899quiet_cmd_cat = CAT $@
@@ -938,7 +938,8 @@ ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
938 @echo >&2 "====================================================" 938 @echo >&2 "===================================================="
939endif 939endif
940endif 940endif
941ifeq ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y) 941ifeq ($(CONFIG_LIBATA)$(CONFIG_MVSATA_IDE),y)
942ifneq ($(CONFIG_DM_SCSI),y)
942 @echo >&2 "===================== WARNING ======================" 943 @echo >&2 "===================== WARNING ======================"
943 @echo >&2 "This board does not use CONFIG_DM_SCSI. Please update" 944 @echo >&2 "This board does not use CONFIG_DM_SCSI. Please update"
944 @echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release." 945 @echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release."
@@ -946,6 +947,27 @@ ifeq ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y)
946 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." 947 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
947 @echo >&2 "====================================================" 948 @echo >&2 "===================================================="
948endif 949endif
950endif
951ifeq ($(CONFIG_PCI),y)
952ifneq ($(CONFIG_DM_PCI),y)
953 @echo >&2 "===================== WARNING ======================"
954 @echo >&2 "This board does not use CONFIG_DM_PCI Please update"
955 @echo >&2 "the board to use CONFIG_DM_PCI before the v2019.07 release."
956 @echo >&2 "Failure to update by the deadline may result in board removal."
957 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
958 @echo >&2 "===================================================="
959endif
960endif
961ifneq ($(CONFIG_LCD)$(CONFIG_VIDEO),)
962ifneq ($(CONFIG_DM_VIDEO),y)
963 @echo >&2 "===================== WARNING ======================"
964 @echo >&2 "This board does not use CONFIG_DM_VIDEO Please update"
965 @echo >&2 "the board to use CONFIG_DM_VIDEO before the v2019.07 release."
966 @echo >&2 "Failure to update by the deadline may result in board removal."
967 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
968 @echo >&2 "===================================================="
969endif
970endif
949ifeq ($(CONFIG_OF_EMBED),y) 971ifeq ($(CONFIG_OF_EMBED),y)
950 @echo >&2 "===================== WARNING ======================" 972 @echo >&2 "===================== WARNING ======================"
951 @echo >&2 "CONFIG_OF_EMBED is enabled. This option should only" 973 @echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
@@ -954,6 +976,27 @@ ifeq ($(CONFIG_OF_EMBED),y)
954 @echo >&2 "See doc/README.fdt-control for more info." 976 @echo >&2 "See doc/README.fdt-control for more info."
955 @echo >&2 "====================================================" 977 @echo >&2 "===================================================="
956endif 978endif
979ifeq ($(CONFIG_SPI),y)
980ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
981 @echo >&2 "===================== WARNING ======================"
982 @echo >&2 "This board does not use CONFIG_DM_SPI. Please update"
983 @echo >&2 "the board before v2019.04 for no dm conversion"
984 @echo >&2 "and v2019.07 for partially dm converted drivers."
985 @echo >&2 "Failure to update can lead to driver/board removal"
986 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
987 @echo >&2 "===================================================="
988endif
989endif
990ifeq ($(CONFIG_SPI_FLASH),y)
991ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy)
992 @echo >&2 "===================== WARNING ======================"
993 @echo >&2 "This board does not use CONFIG_DM_SPI_FLASH. Please update"
994 @echo >&2 "the board to use CONFIG_SPI_FLASH before the v2019.07 release."
995 @echo >&2 "Failure to update by the deadline may result in board removal."
996 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
997 @echo >&2 "===================================================="
998endif
999endif
957 @# Check that this build does not use CONFIG options that we do not 1000 @# Check that this build does not use CONFIG options that we do not
958 @# know about unless they are in Kconfig. All the existing CONFIG 1001 @# know about unless they are in Kconfig. All the existing CONFIG
959 @# options are whitelisted, so new ones should not be added. 1002 @# options are whitelisted, so new ones should not be added.
@@ -1112,6 +1155,9 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
1112else 1155else
1113ifneq ($(CONFIG_SPL_FIT_GENERATOR),"") 1156ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
1114U_BOOT_ITS := u-boot.its 1157U_BOOT_ITS := u-boot.its
1158ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
1159U_BOOT_ITS_DEPS += u-boot-nodtb.bin
1160endif
1115ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py") 1161ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
1116U_BOOT_ITS_DEPS += u-boot 1162U_BOOT_ITS_DEPS += u-boot
1117endif 1163endif
@@ -1207,6 +1253,11 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
1207SPL: spl/u-boot-spl.bin FORCE 1253SPL: spl/u-boot-spl.bin FORCE
1208 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ 1254 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
1209 1255
1256ifeq ($(CONFIG_ARCH_IMX8M), y)
1257flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
1258 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
1259endif
1260
1210u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE 1261u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
1211 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ 1262 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
1212 1263
diff --git a/api/api_storage.c b/api/api_storage.c
index 8aeeda2715..2b90c18aae 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -99,6 +99,7 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
99{ 99{
100 struct blk_desc *dd; 100 struct blk_desc *dd;
101 int found = 0; 101 int found = 0;
102 int found_last = 0;
102 int i = 0; 103 int i = 0;
103 104
104 /* Wasn't configured for this type, return 0 directly */ 105 /* Wasn't configured for this type, return 0 directly */
@@ -111,9 +112,13 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
111 if (di->cookie == 112 if (di->cookie ==
112 (void *)blk_get_dev(specs[type].name, i)) { 113 (void *)blk_get_dev(specs[type].name, i)) {
113 i += 1; 114 i += 1;
115 found_last = 1;
114 break; 116 break;
115 } 117 }
116 } 118 }
119
120 if (!found_last)
121 i = 0;
117 } 122 }
118 123
119 for (; i < specs[type].max_dev; i++) { 124 for (; i < specs[type].max_dev; i++) {
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cb7ec58079..d6b1629a00 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -607,6 +607,7 @@ config ARCH_EXYNOS
607 select DM_SPI 607 select DM_SPI
608 select DM_SPI_FLASH 608 select DM_SPI_FLASH
609 select SPI 609 select SPI
610 imply SYS_THUMB_BUILD
610 imply CMD_DM 611 imply CMD_DM
611 imply FAT_WRITE 612 imply FAT_WRITE
612 613
@@ -694,7 +695,7 @@ config ARCH_IMX8
694 select DM 695 select DM
695 select OF_CONTROL 696 select OF_CONTROL
696 697
697config ARCH_MX8M 698config ARCH_IMX8M
698 bool "NXP i.MX8M platform" 699 bool "NXP i.MX8M platform"
699 select ARM64 700 select ARM64
700 select DM 701 select DM
@@ -874,7 +875,6 @@ config ARCH_SUNXI
874 imply PRE_CONSOLE_BUFFER 875 imply PRE_CONSOLE_BUFFER
875 imply SPL_GPIO_SUPPORT 876 imply SPL_GPIO_SUPPORT
876 imply SPL_LIBCOMMON_SUPPORT 877 imply SPL_LIBCOMMON_SUPPORT
877 imply SPL_LIBDISK_SUPPORT
878 imply SPL_LIBGENERIC_SUPPORT 878 imply SPL_LIBGENERIC_SUPPORT
879 imply SPL_MMC_SUPPORT if MMC 879 imply SPL_MMC_SUPPORT if MMC
880 imply SPL_POWER_SUPPORT 880 imply SPL_POWER_SUPPORT
@@ -1451,7 +1451,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig"
1451 1451
1452source "arch/arm/mach-imx/imx8/Kconfig" 1452source "arch/arm/mach-imx/imx8/Kconfig"
1453 1453
1454source "arch/arm/mach-imx/mx8m/Kconfig" 1454source "arch/arm/mach-imx/imx8m/Kconfig"
1455 1455
1456source "arch/arm/mach-imx/mxs/Kconfig" 1456source "arch/arm/mach-imx/mxs/Kconfig"
1457 1457
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c38ef3cb69..87d9d4b9f7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -103,11 +103,11 @@ libs-y += arch/arm/cpu/
103libs-y += arch/arm/lib/ 103libs-y += arch/arm/lib/
104 104
105ifeq ($(CONFIG_SPL_BUILD),y) 105ifeq ($(CONFIG_SPL_BUILD),y)
106ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) 106ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
107libs-y += arch/arm/mach-imx/ 107libs-y += arch/arm/mach-imx/
108endif 108endif
109else 109else
110ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) 110ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
111libs-y += arch/arm/mach-imx/ 111libs-y += arch/arm/mach-imx/
112endif 112endif
113endif 113endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
index a6ef830069..9583bf743e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
@@ -8,3 +8,14 @@ Freescale LayerScape with Chassis Generation 2
8 8
9This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, 9This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
10for example LS1043A. 10for example LS1043A.
11
12Watchdog support Overview
13-------------------
14Support watchdog driver for LSCH2. The driver is disabled in default.
15You can enable it by setting CONFIG_IMX_WATCHDOG.
16Use following config to set watchdog timeout, if this config is not defined,
17the default timeout value is 128s which is the maximum. Set 10 seconds for
18example:
19 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000
20Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the
21watchdog will not be fed in u-boot.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dc6f6b233a..dda4e59491 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -466,6 +466,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
466 466
467dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb 467dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
468 468
469dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
470
469dtb-$(CONFIG_RCAR_GEN3) += \ 471dtb-$(CONFIG_RCAR_GEN3) += \
470 r8a7795-h3ulcb-u-boot.dtb \ 472 r8a7795-h3ulcb-u-boot.dtb \
471 r8a7795-salvator-x-u-boot.dtb \ 473 r8a7795-salvator-x-u-boot.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
new file mode 100644
index 0000000000..4a08099b3c
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -0,0 +1,414 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6/dts-v1/;
7
8/* First 128KB is for PSCI ATF. */
9/memreserve/ 0x40000000 0x00020000;
10
11#include "fsl-imx8mq.dtsi"
12
13/ {
14 model = "Freescale i.MX8MQ EVK";
15 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16
17 chosen {
18 bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 reg_usdhc2_vmmc: usdhc2_vmmc {
27 compatible = "regulator-fixed";
28 regulator-name = "VSD_3V3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32 enable-active-high;
33 };
34 };
35
36 pwmleds {
37 compatible = "pwm-leds";
38
39 ledpwm2 {
40 label = "PWM2";
41 pwms = <&pwm2 0 50000>;
42 max-brightness = <255>;
43 };
44 };
45};
46
47&iomuxc {
48 pinctrl-names = "default";
49
50 imx8mq-evk {
51 pinctrl_fec1: fec1grp {
52 fsl,pins = <
53 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
54 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
55 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
56 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
57 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
58 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
59 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
60 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
61 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
62 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
63 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
64 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
65 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
66 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
67 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
68 >;
69 };
70
71 pinctrl_i2c1: i2c1grp {
72 fsl,pins = <
73 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
74 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
75 >;
76 };
77
78 pinctrl_i2c2: i2c2grp {
79 fsl,pins = <
80 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
81 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
82 >;
83 };
84
85 pinctrl_pwm2: pwm2grp {
86 fsl,pins = <
87 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
88 >;
89 };
90
91 pinctrl_qspi: qspigrp {
92 fsl,pins = <
93 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
94 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
95 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
96 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
97 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
98 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
99
100 >;
101 };
102
103 pinctrl_usdhc1: usdhc1grp {
104 fsl,pins = <
105 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
106 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
107 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
108 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
109 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
110 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
111 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
112 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
113 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
114 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
115 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
116 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
117 >;
118 };
119
120 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
121 fsl,pins = <
122 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
123 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
124 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
125 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
126 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
127 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
128 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
129 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
130 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
131 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
132 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
133 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
134 >;
135 };
136
137 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
138 fsl,pins = <
139 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
140 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
141 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
142 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
143 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
144 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
145 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
146 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
147 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
148 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
149 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
150 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
151 >;
152 };
153
154 pinctrl_usdhc2_gpio: usdhc2grpgpio {
155 fsl,pins = <
156 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
157 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
158 >;
159 };
160
161 pinctrl_usdhc2: usdhc2grp {
162 fsl,pins = <
163 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
164 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
165 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
166 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
167 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
168 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
169 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
170 >;
171 };
172
173 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
174 fsl,pins = <
175 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
176 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
177 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
178 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
179 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
180 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
181 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
182 >;
183 };
184
185 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
186 fsl,pins = <
187 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
188 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
189 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
190 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
191 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
192 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
193 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
194 >;
195 };
196
197 pinctrl_sai2: sai2grp {
198 fsl,pins = <
199 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
200 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
201 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
202 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
203 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
204 >;
205 };
206
207 pinctrl_wdog: wdoggrp {
208 fsl,pins = <
209 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
210 >;
211 };
212 };
213};
214
215&fec1 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_fec1>;
218 phy-mode = "rgmii-id";
219 phy-handle = <&ethphy0>;
220 fsl,magic-packet;
221 status = "okay";
222
223 mdio {
224 #address-cells = <1>;
225 #size-cells = <0>;
226
227 ethphy0: ethernet-phy@0 {
228 compatible = "ethernet-phy-ieee802.3-c22";
229 reg = <0>;
230 at803x,led-act-blind-workaround;
231 at803x,eee-disabled;
232 };
233 };
234};
235
236&i2c1 {
237 clock-frequency = <100000>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c1>;
240 status = "okay";
241
242 pmic: pfuze100@08 {
243 compatible = "fsl,pfuze100";
244 reg = <0x08>;
245
246 regulators {
247 sw1a_reg: sw1ab {
248 regulator-min-microvolt = <300000>;
249 regulator-max-microvolt = <1875000>;
250 regulator-always-on;
251 };
252
253 sw1c_reg: sw1c {
254 regulator-min-microvolt = <300000>;
255 regulator-max-microvolt = <1875000>;
256 regulator-always-on;
257 };
258
259 sw2_reg: sw2 {
260 regulator-min-microvolt = <800000>;
261 regulator-max-microvolt = <3300000>;
262 regulator-always-on;
263 };
264
265 sw3a_reg: sw3ab {
266 regulator-min-microvolt = <400000>;
267 regulator-max-microvolt = <1975000>;
268 regulator-always-on;
269 };
270
271 sw4_reg: sw4 {
272 regulator-min-microvolt = <800000>;
273 regulator-max-microvolt = <3300000>;
274 regulator-always-on;
275 };
276
277 swbst_reg: swbst {
278 regulator-min-microvolt = <5000000>;
279 regulator-max-microvolt = <5150000>;
280 };
281
282 snvs_reg: vsnvs {
283 regulator-min-microvolt = <1000000>;
284 regulator-max-microvolt = <3000000>;
285 regulator-always-on;
286 };
287
288 vref_reg: vrefddr {
289 regulator-always-on;
290 };
291
292 vgen1_reg: vgen1 {
293 regulator-min-microvolt = <800000>;
294 regulator-max-microvolt = <1550000>;
295 };
296
297 vgen2_reg: vgen2 {
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1550000>;
300 regulator-always-on;
301 };
302
303 vgen3_reg: vgen3 {
304 regulator-min-microvolt = <1800000>;
305 regulator-max-microvolt = <3300000>;
306 regulator-always-on;
307 };
308
309 vgen4_reg: vgen4 {
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-always-on;
313 };
314
315 vgen5_reg: vgen5 {
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3300000>;
318 regulator-always-on;
319 };
320
321 vgen6_reg: vgen6 {
322 regulator-min-microvolt = <1800000>;
323 regulator-max-microvolt = <3300000>;
324 };
325 };
326 };
327};
328
329&i2c2 {
330 clock-frequency = <100000>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_i2c2>;
333 status = "disabled";
334};
335
336&pwm2 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_pwm2>;
339 status = "okay";
340};
341
342&lcdif {
343 status = "okay";
344 disp-dev = "mipi_dsi_northwest";
345 display = <&display0>;
346
347 display0: display@0 {
348 bits-per-pixel = <24>;
349 bus-width = <24>;
350
351 display-timings {
352 native-mode = <&timing0>;
353 timing0: timing0 {
354 clock-frequency = <9200000>;
355 hactive = <480>;
356 vactive = <272>;
357 hfront-porch = <8>;
358 hback-porch = <4>;
359 hsync-len = <41>;
360 vback-porch = <2>;
361 vfront-porch = <4>;
362 vsync-len = <10>;
363
364 hsync-active = <0>;
365 vsync-active = <0>;
366 de-active = <1>;
367 pixelclk-active = <0>;
368 };
369 };
370 };
371};
372
373&qspi {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_qspi>;
376 status = "okay";
377
378 flash0: n25q256a@0 {
379 reg = <0>;
380 #address-cells = <1>;
381 #size-cells = <1>;
382 compatible = "micron,n25q256a";
383 spi-max-frequency = <29000000>;
384 spi-nor,ddr-quad-read-dummy = <6>;
385 };
386};
387
388&usdhc1 {
389 pinctrl-names = "default", "state_100mhz", "state_200mhz";
390 pinctrl-0 = <&pinctrl_usdhc1>;
391 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
392 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
393 bus-width = <8>;
394 non-removable;
395 status = "okay";
396};
397
398&usdhc2 {
399 pinctrl-names = "default", "state_100mhz", "state_200mhz";
400 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
401 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
402 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
403 bus-width = <4>;
404 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
405 vmmc-supply = <&reg_usdhc2_vmmc>;
406 status = "okay";
407};
408
409&wdog1 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_wdog>;
412 fsl,ext-reset-output;
413 status = "okay";
414};
diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
new file mode 100644
index 0000000000..c46eb3f38d
--- /dev/null
+++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6/* wifi module */
7&sd_emmc_b {
8 status = "disabled";
9};
10
11/* emmc storage */
12&sd_emmc_c {
13 status = "okay";
14};
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index 1eb50cd438..54a7285e6e 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -12,6 +12,11 @@
12 tick-timer = &timer2; 12 tick-timer = &timer2;
13 }; 13 };
14 14
15 aliases {
16 usb0 = &usb1;
17 usb1 = &usb2;
18 };
19
15 ocp { 20 ocp {
16 u-boot,dm-spl; 21 u-boot,dm-spl;
17 22
diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi
index 9a61fbb453..8304f67192 100644
--- a/arch/arm/dts/rk3399-puma.dtsi
+++ b/arch/arm/dts/rk3399-puma.dtsi
@@ -172,10 +172,7 @@
172 regulator-max-microvolt = <1400000>; 172 regulator-max-microvolt = <1400000>;
173 regulator-always-on; 173 regulator-always-on;
174 regulator-boot-on; 174 regulator-boot-on;
175 175 regulator-init-microvolt = <950000>;
176 /* for rockchip boot on */
177 rockchip,pwm_id= <2>;
178 rockchip,pwm_voltage = <1000000>;
179 }; 176 };
180}; 177};
181 178
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 2c5249c1eb..c11a5c0cc1 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -660,6 +660,7 @@
660 fifo-depth = <0x400>; 660 fifo-depth = <0x400>;
661 clocks = <&l4_mp_clk>, <&sdmmc_clk>; 661 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
662 clock-names = "biu", "ciu"; 662 clock-names = "biu", "ciu";
663 resets = <&rst SDMMC_RESET>;
663 status = "disabled"; 664 status = "disabled";
664 }; 665 };
665 666
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index d63b56e944..31ba52b14e 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -116,6 +116,28 @@
116 #size-cells = <1>; 116 #size-cells = <1>;
117 ranges = <0 0 0 0xffffffff>; 117 ranges = <0 0 0 0xffffffff>;
118 118
119 spi0: spi@54006000 {
120 compatible = "socionext,uniphier-scssi";
121 status = "disabled";
122 reg = <0x54006000 0x100>;
123 interrupts = <0 39 4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_spi0>;
126 clocks = <&peri_clk 11>;
127 resets = <&peri_rst 11>;
128 };
129
130 spi1: spi@54006100 {
131 compatible = "socionext,uniphier-scssi";
132 status = "disabled";
133 reg = <0x54006100 0x100>;
134 interrupts = <0 216 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_spi1>;
137 clocks = <&peri_clk 11>;
138 resets = <&peri_rst 11>;
139 };
140
119 serial0: serial@54006800 { 141 serial0: serial@54006800 {
120 compatible = "socionext,uniphier-uart"; 142 compatible = "socionext,uniphier-uart";
121 status = "disabled"; 143 status = "disabled";
@@ -432,6 +454,8 @@
432 <&mio_clk 12>; 454 <&mio_clk 12>;
433 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 455 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
434 <&mio_rst 12>; 456 <&mio_rst 12>;
457 phy-names = "usb";
458 phys = <&usb_phy0>;
435 has-transaction-translator; 459 has-transaction-translator;
436 }; 460 };
437 461
@@ -446,6 +470,8 @@
446 <&mio_clk 13>; 470 <&mio_clk 13>;
447 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 471 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
448 <&mio_rst 13>; 472 <&mio_rst 13>;
473 phy-names = "usb";
474 phys = <&usb_phy1>;
449 has-transaction-translator; 475 has-transaction-translator;
450 }; 476 };
451 477
@@ -460,6 +486,8 @@
460 <&mio_clk 14>; 486 <&mio_clk 14>;
461 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 487 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
462 <&mio_rst 14>; 488 <&mio_rst 14>;
489 phy-names = "usb";
490 phys = <&usb_phy2>;
463 has-transaction-translator; 491 has-transaction-translator;
464 }; 492 };
465 493
@@ -488,6 +516,27 @@
488 pinctrl: pinctrl { 516 pinctrl: pinctrl {
489 compatible = "socionext,uniphier-ld11-pinctrl"; 517 compatible = "socionext,uniphier-ld11-pinctrl";
490 }; 518 };
519
520 usb-phy {
521 compatible = "socionext,uniphier-ld11-usb2-phy";
522 #address-cells = <1>;
523 #size-cells = <0>;
524
525 usb_phy0: phy@0 {
526 reg = <0>;
527 #phy-cells = <0>;
528 };
529
530 usb_phy1: phy@1 {
531 reg = <1>;
532 #phy-cells = <0>;
533 };
534
535 usb_phy2: phy@2 {
536 reg = <2>;
537 #phy-cells = <0>;
538 };
539 };
491 }; 540 };
492 541
493 soc-glue@5f900000 { 542 soc-glue@5f900000 {
@@ -571,7 +620,8 @@
571 interrupts = <0 65 4>; 620 interrupts = <0 65 4>;
572 pinctrl-names = "default"; 621 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_nand>; 622 pinctrl-0 = <&pinctrl_nand>;
574 clocks = <&sys_clk 2>; 623 clock-names = "nand", "nand_x", "ecc";
624 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
575 resets = <&sys_rst 2>; 625 resets = <&sys_rst 2>;
576 }; 626 };
577 }; 627 };
diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts
index 1a5e7c24b9..9ca692ed1b 100644
--- a/arch/arm/dts/uniphier-ld20-global.dts
+++ b/arch/arm/dts/uniphier-ld20-global.dts
@@ -145,6 +145,10 @@
145 }; 145 };
146}; 146};
147 147
148&usb {
149 status = "okay";
150};
151
148&nand { 152&nand {
149 status = "okay"; 153 status = "okay";
150}; 154};
diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts
index 440c2e6a63..406244a5c8 100644
--- a/arch/arm/dts/uniphier-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ld20-ref.dts
@@ -75,3 +75,7 @@
75 drive-strength = <9>; 75 drive-strength = <9>;
76 }; 76 };
77}; 77};
78
79&usb {
80 status = "okay";
81};
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 9970497039..b9ed613ace 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -224,6 +224,50 @@
224 #size-cells = <1>; 224 #size-cells = <1>;
225 ranges = <0 0 0 0xffffffff>; 225 ranges = <0 0 0 0xffffffff>;
226 226
227 spi0: spi@54006000 {
228 compatible = "socionext,uniphier-scssi";
229 status = "disabled";
230 reg = <0x54006000 0x100>;
231 interrupts = <0 39 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_spi0>;
234 clocks = <&peri_clk 11>;
235 resets = <&peri_rst 11>;
236 };
237
238 spi1: spi@54006100 {
239 compatible = "socionext,uniphier-scssi";
240 status = "disabled";
241 reg = <0x54006100 0x100>;
242 interrupts = <0 216 4>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_spi1>;
245 clocks = <&peri_clk 11>;
246 resets = <&peri_rst 11>;
247 };
248
249 spi2: spi@54006200 {
250 compatible = "socionext,uniphier-scssi";
251 status = "disabled";
252 reg = <0x54006200 0x100>;
253 interrupts = <0 229 4>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_spi2>;
256 clocks = <&peri_clk 11>;
257 resets = <&peri_rst 11>;
258 };
259
260 spi3: spi@54006300 {
261 compatible = "socionext,uniphier-scssi";
262 status = "disabled";
263 reg = <0x54006300 0x100>;
264 interrupts = <0 230 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_spi3>;
267 clocks = <&peri_clk 11>;
268 resets = <&peri_rst 11>;
269 };
270
227 serial0: serial@54006800 { 271 serial0: serial@54006800 {
228 compatible = "socionext,uniphier-uart"; 272 compatible = "socionext,uniphier-uart";
229 status = "disabled"; 273 status = "disabled";
@@ -567,6 +611,50 @@
567 efuse@200 { 611 efuse@200 {
568 compatible = "socionext,uniphier-efuse"; 612 compatible = "socionext,uniphier-efuse";
569 reg = <0x200 0x68>; 613 reg = <0x200 0x68>;
614 #address-cells = <1>;
615 #size-cells = <1>;
616
617 /* USB cells */
618 usb_rterm0: trim@54,4 {
619 reg = <0x54 1>;
620 bits = <4 2>;
621 };
622 usb_rterm1: trim@55,4 {
623 reg = <0x55 1>;
624 bits = <4 2>;
625 };
626 usb_rterm2: trim@58,4 {
627 reg = <0x58 1>;
628 bits = <4 2>;
629 };
630 usb_rterm3: trim@59,4 {
631 reg = <0x59 1>;
632 bits = <4 2>;
633 };
634 usb_sel_t0: trim@54,0 {
635 reg = <0x54 1>;
636 bits = <0 4>;
637 };
638 usb_sel_t1: trim@55,0 {
639 reg = <0x55 1>;
640 bits = <0 4>;
641 };
642 usb_sel_t2: trim@58,0 {
643 reg = <0x58 1>;
644 bits = <0 4>;
645 };
646 usb_sel_t3: trim@59,0 {
647 reg = <0x59 1>;
648 bits = <0 4>;
649 };
650 usb_hs_i0: trim@56,0 {
651 reg = <0x56 1>;
652 bits = <0 4>;
653 };
654 usb_hs_i2: trim@5a,0 {
655 reg = <0x5a 1>;
656 bits = <0 4>;
657 };
570 }; 658 };
571 }; 659 };
572 660
@@ -634,6 +722,157 @@
634 }; 722 };
635 }; 723 };
636 724
725 _usb: usb@65a00000 {
726 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
727 status = "disabled";
728 reg = <0x65a00000 0xcd00>;
729 interrupt-names = "host";
730 interrupts = <0 134 4>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
733 <&pinctrl_usb2>, <&pinctrl_usb3>;
734 clock-names = "ref", "bus_early", "suspend";
735 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
736 resets = <&usb_rst 15>;
737 phys = <&usb_hsphy0>, <&usb_hsphy1>,
738 <&usb_hsphy2>, <&usb_hsphy3>,
739 <&usb_ssphy0>, <&usb_ssphy1>;
740 dr_mode = "host";
741 };
742
743 usb-glue@65b00000 {
744 compatible = "socionext,uniphier-ld20-dwc3-glue",
745 "simple-mfd";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 ranges = <0 0x65b00000 0x400>;
749
750 usb_rst: reset@0 {
751 compatible = "socionext,uniphier-ld20-usb3-reset";
752 reg = <0x0 0x4>;
753 #reset-cells = <1>;
754 clock-names = "link";
755 clocks = <&sys_clk 14>;
756 reset-names = "link";
757 resets = <&sys_rst 14>;
758 };
759
760 usb_vbus0: regulator@100 {
761 compatible = "socionext,uniphier-ld20-usb3-regulator";
762 reg = <0x100 0x10>;
763 clock-names = "link";
764 clocks = <&sys_clk 14>;
765 reset-names = "link";
766 resets = <&sys_rst 14>;
767 };
768
769 usb_vbus1: regulator@110 {
770 compatible = "socionext,uniphier-ld20-usb3-regulator";
771 reg = <0x110 0x10>;
772 clock-names = "link";
773 clocks = <&sys_clk 14>;
774 reset-names = "link";
775 resets = <&sys_rst 14>;
776 };
777
778 usb_vbus2: regulator@120 {
779 compatible = "socionext,uniphier-ld20-usb3-regulator";
780 reg = <0x120 0x10>;
781 clock-names = "link";
782 clocks = <&sys_clk 14>;
783 reset-names = "link";
784 resets = <&sys_rst 14>;
785 };
786
787 usb_vbus3: regulator@130 {
788 compatible = "socionext,uniphier-ld20-usb3-regulator";
789 reg = <0x130 0x10>;
790 clock-names = "link";
791 clocks = <&sys_clk 14>;
792 reset-names = "link";
793 resets = <&sys_rst 14>;
794 };
795
796 usb_hsphy0: hs-phy@200 {
797 compatible = "socionext,uniphier-ld20-usb3-hsphy";
798 reg = <0x200 0x10>;
799 #phy-cells = <0>;
800 clock-names = "link", "phy";
801 clocks = <&sys_clk 14>, <&sys_clk 16>;
802 reset-names = "link", "phy";
803 resets = <&sys_rst 14>, <&sys_rst 16>;
804 vbus-supply = <&usb_vbus0>;
805 nvmem-cell-names = "rterm", "sel_t", "hs_i";
806 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
807 <&usb_hs_i0>;
808 };
809
810 usb_hsphy1: hs-phy@210 {
811 compatible = "socionext,uniphier-ld20-usb3-hsphy";
812 reg = <0x210 0x10>;
813 #phy-cells = <0>;
814 clock-names = "link", "phy";
815 clocks = <&sys_clk 14>, <&sys_clk 16>;
816 reset-names = "link", "phy";
817 resets = <&sys_rst 14>, <&sys_rst 16>;
818 vbus-supply = <&usb_vbus1>;
819 nvmem-cell-names = "rterm", "sel_t", "hs_i";
820 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
821 <&usb_hs_i0>;
822 };
823
824 usb_hsphy2: hs-phy@220 {
825 compatible = "socionext,uniphier-ld20-usb3-hsphy";
826 reg = <0x220 0x10>;
827 #phy-cells = <0>;
828 clock-names = "link", "phy";
829 clocks = <&sys_clk 14>, <&sys_clk 17>;
830 reset-names = "link", "phy";
831 resets = <&sys_rst 14>, <&sys_rst 17>;
832 vbus-supply = <&usb_vbus2>;
833 nvmem-cell-names = "rterm", "sel_t", "hs_i";
834 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
835 <&usb_hs_i2>;
836 };
837
838 usb_hsphy3: hs-phy@230 {
839 compatible = "socionext,uniphier-ld20-usb3-hsphy";
840 reg = <0x230 0x10>;
841 #phy-cells = <0>;
842 clock-names = "link", "phy";
843 clocks = <&sys_clk 14>, <&sys_clk 17>;
844 reset-names = "link", "phy";
845 resets = <&sys_rst 14>, <&sys_rst 17>;
846 vbus-supply = <&usb_vbus3>;
847 nvmem-cell-names = "rterm", "sel_t", "hs_i";
848 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
849 <&usb_hs_i2>;
850 };
851
852 usb_ssphy0: ss-phy@300 {
853 compatible = "socionext,uniphier-ld20-usb3-ssphy";
854 reg = <0x300 0x10>;
855 #phy-cells = <0>;
856 clock-names = "link", "phy";
857 clocks = <&sys_clk 14>, <&sys_clk 18>;
858 reset-names = "link", "phy";
859 resets = <&sys_rst 14>, <&sys_rst 18>;
860 vbus-supply = <&usb_vbus0>;
861 };
862
863 usb_ssphy1: ss-phy@310 {
864 compatible = "socionext,uniphier-ld20-usb3-ssphy";
865 reg = <0x310 0x10>;
866 #phy-cells = <0>;
867 clock-names = "link", "phy";
868 clocks = <&sys_clk 14>, <&sys_clk 19>;
869 reset-names = "link", "phy";
870 resets = <&sys_rst 14>, <&sys_rst 19>;
871 vbus-supply = <&usb_vbus1>;
872 };
873 };
874
875 /* FIXME: U-Boot own node */
637 usb: usb@65b00000 { 876 usb: usb@65b00000 {
638 compatible = "socionext,uniphier-ld20-dwc3"; 877 compatible = "socionext,uniphier-ld20-dwc3";
639 reg = <0x65b00000 0x1000>; 878 reg = <0x65b00000 0x1000>;
@@ -660,7 +899,8 @@
660 interrupts = <0 65 4>; 899 interrupts = <0 65 4>;
661 pinctrl-names = "default"; 900 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_nand>; 901 pinctrl-0 = <&pinctrl_nand>;
663 clocks = <&sys_clk 2>; 902 clock-names = "nand", "nand_x", "ecc";
903 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
664 resets = <&sys_rst 2>; 904 resets = <&sys_rst 2>;
665 }; 905 };
666 }; 906 };
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index f505f643f7..b73d594b6d 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -63,6 +63,17 @@
63 cache-level = <2>; 63 cache-level = <2>;
64 }; 64 };
65 65
66 spi: spi@54006000 {
67 compatible = "socionext,uniphier-scssi";
68 status = "disabled";
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_spi0>;
73 clocks = <&peri_clk 11>;
74 resets = <&peri_rst 11>;
75 };
76
66 serial0: serial@54006800 { 77 serial0: serial@54006800 {
67 compatible = "socionext,uniphier-uart"; 78 compatible = "socionext,uniphier-uart";
68 status = "disabled"; 79 status = "disabled";
@@ -381,7 +392,8 @@
381 interrupts = <0 65 4>; 392 interrupts = <0 65 4>;
382 pinctrl-names = "default"; 393 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_nand2cs>; 394 pinctrl-0 = <&pinctrl_nand2cs>;
384 clocks = <&sys_clk 2>; 395 clock-names = "nand", "nand_x", "ecc";
396 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
385 resets = <&sys_rst 2>; 397 resets = <&sys_rst 2>;
386 }; 398 };
387 }; 399 };
diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi
index aeb47b0ffe..1fee5ffbfb 100644
--- a/arch/arm/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/dts/uniphier-pinctrl.dtsi
@@ -131,6 +131,26 @@
131 function = "sd1"; 131 function = "sd1";
132 }; 132 };
133 133
134 pinctrl_spi0: spi0 {
135 groups = "spi0";
136 function = "spi0";
137 };
138
139 pinctrl_spi1: spi1 {
140 groups = "spi1";
141 function = "spi1";
142 };
143
144 pinctrl_spi2: spi2 {
145 groups = "spi2";
146 function = "spi2";
147 };
148
149 pinctrl_spi3: spi3 {
150 groups = "spi3";
151 function = "spi3";
152 };
153
134 pinctrl_system_bus: system-bus { 154 pinctrl_system_bus: system-bus {
135 groups = "system_bus", "system_bus_cs1"; 155 groups = "system_bus", "system_bus_cs1";
136 function = "system_bus"; 156 function = "system_bus";
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts
index bff90c256b..ce8ea7b79b 100644
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -73,11 +73,11 @@
73 status = "okay"; 73 status = "okay";
74}; 74};
75 75
76&usb0 { 76&usb2 {
77 status = "okay"; 77 status = "okay";
78}; 78};
79 79
80&usb1 { 80&usb3 {
81 status = "okay"; 81 status = "okay";
82}; 82};
83 83
@@ -92,10 +92,10 @@
92 }; 92 };
93}; 93};
94 94
95&usb2 { 95&usb0 {
96 status = "okay"; 96 status = "okay";
97}; 97};
98 98
99&usb3 { 99&usb1 {
100 status = "okay"; 100 status = "okay";
101}; 101};
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts
index 7f5b957f98..686dd3af7e 100644
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -68,11 +68,11 @@
68 status = "okay"; 68 status = "okay";
69}; 69};
70 70
71&usb0 { 71&usb2 {
72 status = "okay"; 72 status = "okay";
73}; 73};
74 74
75&usb1 { 75&usb3 {
76 status = "okay"; 76 status = "okay";
77}; 77};
78 78
@@ -87,10 +87,10 @@
87 }; 87 };
88}; 88};
89 89
90&usb2 { 90&usb0 {
91 status = "okay"; 91 status = "okay";
92}; 92};
93 93
94&usb3 { 94&usb1 {
95 status = "okay"; 95 status = "okay";
96}; 96};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 8974844541..ef342088e1 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -71,6 +71,17 @@
71 cache-level = <2>; 71 cache-level = <2>;
72 }; 72 };
73 73
74 spi0: spi@54006000 {
75 compatible = "socionext,uniphier-scssi";
76 status = "disabled";
77 reg = <0x54006000 0x100>;
78 interrupts = <0 39 4>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_spi0>;
81 clocks = <&peri_clk 11>;
82 resets = <&peri_rst 11>;
83 };
84
74 serial0: serial@54006800 { 85 serial0: serial@54006800 {
75 compatible = "socionext,uniphier-uart"; 86 compatible = "socionext,uniphier-uart";
76 status = "disabled"; 87 status = "disabled";
@@ -317,6 +328,8 @@
317 <&mio_clk 12>; 328 <&mio_clk 12>;
318 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 329 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
319 <&mio_rst 12>; 330 <&mio_rst 12>;
331 phy-names = "usb";
332 phys = <&usb_phy0>;
320 has-transaction-translator; 333 has-transaction-translator;
321 }; 334 };
322 335
@@ -331,6 +344,8 @@
331 <&mio_clk 13>; 344 <&mio_clk 13>;
332 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 345 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
333 <&mio_rst 13>; 346 <&mio_rst 13>;
347 phy-names = "usb";
348 phys = <&usb_phy1>;
334 has-transaction-translator; 349 has-transaction-translator;
335 }; 350 };
336 351
@@ -342,6 +357,34 @@
342 pinctrl: pinctrl { 357 pinctrl: pinctrl {
343 compatible = "socionext,uniphier-pro4-pinctrl"; 358 compatible = "socionext,uniphier-pro4-pinctrl";
344 }; 359 };
360
361 usb-phy {
362 compatible = "socionext,uniphier-pro4-usb2-phy";
363 #address-cells = <1>;
364 #size-cells = <0>;
365
366 usb_phy0: phy@0 {
367 reg = <0>;
368 #phy-cells = <0>;
369 };
370
371 usb_phy1: phy@1 {
372 reg = <1>;
373 #phy-cells = <0>;
374 };
375
376 usb_phy2: phy@2 {
377 reg = <2>;
378 #phy-cells = <0>;
379 vbus-supply = <&usb0_vbus>;
380 };
381
382 usb_phy3: phy@3 {
383 reg = <3>;
384 #phy-cells = <0>;
385 vbus-supply = <&usb1_vbus>;
386 };
387 };
345 }; 388 };
346 389
347 soc-glue@5f900000 { 390 soc-glue@5f900000 {
@@ -434,6 +477,60 @@
434 }; 477 };
435 }; 478 };
436 479
480 _usb0: usb@65a00000 {
481 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
482 status = "disabled";
483 reg = <0x65a00000 0xcd00>;
484 interrupt-names = "host", "peripheral";
485 interrupts = <0 134 4>, <0 135 4>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_usb0>;
488 clock-names = "ref", "bus_early", "suspend";
489 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
490 resets = <&usb0_rst 4>;
491 phys = <&usb_phy2>, <&usb0_ssphy>;
492 dr_mode = "host";
493 };
494
495 usb-glue@65b00000 {
496 compatible = "socionext,uniphier-pro4-dwc3-glue",
497 "simple-mfd";
498 #address-cells = <1>;
499 #size-cells = <1>;
500 ranges = <0 0x65b00000 0x100>;
501
502 usb0_vbus: regulator@0 {
503 compatible = "socionext,uniphier-pro4-usb3-regulator";
504 reg = <0 0x10>;
505 clock-names = "gio", "link";
506 clocks = <&sys_clk 12>, <&sys_clk 14>;
507 reset-names = "gio", "link";
508 resets = <&sys_rst 12>, <&sys_rst 14>;
509 };
510
511 usb0_ssphy: ss-phy@10 {
512 compatible = "socionext,uniphier-pro4-usb3-ssphy";
513 reg = <0x10 0x10>;
514 #phy-cells = <0>;
515 clock-names = "gio", "link";
516 clocks = <&sys_clk 12>, <&sys_clk 14>;
517 reset-names = "gio", "link";
518 resets = <&sys_rst 12>, <&sys_rst 14>;
519 vbus-supply = <&usb0_vbus>;
520 };
521
522 usb0_rst: reset@40 {
523 compatible = "socionext,uniphier-pro4-usb3-reset";
524 reg = <0x40 0x4>;
525 #reset-cells = <1>;
526 clock-names = "gio", "link";
527 clocks = <&sys_clk 12>, <&sys_clk 14>;
528 reset-names = "gio", "link";
529 resets = <&sys_rst 12>, <&sys_rst 14>;
530 };
531 };
532
533 /* FIXME: U-Boot own node */
437 usb0: usb@65b00000 { 534 usb0: usb@65b00000 {
438 compatible = "socionext,uniphier-pro4-dwc3"; 535 compatible = "socionext,uniphier-pro4-dwc3";
439 status = "disabled"; 536 status = "disabled";
@@ -452,6 +549,49 @@
452 }; 549 };
453 }; 550 };
454 551
552 _usb1: usb@65c00000 {
553 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
554 status = "disabled";
555 reg = <0x65c00000 0xcd00>;
556 interrupt-names = "host", "peripheral";
557 interrupts = <0 137 4>, <0 138 4>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_usb1>;
560 clock-names = "ref", "bus_early", "suspend";
561 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
562 resets = <&usb1_rst 4>;
563 phys = <&usb_phy3>;
564 dr_mode = "host";
565 };
566
567 usb-glue@65d00000 {
568 compatible = "socionext,uniphier-pro4-dwc3-glue",
569 "simple-mfd";
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges = <0 0x65d00000 0x100>;
573
574 usb1_vbus: regulator@0 {
575 compatible = "socionext,uniphier-pro4-usb3-regulator";
576 reg = <0 0x10>;
577 clock-names = "gio", "link";
578 clocks = <&sys_clk 12>, <&sys_clk 15>;
579 reset-names = "gio", "link";
580 resets = <&sys_rst 12>, <&sys_rst 15>;
581 };
582
583 usb1_rst: reset@40 {
584 compatible = "socionext,uniphier-pro4-usb3-reset";
585 reg = <0x40 0x4>;
586 #reset-cells = <1>;
587 clock-names = "gio", "link";
588 clocks = <&sys_clk 12>, <&sys_clk 15>;
589 reset-names = "gio", "link";
590 resets = <&sys_rst 12>, <&sys_rst 15>;
591 };
592 };
593
594 /* FIXME: U-Boot own node */
455 usb1: usb@65d00000 { 595 usb1: usb@65d00000 {
456 compatible = "socionext,uniphier-pro4-dwc3"; 596 compatible = "socionext,uniphier-pro4-dwc3";
457 status = "disabled"; 597 status = "disabled";
@@ -478,7 +618,8 @@
478 interrupts = <0 65 4>; 618 interrupts = <0 65 4>;
479 pinctrl-names = "default"; 619 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_nand>; 620 pinctrl-0 = <&pinctrl_nand>;
481 clocks = <&sys_clk 2>; 621 clock-names = "nand", "nand_x", "ecc";
622 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
482 resets = <&sys_rst 2>; 623 resets = <&sys_rst 2>;
483 }; 624 };
484 }; 625 };
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 6e0ea7976e..9cad79d086 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -156,6 +156,28 @@
156 cache-level = <3>; 156 cache-level = <3>;
157 }; 157 };
158 158
159 spi0: spi@54006000 {
160 compatible = "socionext,uniphier-scssi";
161 status = "disabled";
162 reg = <0x54006000 0x100>;
163 interrupts = <0 39 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_spi0>;
166 clocks = <&peri_clk 11>;
167 resets = <&peri_rst 11>;
168 };
169
170 spi1: spi@54006100 {
171 compatible = "socionext,uniphier-scssi";
172 status = "disabled";
173 reg = <0x54006100 0x100>;
174 interrupts = <0 216 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi1>;
177 clocks = <&peri_clk 11>;
178 resets = <&peri_rst 11>;
179 };
180
159 serial0: serial@54006800 { 181 serial0: serial@54006800 {
160 compatible = "socionext,uniphier-uart"; 182 compatible = "socionext,uniphier-uart";
161 status = "disabled"; 183 status = "disabled";
@@ -475,7 +497,8 @@
475 interrupts = <0 65 4>; 497 interrupts = <0 65 4>;
476 pinctrl-names = "default"; 498 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_nand2cs>; 499 pinctrl-0 = <&pinctrl_nand2cs>;
478 clocks = <&sys_clk 2>; 500 clock-names = "nand", "nand_x", "ecc";
501 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
479 resets = <&sys_rst 2>; 502 resets = <&sys_rst 2>;
480 }; 503 };
481 504
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 63c1c2ce60..fa25ffd97f 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -167,6 +167,28 @@
167 cache-level = <2>; 167 cache-level = <2>;
168 }; 168 };
169 169
170 spi0: spi@54006000 {
171 compatible = "socionext,uniphier-scssi";
172 status = "disabled";
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi0>;
177 clocks = <&peri_clk 11>;
178 resets = <&peri_rst 11>;
179 };
180
181 spi1: spi@54006100 {
182 compatible = "socionext,uniphier-scssi";
183 status = "disabled";
184 reg = <0x54006100 0x100>;
185 interrupts = <0 216 4>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_spi1>;
188 clocks = <&peri_clk 11>;
189 resets = <&peri_rst 11>;
190 };
191
170 serial0: serial@54006800 { 192 serial0: serial@54006800 {
171 compatible = "socionext,uniphier-uart"; 193 compatible = "socionext,uniphier-uart";
172 status = "disabled"; 194 status = "disabled";
@@ -557,6 +579,103 @@
557 }; 579 };
558 }; 580 };
559 581
582 _usb0: usb@65a00000 {
583 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
584 status = "disabled";
585 reg = <0x65a00000 0xcd00>;
586 interrupt-names = "host", "peripheral";
587 interrupts = <0 134 4>, <0 135 4>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
590 clock-names = "ref", "bus_early", "suspend";
591 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
592 resets = <&usb0_rst 15>;
593 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
594 <&usb0_ssphy0>, <&usb0_ssphy1>;
595 dr_mode = "host";
596 };
597
598 usb-glue@65b00000 {
599 compatible = "socionext,uniphier-pxs2-dwc3-glue",
600 "simple-mfd";
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges = <0 0x65b00000 0x400>;
604
605 usb0_rst: reset@0 {
606 compatible = "socionext,uniphier-pxs2-usb3-reset";
607 reg = <0x0 0x4>;
608 #reset-cells = <1>;
609 clock-names = "link";
610 clocks = <&sys_clk 14>;
611 reset-names = "link";
612 resets = <&sys_rst 14>;
613 };
614
615 usb0_vbus0: regulator@100 {
616 compatible = "socionext,uniphier-pxs2-usb3-regulator";
617 reg = <0x100 0x10>;
618 clock-names = "link";
619 clocks = <&sys_clk 14>;
620 reset-names = "link";
621 resets = <&sys_rst 14>;
622 };
623
624 usb0_vbus1: regulator@110 {
625 compatible = "socionext,uniphier-pxs2-usb3-regulator";
626 reg = <0x110 0x10>;
627 clock-names = "link";
628 clocks = <&sys_clk 14>;
629 reset-names = "link";
630 resets = <&sys_rst 14>;
631 };
632
633 usb0_hsphy0: hs-phy@200 {
634 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
635 reg = <0x200 0x10>;
636 #phy-cells = <0>;
637 clock-names = "link", "phy";
638 clocks = <&sys_clk 14>, <&sys_clk 16>;
639 reset-names = "link", "phy";
640 resets = <&sys_rst 14>, <&sys_rst 16>;
641 vbus-supply = <&usb0_vbus0>;
642 };
643
644 usb0_hsphy1: hs-phy@210 {
645 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
646 reg = <0x210 0x10>;
647 #phy-cells = <0>;
648 clock-names = "link", "phy";
649 clocks = <&sys_clk 14>, <&sys_clk 16>;
650 reset-names = "link", "phy";
651 resets = <&sys_rst 14>, <&sys_rst 16>;
652 vbus-supply = <&usb0_vbus1>;
653 };
654
655 usb0_ssphy0: ss-phy@300 {
656 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
657 reg = <0x300 0x10>;
658 #phy-cells = <0>;
659 clock-names = "link", "phy";
660 clocks = <&sys_clk 14>, <&sys_clk 17>;
661 reset-names = "link", "phy";
662 resets = <&sys_rst 14>, <&sys_rst 17>;
663 vbus-supply = <&usb0_vbus0>;
664 };
665
666 usb0_ssphy1: ss-phy@310 {
667 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
668 reg = <0x310 0x10>;
669 #phy-cells = <0>;
670 clock-names = "link", "phy";
671 clocks = <&sys_clk 14>, <&sys_clk 18>;
672 reset-names = "link", "phy";
673 resets = <&sys_rst 14>, <&sys_rst 18>;
674 vbus-supply = <&usb0_vbus1>;
675 };
676 };
677
678 /* FIXME: U-Boot own node */
560 usb0: usb@65b00000 { 679 usb0: usb@65b00000 {
561 compatible = "socionext,uniphier-pxs2-dwc3"; 680 compatible = "socionext,uniphier-pxs2-dwc3";
562 status = "disabled"; 681 status = "disabled";
@@ -575,6 +694,91 @@
575 }; 694 };
576 }; 695 };
577 696
697 _usb1: usb@65c00000 {
698 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
699 status = "disabled";
700 reg = <0x65c00000 0xcd00>;
701 interrupt-names = "host", "peripheral";
702 interrupts = <0 137 4>, <0 138 4>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
705 clock-names = "ref", "bus_early", "suspend";
706 clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
707 resets = <&usb1_rst 15>;
708 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
709 dr_mode = "host";
710 };
711
712 usb-glue@65d00000 {
713 compatible = "socionext,uniphier-pxs2-dwc3-glue",
714 "simple-mfd";
715 #address-cells = <1>;
716 #size-cells = <1>;
717 ranges = <0 0x65d00000 0x400>;
718
719 usb1_rst: reset@0 {
720 compatible = "socionext,uniphier-pxs2-usb3-reset";
721 reg = <0x0 0x4>;
722 #reset-cells = <1>;
723 clock-names = "link";
724 clocks = <&sys_clk 15>;
725 reset-names = "link";
726 resets = <&sys_rst 15>;
727 };
728
729 usb1_vbus0: regulator@100 {
730 compatible = "socionext,uniphier-pxs2-usb3-regulator";
731 reg = <0x100 0x10>;
732 clock-names = "link";
733 clocks = <&sys_clk 15>;
734 reset-names = "link";
735 resets = <&sys_rst 15>;
736 };
737
738 usb1_vbus1: regulator@110 {
739 compatible = "socionext,uniphier-pxs2-usb3-regulator";
740 reg = <0x110 0x10>;
741 clock-names = "link";
742 clocks = <&sys_clk 15>;
743 reset-names = "link";
744 resets = <&sys_rst 15>;
745 };
746
747 usb1_hsphy0: hs-phy@200 {
748 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
749 reg = <0x200 0x10>;
750 #phy-cells = <0>;
751 clock-names = "link", "phy";
752 clocks = <&sys_clk 15>, <&sys_clk 20>;
753 reset-names = "link", "phy";
754 resets = <&sys_rst 15>, <&sys_rst 20>;
755 vbus-supply = <&usb1_vbus0>;
756 };
757
758 usb1_hsphy1: hs-phy@210 {
759 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
760 reg = <0x210 0x10>;
761 #phy-cells = <0>;
762 clock-names = "link", "phy";
763 clocks = <&sys_clk 15>, <&sys_clk 20>;
764 reset-names = "link", "phy";
765 resets = <&sys_rst 15>, <&sys_rst 20>;
766 vbus-supply = <&usb1_vbus1>;
767 };
768
769 usb1_ssphy0: ss-phy@300 {
770 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
771 reg = <0x300 0x10>;
772 #phy-cells = <0>;
773 clock-names = "link", "phy";
774 clocks = <&sys_clk 15>, <&sys_clk 21>;
775 reset-names = "link", "phy";
776 resets = <&sys_rst 15>, <&sys_rst 21>;
777 vbus-supply = <&usb1_vbus0>;
778 };
779 };
780
781 /* FIXME: U-Boot own node */
578 usb1: usb@65d00000 { 782 usb1: usb@65d00000 {
579 compatible = "socionext,uniphier-pxs2-dwc3"; 783 compatible = "socionext,uniphier-pxs2-dwc3";
580 status = "disabled"; 784 status = "disabled";
@@ -601,7 +805,8 @@
601 interrupts = <0 65 4>; 805 interrupts = <0 65 4>;
602 pinctrl-names = "default"; 806 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_nand2cs>; 807 pinctrl-0 = <&pinctrl_nand2cs>;
604 clocks = <&sys_clk 2>; 808 clock-names = "nand", "nand_x", "ecc";
809 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
605 resets = <&sys_rst 2>; 810 resets = <&sys_rst 2>;
606 }; 811 };
607 }; 812 };
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index daf74531e4..f629c6a862 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -144,6 +144,28 @@
144 #size-cells = <1>; 144 #size-cells = <1>;
145 ranges = <0 0 0 0xffffffff>; 145 ranges = <0 0 0 0xffffffff>;
146 146
147 spi0: spi@54006000 {
148 compatible = "socionext,uniphier-scssi";
149 status = "disabled";
150 reg = <0x54006000 0x100>;
151 interrupts = <0 39 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_spi0>;
154 clocks = <&peri_clk 11>;
155 resets = <&peri_rst 11>;
156 };
157
158 spi1: spi@54006100 {
159 compatible = "socionext,uniphier-scssi";
160 status = "disabled";
161 reg = <0x54006100 0x100>;
162 interrupts = <0 216 4>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_spi1>;
165 clocks = <&peri_clk 11>;
166 resets = <&peri_rst 11>;
167 };
168
147 serial0: serial@54006800 { 169 serial0: serial@54006800 {
148 compatible = "socionext,uniphier-uart"; 170 compatible = "socionext,uniphier-uart";
149 status = "disabled"; 171 status = "disabled";
@@ -384,6 +406,50 @@
384 efuse@200 { 406 efuse@200 {
385 compatible = "socionext,uniphier-efuse"; 407 compatible = "socionext,uniphier-efuse";
386 reg = <0x200 0x68>; 408 reg = <0x200 0x68>;
409 #address-cells = <1>;
410 #size-cells = <1>;
411
412 /* USB cells */
413 usb_rterm0: trim@54,4 {
414 reg = <0x54 1>;
415 bits = <4 2>;
416 };
417 usb_rterm1: trim@55,4 {
418 reg = <0x55 1>;
419 bits = <4 2>;
420 };
421 usb_rterm2: trim@58,4 {
422 reg = <0x58 1>;
423 bits = <4 2>;
424 };
425 usb_rterm3: trim@59,4 {
426 reg = <0x59 1>;
427 bits = <4 2>;
428 };
429 usb_sel_t0: trim@54,0 {
430 reg = <0x54 1>;
431 bits = <0 4>;
432 };
433 usb_sel_t1: trim@55,0 {
434 reg = <0x55 1>;
435 bits = <0 4>;
436 };
437 usb_sel_t2: trim@58,0 {
438 reg = <0x58 1>;
439 bits = <0 4>;
440 };
441 usb_sel_t3: trim@59,0 {
442 reg = <0x59 1>;
443 bits = <0 4>;
444 };
445 usb_hs_i0: trim@56,0 {
446 reg = <0x56 1>;
447 bits = <0 4>;
448 };
449 usb_hs_i2: trim@5a,0 {
450 reg = <0x5a 1>;
451 bits = <0 4>;
452 };
387 }; 453 };
388 }; 454 };
389 455
@@ -465,6 +531,109 @@
465 }; 531 };
466 }; 532 };
467 533
534 _usb0: usb@65a00000 {
535 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
536 status = "disabled";
537 reg = <0x65a00000 0xcd00>;
538 interrupt-names = "host", "peripheral";
539 interrupts = <0 134 4>, <0 135 4>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
542 clock-names = "ref", "bus_early", "suspend";
543 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
544 resets = <&usb0_rst 15>;
545 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
546 <&usb0_ssphy0>, <&usb0_ssphy1>;
547 dr_mode = "host";
548 };
549
550 usb-glue@65b00000 {
551 compatible = "socionext,uniphier-pxs3-dwc3-glue",
552 "simple-mfd";
553 #address-cells = <1>;
554 #size-cells = <1>;
555 ranges = <0 0x65b00000 0x400>;
556
557 usb0_rst: reset@0 {
558 compatible = "socionext,uniphier-pxs3-usb3-reset";
559 reg = <0x0 0x4>;
560 #reset-cells = <1>;
561 clock-names = "link";
562 clocks = <&sys_clk 12>;
563 reset-names = "link";
564 resets = <&sys_rst 12>;
565 };
566
567 usb0_vbus0: regulator@100 {
568 compatible = "socionext,uniphier-pxs3-usb3-regulator";
569 reg = <0x100 0x10>;
570 clock-names = "link";
571 clocks = <&sys_clk 12>;
572 reset-names = "link";
573 resets = <&sys_rst 12>;
574 };
575
576 usb0_vbus1: regulator@110 {
577 compatible = "socionext,uniphier-pxs3-usb3-regulator";
578 reg = <0x110 0x10>;
579 clock-names = "link";
580 clocks = <&sys_clk 12>;
581 reset-names = "link";
582 resets = <&sys_rst 12>;
583 };
584
585 usb0_hsphy0: hs-phy@200 {
586 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
587 reg = <0x200 0x10>;
588 #phy-cells = <0>;
589 clock-names = "link", "phy";
590 clocks = <&sys_clk 12>, <&sys_clk 16>;
591 reset-names = "link", "phy";
592 resets = <&sys_rst 12>, <&sys_rst 16>;
593 vbus-supply = <&usb0_vbus0>;
594 nvmem-cell-names = "rterm", "sel_t", "hs_i";
595 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
596 <&usb_hs_i0>;
597 };
598
599 usb0_hsphy1: hs-phy@210 {
600 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
601 reg = <0x210 0x10>;
602 #phy-cells = <0>;
603 clock-names = "link", "phy";
604 clocks = <&sys_clk 12>, <&sys_clk 16>;
605 reset-names = "link", "phy";
606 resets = <&sys_rst 12>, <&sys_rst 16>;
607 vbus-supply = <&usb0_vbus1>;
608 nvmem-cell-names = "rterm", "sel_t", "hs_i";
609 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
610 <&usb_hs_i0>;
611 };
612
613 usb0_ssphy0: ss-phy@300 {
614 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
615 reg = <0x300 0x10>;
616 #phy-cells = <0>;
617 clock-names = "link", "phy";
618 clocks = <&sys_clk 12>, <&sys_clk 17>;
619 reset-names = "link", "phy";
620 resets = <&sys_rst 12>, <&sys_rst 17>;
621 vbus-supply = <&usb0_vbus0>;
622 };
623
624 usb0_ssphy1: ss-phy@310 {
625 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
626 reg = <0x310 0x10>;
627 #phy-cells = <0>;
628 clock-names = "link", "phy";
629 clocks = <&sys_clk 12>, <&sys_clk 18>;
630 reset-names = "link", "phy";
631 resets = <&sys_rst 12>, <&sys_rst 18>;
632 vbus-supply = <&usb0_vbus1>;
633 };
634 };
635
636 /* FIXME: U-Boot own node */
468 usb0: usb@65b00000 { 637 usb0: usb@65b00000 {
469 compatible = "socionext,uniphier-pxs3-dwc3"; 638 compatible = "socionext,uniphier-pxs3-dwc3";
470 status = "disabled"; 639 status = "disabled";
@@ -483,6 +652,101 @@
483 }; 652 };
484 }; 653 };
485 654
655 _usb1: usb@65c00000 {
656 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
657 status = "disabled";
658 reg = <0x65c00000 0xcd00>;
659 interrupt-names = "host", "peripheral";
660 interrupts = <0 137 4>, <0 138 4>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
663 clock-names = "ref", "bus_early", "suspend";
664 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
665 resets = <&usb1_rst 15>;
666 phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
667 <&usb1_ssphy0>;
668 dr_mode = "host";
669 };
670
671 usb-glue@65d00000 {
672 compatible = "socionext,uniphier-pxs3-dwc3-glue",
673 "simple-mfd";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 ranges = <0 0x65d00000 0x400>;
677
678 usb1_rst: reset@0 {
679 compatible = "socionext,uniphier-pxs3-usb3-reset";
680 reg = <0x0 0x4>;
681 #reset-cells = <1>;
682 clock-names = "link";
683 clocks = <&sys_clk 13>;
684 reset-names = "link";
685 resets = <&sys_rst 13>;
686 };
687
688 usb1_vbus0: regulator@100 {
689 compatible = "socionext,uniphier-pxs3-usb3-regulator";
690 reg = <0x100 0x10>;
691 clock-names = "link";
692 clocks = <&sys_clk 13>;
693 reset-names = "link";
694 resets = <&sys_rst 13>;
695 };
696
697 usb1_vbus1: regulator@110 {
698 compatible = "socionext,uniphier-pxs3-usb3-regulator";
699 reg = <0x110 0x10>;
700 clock-names = "link";
701 clocks = <&sys_clk 13>;
702 reset-names = "link";
703 resets = <&sys_rst 13>;
704 };
705
706 usb1_hsphy0: hs-phy@200 {
707 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
708 reg = <0x200 0x10>;
709 #phy-cells = <0>;
710 clock-names = "link", "phy", "phy-ext";
711 clocks = <&sys_clk 13>, <&sys_clk 20>,
712 <&sys_clk 14>;
713 reset-names = "link", "phy";
714 resets = <&sys_rst 13>, <&sys_rst 20>;
715 vbus-supply = <&usb1_vbus0>;
716 nvmem-cell-names = "rterm", "sel_t", "hs_i";
717 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
718 <&usb_hs_i2>;
719 };
720
721 usb1_hsphy1: hs-phy@210 {
722 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
723 reg = <0x210 0x10>;
724 #phy-cells = <0>;
725 clock-names = "link", "phy", "phy-ext";
726 clocks = <&sys_clk 13>, <&sys_clk 20>,
727 <&sys_clk 14>;
728 reset-names = "link", "phy";
729 resets = <&sys_rst 13>, <&sys_rst 20>;
730 vbus-supply = <&usb1_vbus1>;
731 nvmem-cell-names = "rterm", "sel_t", "hs_i";
732 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
733 <&usb_hs_i2>;
734 };
735
736 usb1_ssphy0: ss-phy@300 {
737 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
738 reg = <0x300 0x10>;
739 #phy-cells = <0>;
740 clock-names = "link", "phy", "phy-ext";
741 clocks = <&sys_clk 13>, <&sys_clk 21>,
742 <&sys_clk 14>;
743 reset-names = "link", "phy";
744 resets = <&sys_rst 13>, <&sys_rst 21>;
745 vbus-supply = <&usb1_vbus0>;
746 };
747 };
748
749 /* FIXME: U-Boot own node */
486 usb1: usb@65d00000 { 750 usb1: usb@65d00000 {
487 compatible = "socionext,uniphier-pxs3-dwc3"; 751 compatible = "socionext,uniphier-pxs3-dwc3";
488 status = "disabled"; 752 status = "disabled";
@@ -509,7 +773,8 @@
509 interrupts = <0 65 4>; 773 interrupts = <0 65 4>;
510 pinctrl-names = "default"; 774 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_nand>; 775 pinctrl-0 = <&pinctrl_nand>;
512 clocks = <&sys_clk 2>; 776 clock-names = "nand", "nand_x", "ecc";
777 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
513 resets = <&sys_rst 2>; 778 resets = <&sys_rst 2>;
514 }; 779 };
515 }; 780 };
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index 437265bb73..f7fcf6b459 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -63,6 +63,17 @@
63 cache-level = <2>; 63 cache-level = <2>;
64 }; 64 };
65 65
66 spi: spi@54006000 {
67 compatible = "socionext,uniphier-scssi";
68 status = "disabled";
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_spi0>;
73 clocks = <&peri_clk 11>;
74 resets = <&peri_rst 11>;
75 };
76
66 serial0: serial@54006800 { 77 serial0: serial@54006800 {
67 compatible = "socionext,uniphier-uart"; 78 compatible = "socionext,uniphier-uart";
68 status = "disabled"; 79 status = "disabled";
@@ -385,7 +396,8 @@
385 interrupts = <0 65 4>; 396 interrupts = <0 65 4>;
386 pinctrl-names = "default"; 397 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_nand2cs>; 398 pinctrl-0 = <&pinctrl_nand2cs>;
388 clocks = <&sys_clk 2>; 399 clock-names = "nand", "nand_x", "ecc";
400 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
389 resets = <&sys_rst 2>; 401 resets = <&sys_rst 2>;
390 }; 402 };
391 }; 403 };
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 5198eee024..ad30059b9a 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -89,6 +89,12 @@
89 status = "disabled"; 89 status = "disabled";
90 }; 90 };
91 91
92 iomuxc: iomuxc@40048000 {
93 compatible = "fsl,vf610-iomuxc";
94 reg = <0x40048000 0x1000>;
95 fsl,mux_mask = <0x700000>;
96 };
97
92 gpio0: gpio@40049000 { 98 gpio0: gpio@40049000 {
93 compatible = "fsl,vf610-gpio"; 99 compatible = "fsl,vf610-gpio";
94 reg = <0x400ff000 0x40>; 100 reg = <0x400ff000 0x40>;
diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
new file mode 100644
index 0000000000..fcad7132c8
--- /dev/null
+++ b/arch/arm/dts/vf610-pinfunc.h
@@ -0,0 +1,810 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_VF610_PINFUNC_H
11#define __DTS_VF610_PINFUNC_H
12
13/*
14 * The pin function ID for VF610 is a tuple of:
15 * <mux_reg input_reg mux_mode input_val>
16 */
17
18#define ALT0 0x0
19#define ALT1 0x1
20#define ALT2 0x2
21#define ALT3 0x3
22#define ALT4 0x4
23#define ALT5 0x5
24#define ALT6 0x6
25#define ALT7 0x7
26
27
28#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
29#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
30#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0
31#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0
32#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0
33#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0
34#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
35#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0
36#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0
37#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0
38#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
39#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0
40#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1
41#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0
42#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0
43#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0
44#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
45#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0
46#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0
47#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0
48#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0
49#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0
50#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
51#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0
52#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0
53#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0
54#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
55#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1
56#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0
57#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0
58#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0
59#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
60#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0
61#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0
62#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0
63#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0
64#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0
65#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0
66#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0
67#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
68#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0
69#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0
70#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0
71#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0
72#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0
73#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0
74#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0
75#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
76#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0
77#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0
78#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0
79#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0
80#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0
81#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0
82#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0
83#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
84#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0
85#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0
86#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0
87#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0
88#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0
89#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0
90#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0
91#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
92#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0
93#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0
94#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0
95#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0
96#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
97#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0
98#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0
99#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0
100#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0
101#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0
102#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0
103#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0
104#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0
105#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0
106#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0
107#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0
108#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0
109#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0
110#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0
111#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0
112#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0
113#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0
114#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0
115#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0
116#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0
117#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0
118#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0
119#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0
120#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0
121#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0
122#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0
123#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0
124#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0
125#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0
126#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0
127#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0
128#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0
129#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0
130#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0
131#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0
132#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0
133#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0
134#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0
135#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0
136#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0
137#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0
138#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0
139#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0
140#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0
141#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0
142#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0
143#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0
144#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0
145#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0
146#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0
147#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0
148#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0
149#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0
150#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0
151#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1
152#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0
153#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0
154#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0
155#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0
156#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0
157#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0
158#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1
159#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0
160#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0
161#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0
162#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0
163#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0
164#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1
165#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0
166#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0
167#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0
168#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0
169#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0
170#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0
171#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0
172#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1
173#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0
174#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0
175#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0
176#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0
177#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0
178#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0
179#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0
180#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1
181#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0
182#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0
183#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0
184#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0
185#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0
186#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0
187#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0
188#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0
189#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0
190#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0
191#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0
192#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0
193#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0
194#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0
195#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0
196#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0
197#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0
198#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0
199#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0
200#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0
201#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0
202#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0
203#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0
204#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0
205#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0
206#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0
207#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0
208#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0
209#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0
210#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0
211#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0
212#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0
213#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0
214#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0
215#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0
216#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0
217#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0
218#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0
219#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0
220#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0
221#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0
222#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1
223#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1
224#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0
225#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0
226#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0
227#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1
228#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0
229#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0
230#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0
231#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0
232#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2
233#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0
234#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1
235#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0
236#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0
237#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0
238#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0
239#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0
240#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0
241#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0
242#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0
243#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0
244#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0
245#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0
246#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0
247#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0
248#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0
249#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0
250#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0
251#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0
252#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0
253#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0
254#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0
255#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0
256#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1
257#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0
258#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0
259#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0
260#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0
261#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1
262#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0
263#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0
264#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0
265#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0
266#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1
267#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0
268#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0
269#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0
270#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1
271#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0
272#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0
273#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0
274#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2
275#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0
276#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0
277#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0
278#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0
279#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0
280#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0
281#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0
282#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0
283#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0
284#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0
285#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0
286#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0
287#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0
288#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0
289#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0
290#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0
291#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1
292#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0
293#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0
294#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1
295#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0
296#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0
297#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0
298#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0
299#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0
300#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0
301#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0
302#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1
303#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0
304#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0
305#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0
306#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0
307#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0
308#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0
309#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0
310#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1
311#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0
312#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0
313#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0
314#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0
315#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0
316#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0
317#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1
318#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0
319#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0
320#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0
321#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0
322#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0
323#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0
324#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0
325#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0
326#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0
327#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0
328#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0
329#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0
330#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0
331#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0
332#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1
333#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0
334#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0
335#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0
336#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0
337#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0
338#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0
339#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0
340#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0
341#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0
342#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0
343#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0
344#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0
345#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0
346#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0
347#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0
348#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0
349#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0
350#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0
351#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0
352#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0
353#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0
354#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0
355#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0
356#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0
357#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0
358#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1
359#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1
360#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0
361#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0
362#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0
363#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1
364#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1
365#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0
366#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0
367#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0
368#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1
369#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1
370#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0
371#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0
372#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0
373#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1
374#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1
375#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0
376#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0
377#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0
378#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1
379#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2
380#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0
381#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0
382#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0
383#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1
384#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0
385#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2
386#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0
387#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0
388#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0
389#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0
390#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1
391#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0
392#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0
393#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0
394#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0
395#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0
396#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0
397#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1
398#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0
399#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2
400#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0
401#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0
402#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0
403#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0
404#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0
405#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0
406#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1
407#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0
408#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0
409#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0
410#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0
411#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0
412#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0
413#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0
414#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0
415#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0
416#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0
417#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0
418#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0
419#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0
420#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0
421#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0
422#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0
423#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0
424#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
425#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
426#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
427#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
428#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
429#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
430#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
431#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0
432#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0
433#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0
434#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0
435#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0
436#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0
437#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1
438#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0
439#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0
440#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0
441#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0
442#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0
443#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0
444#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0
445#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0
446#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0
447#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0
448#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0
449#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0
450#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0
451#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0
452#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0
453#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0
454#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0
455#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0
456#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0
457#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0
458#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0
459#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0