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authorLokesh Vutla2017-07-24 10:11:59 -0500
committerJean-Jacques Hiblot2017-08-02 09:13:38 -0500
commit9316824bb7155088821a38f72a52f065aba8c058 (patch)
tree5c68063e14f861b344a0c50cc9c33b7cb4b74d0e
parent243b3447542da792b53a68c8c9d1d612608703e0 (diff)
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board: ti: dra76-evm: Add DDR data
dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c1
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c2
-rw-r--r--board/ti/dra7xx/evm.c61
3 files changed, 62 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 97ea46865f..ed016cb7de 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -781,6 +781,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
781 case DRA752_ES1_0: 781 case DRA752_ES1_0:
782 case DRA752_ES1_1: 782 case DRA752_ES1_1:
783 case DRA752_ES2_0: 783 case DRA752_ES2_0:
784 case DRA762_ES1_0:
784 *regs = &ioregs_dra7xx_es1; 785 *regs = &ioregs_dra7xx_es1;
785 break; 786 break;
786 case DRA722_ES1_0: 787 case DRA722_ES1_0:
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7712923d85..67ff63b9f6 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -480,6 +480,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
480 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; 480 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
481 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); 481 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
482 break; 482 break;
483 case DRA762_ES1_0:
483 case DRA722_ES2_0: 484 case DRA722_ES2_0:
484 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; 485 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
485 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); 486 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
@@ -709,6 +710,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
709 *iterations = sizeof(omap5_bug_00339_regs)/ 710 *iterations = sizeof(omap5_bug_00339_regs)/
710 sizeof(omap5_bug_00339_regs[0]); 711 sizeof(omap5_bug_00339_regs[0]);
711 break; 712 break;
713 case DRA762_ES1_0:
712 case DRA752_ES1_0: 714 case DRA752_ES1_0:
713 case DRA752_ES1_1: 715 case DRA752_ES1_1:
714 case DRA752_ES2_0: 716 case DRA752_ES2_0:
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 42aba549f2..0f84327b73 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -210,6 +210,56 @@ const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
210 .emif_rd_wr_exec_thresh = 0x00000305 210 .emif_rd_wr_exec_thresh = 0x00000305
211}; 211};
212 212
213const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
214 .sdram_config_init = 0x61862B32,
215 .sdram_config = 0x61862B32,
216 .sdram_config2 = 0x00000000,
217 .ref_ctrl = 0x0000514C,
218 .ref_ctrl_final = 0x0000144A,
219 .sdram_tim1 = 0xD113783C,
220 .sdram_tim2 = 0x30B47FE3,
221 .sdram_tim3 = 0x409F8AD8,
222 .read_idle_ctrl = 0x00050000,
223 .zq_config = 0x5007190B,
224 .temp_alert_config = 0x00000000,
225 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
226 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
227 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
228 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
229 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
230 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
231 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
232 .emif_rd_wr_lvl_rmp_win = 0x00000000,
233 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
234 .emif_rd_wr_lvl_ctl = 0x00000000,
235 .emif_rd_wr_exec_thresh = 0x00000305
236};
237
238const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
239 .sdram_config_init = 0x61862B32,
240 .sdram_config = 0x61862B32,
241 .sdram_config2 = 0x00000000,
242 .ref_ctrl = 0x0000514C,
243 .ref_ctrl_final = 0x0000144A,
244 .sdram_tim1 = 0xD113781C,
245 .sdram_tim2 = 0x30B47FE3,
246 .sdram_tim3 = 0x409F8AD8,
247 .read_idle_ctrl = 0x00050000,
248 .zq_config = 0x5007190B,
249 .temp_alert_config = 0x00000000,
250 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
251 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
252 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
253 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
254 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
255 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
256 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
257 .emif_rd_wr_lvl_rmp_win = 0x00000000,
258 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
259 .emif_rd_wr_lvl_ctl = 0x00000000,
260 .emif_rd_wr_exec_thresh = 0x00000305
261};
262
213void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 263void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
214{ 264{
215 u64 ram_size; 265 u64 ram_size;
@@ -235,6 +285,12 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
235 break; 285 break;
236 } 286 }
237 break; 287 break;
288 case DRA762_ES1_0:
289 if (emif_nr == 1)
290 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
291 else
292 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
293 break;
238 case DRA722_ES1_0: 294 case DRA722_ES1_0:
239 case DRA722_ES2_0: 295 case DRA722_ES2_0:
240 if (ram_size < CONFIG_MAX_MEM_MAPPED) 296 if (ram_size < CONFIG_MAX_MEM_MAPPED)
@@ -290,6 +346,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
290 ram_size = board_ti_get_emif_size(); 346 ram_size = board_ti_get_emif_size();
291 347
292 switch (omap_revision()) { 348 switch (omap_revision()) {
349 case DRA762_ES1_0:
293 case DRA752_ES1_0: 350 case DRA752_ES1_0:
294 case DRA752_ES1_1: 351 case DRA752_ES1_1:
295 case DRA752_ES2_0: 352 case DRA752_ES2_0:
@@ -1087,8 +1144,8 @@ static inline void vtt_regulator_enable(void)
1087 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 1144 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1088 return; 1145 return;
1089 1146
1090 /* Do not enable VTT for DRA722 */ 1147 /* Do not enable VTT for DRA722 or DRA76x */
1091 if (is_dra72x()) 1148 if (is_dra72x() || is_dra76x())
1092 return; 1149 return;
1093 1150
1094 /* 1151 /*