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author | Praneeth Bajjuri | 2017-12-11 12:36:19 -0600 |
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committer | Praneeth Bajjuri | 2017-12-11 12:36:19 -0600 |
commit | aba7e6a1e7483fbe2c4649410cc9fef49280c7a1 (patch) | |
tree | 4e0f947659fdb9b8bcf06e0e53e03819139bd128 | |
parent | 7dbb2953cf10a266dbf623a279e6aa28fc9c595c (diff) | |
parent | 333293e877c338e251c65e8a8a7c45b2cf5c6a06 (diff) | |
download | u-boot-aba7e6a1e7483fbe2c4649410cc9fef49280c7a1.tar.gz u-boot-aba7e6a1e7483fbe2c4649410cc9fef49280c7a1.tar.xz u-boot-aba7e6a1e7483fbe2c4649410cc9fef49280c7a1.zip |
Merge branch 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot into p-ti-u-boot-2016.05p-ti-u-boot-2016.05
* 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot:
ti: dra76: Remove Vin1a_fld conflicting with VOUT1 HDMI power
ARM: DRA7: Add clock fixup for DSP on dra76x
ARM: DRA7: Add OPP_PLUS for GPU
Revert "arm: dra7: Define board specific boot arguments"
ti: dra76: mux_data: Add pinmux for VIN1A for JAMR3
ti: dra76: mux_data: Add pinmux for JAMR use cases
dra7x: fastboot: Increase recovery partition size
omap-common: fastboot: extend cpu type for DRA76x rev 1.0
omap-common: fastboot: update cpu device name
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
-rw-r--r-- | arch/arm/cpu/armv7/omap-common/utils.c | 7 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/Kconfig | 3 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/fdt.c | 20 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 13 | ||||
-rw-r--r-- | arch/arm/include/asm/omap_common.h | 1 | ||||
-rw-r--r-- | board/ti/am57xx/board.c | 6 | ||||
-rw-r--r-- | board/ti/dra7xx/evm.c | 8 | ||||
-rw-r--r-- | board/ti/dra7xx/mux_data.h | 32 | ||||
-rw-r--r-- | configs/dra7xx_evm_defconfig | 2 | ||||
-rw-r--r-- | configs/dra7xx_evm_nodt_defconfig | 2 | ||||
-rw-r--r-- | configs/dra7xx_evm_vision_defconfig | 2 | ||||
-rw-r--r-- | configs/dra7xx_hs_evm_defconfig | 2 | ||||
-rw-r--r-- | include/configs/dra7xx_evm.h | 4 |
13 files changed, 88 insertions, 14 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c index ff5e4818e5..0b09476830 100644 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ b/arch/arm/cpu/armv7/omap-common/utils.c | |||
@@ -132,15 +132,18 @@ static void omap_set_fastboot_cpu(void) | |||
132 | char *cpu; | 132 | char *cpu; |
133 | 133 | ||
134 | switch (omap_revision()) { | 134 | switch (omap_revision()) { |
135 | case DRA762_ES1_0: | ||
136 | cpu = "DRA762"; | ||
137 | break; | ||
135 | case DRA752_ES1_0: | 138 | case DRA752_ES1_0: |
136 | case DRA752_ES1_1: | 139 | case DRA752_ES1_1: |
137 | case DRA752_ES2_0: | 140 | case DRA752_ES2_0: |
138 | cpu = "J6"; | 141 | cpu = "DRA752"; |
139 | break; | 142 | break; |
140 | case DRA722_ES1_0: | 143 | case DRA722_ES1_0: |
141 | case DRA722_ES2_0: | 144 | case DRA722_ES2_0: |
142 | case DRA722_ES2_1: | 145 | case DRA722_ES2_1: |
143 | cpu = "J6ECO"; | 146 | cpu = "DRA722"; |
144 | break; | 147 | break; |
145 | default: | 148 | default: |
146 | cpu = "unknown"; | 149 | cpu = "unknown"; |
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 13b6975731..e93af652a2 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig | |||
@@ -114,6 +114,9 @@ config DRA7_GPU_OPP_OD | |||
114 | config DRA7_GPU_OPP_HIGH | 114 | config DRA7_GPU_OPP_HIGH |
115 | bool "OPP HIGH" | 115 | bool "OPP HIGH" |
116 | 116 | ||
117 | config DRA7_GPU_OPP_PLUS | ||
118 | bool "OPP PLUS" | ||
119 | |||
117 | endchoice | 120 | endchoice |
118 | 121 | ||
119 | endmenu | 122 | endmenu |
diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c index 7215a0dfc1..d74e982ac2 100644 --- a/arch/arm/cpu/armv7/omap5/fdt.c +++ b/arch/arm/cpu/armv7/omap5/fdt.c | |||
@@ -292,6 +292,15 @@ u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = { | |||
292 | {600000000, 600000000, 400000000}, /* OPP_NOM */ | 292 | {600000000, 600000000, 400000000}, /* OPP_NOM */ |
293 | {700000000, 700000000, 466666667}, /* OPP_OD */ | 293 | {700000000, 700000000, 466666667}, /* OPP_OD */ |
294 | {750000000, 750000000, 500000000}, /* OPP_HIGH */ | 294 | {750000000, 750000000, 500000000}, /* OPP_HIGH */ |
295 | {}, /*OPP_PLUS */ | ||
296 | }; | ||
297 | |||
298 | u32 dra76_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = { | ||
299 | {}, /*OPP_LOW */ | ||
300 | {600000000, 600000000, 400000000}, /* OPP_NOM */ | ||
301 | {700000000, 700000000, 466666667}, /* OPP_OD */ | ||
302 | {850000000, 850000000, 500000000}, /* OPP_HIGH */ | ||
303 | {}, /*OPP_PLUS */ | ||
295 | }; | 304 | }; |
296 | 305 | ||
297 | /* IVA voltage domain */ | 306 | /* IVA voltage domain */ |
@@ -300,6 +309,7 @@ u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = { | |||
300 | {1165000000, 388333334}, /* OPP_NOM */ | 309 | {1165000000, 388333334}, /* OPP_NOM */ |
301 | {860000000, 430000000}, /* OPP_OD */ | 310 | {860000000, 430000000}, /* OPP_OD */ |
302 | {1064000000, 532000000}, /* OPP_HIGH */ | 311 | {1064000000, 532000000}, /* OPP_HIGH */ |
312 | {}, /*OPP_PLUS */ | ||
303 | }; | 313 | }; |
304 | 314 | ||
305 | /* GPU voltage domain */ | 315 | /* GPU voltage domain */ |
@@ -308,6 +318,7 @@ u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = { | |||
308 | {1277000000, 425666667}, /* OPP_NOM */ | 318 | {1277000000, 425666667}, /* OPP_NOM */ |
309 | {1000000000, 500000000}, /* OPP_OD */ | 319 | {1000000000, 500000000}, /* OPP_OD */ |
310 | {1064000000, 532000000}, /* OPP_HIGH */ | 320 | {1064000000, 532000000}, /* OPP_HIGH */ |
321 | {1330000000, 665000000}, /* OPP_PLUS */ | ||
311 | }; | 322 | }; |
312 | 323 | ||
313 | static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num) | 324 | static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num) |
@@ -368,7 +379,14 @@ static void ft_opp_clock_fixups(void *fdt, bd_t *bd) | |||
368 | 379 | ||
369 | /* fixup DSP clocks */ | 380 | /* fixup DSP clocks */ |
370 | clk_names = dra7_opp_dsp_clk_names; | 381 | clk_names = dra7_opp_dsp_clk_names; |
371 | clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; | 382 | |
383 | if (is_dra76x()) | ||
384 | clk_rates = | ||
385 | dra76_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; | ||
386 | else | ||
387 | clk_rates = | ||
388 | dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; | ||
389 | |||
372 | ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM); | 390 | ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM); |
373 | if (ret) { | 391 | if (ret) { |
374 | printf("ft_fixup_clocks failed for DSP voltage domain: %s\n", | 392 | printf("ft_fixup_clocks failed for DSP voltage domain: %s\n", |
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 489815e644..80077d7b71 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h | |||
@@ -256,6 +256,9 @@ | |||
256 | #define VDD_GPU_DRA7_HIGH 1250 | 256 | #define VDD_GPU_DRA7_HIGH 1250 |
257 | #define VDD_IVA_DRA7_HIGH 1250 | 257 | #define VDD_IVA_DRA7_HIGH 1250 |
258 | 258 | ||
259 | /* DRA76x voltage settings in mv for OPP_PLUS per DM */ | ||
260 | #define VDD_GPU_DRA7_PLUS 1250 | ||
261 | |||
259 | /* Efuse register offsets for DRA7xx platform */ | 262 | /* Efuse register offsets for DRA7xx platform */ |
260 | #define DRA752_EFUSE_BASE 0x4A002000 | 263 | #define DRA752_EFUSE_BASE 0x4A002000 |
261 | #define DRA752_EFUSE_REGBITS 16 | 264 | #define DRA752_EFUSE_REGBITS 16 |
@@ -279,6 +282,8 @@ | |||
279 | #define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) | 282 | #define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) |
280 | /* STD_FUSE_OPP_VMIN_GPU_4 */ | 283 | /* STD_FUSE_OPP_VMIN_GPU_4 */ |
281 | #define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) | 284 | #define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) |
285 | /* STD_FUSE_OPP_VMIN_GPU_5 */ | ||
286 | #define STD_FUSE_OPP_VMIN_GPU_PLUS (DRA752_EFUSE_BASE + 0x1B14) | ||
282 | /* STD_FUSE_OPP_VMIN_MPU_2 */ | 287 | /* STD_FUSE_OPP_VMIN_MPU_2 */ |
283 | #define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) | 288 | #define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) |
284 | /* STD_FUSE_OPP_VMIN_MPU_3 */ | 289 | /* STD_FUSE_OPP_VMIN_MPU_3 */ |
@@ -291,13 +296,13 @@ | |||
291 | #define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM | 296 | #define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM |
292 | #define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM | 297 | #define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM |
293 | #define VDD_EVE_DRA7 VDD_EVE_DRA7_HIGH | 298 | #define VDD_EVE_DRA7 VDD_EVE_DRA7_HIGH |
294 | #define VDD_GPU_DRA7 VDD_GPU_DRA7_HIGH | 299 | #define VDD_GPU_DRA7 VDD_GPU_DRA7_PLUS |
295 | #define VDD_IVA_DRA7 VDD_IVA_DRA7_HIGH | 300 | #define VDD_IVA_DRA7 VDD_IVA_DRA7_HIGH |
296 | 301 | ||
297 | #define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM | 302 | #define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM |
298 | #define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM | 303 | #define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM |
299 | #define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_HIGH | 304 | #define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_HIGH |
300 | #define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_HIGH | 305 | #define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_PLUS |
301 | #define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_HIGH | 306 | #define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_HIGH |
302 | 307 | ||
303 | /* Common OPP selection for DRA7xx devices */ | 308 | /* Common OPP selection for DRA7xx devices */ |
@@ -327,7 +332,9 @@ | |||
327 | #define DRA7_IVA_OPP OPP_NOM | 332 | #define DRA7_IVA_OPP OPP_NOM |
328 | #endif | 333 | #endif |
329 | 334 | ||
330 | #if defined(CONFIG_DRA7_GPU_OPP_HIGH) | 335 | #if defined(CONFIG_DRA7_GPU_OPP_PLUS) |
336 | #define DRA7_GPU_OPP OPP_PLUS | ||
337 | #elif defined(CONFIG_DRA7_GPU_OPP_HIGH) | ||
331 | #define DRA7_GPU_OPP OPP_HIGH | 338 | #define DRA7_GPU_OPP OPP_HIGH |
332 | #elif defined(CONFIG_DRA7_GPU_OPP_OD) | 339 | #elif defined(CONFIG_DRA7_GPU_OPP_OD) |
333 | #define DRA7_GPU_OPP OPP_OD | 340 | #define DRA7_GPU_OPP OPP_OD |
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 951a407515..32575348ba 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h | |||
@@ -545,6 +545,7 @@ enum { | |||
545 | OPP_NOM, | 545 | OPP_NOM, |
546 | OPP_OD, | 546 | OPP_OD, |
547 | OPP_HIGH, | 547 | OPP_HIGH, |
548 | OPP_PLUS, | ||
548 | NUM_OPPS, | 549 | NUM_OPPS, |
549 | }; | 550 | }; |
550 | 551 | ||
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 72c4312837..67c8d2ecae 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c | |||
@@ -269,9 +269,11 @@ struct vcores_data beagle_x15_volts = { | |||
269 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, | 269 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
270 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | 270 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
271 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | 271 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
272 | .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS, | ||
272 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | 273 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
273 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | 274 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
274 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | 275 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
276 | .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS, | ||
275 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | 277 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
276 | .gpu.addr = TPS659038_REG_ADDR_SMPS45, | 278 | .gpu.addr = TPS659038_REG_ADDR_SMPS45, |
277 | .gpu.pmic = &tps659038, | 279 | .gpu.pmic = &tps659038, |
@@ -317,9 +319,11 @@ struct vcores_data am571x_idk_volts = { | |||
317 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, | 319 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
318 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | 320 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
319 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | 321 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
322 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_PLUS, | ||
320 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | 323 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
321 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | 324 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
322 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | 325 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
326 | .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS, | ||
323 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | 327 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
324 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, | 328 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, |
325 | .gpu.pmic = &tps659038, | 329 | .gpu.pmic = &tps659038, |
@@ -365,9 +369,11 @@ struct vcores_data am572x_idk_volts = { | |||
365 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, | 369 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
366 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | 370 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
367 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | 371 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
372 | .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS, | ||
368 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | 373 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
369 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | 374 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
370 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | 375 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
376 | .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS, | ||
371 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | 377 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
372 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, | 378 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, |
373 | .gpu.pmic = &tps659038, | 379 | .gpu.pmic = &tps659038, |
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 685edf07c8..08c0987afe 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c | |||
@@ -391,9 +391,11 @@ struct vcores_data dra752_volts = { | |||
391 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, | 391 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
392 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | 392 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
393 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | 393 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
394 | .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS, | ||
394 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | 395 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
395 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | 396 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
396 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | 397 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
398 | .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS, | ||
397 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | 399 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
398 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, | 400 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, |
399 | .gpu.pmic = &tps659038, | 401 | .gpu.pmic = &tps659038, |
@@ -439,9 +441,11 @@ struct vcores_data dra76x_volts = { | |||
439 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, | 441 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
440 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | 442 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
441 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | 443 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
444 | .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS, | ||
442 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | 445 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
443 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | 446 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
444 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | 447 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
448 | .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS, | ||
445 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | 449 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
446 | .gpu.addr = LP87565_REG_ADDR_BUCK23, | 450 | .gpu.addr = LP87565_REG_ADDR_BUCK23, |
447 | .gpu.pmic = &lp87565, | 451 | .gpu.pmic = &lp87565, |
@@ -486,9 +490,11 @@ struct vcores_data dra722_volts = { | |||
486 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, | 490 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
487 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, | 491 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
488 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, | 492 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
493 | .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS, | ||
489 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, | 494 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
490 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, | 495 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
491 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, | 496 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
497 | .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS, | ||
492 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | 498 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
493 | .gpu.addr = TPS65917_REG_ADDR_SMPS3, | 499 | .gpu.addr = TPS65917_REG_ADDR_SMPS3, |
494 | .gpu.pmic = &tps659038, | 500 | .gpu.pmic = &tps659038, |
@@ -587,6 +593,8 @@ int get_voltrail_opp(int rail_offset) | |||
587 | /* DRA71x supports only OPP_NOM for GPU */ | 593 | /* DRA71x supports only OPP_NOM for GPU */ |
588 | if (board_is_dra71x_evm()) | 594 | if (board_is_dra71x_evm()) |
589 | opp = OPP_NOM; | 595 | opp = OPP_NOM; |
596 | else if (!board_is_dra76x_evm() && opp == OPP_PLUS) | ||
597 | opp = OPP_HIGH; | ||
590 | break; | 598 | break; |
591 | case VOLT_EVE: | 599 | case VOLT_EVE: |
592 | opp = DRA7_DSPEVE_OPP; | 600 | opp = DRA7_DSPEVE_OPP; |
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 7e9dea677e..d0cc4b68b5 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h | |||
@@ -1109,6 +1109,38 @@ const struct pad_conf_entry dra76x_core_padconf_array[] = { | |||
1109 | {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */ | 1109 | {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */ |
1110 | {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */ | 1110 | {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */ |
1111 | {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */ | 1111 | {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */ |
1112 | #ifdef CONFIG_DRA7XX_JAMR3 | ||
1113 | {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_clk0.vin1a_clk0 */ | ||
1114 | {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_de0.vin1a_de0 */ | ||
1115 | {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_hsync0.vin1a_hsync0 */ | ||
1116 | {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_vsync0.vin1a_vsync0 */ | ||
1117 | {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d0.vin1a_d0 */ | ||
1118 | {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d1.vin1a_d1 */ | ||
1119 | {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.vin1a_d2 */ | ||
1120 | {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.vin1a_d3 */ | ||
1121 | {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.vin1a_d4 */ | ||
1122 | {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.vin1a_d5 */ | ||
1123 | {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.vin1a_d6 */ | ||
1124 | {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.vin1a_d7 */ | ||
1125 | {XREF_CLK1, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.atl_clk1 */ | ||
1126 | {XREF_CLK3, (M14 | PIN_INPUT)}, /* xref_clk3.gpio6_20 */ | ||
1127 | {MCASP1_AXR8, (M1 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr8.mcasp6_axr0 */ | ||
1128 | {MCASP1_AXR9, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.mcasp6_axr1 */ | ||
1129 | {MCASP1_AXR10, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.mcasp6_aclkx */ | ||
1130 | {MCASP1_AXR11, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.mcasp6_fsx */ | ||
1131 | {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* mcasp2_aclkx.mcasp2_aclkx */ | ||
1132 | {MCASP2_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_fsx.mcasp2_fsx */ | ||
1133 | {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr0.mcasp2_axr0 */ | ||
1134 | {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr1.mcasp2_axr1 */ | ||
1135 | {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_axr2.mcasp2_axr2 */ | ||
1136 | {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_axr3.mcasp2_axr3 */ | ||
1137 | {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr4.mcasp2_axr4 */ | ||
1138 | {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr5.mcasp2_axr5 */ | ||
1139 | {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr6.mcasp2_axr6 */ | ||
1140 | {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr7.mcasp2_axr7 */ | ||
1141 | {MCASP4_ACLKX, (M4 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.i2c4_sda */ | ||
1142 | {MCASP4_FSX, (M4 | PIN_INPUT_PULLUP)}, /* mcasp4_fsx.i2c4_scl */ | ||
1143 | #endif | ||
1112 | }; | 1144 | }; |
1113 | 1145 | ||
1114 | #ifdef CONFIG_IODELAY_RECALIBRATION | 1146 | #ifdef CONFIG_IODELAY_RECALIBRATION |
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index e125593e41..a6cec9d5fa 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig | |||
@@ -68,7 +68,7 @@ CONFIG_OF_LIBFDT=y | |||
68 | CONFIG_OF_BOARD_SETUP=y | 68 | CONFIG_OF_BOARD_SETUP=y |
69 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y | 69 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y |
70 | CONFIG_DRA7_IVA_OPP_HIGH=y | 70 | CONFIG_DRA7_IVA_OPP_HIGH=y |
71 | CONFIG_DRA7_GPU_OPP_HIGH=y | 71 | CONFIG_DRA7_GPU_OPP_PLUS=y |
72 | CONFIG_CMD_TIME=y | 72 | CONFIG_CMD_TIME=y |
73 | CONFIG_DM_I2C=y | 73 | CONFIG_DM_I2C=y |
74 | CONFIG_DM_REGULATOR=y | 74 | CONFIG_DM_REGULATOR=y |
diff --git a/configs/dra7xx_evm_nodt_defconfig b/configs/dra7xx_evm_nodt_defconfig index 9c13366939..64609f31b4 100644 --- a/configs/dra7xx_evm_nodt_defconfig +++ b/configs/dra7xx_evm_nodt_defconfig | |||
@@ -45,4 +45,4 @@ CONFIG_SPL_OF_LIBFDT=y | |||
45 | CONFIG_OF_BOARD_SETUP=y | 45 | CONFIG_OF_BOARD_SETUP=y |
46 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y | 46 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y |
47 | CONFIG_DRA7_IVA_OPP_HIGH=y | 47 | CONFIG_DRA7_IVA_OPP_HIGH=y |
48 | CONFIG_DRA7_GPU_OPP_HIGH=y | 48 | CONFIG_DRA7_GPU_OPP_PLUS=y |
diff --git a/configs/dra7xx_evm_vision_defconfig b/configs/dra7xx_evm_vision_defconfig index 8b97ec7b69..8f78fc1731 100644 --- a/configs/dra7xx_evm_vision_defconfig +++ b/configs/dra7xx_evm_vision_defconfig | |||
@@ -62,7 +62,7 @@ CONFIG_OF_LIBFDT=y | |||
62 | CONFIG_OF_BOARD_SETUP=y | 62 | CONFIG_OF_BOARD_SETUP=y |
63 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y | 63 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y |
64 | CONFIG_DRA7_IVA_OPP_HIGH=y | 64 | CONFIG_DRA7_IVA_OPP_HIGH=y |
65 | CONFIG_DRA7_GPU_OPP_HIGH=y | 65 | CONFIG_DRA7_GPU_OPP_PLUS=y |
66 | CONFIG_CMD_TIME=y | 66 | CONFIG_CMD_TIME=y |
67 | CONFIG_DM_I2C=y | 67 | CONFIG_DM_I2C=y |
68 | CONFIG_DM_REGULATOR=y | 68 | CONFIG_DM_REGULATOR=y |
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 87efcb262d..0279e0e073 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig | |||
@@ -72,7 +72,7 @@ CONFIG_ERRNO_STR=y | |||
72 | CONFIG_OF_BOARD_SETUP=y | 72 | CONFIG_OF_BOARD_SETUP=y |
73 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y | 73 | CONFIG_DRA7_DSPEVE_OPP_HIGH=y |
74 | CONFIG_DRA7_IVA_OPP_HIGH=y | 74 | CONFIG_DRA7_IVA_OPP_HIGH=y |
75 | CONFIG_DRA7_GPU_OPP_HIGH=y | 75 | CONFIG_DRA7_GPU_OPP_PLUS=y |
76 | CONFIG_CMD_TIME=y | 76 | CONFIG_CMD_TIME=y |
77 | CONFIG_CMD_PMIC=y | 77 | CONFIG_CMD_PMIC=y |
78 | CONFIG_CMD_REGULATOR=y | 78 | CONFIG_CMD_REGULATOR=y |
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 8bb9811924..fadeb78a16 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h | |||
@@ -92,10 +92,6 @@ | |||
92 | 92 | ||
93 | #define CONFIG_ANDROID_BOOT_IMAGE | 93 | #define CONFIG_ANDROID_BOOT_IMAGE |
94 | 94 | ||
95 | #define CONFIG_BOOTARGS_BOARD "console=ttyS0,115200 " \ | ||
96 | "androidboot.console=ttyS0 " \ | ||
97 | "androidboot.hardware=jacinto6evmboard" | ||
98 | |||
99 | #ifdef CONFIG_SPL_BUILD | 95 | #ifdef CONFIG_SPL_BUILD |
100 | #undef CONFIG_CMD_BOOTD | 96 | #undef CONFIG_CMD_BOOTD |
101 | #ifdef CONFIG_SPL_DFU_SUPPORT | 97 | #ifdef CONFIG_SPL_DFU_SUPPORT |