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authorTom Rini2018-11-14 17:25:34 -0600
committerTom Rini2018-11-14 17:25:34 -0600
commit6f443330186676004148930b4dd77f1c2735bd36 (patch)
treef1cc00c2b5210e7bd13f527b0698bfeaf783ac86
parent208ecbad2ea83333e8f3c9933213867addf16f4a (diff)
parent7d121a8ea4e0dbf0d7e105b57c3dbd7d8bd2e729 (diff)
downloadu-boot-6f443330186676004148930b4dd77f1c2735bd36.tar.gz
u-boot-6f443330186676004148930b4dd77f1c2735bd36.tar.xz
u-boot-6f443330186676004148930b4dd77f1c2735bd36.zip
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/sun50i-a64-amarula-relic.dts168
-rw-r--r--arch/arm/dts/sun50i-a64-bananapi-m64.dts34
-rw-r--r--arch/arm/dts/sun50i-a64-nanopi-a64.dts89
-rw-r--r--arch/arm/dts/sun50i-a64-olinuxino.dts103
-rw-r--r--arch/arm/dts/sun50i-a64-orangepi-win.dts179
-rw-r--r--arch/arm/dts/sun50i-a64-pine64-lts.dts13
-rw-r--r--arch/arm/dts/sun50i-a64-pine64.dts32
-rw-r--r--arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi15
-rw-r--r--arch/arm/dts/sun50i-a64-pinebook.dts294
-rw-r--r--arch/arm/dts/sun50i-a64-sopine-baseboard.dts32
-rw-r--r--arch/arm/dts/sun50i-a64-sopine.dtsi15
-rw-r--r--arch/arm/dts/sun50i-a64.dtsi312
-rw-r--r--arch/arm/dts/sun50i-h5-orangepi-pc2.dts12
-rw-r--r--arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts2
-rw-r--r--arch/arm/dts/sun50i-h6-orangepi-lite2.dts11
-rw-r--r--arch/arm/dts/sun50i-h6-orangepi-one-plus.dts140
-rw-r--r--arch/arm/dts/sun50i-h6-orangepi.dtsi150
-rw-r--r--arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts121
-rw-r--r--arch/arm/dts/sun8i-h3.dtsi31
-rw-r--r--arch/arm/dts/sunxi-h3-h5.dtsi2
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h1
-rw-r--r--arch/arm/include/asm/arch-sunxi/mmc.h6
-rw-r--r--arch/arm/mach-sunxi/Kconfig1
-rw-r--r--arch/arm/mach-sunxi/clock_sun6i.c4
-rw-r--r--board/sunxi/MAINTAINERS10
-rw-r--r--board/sunxi/board.c6
-rw-r--r--configs/bananapi_m2_zero_defconfig13
-rw-r--r--configs/orangepi_lite2_defconfig12
-rw-r--r--configs/pine64-lts_defconfig19
-rw-r--r--configs/pinebook_defconfig22
-rw-r--r--drivers/mmc/sunxi_mmc.c21
-rw-r--r--drivers/video/bridge/video-bridge-uclass.c16
-rw-r--r--drivers/video/sunxi/lcdc.c22
35 files changed, 1710 insertions, 202 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f3fa1575a..2899a60793 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -848,6 +848,7 @@ config ARCH_SUNXI
848 imply CMD_UBI if NAND 848 imply CMD_UBI if NAND
849 imply DISTRO_DEFAULTS 849 imply DISTRO_DEFAULTS
850 imply FAT_WRITE 850 imply FAT_WRITE
851 imply FIT
851 imply OF_LIBFDT_OVERLAY 852 imply OF_LIBFDT_OVERLAY
852 imply PRE_CONSOLE_BUFFER 853 imply PRE_CONSOLE_BUFFER
853 imply SPL_GPIO_SUPPORT 854 imply SPL_GPIO_SUPPORT
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d36447d18d..1cbb45d679 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -365,6 +365,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
365 sun8i-a83t-cubietruck-plus.dtb \ 365 sun8i-a83t-cubietruck-plus.dtb \
366 sun8i-a83t-tbs-a711.dts 366 sun8i-a83t-tbs-a711.dts
367dtb-$(CONFIG_MACH_SUN8I_H3) += \ 367dtb-$(CONFIG_MACH_SUN8I_H3) += \
368 sun8i-h2-plus-bananapi-m2-zero.dtb \
368 sun8i-h2-plus-libretech-all-h3-cc.dtb \ 369 sun8i-h2-plus-libretech-all-h3-cc.dtb \
369 sun8i-h2-plus-orangepi-r1.dtb \ 370 sun8i-h2-plus-orangepi-r1.dtb \
370 sun8i-h2-plus-orangepi-zero.dtb \ 371 sun8i-h2-plus-orangepi-zero.dtb \
@@ -395,6 +396,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
395 sun50i-h5-orangepi-prime.dtb \ 396 sun50i-h5-orangepi-prime.dtb \
396 sun50i-h5-orangepi-zero-plus2.dtb 397 sun50i-h5-orangepi-zero-plus2.dtb
397dtb-$(CONFIG_MACH_SUN50I_H6) += \ 398dtb-$(CONFIG_MACH_SUN50I_H6) += \
399 sun50i-h6-orangepi-lite2.dtb \
398 sun50i-h6-orangepi-one-plus.dtb \ 400 sun50i-h6-orangepi-one-plus.dtb \
399 sun50i-h6-pine-h64.dtb 401 sun50i-h6-pine-h64.dtb
400dtb-$(CONFIG_MACH_SUN50I) += \ 402dtb-$(CONFIG_MACH_SUN50I) += \
@@ -405,6 +407,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \
405 sun50i-a64-orangepi-win.dtb \ 407 sun50i-a64-orangepi-win.dtb \
406 sun50i-a64-pine64-plus.dtb \ 408 sun50i-a64-pine64-plus.dtb \
407 sun50i-a64-pine64.dtb \ 409 sun50i-a64-pine64.dtb \
410 sun50i-a64-pinebook.dtb \
408 sun50i-a64-sopine-baseboard.dtb 411 sun50i-a64-sopine-baseboard.dtb
409dtb-$(CONFIG_MACH_SUN9I) += \ 412dtb-$(CONFIG_MACH_SUN9I) += \
410 sun9i-a80-optimus.dtb \ 413 sun9i-a80-optimus.dtb \
diff --git a/arch/arm/dts/sun50i-a64-amarula-relic.dts b/arch/arm/dts/sun50i-a64-amarula-relic.dts
index f3b4e93ece..6cb2b7f0c8 100644
--- a/arch/arm/dts/sun50i-a64-amarula-relic.dts
+++ b/arch/arm/dts/sun50i-a64-amarula-relic.dts
@@ -22,11 +22,11 @@
22 stdout-path = "serial0:115200n8"; 22 stdout-path = "serial0:115200n8";
23 }; 23 };
24 24
25 reg_vcc3v3: vcc3v3 { 25 wifi_pwrseq: wifi-pwrseq {
26 compatible = "regulator-fixed"; 26 compatible = "mmc-pwrseq-simple";
27 regulator-name = "vcc3v3"; 27 clocks = <&rtc 1>;
28 regulator-min-microvolt = <3300000>; 28 clock-names = "ext_clock";
29 regulator-max-microvolt = <3300000>; 29 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
30 }; 30 };
31}; 31};
32 32
@@ -34,10 +34,34 @@
34 status = "okay"; 34 status = "okay";
35}; 35};
36 36
37&mmc1 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&mmc1_pins>;
40 vmmc-supply = <&reg_dcdc1>;
41 /*
42 * Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but
43 * dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with
44 * 0Ohm register to vcc-io-wifi so eldo1 is used.
45 */
46 vqmmc-supply = <&reg_eldo1>;
47 mmc-pwrseq = <&wifi_pwrseq>;
48 bus-width = <4>;
49 non-removable;
50 status = "okay";
51
52 brcmf: wifi@1 {
53 reg = <1>;
54 compatible = "brcm,bcm4329-fmac";
55 interrupt-parent = <&r_pio>;
56 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */
57 interrupt-names = "host-wake";
58 };
59};
60
37&mmc2 { 61&mmc2 {
38 pinctrl-names = "default"; 62 pinctrl-names = "default";
39 pinctrl-0 = <&mmc2_pins>; 63 pinctrl-0 = <&mmc2_pins>;
40 vmmc-supply = <&reg_vcc3v3>; 64 vmmc-supply = <&reg_dcdc1>;
41 bus-width = <8>; 65 bus-width = <8>;
42 non-removable; 66 non-removable;
43 cap-mmc-hw-reset; 67 cap-mmc-hw-reset;
@@ -48,9 +72,138 @@
48 status = "okay"; 72 status = "okay";
49}; 73};
50 74
75&r_rsb {
76 status = "okay";
77
78 axp803: pmic@3a3 {
79 compatible = "x-powers,axp803";
80 reg = <0x3a3>;
81 interrupt-parent = <&r_intc>;
82 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
83 x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
84 };
85};
86
87#include "axp803.dtsi"
88
89&reg_aldo1 {
90 regulator-always-on;
91 regulator-min-microvolt = <2800000>;
92 regulator-max-microvolt = <2800000>;
93 regulator-name = "avdd-csi";
94};
95
96&reg_aldo2 {
97 regulator-always-on;
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <3300000>;
100 regulator-name = "vcc-pl";
101};
102
103&reg_aldo3 {
104 regulator-always-on;
105 regulator-min-microvolt = <3000000>;
106 regulator-max-microvolt = <3000000>;
107 regulator-name = "vcc-pll-avcc";
108};
109
110&reg_dcdc1 {
111 regulator-always-on;
112 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>;
114 regulator-name = "vcc-3v3";
115};
116
117&reg_dcdc2 {
118 regulator-always-on;
119 regulator-min-microvolt = <1040000>;
120 regulator-max-microvolt = <1300000>;
121 regulator-name = "vdd-cpux";
122};
123
124/* DCDC3 is polyphased with DCDC2 */
125
126&reg_dcdc5 {
127 regulator-always-on;
128 regulator-min-microvolt = <1500000>;
129 regulator-max-microvolt = <1500000>;
130 regulator-name = "vcc-dram";
131};
132
133&reg_dcdc6 {
134 regulator-always-on;
135 regulator-min-microvolt = <1100000>;
136 regulator-max-microvolt = <1100000>;
137 regulator-name = "vdd-sys";
138};
139
140&reg_dldo1 {
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 regulator-name = "vcc-hdmi-dsi-sensor";
144};
145
146&reg_dldo2 {
147 regulator-min-microvolt = <3300000>;
148 regulator-max-microvolt = <3300000>;
149 regulator-name = "vcc-mipi";
150};
151
152&reg_dldo3 {
153 regulator-min-microvolt = <2800000>;
154 regulator-max-microvolt = <2800000>;
155 regulator-name = "dovdd-csi";
156};
157
158&reg_dldo4 {
159 regulator-min-microvolt = <3300000>;
160 regulator-max-microvolt = <3300000>;
161 regulator-name = "vcc-wifi-io";
162};
163
164&reg_drivevbus {
165 regulator-name = "usb0-vbus";
166 status = "okay";
167};
168
169&reg_eldo1 {
170 regulator-always-on;
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 regulator-name = "cpvdd";
174};
175
176&reg_eldo3 {
177 regulator-min-microvolt = <1800000>;
178 regulator-max-microvolt = <1800000>;
179 regulator-name = "dvdd-csi";
180};
181
182&reg_fldo1 {
183 regulator-min-microvolt = <1200000>;
184 regulator-max-microvolt = <1200000>;
185 regulator-name = "vcc-1v2-hsic";
186};
187
188/*
189 * The A64 chip cannot work without this regulator off, although
190 * it seems to be only driving the AR100 core.
191 * Maybe we don't still know well about CPUs domain.
192 */
193&reg_fldo2 {
194 regulator-always-on;
195 regulator-min-microvolt = <1100000>;
196 regulator-max-microvolt = <1100000>;
197 regulator-name = "vdd-cpus";
198};
199
200&reg_rtc_ldo {
201 regulator-name = "vcc-rtc";
202};
203
51&uart0 { 204&uart0 {
52 pinctrl-names = "default"; 205 pinctrl-names = "default";
53 pinctrl-0 = <&uart0_pins_a>; 206 pinctrl-0 = <&uart0_pb_pins>;
54 status = "okay"; 207 status = "okay";
55}; 208};
56 209
@@ -61,5 +214,6 @@
61 214
62&usbphy { 215&usbphy {
63 usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ 216 usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
217 usb0_vbus-supply = <&reg_drivevbus>;
64 status = "okay"; 218 status = "okay";
65}; 219};
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
index 0716b14411..ef1c90401b 100644
--- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
@@ -60,6 +60,17 @@
60 stdout-path = "serial0:115200n8"; 60 stdout-path = "serial0:115200n8";
61 }; 61 };
62 62
63 hdmi-connector {
64 compatible = "hdmi-connector";
65 type = "a";
66
67 port {
68 hdmi_con_in: endpoint {
69 remote-endpoint = <&hdmi_out_con>;
70 };
71 };
72 };
73
63 leds { 74 leds {
64 compatible = "gpio-leds"; 75 compatible = "gpio-leds";
65 76
@@ -86,6 +97,10 @@
86 }; 97 };
87}; 98};
88 99
100&de {
101 status = "okay";
102};
103
89&ehci0 { 104&ehci0 {
90 status = "okay"; 105 status = "okay";
91}; 106};
@@ -103,6 +118,17 @@
103 status = "okay"; 118 status = "okay";
104}; 119};
105 120
121&hdmi {
122 hvcc-supply = <&reg_dldo1>;
123 status = "okay";
124};
125
126&hdmi_out {
127 hdmi_out_con: endpoint {
128 remote-endpoint = <&hdmi_con_in>;
129 };
130};
131
106&i2c1 { 132&i2c1 {
107 pinctrl-names = "default"; 133 pinctrl-names = "default";
108 pinctrl-0 = <&i2c1_pins>; 134 pinctrl-0 = <&i2c1_pins>;
@@ -151,7 +177,7 @@
151 177
152&mmc2 { 178&mmc2 {
153 pinctrl-names = "default"; 179 pinctrl-names = "default";
154 pinctrl-0 = <&mmc2_pins>; 180 pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
155 vmmc-supply = <&reg_dcdc1>; 181 vmmc-supply = <&reg_dcdc1>;
156 bus-width = <8>; 182 bus-width = <8>;
157 non-removable; 183 non-removable;
@@ -296,9 +322,13 @@
296 regulator-name = "vcc-rtc"; 322 regulator-name = "vcc-rtc";
297}; 323};
298 324
325&simplefb_hdmi {
326 vcc-hdmi-supply = <&reg_dldo1>;
327};
328
299&uart0 { 329&uart0 {
300 pinctrl-names = "default"; 330 pinctrl-names = "default";
301 pinctrl-0 = <&uart0_pins_a>; 331 pinctrl-0 = <&uart0_pb_pins>;
302 status = "okay"; 332 status = "okay";
303}; 333};
304 334
diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
index e2dce48fa2..31884dbc88 100644
--- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
@@ -51,12 +51,44 @@
51 compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; 51 compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
52 52
53 aliases { 53 aliases {
54 ethernet0 = &emac;
54 serial0 = &uart0; 55 serial0 = &uart0;
55 }; 56 };
56 57
57 chosen { 58 chosen {
58 stdout-path = "serial0:115200n8"; 59 stdout-path = "serial0:115200n8";
59 }; 60 };
61
62 hdmi-connector {
63 compatible = "hdmi-connector";
64 type = "a";
65
66 port {
67 hdmi_con_in: endpoint {
68 remote-endpoint = <&hdmi_out_con>;
69 };
70 };
71 };
72
73 leds {
74 compatible = "gpio-leds";
75
76 blue {
77 label = "nanopi-a64:blue:status";
78 gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
79 };
80 };
81
82 wifi_pwrseq: wifi_pwrseq {
83 compatible = "mmc-pwrseq-simple";
84 clocks = <&rtc 1>;
85 clock-names = "ext_clock";
86 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
87 };
88};
89
90&de {
91 status = "okay";
60}; 92};
61 93
62&ehci0 { 94&ehci0 {
@@ -67,6 +99,26 @@
67 status = "okay"; 99 status = "okay";
68}; 100};
69 101
102&emac {
103 pinctrl-names = "default";
104 pinctrl-0 = <&rgmii_pins>;
105 phy-mode = "rgmii";
106 phy-handle = <&ext_rgmii_phy>;
107 phy-supply = <&reg_dcdc1>;
108 status = "okay";
109};
110
111&hdmi {
112 hvcc-supply = <&reg_dldo1>;
113 status = "okay";
114};
115
116&hdmi_out {
117 hdmi_out_con: endpoint {
118 remote-endpoint = <&hdmi_con_in>;
119 };
120};
121
70/* i2c1 connected with gpio headers like pine64, bananapi */ 122/* i2c1 connected with gpio headers like pine64, bananapi */
71&i2c1 { 123&i2c1 {
72 pinctrl-names = "default"; 124 pinctrl-names = "default";
@@ -78,6 +130,13 @@
78 bias-pull-up; 130 bias-pull-up;
79}; 131};
80 132
133&mdio {
134 ext_rgmii_phy: ethernet-phy@1 {
135 compatible = "ethernet-phy-ieee802.3-c22";
136 reg = <7>;
137 };
138};
139
81&mmc0 { 140&mmc0 {
82 pinctrl-names = "default"; 141 pinctrl-names = "default";
83 pinctrl-0 = <&mmc0_pins>; 142 pinctrl-0 = <&mmc0_pins>;
@@ -88,6 +147,24 @@
88 status = "okay"; 147 status = "okay";
89}; 148};
90 149
150&mmc1 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&mmc1_pins>;
153 vmmc-supply = <&reg_dcdc1>;
154 vqmmc-supply = <&reg_dldo4>;
155 mmc-pwrseq = <&wifi_pwrseq>;
156 bus-width = <4>;
157 non-removable;
158 status = "okay";
159
160 rtl8189etv: wifi@1 {
161 reg = <1>;
162 interrupt-parent = <&r_pio>;
163 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
164 interrupt-names = "host-wake";
165 };
166};
167
91&ohci0 { 168&ohci0 {
92 status = "okay"; 169 status = "okay";
93}; 170};
@@ -125,9 +202,9 @@
125 202
126&reg_dcdc1 { 203&reg_dcdc1 {
127 regulator-always-on; 204 regulator-always-on;
128 regulator-min-microvolt = <3000000>; 205 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3000000>; 206 regulator-max-microvolt = <3300000>;
130 regulator-name = "vcc-3v"; 207 regulator-name = "vcc-3v3";
131}; 208};
132 209
133&reg_dcdc2 { 210&reg_dcdc2 {
@@ -195,9 +272,13 @@
195 regulator-name = "vcc-rtc"; 272 regulator-name = "vcc-rtc";
196}; 273};
197 274
275&simplefb_hdmi {
276 vcc-hdmi-supply = <&reg_dldo1>;
277};
278
198&uart0 { 279&uart0 {
199 pinctrl-names = "default"; 280 pinctrl-names = "default";
200 pinctrl-0 = <&uart0_pins_a>; 281 pinctrl-0 = <&uart0_pb_pins>;
201 status = "okay"; 282 status = "okay";
202}; 283};
203 284
diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts
index 3b3081b10e..f7a4bccaa5 100644
--- a/arch/arm/dts/sun50i-a64-olinuxino.dts
+++ b/arch/arm/dts/sun50i-a64-olinuxino.dts
@@ -51,6 +51,7 @@
51 compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; 51 compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
52 52
53 aliases { 53 aliases {
54 ethernet0 = &emac;
54 serial0 = &uart0; 55 serial0 = &uart0;
55 }; 56 };
56 57
@@ -58,12 +59,74 @@
58 stdout-path = "serial0:115200n8"; 59 stdout-path = "serial0:115200n8";
59 }; 60 };
60 61
62 hdmi-connector {
63 compatible = "hdmi-connector";
64 type = "a";
65
66 port {
67 hdmi_con_in: endpoint {
68 remote-endpoint = <&hdmi_out_con>;
69 };
70 };
71 };
72
73 reg_usb1_vbus: usb1-vbus {
74 compatible = "regulator-fixed";
75 regulator-name = "usb1-vbus";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
78 regulator-boot-on;
79 enable-active-high;
80 gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
81 status = "okay";
82 };
83
61 wifi_pwrseq: wifi_pwrseq { 84 wifi_pwrseq: wifi_pwrseq {
62 compatible = "mmc-pwrseq-simple"; 85 compatible = "mmc-pwrseq-simple";
63 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ 86 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
64 }; 87 };
65}; 88};
66 89
90&de {
91 status = "okay";
92};
93
94&ehci0 {
95 status = "okay";
96};
97
98&ehci1 {
99 status = "okay";
100};
101
102&emac {
103 pinctrl-names = "default";
104 pinctrl-0 = <&rgmii_pins>;
105 phy-mode = "rgmii";
106 phy-handle = <&ext_rgmii_phy>;
107 phy-supply = <&reg_dcdc1>;
108 allwinner,tx-delay-ps = <600>;
109 status = "okay";
110};
111
112&hdmi {
113 hvcc-supply = <&reg_dldo1>;
114 status = "okay";
115};
116
117&hdmi_out {
118 hdmi_out_con: endpoint {
119 remote-endpoint = <&hdmi_con_in>;
120 };
121};
122
123&mdio {
124 ext_rgmii_phy: ethernet-phy@1 {
125 compatible = "ethernet-phy-ieee802.3-c22";
126 reg = <1>;
127 };
128};
129
67&mmc0 { 130&mmc0 {
68 pinctrl-names = "default"; 131 pinctrl-names = "default";
69 pinctrl-0 = <&mmc0_pins>; 132 pinctrl-0 = <&mmc0_pins>;
@@ -92,6 +155,14 @@
92 }; 155 };
93}; 156};
94 157
158&ohci0 {
159 status = "okay";
160};
161
162&ohci1 {
163 status = "okay";
164};
165
95&r_rsb { 166&r_rsb {
96 status = "okay"; 167 status = "okay";
97 168
@@ -100,6 +171,7 @@
100 reg = <0x3a3>; 171 reg = <0x3a3>;
101 interrupt-parent = <&r_intc>; 172 interrupt-parent = <&r_intc>;
102 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 173 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
174 x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
103 }; 175 };
104}; 176};
105 177
@@ -142,10 +214,14 @@
142 214
143/* DCDC3 is polyphased with DCDC2 */ 215/* DCDC3 is polyphased with DCDC2 */
144 216
217/*
218 * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
219 * 1.35V that the PMIC can drive.
220 */
145&reg_dcdc5 { 221&reg_dcdc5 {
146 regulator-always-on; 222 regulator-always-on;
147 regulator-min-microvolt = <1500000>; 223 regulator-min-microvolt = <1360000>;
148 regulator-max-microvolt = <1500000>; 224 regulator-max-microvolt = <1360000>;
149 regulator-name = "vcc-ddr3"; 225 regulator-name = "vcc-ddr3";
150}; 226};
151 227
@@ -180,6 +256,11 @@
180 regulator-name = "vcc-wifi-io"; 256 regulator-name = "vcc-wifi-io";
181}; 257};
182 258
259&reg_drivevbus {
260 regulator-name = "usb0-vbus";
261 status = "okay";
262};
263
183&reg_eldo1 { 264&reg_eldo1 {
184 regulator-min-microvolt = <1800000>; 265 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <1800000>; 266 regulator-max-microvolt = <1800000>;
@@ -214,8 +295,24 @@
214 regulator-name = "vcc-rtc"; 295 regulator-name = "vcc-rtc";
215}; 296};
216 297
298&simplefb_hdmi {
299 vcc-hdmi-supply = <&reg_dldo1>;
300};
301
217&uart0 { 302&uart0 {
218 pinctrl-names = "default"; 303 pinctrl-names = "default";
219 pinctrl-0 = <&uart0_pins_a>; 304 pinctrl-0 = <&uart0_pb_pins>;
305 status = "okay";
306};
307
308&usb_otg {
309 dr_mode = "otg";
310 status = "okay";
311};
312
313&usbphy {
220 status = "okay"; 314 status = "okay";
315 usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
316 usb0_vbus-supply = <&reg_drivevbus>;
317 usb1_vbus-supply = <&reg_usb1_vbus>;
221}; 318};
diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts
index bf42690a33..b0c64f7579 100644
--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts
+++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> 2 * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
3 * Copyright (C) 2017-2018 Samuel Holland <samuel@sholland.org>
3 * 4 *
4 * This file is dual-licensed: you can use it either under the terms 5 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 6 * of the GPL or the X11 license, at your option. Note that this dual
@@ -51,23 +52,127 @@
51 compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64"; 52 compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
52 53
53 aliases { 54 aliases {
55 ethernet0 = &emac;
54 serial0 = &uart0; 56 serial0 = &uart0;
57 serial1 = &uart1;
58 serial2 = &uart2;
59 serial3 = &uart3;
60 serial4 = &uart4;
55 }; 61 };
56 62
57 chosen { 63 chosen {
58 stdout-path = "serial0:115200n8"; 64 stdout-path = "serial0:115200n8";
59 }; 65 };
66
67 hdmi-connector {
68 compatible = "hdmi-connector";
69 type = "a";
70
71 port {
72 hdmi_con_in: endpoint {
73 remote-endpoint = <&hdmi_out_con>;
74 };
75 };
76 };
77
78 leds {
79 compatible = "gpio-leds";
80
81 status {
82 label = "orangepi:green:status";
83 gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
84 };
85 };
86
87 reg_gmac_3v3: gmac-3v3 {
88 compatible = "regulator-fixed";
89 regulator-name = "gmac-3v3";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-boot-on;
93 enable-active-high;
94 gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */
95 status = "okay";
96 };
97
98 reg_usb1_vbus: usb1-vbus {
99 compatible = "regulator-fixed";
100 regulator-name = "usb1-vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-boot-on;
104 enable-active-high;
105 gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */
106 status = "okay";
107 };
108
109 wifi_pwrseq: wifi_pwrseq {
110 compatible = "mmc-pwrseq-simple";
111 reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
112 };
113};
114
115&de {
116 status = "okay";
117};
118
119&ehci0 {
120 status = "okay";
60}; 121};
61 122
62&ehci1 { 123&ehci1 {
63 status = "okay"; 124 status = "okay";
64}; 125};
65 126
127&emac {
128 pinctrl-names = "default";
129 pinctrl-0 = <&rgmii_pins>;
130 phy-mode = "rgmii";
131 phy-handle = <&ext_rgmii_phy>;
132 phy-supply = <&reg_gmac_3v3>;
133 status = "okay";
134};
135
136&hdmi {
137 hvcc-supply = <&reg_dldo1>;
138 status = "okay";
139};
140
141&hdmi_out {
142 hdmi_out_con: endpoint {
143 remote-endpoint = <&hdmi_con_in>;
144 };
145};
146
147&mdio {
148 ext_rgmii_phy: ethernet-phy@1 {
149 compatible = "ethernet-phy-ieee802.3-c22";
150 reg = <1>;
151 };
152};
153
66&mmc0 { 154&mmc0 {
67 pinctrl-names = "default"; 155 pinctrl-names = "default";
68 pinctrl-0 = <&mmc0_pins>; 156 pinctrl-0 = <&mmc0_pins>;
69 vmmc-supply = <&reg_dcdc1>; 157 vmmc-supply = <&reg_dcdc1>;
70 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 158 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
159 disable-wp;
160 bus-width = <4>;
161 status = "okay";
162};
163
164&mmc1 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&mmc1_pins>;
167 vmmc-supply = <&reg_dldo2>;
168 vqmmc-supply = <&reg_dldo4>;
169 mmc-pwrseq = <&wifi_pwrseq>;
170 bus-width = <4>;
171 non-removable;
172 status = "okay";
173};
174
175&ohci0 {
71 status = "okay"; 176 status = "okay";
72}; 177};
73 178
@@ -89,9 +194,8 @@
89#include "axp803.dtsi" 194#include "axp803.dtsi"
90 195
91&reg_aldo1 { 196&reg_aldo1 {
92 regulator-always-on; 197 regulator-min-microvolt = <2800000>;
93 regulator-min-microvolt = <1800000>; 198 regulator-max-microvolt = <2800000>;
94 regulator-max-microvolt = <3300000>;
95 regulator-name = "afvcc-csi"; 199 regulator-name = "afvcc-csi";
96}; 200};
97 201
@@ -163,12 +267,23 @@
163 regulator-name = "vcc-wifi-io"; 267 regulator-name = "vcc-wifi-io";
164}; 268};
165 269
270&reg_drivevbus {
271 regulator-name = "usb0-vbus";
272 status = "okay";
273};
274
166&reg_eldo1 { 275&reg_eldo1 {
167 regulator-min-microvolt = <1800000>; 276 regulator-min-microvolt = <1800000>;
168 regulator-max-microvolt = <1800000>; 277 regulator-max-microvolt = <1800000>;
169 regulator-name = "cpvdd"; 278 regulator-name = "cpvdd";
170}; 279};
171 280
281&reg_eldo3 {
282 regulator-min-microvolt = <1500000>;
283 regulator-max-microvolt = <1800000>;
284 regulator-name = "dvdd-csi";
285};
286
172&reg_fldo1 { 287&reg_fldo1 {
173 regulator-min-microvolt = <1200000>; 288 regulator-min-microvolt = <1200000>;
174 regulator-max-microvolt = <1200000>; 289 regulator-max-microvolt = <1200000>;
@@ -191,13 +306,65 @@
191 regulator-name = "vcc-rtc"; 306 regulator-name = "vcc-rtc";
192}; 307};
193 308
309&simplefb_hdmi {
310 vcc-hdmi-supply = <&reg_dldo1>;
311};
312
313&spi0 {
314 status = "okay";
315
316 spi-flash@0 {
317 compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
318 reg = <0>;
319 spi-max-frequency = <80000000>;
320 m25p,fast-read;
321 status = "okay";
322 };
323};
324
325/* On debug connector */
194&uart0 { 326&uart0 {
195 pinctrl-names = "default"; 327 pinctrl-names = "default";
196 pinctrl-0 = <&uart0_pins_a>; 328 pinctrl-0 = <&uart0_pb_pins>;
197 status = "okay"; 329 status = "okay";
198}; 330};
199 331
200&usbphy { 332/* Bluetooth */
333&uart1 {
334 pinctrl-names = "default";
335 pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
336 status = "okay";
337};
338
339/* On Pi-2 connector, RTS/CTS optional */
340&uart2 {
341 pinctrl-names = "default";
342 pinctrl-0 = <&uart2_pins>;
343 status = "disabled";
344};
345
346/* On Pi-2 connector, RTS/CTS optional */
347&uart3 {
348 pinctrl-names = "default";
349 pinctrl-0 = <&uart3_pins>;
350 status = "disabled";
351};
352
353/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
354&uart4 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&uart4_pins>;
357 status = "disabled";
358};
359
360&usb_otg {
361 dr_mode = "otg";
201 status = "okay"; 362 status = "okay";
202}; 363};
203 364
365&usbphy {
366 usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
367 usb0_vbus-supply = <&reg_drivevbus>;
368 usb1_vbus-supply = <&reg_usb1_vbus>;
369 status = "okay";
370};
diff --git a/arch/arm/dts/sun50i-a64-pine64-lts.dts b/arch/arm/dts/sun50i-a64-pine64-lts.dts
new file mode 100644
index 0000000000..72d6961dc3
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pine64-lts.dts
@@ -0,0 +1,13 @@
1/*
2 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 *
4 * Copyright (c) 2018 ARM Ltd.
5 */
6
7#include "sun50i-a64-sopine-baseboard.dts"
8
9/ {
10 model = "Pine64 LTS";
11 compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",
12 "allwinner,sun50i-a64";
13};
diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts
index a75825798a..c077b6c1f4 100644
--- a/arch/arm/dts/sun50i-a64-pine64.dts
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -62,6 +62,21 @@
62 chosen { 62 chosen {
63 stdout-path = "serial0:115200n8"; 63 stdout-path = "serial0:115200n8";
64 }; 64 };
65
66 hdmi-connector {
67 compatible = "hdmi-connector";
68 type = "a";
69
70 port {
71 hdmi_con_in: endpoint {
72 remote-endpoint = <&hdmi_out_con>;
73 };
74 };
75 };
76};
77
78&de {
79 status = "okay";
65}; 80};
66 81
67&ehci0 { 82&ehci0 {
@@ -82,6 +97,17 @@
82 97
83}; 98};
84 99
100&hdmi {
101 hvcc-supply = <&reg_dldo1>;
102 status = "okay";
103};
104
105&hdmi_out {
106 hdmi_out_con: endpoint {
107 remote-endpoint = <&hdmi_con_in>;
108 };
109};
110
85&i2c1 { 111&i2c1 {
86 pinctrl-names = "default"; 112 pinctrl-names = "default";
87 pinctrl-0 = <&i2c1_pins>; 113 pinctrl-0 = <&i2c1_pins>;
@@ -229,6 +255,10 @@
229 regulator-name = "vcc-rtc"; 255 regulator-name = "vcc-rtc";
230}; 256};
231 257
258&simplefb_hdmi {
259 vcc-hdmi-supply = <&reg_dldo1>;
260};
261
232/* On Euler connector */ 262/* On Euler connector */
233&spdif { 263&spdif {
234 status = "disabled"; 264 status = "disabled";
@@ -237,7 +267,7 @@
237/* On Exp and Euler connectors */ 267/* On Exp and Euler connectors */
238&uart0 { 268&uart0 {
239 pinctrl-names = "default"; 269 pinctrl-names = "default";
240 pinctrl-0 = <&uart0_pins_a>; 270 pinctrl-0 = <&uart0_pb_pins>;
241 status = "okay"; 271 status = "okay";
242}; 272};
243 273
diff --git a/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi
new file mode 100644
index 0000000000..a99b7171d0
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi
@@ -0,0 +1,15 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
4 *
5 */
6
7/* The ANX6345 eDP-bridge is on r_i2c */
8&r_i2c {
9 anx6345: edp-bridge@38 {
10 compatible = "analogix,anx6345";
11 reg = <0x38>;
12 reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
13 status = "okay";
14 };
15};
diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts
new file mode 100644
index 0000000000..ec537c5297
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pinebook.dts
@@ -0,0 +1,294 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
4 * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
5 *
6 */
7
8/dts-v1/;
9
10#include "sun50i-a64.dtsi"
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pwm/pwm.h>
15
16/ {
17 model = "Pinebook";
18 compatible = "pine64,pinebook", "allwinner,sun50i-a64";
19
20 aliases {
21 serial0 = &uart0;
22 ethernet0 = &rtl8723cs;
23 };
24
25 vdd_bl: regulator@0 {
26 compatible = "regulator-fixed";
27 regulator-name = "bl-3v3";
28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>;
30 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
31 enable-active-high;
32 };
33
34 backlight: backlight {
35 compatible = "pwm-backlight";
36 pwms = <&pwm 0 50000 0>;
37 brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
38 default-brightness-level = <2>;
39 enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
40 power-supply = <&vdd_bl>;
41 };
42
43 chosen {
44 stdout-path = "serial0:115200n8";
45
46 framebuffer-lcd {
47 panel-supply = <&reg_dc1sw>;
48 dvdd25-supply = <&reg_dldo2>;
49 dvdd12-supply = <&reg_fldo1>;
50 };
51 };
52
53 gpio_keys {
54 compatible = "gpio-keys";
55
56 lid_switch {
57 label = "Lid Switch";
58 gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
59 linux,input-type = <EV_SW>;
60 linux,code = <SW_LID>;
61 linux,can-disable;
62 wakeup-source;
63 };
64 };
65
66 reg_vcc3v3: vcc3v3 {
67 compatible = "regulator-fixed";
68 regulator-name = "vcc3v3";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 };
72
73 wifi_pwrseq: wifi_pwrseq {
74 compatible = "mmc-pwrseq-simple";
75 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
76 };
77};
78
79&ehci0 {
80 phys = <&usbphy 0>;
81 phy-names = "usb";
82 status = "okay";
83};
84
85&ehci1 {
86 status = "okay";
87};
88
89&mmc0 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&mmc0_pins>;
92 vmmc-supply = <&reg_dcdc1>;
93 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
94 disable-wp;
95 bus-width = <4>;
96 status = "okay";
97};
98
99&mmc1 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&mmc1_pins>;
102 vmmc-supply = <&reg_dldo4>;
103 vqmmc-supply = <&reg_eldo1>;
104 mmc-pwrseq = <&wifi_pwrseq>;
105 bus-width = <4>;
106 non-removable;
107 status = "okay";
108
109 rtl8723cs: wifi@1 {
110 reg = <1>;
111 };
112};
113
114&mmc2 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
117 vmmc-supply = <&reg_dcdc1>;
118 vqmmc-supply = <&reg_eldo1>;
119 bus-width = <8>;
120 non-removable;
121 cap-mmc-hw-reset;
122 mmc-hs200-1_8v;
123 status = "okay";
124};
125
126&ohci0 {
127 phys = <&usbphy 0>;
128 phy-names = "usb";
129 status = "okay";
130};
131
132&ohci1 {
133 status = "okay";
134};
135
136&pwm {
137 status = "okay";
138};
139
140&r_rsb {
141 status = "okay";
142
143 axp803: pmic@3a3 {
144 compatible = "x-powers,axp803";
145 reg = <0x3a3>;
146 interrupt-parent = <&r_intc>;
147 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
148 };
149};
150
151/* The ANX6345 eDP-bridge is on r_i2c */
152&r_i2c {
153 clock-frequency = <100000>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&r_i2c_pl89_pins>;
156 status = "okay";
157};
158
159#include "axp803.dtsi"
160
161&reg_aldo1 {
162 regulator-min-microvolt = <2800000>;
163 regulator-max-microvolt = <2800000>;
164 regulator-name = "vcc-csi";
165};
166
167&reg_aldo2 {
168 regulator-always-on;
169 regulator-min-microvolt = <1800000>;
170 regulator-max-microvolt = <3300000>;
171 regulator-name = "vcc-pl";
172};
173
174&reg_aldo3 {
175 regulator-always-on;
176 regulator-min-microvolt = <2700000>;
177 regulator-max-microvolt = <3300000>;
178 regulator-name = "vcc-pll-avcc";
179};
180
181&reg_dc1sw {
182 regulator-name = "vcc-lcd";
183};
184
185&reg_dcdc1 {
186 regulator-always-on;
187 regulator-min-microvolt = <3300000>;
188 regulator-max-microvolt = <3300000>;
189 regulator-name = "vcc-3v3";
190};
191
192&reg_dcdc2 {
193 regulator-always-on;
194 regulator-min-microvolt = <1000000>;
195 regulator-max-microvolt = <1300000>;
196 regulator-name = "vdd-cpux";
197};
198
199/* DCDC3 is polyphased with DCDC2 */
200
201&reg_dcdc5 {
202 regulator-always-on;
203 regulator-min-microvolt = <1200000>;
204 regulator-max-microvolt = <1200000>;
205 regulator-name = "vcc-dram";
206};
207
208&reg_dcdc6 {
209 regulator-always-on;
210 regulator-min-microvolt = <1100000>;
211 regulator-max-microvolt = <1100000>;
212 regulator-name = "vdd-sys";
213};
214
215&reg_dldo1 {
216 regulator-min-microvolt = <3300000>;
217 regulator-max-microvolt = <3300000>;
218 regulator-name = "vcc-hdmi";
219};
220
221&reg_dldo2 {
222 regulator-min-microvolt = <2500000>;
223 regulator-max-microvolt = <2500000>;
224 regulator-name = "vcc-edp";
225};
226
227&reg_dldo3 {
228 regulator-min-microvolt = <3300000>;
229 regulator-max-microvolt = <3300000>;
230 regulator-name = "avdd-csi";
231};
232
233&reg_dldo4 {
234 regulator-min-microvolt = <3300000>;
235 regulator-max-microvolt = <3300000>;
236 regulator-name = "vcc-wifi";
237};
238
239&reg_eldo1 {
240 regulator-always-on;
241 regulator-min-microvolt = <1800000>;
242 regulator-max-microvolt = <1800000>;
243 regulator-name = "cpvdd";
244};
245
246&reg_eldo3 {
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <1800000>;
249 regulator-name = "vdd-1v8-csi";
250};
251
252&reg_fldo1 {
253 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1200000>;
255 regulator-name = "vcc-1v2-hsic";
256};
257
258&reg_fldo2 {
259 regulator-always-on;
260 regulator-min-microvolt = <1100000>;
261 regulator-max-microvolt = <1100000>;
262 regulator-name = "vdd-cpus";
263};
264
265&reg_ldo_io0 {
266 regulator-min-microvolt = <3300000>;
267 regulator-max-microvolt = <3300000>;
268 regulator-name = "vcc-usb";
269 status = "okay";
270};
271
272&reg_rtc_ldo {
273 regulator-name = "vcc-rtc";
274};
275
276&simplefb_hdmi {
277 vcc-hdmi-supply = <&reg_dldo1>;
278};
279
280&uart0 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart0_pb_pins>;
283 status = "okay";
284};
285
286&usb_otg {
287 dr_mode = "host";
288};
289
290&usbphy {
291 usb0_vbus-supply = <&reg_ldo_io0>;
292 usb1_vbus-supply = <&reg_ldo_io0>;
293 status = "okay";
294};
diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
index abe179de35..53fcc9098d 100644
--- a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
@@ -61,6 +61,17 @@
61 stdout-path = "serial0:115200n8"; 61 stdout-path = "serial0:115200n8";
62 }; 62 };
63 63
64 hdmi-connector {
65 compatible = "hdmi-connector";
66 type = "a";
67
68 port {
69 hdmi_con_in: endpoint {
70 remote-endpoint = <&hdmi_out_con>;
71 };
72 };
73 };
74
64 reg_vcc1v8: vcc1v8 { 75 reg_vcc1v8: vcc1v8 {
65 compatible = "regulator-fixed"; 76 compatible = "regulator-fixed";
66 regulator-name = "vcc1v8"; 77 regulator-name = "vcc1v8";
@@ -69,6 +80,10 @@
69 }; 80 };
70}; 81};
71 82
83&de {
84 status = "okay";
85};
86
72&ehci0 { 87&ehci0 {
73 status = "okay"; 88 status = "okay";
74}; 89};
@@ -86,6 +101,17 @@
86 status = "okay"; 101 status = "okay";
87}; 102};
88 103
104&hdmi {
105 hvcc-supply = <&reg_dldo1>;
106 status = "okay";
107};
108
109&hdmi_out {
110 hdmi_out_con: endpoint {
111 remote-endpoint = <&hdmi_con_in>;
112 };
113};
114
89&mdio { 115&mdio {
90 ext_rgmii_phy: ethernet-phy@1 { 116 ext_rgmii_phy: ethernet-phy@1 {
91 compatible = "ethernet-phy-ieee802.3-c22"; 117 compatible = "ethernet-phy-ieee802.3-c22";
@@ -134,9 +160,13 @@
134 regulator-name = "vcc-wifi"; 160 regulator-name = "vcc-wifi";
135}; 161};
136 162
163&simplefb_hdmi {
164 vcc-hdmi-supply = <&reg_dldo1>;
165};
166
137&uart0 { 167&uart0 {
138 pinctrl-names = "default"; 168 pinctrl-names = "default";
139 pinctrl-0 = <&uart0_pins_a>; 169 pinctrl-0 = <&uart0_pb_pins>;
140 status = "okay"; 170 status = "okay";
141}; 171};
142 172
diff --git a/arch/arm/dts/sun50i-a64-sopine.dtsi b/arch/arm/dts/sun50i-a64-sopine.dtsi
index 43418bd881..6723b8695e 100644
--- a/arch/arm/dts/sun50i-a64-sopine.dtsi
+++ b/arch/arm/dts/sun50i-a64-sopine.dtsi
@@ -45,6 +45,8 @@
45 45
46#include "sun50i-a64.dtsi" 46#include "sun50i-a64.dtsi"
47 47
48#include <dt-bindings/gpio/gpio.h>
49
48&mmc0 { 50&mmc0 {
49 pinctrl-names = "default"; 51 pinctrl-names = "default";
50 pinctrl-0 = <&mmc0_pins>; 52 pinctrl-0 = <&mmc0_pins>;
@@ -52,6 +54,7 @@
52 non-removable; 54 non-removable;
53 disable-wp; 55 disable-wp;
54 bus-width = <4>; 56 bus-width = <4>;
57 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
55 status = "okay"; 58 status = "okay";
56}; 59};
57 60
@@ -66,6 +69,18 @@
66 }; 69 };
67}; 70};
68 71
72&spi0 {
73 status = "okay";
74
75 flash@0 {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "jedec,spi-nor";
79 reg = <0>;
80 spi-max-frequency = <40000000>;
81 };
82};
83
69#include "axp803.dtsi" 84#include "axp803.dtsi"
70 85
71&reg_aldo2 { 86&reg_aldo2 {
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 7a083637c4..ff41abc96a 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -43,9 +43,12 @@
43 */ 43 */
44 44
45#include <dt-bindings/clock/sun50i-a64-ccu.h> 45#include <dt-bindings/clock/sun50i-a64-ccu.h>
46#include <dt-bindings/clock/sun8i-de2.h>
46#include <dt-bindings/clock/sun8i-r-ccu.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h>
47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/reset/sun50i-a64-ccu.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h>
50#include <dt-bindings/reset/sun8i-de2.h>
51#include <dt-bindings/reset/sun8i-r-ccu.h>
49 52
50/ { 53/ {
51 interrupt-parent = <&gic>; 54 interrupt-parent = <&gic>;
@@ -57,17 +60,21 @@
57 #size-cells = <1>; 60 #size-cells = <1>;
58 ranges; 61 ranges;
59 62
60/*
61 * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
62 * However there is no support for this clock on A64 yet, so we depend
63 * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
64 */
65 simplefb_lcd: framebuffer-lcd { 63 simplefb_lcd: framebuffer-lcd {
66 compatible = "allwinner,simple-framebuffer", 64 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer"; 65 "simple-framebuffer";
68 allwinner,pipeline = "mixer0-lcd0"; 66 allwinner,pipeline = "mixer0-lcd0";
69 clocks = <&ccu CLK_TCON0>, 67 clocks = <&ccu CLK_TCON0>,
70 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; 68 <&display_clocks CLK_MIXER0>;
69 status = "disabled";
70 };
71
72 simplefb_hdmi: framebuffer-hdmi {
73 compatible = "allwinner,simple-framebuffer",
74 "simple-framebuffer";
75 allwinner,pipeline = "mixer1-lcd1-hdmi";
76 clocks = <&display_clocks CLK_MIXER1>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
71 status = "disabled"; 78 status = "disabled";
72 }; 79 };
73 }; 80 };
@@ -81,6 +88,7 @@
81 device_type = "cpu"; 88 device_type = "cpu";
82 reg = <0>; 89 reg = <0>;
83 enable-method = "psci"; 90 enable-method = "psci";
91 next-level-cache = <&L2>;
84 }; 92 };
85 93
86 cpu1: cpu@1 { 94 cpu1: cpu@1 {
@@ -88,6 +96,7 @@
88 device_type = "cpu"; 96 device_type = "cpu";
89 reg = <1>; 97 reg = <1>;
90 enable-method = "psci"; 98 enable-method = "psci";
99 next-level-cache = <&L2>;
91 }; 100 };
92 101
93 cpu2: cpu@2 { 102 cpu2: cpu@2 {
@@ -95,6 +104,7 @@
95 device_type = "cpu"; 104 device_type = "cpu";
96 reg = <2>; 105 reg = <2>;
97 enable-method = "psci"; 106 enable-method = "psci";
107 next-level-cache = <&L2>;
98 }; 108 };
99 109
100 cpu3: cpu@3 { 110 cpu3: cpu@3 {
@@ -102,7 +112,20 @@
102 device_type = "cpu"; 112 device_type = "cpu";
103 reg = <3>; 113 reg = <3>;
104 enable-method = "psci"; 114 enable-method = "psci";
115 next-level-cache = <&L2>;
105 }; 116 };
117
118 L2: l2-cache {
119 compatible = "cache";
120 cache-level = <2>;
121 };
122 };
123
124 de: display-engine {
125 compatible = "allwinner,sun50i-a64-display-engine";
126 allwinner,pipelines = <&mixer0>,
127 <&mixer1>;
128 status = "disabled";
106 }; 129 };
107 130
108 osc24M: osc24M_clk { 131 osc24M: osc24M_clk {
@@ -168,10 +191,93 @@
168 #size-cells = <1>; 191 #size-cells = <1>;
169 ranges; 192 ranges;
170 193
194 de2@1000000 {
195 compatible = "allwinner,sun50i-a64-de2";
196 reg = <0x1000000 0x400000>;
197 allwinner,sram = <&de2_sram 1>;
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges = <0 0x1000000 0x400000>;
201
202 display_clocks: clock@0 {
203 compatible = "allwinner,sun50i-a64-de2-clk";
204 reg = <0x0 0x100000>;
205 clocks = <&ccu CLK_DE>,
206 <&ccu CLK_BUS_DE>;
207 clock-names = "mod",
208 "bus";
209 resets = <&ccu RST_BUS_DE>;
210 #clock-cells = <1>;
211 #reset-cells = <1>;
212 };
213
214 mixer0: mixer@100000 {
215 compatible = "allwinner,sun50i-a64-de2-mixer-0";
216 reg = <0x100000 0x100000>;
217 clocks = <&display_clocks CLK_BUS_MIXER0>,
218 <&display_clocks CLK_MIXER0>;
219 clock-names = "bus",
220 "mod";
221 resets = <&display_clocks RST_MIXER0>;
222
223 ports {
224 #address-cells = <1>;
225 #size-cells = <0>;
226
227 mixer0_out: port@1 {
228 reg = <1>;
229
230 mixer0_out_tcon0: endpoint {
231 remote-endpoint = <&tcon0_in_mixer0>;
232 };
233 };
234 };
235 };
236
237 mixer1: mixer@200000 {
238 compatible = "allwinner,sun50i-a64-de2-mixer-1";
239 reg = <0x200000 0x100000>;
240 clocks = <&display_clocks CLK_BUS_MIXER1>,
241 <&display_clocks CLK_MIXER1>;
242 clock-names = "bus",
243 "mod";
244 resets = <&display_clocks RST_MIXER1>;
245
246 ports {
247 #address-cells = <1>;
248 #size-cells = <0>;
249
250 mixer1_out: port@1 {
251 reg = <1>;
252
253 mixer1_out_tcon1: endpoint {
254 remote-endpoint = <&tcon1_in_mixer1>;
255 };
256 };
257 };
258 };
259 };
260
171 syscon: syscon@1c00000 { 261 syscon: syscon@1c00000 {
172 compatible = "allwinner,sun50i-a64-system-controller", 262 compatible = "allwinner,sun50i-a64-system-control",
173 "syscon"; 263 "syscon";
174 reg = <0x01c00000 0x1000>; 264 reg = <0x01c00000 0x1000>;
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges;
268
269 sram_c: sram@18000 {
270 compatible = "mmio-sram";
271 reg = <0x00018000 0x28000>;
272 #address-cells = <1>;
273 #size-cells = <1>;
274 ranges = <0 0x00018000 0x28000>;
275
276 de2_sram: sram-section@0 {
277 compatible = "allwinner,sun50i-a64-sram-c";
278 reg = <0x0000 0x28000>;
279 };
280 };
175 }; 281 };
176 282
177 dma: dma-controller@1c02000 { 283 dma: dma-controller@1c02000 {
@@ -185,6 +291,75 @@
185 #dma-cells = <1>; 291 #dma-cells = <1>;
186 }; 292 };
187 293
294 tcon0: lcd-controller@1c0c000 {
295 compatible = "allwinner,sun50i-a64-tcon-lcd",
296 "allwinner,sun8i-a83t-tcon-lcd";
297 reg = <0x01c0c000 0x1000>;
298 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
300 clock-names = "ahb", "tcon-ch0";
301 clock-output-names = "tcon-pixel-clock";
302 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
303 reset-names = "lcd", "lvds";
304
305 ports {
306 #address-cells = <1>;
307 #size-cells = <0>;
308
309 tcon0_in: port@0 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <0>;
313
314 tcon0_in_mixer0: endpoint@0 {
315 reg = <0>;
316 remote-endpoint = <&mixer0_out_tcon0>;
317 };
318 };
319
320 tcon0_out: port@1 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <1>;
324 };
325 };
326 };
327
328 tcon1: lcd-controller@1c0d000 {
329 compatible = "allwinner,sun50i-a64-tcon-tv",
330 "allwinner,sun8i-a83t-tcon-tv";
331 reg = <0x01c0d000 0x1000>;
332 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
334 clock-names = "ahb", "tcon-ch1";
335 resets = <&ccu RST_BUS_TCON1>;
336 reset-names = "lcd";
337
338 ports {
339 #address-cells = <1>;
340 #size-cells = <0>;
341
342 tcon1_in: port@0 {
343 reg = <0>;
344
345 tcon1_in_mixer1: endpoint {
346 remote-endpoint = <&mixer1_out_tcon1>;
347 };
348 };
349
350 tcon1_out: port@1 {
351 #address-cells = <1>;
352 #size-cells = <0>;
353 reg = <1>;
354
355 tcon1_out_hdmi: endpoint@1 {
356 reg = <1>;
357 remote-endpoint = <&hdmi_in_tcon1>;
358 };
359 };
360 };
361 };
362
188 mmc0: mmc@1c0f000 { 363 mmc0: mmc@1c0f000 {
189 compatible = "allwinner,sun50i-a64-mmc"; 364 compatible = "allwinner,sun50i-a64-mmc";
190 reg = <0x01c0f000 0x1000>; 365 reg = <0x01c0f000 0x1000>;
@@ -227,6 +402,11 @@
227 #size-cells = <0>; 402 #size-cells = <0>;
228 }; 403 };
229 404
405 sid: eeprom@1c14000 {
406 compatible = "allwinner,sun50i-a64-sid";
407 reg = <0x1c14000 0x400>;
408 };
409
230 usb_otg: usb@1c19000 { 410 usb_otg: usb@1c19000 {
231 compatible = "allwinner,sun8i-a33-musb"; 411 compatible = "allwinner,sun8i-a33-musb";
232 reg = <0x01c19000 0x0400>; 412 reg = <0x01c19000 0x0400>;
@@ -356,7 +536,7 @@
356 }; 536 };
357 537
358 mmc2_pins: mmc2-pins { 538 mmc2_pins: mmc2-pins {
359 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 539 pins = "PC5", "PC6", "PC8", "PC9",
360 "PC10","PC11", "PC12", "PC13", 540 "PC10","PC11", "PC12", "PC13",
361 "PC14", "PC15", "PC16"; 541 "PC14", "PC15", "PC16";
362 function = "mmc2"; 542 function = "mmc2";
@@ -364,6 +544,18 @@
364 bias-pull-up; 544 bias-pull-up;
365 }; 545 };
366 546
547 mmc2_ds_pin: mmc2-ds-pin {
548 pins = "PC1";
549 function = "mmc2";
550 drive-strength = <30>;
551 bias-pull-up;
552 };
553
554 pwm_pin: pwm_pin {
555 pins = "PD22";
556 function = "pwm";
557 };
558
367 rmii_pins: rmii_pins { 559 rmii_pins: rmii_pins {
368 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 560 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
369 "PD18", "PD19", "PD20", "PD22", "PD23"; 561 "PD18", "PD19", "PD20", "PD22", "PD23";
@@ -394,7 +586,7 @@
394 function = "spi1"; 586 function = "spi1";
395 }; 587 };
396 588
397 uart0_pins_a: uart0 { 589 uart0_pb_pins: uart0-pb-pins {
398 pins = "PB8", "PB9"; 590 pins = "PB8", "PB9";
399 function = "uart0"; 591 function = "uart0";
400 }; 592 };
@@ -474,15 +666,6 @@
474 status = "disabled"; 666 status = "disabled";
475 }; 667 };
476 668
477 pwm: pwm@1c21400 {
478 compatible = "allwinner,sun50i-a64-pwm",
479 "allwinner,sun5i-a13-pwm";
480 reg = <0x01c21400 0x8>;
481 clocks = <&osc24M>;
482 #pwm-cells = <3>;
483 status = "disabled";
484 };
485
486 uart0: serial@1c28000 { 669 uart0: serial@1c28000 {
487 compatible = "snps,dw-apb-uart"; 670 compatible = "snps,dw-apb-uart";
488 reg = <0x01c28000 0x400>; 671 reg = <0x01c28000 0x400>;
@@ -617,8 +800,6 @@
617 clocks = <&ccu CLK_BUS_EMAC>; 800 clocks = <&ccu CLK_BUS_EMAC>;
618 clock-names = "stmmaceth"; 801 clock-names = "stmmaceth";
619 status = "disabled"; 802 status = "disabled";
620 #address-cells = <1>;
621 #size-cells = <0>;
622 803
623 mdio: mdio { 804 mdio: mdio {
624 compatible = "snps,dwmac-mdio"; 805 compatible = "snps,dwmac-mdio";
@@ -638,11 +819,69 @@
638 #interrupt-cells = <3>; 819 #interrupt-cells = <3>;
639 }; 820 };
640 821
822 pwm: pwm@1c21400 {
823 compatible = "allwinner,sun50i-a64-pwm",
824 "allwinner,sun5i-a13-pwm";
825 reg = <0x01c21400 0x400>;
826 clocks = <&osc24M>;
827 pinctrl-names = "default";
828 pinctrl-0 = <&pwm_pin>;
829 #pwm-cells = <3>;
830 status = "disabled";
831 };
832
833 hdmi: hdmi@1ee0000 {
834 compatible = "allwinner,sun50i-a64-dw-hdmi",
835 "allwinner,sun8i-a83t-dw-hdmi";
836 reg = <0x01ee0000 0x10000>;
837 reg-io-width = <1>;
838 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
840 <&ccu CLK_HDMI>;
841 clock-names = "iahb", "isfr", "tmds";
842 resets = <&ccu RST_BUS_HDMI1>;
843 reset-names = "ctrl";
844 phys = <&hdmi_phy>;
845 phy-names = "hdmi-phy";
846 status = "disabled";
847
848 ports {
849 #address-cells = <1>;
850 #size-cells = <0>;
851
852 hdmi_in: port@0 {
853 reg = <0>;
854
855 hdmi_in_tcon1: endpoint {
856 remote-endpoint = <&tcon1_out_hdmi>;
857 };
858 };
859
860 hdmi_out: port@1 {
861 reg = <1>;
862 };
863 };
864 };
865
866 hdmi_phy: hdmi-phy@1ef0000 {
867 compatible = "allwinner,sun50i-a64-hdmi-phy";
868 reg = <0x01ef0000 0x10000>;
869 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
870 <&ccu 7>;
871 clock-names = "bus", "mod", "pll-0";
872 resets = <&ccu RST_BUS_HDMI0>;
873 reset-names = "phy";
874 #phy-cells = <0>;
875 };
876
641 rtc: rtc@1f00000 { 877 rtc: rtc@1f00000 {
642 compatible = "allwinner,sun6i-a31-rtc"; 878 compatible = "allwinner,sun6i-a31-rtc";
643 reg = <0x01f00000 0x54>; 879 reg = <0x01f00000 0x54>;
644 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 880 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 881 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
882 clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
883 clocks = <&osc32k>;
884 #clock-cells = <1>;
646 }; 885 };
647 886
648 r_intc: interrupt-controller@1f00c00 { 887 r_intc: interrupt-controller@1f00c00 {
@@ -664,6 +903,29 @@
664 #reset-cells = <1>; 903 #reset-cells = <1>;
665 }; 904 };
666 905
906 r_i2c: i2c@1f02400 {
907 compatible = "allwinner,sun50i-a64-i2c",
908 "allwinner,sun6i-a31-i2c";
909 reg = <0x01f02400 0x400>;
910 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&r_ccu CLK_APB0_I2C>;
912 resets = <&r_ccu RST_APB0_I2C>;
913 status = "disabled";
914 #address-cells = <1>;
915 #size-cells = <0>;
916 };
917
918 r_pwm: pwm@1f03800 {
919 compatible = "allwinner,sun50i-a64-pwm",
920 "allwinner,sun5i-a13-pwm";
921 reg = <0x01f03800 0x400>;
922 clocks = <&osc24M>;
923 pinctrl-names = "default";
924 pinctrl-0 = <&r_pwm_pin>;
925 #pwm-cells = <3>;
926 status = "disabled";
927 };
928
667 r_pio: pinctrl@1f02c00 { 929 r_pio: pinctrl@1f02c00 {
668 compatible = "allwinner,sun50i-a64-r-pinctrl"; 930 compatible = "allwinner,sun50i-a64-r-pinctrl";
669 reg = <0x01f02c00 0x400>; 931 reg = <0x01f02c00 0x400>;
@@ -675,6 +937,16 @@
675 interrupt-controller; 937 interrupt-controller;
676 #interrupt-cells = <3>; 938 #interrupt-cells = <3>;
677 939
940 r_i2c_pl89_pins: r-i2c-pl89-pins {
941 pins = "PL8", "PL9";
942 function = "s_i2c";
943 };
944
945 r_pwm_pin: pwm {
946 pins = "PL10";
947 function = "s_pwm";
948 };
949
678 r_rsb_pins: rsb { 950 r_rsb_pins: rsb {
679 pins = "PL0", "PL1"; 951 pins = "PL0", "PL1";
680 function = "s_rsb"; 952 function = "s_rsb";
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
index 98862c7c72..3e0d5a9c09 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -207,6 +207,18 @@
207 status = "okay"; 207 status = "okay";
208}; 208};
209 209
210&spi0 {
211 status = "okay";
212
213 flash@0 {
214 #address-cells = <1>;
215 #size-cells = <1>;
216 compatible = "jedec,spi-nor";
217 reg = <0>;
218 spi-max-frequency = <40000000>;
219 };
220};
221
210&uart0 { 222&uart0 {
211 pinctrl-names = "default"; 223 pinctrl-names = "default";
212 pinctrl-0 = <&uart0_pins_a>; 224 pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts
index e79cf3baf4..1238de25a9 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts
@@ -105,7 +105,6 @@
105 }; 105 };
106}; 106};
107 107
108/*
109&spi0 { 108&spi0 {
110 status = "okay"; 109 status = "okay";
111 110
@@ -117,7 +116,6 @@
117 spi-max-frequency = <40000000>; 116 spi-max-frequency = <40000000>;
118 }; 117 };
119}; 118};
120*/
121 119
122&ohci0 { 120&ohci0 {
123 status = "okay"; 121 status = "okay";
diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts
new file mode 100644
index 0000000000..e098a2475f
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts
@@ -0,0 +1,11 @@
1// SPDX-License-Identifier: (GPL-2.0+ or MIT)
2/*
3 * Copyright (C) 2018 Jagan Teki <jagan@openedev.com>
4 */
5
6#include "sun50i-h6-orangepi.dtsi"
7
8/ {
9 model = "OrangePi Lite2";
10 compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
11};
diff --git a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
index 0612c19cd9..12e17567ab 100644
--- a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
+++ b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
@@ -4,147 +4,9 @@
4 * Author: Jagan Teki <jagan@amarulasolutions.com> 4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */ 5 */
6 6
7/dts-v1/; 7#include "sun50i-h6-orangepi.dtsi"
8
9#include "sun50i-h6.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12 8
13/ { 9/ {
14 model = "OrangePi One Plus"; 10 model = "OrangePi One Plus";
15 compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; 11 compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
16
17 aliases {
18 serial0 = &uart0;
19 };
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24};
25
26&mmc0 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_pins>;
29 vmmc-supply = <&reg_cldo1>;
30 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
31 bus-width = <4>;
32 status = "okay";
33};
34
35&r_i2c {
36 status = "okay";
37
38 axp805: pmic@36 {
39 compatible = "x-powers,axp805", "x-powers,axp806";
40 reg = <0x36>;
41 interrupt-parent = <&r_intc>;
42 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 x-powers,self-working-mode;
46
47 regulators {
48 reg_aldo1: aldo1 {
49 regulator-always-on;
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-name = "vcc-pl";
53 };
54
55 reg_aldo2: aldo2 {
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 regulator-name = "vcc-ac200";
59 };
60
61 reg_aldo3: aldo3 {
62 regulator-always-on;
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 regulator-name = "vcc25-dram";
66 };
67
68 reg_bldo1: bldo1 {
69 regulator-always-on;
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <1800000>;
72 regulator-name = "vcc-bias-pll";
73 };
74
75 reg_bldo2: bldo2 {
76 regulator-always-on;
77 regulator-min-microvolt = <1800000>;
78 regulator-max-microvolt = <1800000>;
79 regulator-name = "vcc-efuse-pcie-hdmi-io";
80 };
81
82 reg_bldo3: bldo3 {
83 regulator-always-on;
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
86 regulator-name = "vcc-dcxoio";
87 };
88
89 bldo4 {
90 /* unused */
91 };
92
93 reg_cldo1: cldo1 {
94 regulator-always-on;
95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>;
97 regulator-name = "vcc-3v3";
98 };
99
100 reg_cldo2: cldo2 {
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 regulator-name = "vcc-wifi-1";
104 };
105
106 reg_cldo3: cldo3 {
107 regulator-min-microvolt = <3300000>;
108 regulator-max-microvolt = <3300000>;
109 regulator-name = "vcc-wifi-2";
110 };
111
112 reg_dcdca: dcdca {
113 regulator-always-on;
114 regulator-min-microvolt = <810000>;
115 regulator-max-microvolt = <1080000>;
116 regulator-name = "vdd-cpu";
117 };
118
119 reg_dcdcc: dcdcc {
120 regulator-min-microvolt = <810000>;
121 regulator-max-microvolt = <1080000>;
122 regulator-name = "vdd-gpu";
123 };
124
125 reg_dcdcd: dcdcd {
126 regulator-always-on;
127 regulator-min-microvolt = <960000>;
128 regulator-max-microvolt = <960000>;
129 regulator-name = "vdd-sys";
130 };
131
132 reg_dcdce: dcdce {
133 regulator-always-on;
134 regulator-min-microvolt = <1200000>;
135 regulator-max-microvolt = <1200000>;
136 regulator-name = "vcc-dram";
137 };
138
139 sw {
140 /* unused */
141 };
142 };
143 };
144};
145
146&uart0 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&uart0_ph_pins>;
149 status = "okay";
150}; 12};
diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi
new file mode 100644
index 0000000000..0612c19cd9
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi
@@ -0,0 +1,150 @@
1// SPDX-License-Identifier: (GPL-2.0+ or MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7/dts-v1/;
8
9#include "sun50i-h6.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14 model = "OrangePi One Plus";
15 compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
16
17 aliases {
18 serial0 = &uart0;
19 };
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24};
25
26&mmc0 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_pins>;
29 vmmc-supply = <&reg_cldo1>;
30 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
31 bus-width = <4>;
32 status = "okay";
33};
34
35&r_i2c {
36 status = "okay";
37
38 axp805: pmic@36 {
39 compatible = "x-powers,axp805", "x-powers,axp806";
40 reg = <0x36>;
41 interrupt-parent = <&r_intc>;
42 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 x-powers,self-working-mode;
46
47 regulators {
48 reg_aldo1: aldo1 {
49 regulator-always-on;
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-name = "vcc-pl";
53 };
54
55 reg_aldo2: aldo2 {
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 regulator-name = "vcc-ac200";
59 };
60
61 reg_aldo3: aldo3 {
62 regulator-always-on;
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 regulator-name = "vcc25-dram";
66 };
67
68 reg_bldo1: bldo1 {
69 regulator-always-on;
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <1800000>;
72 regulator-name = "vcc-bias-pll";
73 };
74
75 reg_bldo2: bldo2 {
76 regulator-always-on;
77 regulator-min-microvolt = <1800000>;
78 regulator-max-microvolt = <1800000>;
79 regulator-name = "vcc-efuse-pcie-hdmi-io";
80 };
81
82 reg_bldo3: bldo3 {
83 regulator-always-on;
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
86 regulator-name = "vcc-dcxoio";
87 };
88
89 bldo4 {
90 /* unused */
91 };
92
93 reg_cldo1: cldo1 {
94 regulator-always-on;
95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>;
97 regulator-name = "vcc-3v3";
98 };
99
100 reg_cldo2: cldo2 {
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 regulator-name = "vcc-wifi-1";
104 };
105
106 reg_cldo3: cldo3 {
107 regulator-min-microvolt = <3300000>;
108 regulator-max-microvolt = <3300000>;
109 regulator-name = "vcc-wifi-2";
110 };
111
112 reg_dcdca: dcdca {
113 regulator-always-on;
114 regulator-min-microvolt = <810000>;
115 regulator-max-microvolt = <1080000>;
116 regulator-name = "vdd-cpu";
117 };
118
119 reg_dcdcc: dcdcc {
120 regulator-min-microvolt = <810000>;
121 regulator-max-microvolt = <1080000>;
122 regulator-name = "vdd-gpu";
123 };
124
125 reg_dcdcd: dcdcd {
126 regulator-always-on;
127 regulator-min-microvolt = <960000>;
128 regulator-max-microvolt = <960000>;
129 regulator-name = "vdd-sys";
130 };
131
132 reg_dcdce: dcdce {
133 regulator-always-on;
134 regulator-min-microvolt = <1200000>;
135 regulator-max-microvolt = <1200000>;
136 regulator-name = "vcc-dram";
137 };
138
139 sw {
140 /* unused */
141 };
142 };
143 };
144};
145
146&uart0 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&uart0_ph_pins>;
149 status = "okay";
150};
diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
new file mode 100644
index 0000000000..7d01f93226
--- /dev/null
+++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -0,0 +1,121 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4 *
5 * Based on sun8i-h3-bananapi-m2-plus.dts, which is:
6 * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
7 */
8
9/dts-v1/;
10#include "sun8i-h3.dtsi"
11#include "sunxi-common-regulators.dtsi"
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15
16/ {
17 model = "Banana Pi BPI-M2-Zero";
18 compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32
33 pwr_led {
34 label = "bananapi-m2-zero:red:pwr";
35 gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
36 default-state = "on";
37 };
38 };
39
40 gpio_keys {
41 compatible = "gpio-keys";
42 pinctrl-names = "default";
43
44 sw4 {
45 label = "power";
46 linux,code = <BTN_0>;
47 gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
48 };
49 };
50
51 wifi_pwrseq: wifi_pwrseq {
52 compatible = "mmc-pwrseq-simple";
53 pinctrl-names = "default";
54 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
55 };
56};
57
58&ehci0 {
59 status = "okay";
60};
61
62&mmc0 {
63 vmmc-supply = <&reg_vcc3v3>;
64 bus-width = <4>;
65 /*
66 * On the production batch of this board the card detect GPIO is
67 * high active (card inserted), although on the early samples it's
68 * low active.
69 */
70 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
71 status = "okay";
72};
73
74&mmc1 {
75 vmmc-supply = <&reg_vcc3v3>;
76 vqmmc-supply = <&reg_vcc3v3>;
77 mmc-pwrseq = <&wifi_pwrseq>;
78 bus-width = <4>;
79 non-removable;
80 status = "okay";
81
82 brcmf: wifi@1 {
83 reg = <1>;
84 compatible = "brcm,bcm4329-fmac";
85 interrupt-parent = <&pio>;
86 interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
87 interrupt-names = "host-wake";
88 };
89};
90
91&ohci0 {
92 status = "okay";
93};
94
95&uart0 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&uart0_pins_a>;
98 status = "okay";
99};
100
101&uart1 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
104 status = "okay";
105};
106
107&usb_otg {
108 dr_mode = "otg";
109 status = "okay";
110};
111
112&usbphy {
113 usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
114 /*
115 * There're two micro-USB connectors, one is power-only and another is
116 * OTG. The Vbus of these two connectors are connected together, so
117 * the external USB device will be powered just by the power input
118 * from the power-only USB port.
119 */
120 status = "okay";
121};
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index 41d57c76f2..f0096074a4 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -84,21 +84,30 @@
84 compatible = "arm,cortex-a7"; 84 compatible = "arm,cortex-a7";
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <1>; 86 reg = <1>;
87 clocks = <&ccu CLK_CPUX>;
88 clock-names = "cpu";
87 operating-points-v2 = <&cpu0_opp_table>; 89 operating-points-v2 = <&cpu0_opp_table>;
90 #cooling-cells = <2>;
88 }; 91 };
89 92
90 cpu@2 { 93 cpu@2 {
91 compatible = "arm,cortex-a7"; 94 compatible = "arm,cortex-a7";
92 device_type = "cpu"; 95 device_type = "cpu";
93 reg = <2>; 96 reg = <2>;
97 clocks = <&ccu CLK_CPUX>;
98 clock-names = "cpu";
94 operating-points-v2 = <&cpu0_opp_table>; 99 operating-points-v2 = <&cpu0_opp_table>;
100 #cooling-cells = <2>;
95 }; 101 };
96 102
97 cpu@3 { 103 cpu@3 {
98 compatible = "arm,cortex-a7"; 104 compatible = "arm,cortex-a7";
99 device_type = "cpu"; 105 device_type = "cpu";
100 reg = <3>; 106 reg = <3>;
107 clocks = <&ccu CLK_CPUX>;
108 clock-names = "cpu";
101 operating-points-v2 = <&cpu0_opp_table>; 109 operating-points-v2 = <&cpu0_opp_table>;
110 #cooling-cells = <2>;
102 }; 111 };
103 }; 112 };
104 113
@@ -111,6 +120,28 @@
111 }; 120 };
112 121
113 soc { 122 soc {
123 system-control@1c00000 {
124 compatible = "allwinner,sun8i-h3-system-control";
125 reg = <0x01c00000 0x30>;
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges;
129
130 sram_c: sram@1d00000 {
131 compatible = "mmio-sram";
132 reg = <0x01d00000 0x80000>;
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges = <0 0x01d00000 0x80000>;
136
137 ve_sram: sram-section@0 {
138 compatible = "allwinner,sun8i-h3-sram-c1",
139 "allwinner,sun4i-a10-sram-c1";
140 reg = <0x000000 0x80000>;
141 };
142 };
143 };
144
114 mali: gpu@1c40000 { 145 mali: gpu@1c40000 {
115 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; 146 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
116 reg = <0x01c40000 0x10000>; 147 reg = <0x01c40000 0x10000>;
diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi
index c3bff1105e..fc6131315c 100644
--- a/arch/arm/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/dts/sunxi-h3-h5.dtsi
@@ -506,8 +506,6 @@
506 reset-names = "stmmaceth"; 506 reset-names = "stmmaceth";
507 clocks = <&ccu CLK_BUS_EMAC>; 507 clocks = <&ccu CLK_BUS_EMAC>;
508 clock-names = "stmmaceth"; 508 clock-names = "stmmaceth";
509 #address-cells = <1>;
510 #size-cells = <0>;
511 status = "disabled"; 509 status = "disabled";
512 510
513 mdio: mdio { 511 mdio: mdio {
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 6a5eafc3d3..2daf23f6f5 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -211,6 +211,7 @@ enum sunxi_gpio_number {
211#define SUN8I_H3_GPL_R_TWI 2 211#define SUN8I_H3_GPL_R_TWI 2
212#define SUN8I_A23_GPL_R_TWI 3 212#define SUN8I_A23_GPL_R_TWI 3
213#define SUN8I_GPL_R_UART 2 213#define SUN8I_GPL_R_UART 2
214#define SUN50I_GPL_R_TWI 2
214 215
215#define SUN9I_GPN_R_RSB 3 216#define SUN9I_GPN_R_RSB 3
216 217
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index d98c53faaa..f2deafddd2 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -46,7 +46,9 @@ struct sunxi_mmc {
46 u32 cbda; /* 0x94 */ 46 u32 cbda; /* 0x94 */
47 u32 res2[26]; 47 u32 res2[26];
48#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) 48#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
49 u32 res3[64]; 49 u32 res3[17];
50 u32 samp_dl;
51 u32 res4[46];
50#endif 52#endif
51 u32 fifo; /* 0x100 / 0x200 FIFO access address */ 53 u32 fifo; /* 0x100 / 0x200 FIFO access address */
52}; 54};
@@ -130,5 +132,7 @@ struct sunxi_mmc {
130#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) 132#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
131#define SUNXI_MMC_COMMON_RESET (1 << 18) 133#define SUNXI_MMC_COMMON_RESET (1 << 18)
132 134
135#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
136
133struct mmc *sunxi_mmc_init(int sdc_no); 137struct mmc *sunxi_mmc_init(int sdc_no);
134#endif /* _SUNXI_MMC_H */ 138#endif /* _SUNXI_MMC_H */
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6277abc3cc..560dc9b25d 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -278,6 +278,7 @@ config MACH_SUN50I
278 select ARM64 278 select ARM64
279 select DM_I2C 279 select DM_I2C
280 select PHY_SUN4I_USB 280 select PHY_SUN4I_USB
281 select SUN6I_PRCM
281 select SUNXI_DE2 282 select SUNXI_DE2
282 select SUNXI_GEN_SUN6I 283 select SUNXI_GEN_SUN6I
283 select SUPPORT_SPL 284 select SUPPORT_SPL
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 82f6f7f8e3..1628f3a7b6 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -149,7 +149,11 @@ void clock_set_pll3(unsigned int clk)
149{ 149{
150 struct sunxi_ccm_reg * const ccm = 150 struct sunxi_ccm_reg * const ccm =
151 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 151 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
152#ifdef CONFIG_SUNXI_DE2
153 const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
154#else
152 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ 155 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
156#endif
153 157
154 if (clk == 0) { 158 if (clk == 0) {
155 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); 159 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 2f95976445..478e37285f 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -149,6 +149,11 @@ S: Maintained
149F: configs/Bananapi_m2m_defconfig 149F: configs/Bananapi_m2m_defconfig
150F: arch/arm/dts/sun8i-r16-bananapi-m2m.dts 150F: arch/arm/dts/sun8i-r16-bananapi-m2m.dts
151 151
152BANANAPI M2 ZERO BOARD
153M: Icenowy Zheng <icenowy@aosc.io>
154S: Maintained
155F: configs/bananapi_m2_zero_defconfig
156
152BANANAPI M64 157BANANAPI M64
153M: Jagan Teki <jagan@amarulasolutions.com> 158M: Jagan Teki <jagan@amarulasolutions.com>
154S: Maintained 159S: Maintained
@@ -330,6 +335,11 @@ S: Maintained
330F: configs/A20-Olimex-SOM204-EVB_defconfig 335F: configs/A20-Olimex-SOM204-EVB_defconfig
331F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig 336F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
332 337
338ORANGEPI LITE2 BOARD
339M: Jagan Teki <jagan@openedev.com>
340S: Maintained
341F: configs/orangepi_lite2_defconfig
342
333ORANGEPI ONE PLUS BOARD 343ORANGEPI ONE PLUS BOARD
334M: Jagan Teki <jagan@amarulasolutions.com> 344M: Jagan Teki <jagan@amarulasolutions.com>
335S: Maintained 345S: Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b196d48674..64ccbc7245 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -168,10 +168,16 @@ void i2c_init_board(void)
168#endif 168#endif
169 169
170#ifdef CONFIG_R_I2C_ENABLE 170#ifdef CONFIG_R_I2C_ENABLE
171#ifdef CONFIG_MACH_SUN50I
172 clock_twi_onoff(5, 1);
173 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
174 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
175#else
171 clock_twi_onoff(5, 1); 176 clock_twi_onoff(5, 1);
172 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 177 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
173 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 178 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
174#endif 179#endif
180#endif
175} 181}
176 182
177#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT) 183#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig
new file mode 100644
index 0000000000..91302eb49c
--- /dev/null
+++ b/configs/bananapi_m2_zero_defconfig
@@ -0,0 +1,13 @@
1CONFIG_ARM=y
2CONFIG_ARCH_SUNXI=y
3CONFIG_SPL=y
4CONFIG_MACH_SUN8I_H3=y
5CONFIG_DRAM_CLK=408
6CONFIG_DRAM_ZQ=3881979
7CONFIG_DRAM_ODT_EN=y
8CONFIG_MMC0_CD_PIN=""
9# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
10# CONFIG_CMD_FLASH is not set
11# CONFIG_SPL_DOS_PARTITION is not set
12# CONFIG_SPL_EFI_PARTITION is not set
13CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero"
diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig
new file mode 100644
index 0000000000..e5f7d15bf6
--- /dev/null
+++ b/configs/orangepi_lite2_defconfig
@@ -0,0 +1,12 @@
1CONFIG_ARM=y
2CONFIG_ARCH_SUNXI=y
3CONFIG_SPL=y
4CONFIG_MACH_SUN50I_H6=y
5CONFIG_MMC0_CD_PIN="PF6"
6# CONFIG_PSCI_RESET is not set
7CONFIG_NR_DRAM_BANKS=1
8# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
9# CONFIG_CMD_FLASH is not set
10# CONFIG_SPL_DOS_PARTITION is not set
11# CONFIG_SPL_EFI_PARTITION is not set
12CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-lite2"
diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig
new file mode 100644
index 0000000000..fd3cdeec85
--- /dev/null
+++ b/configs/pine64-lts_defconfig
@@ -0,0 +1,19 @@
1CONFIG_ARM=y
2CONFIG_ARCH_SUNXI=y
3CONFIG_SPL=y
4CONFIG_MACH_SUN50I=y
5CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
6CONFIG_DRAM_CLK=552
7CONFIG_DRAM_ZQ=3881949
8CONFIG_MMC0_CD_PIN=""
9CONFIG_MMC_SUNXI_SLOT_EXTRA=2
10CONFIG_SPL_SPI_SUNXI=y
11CONFIG_NR_DRAM_BANKS=1
12# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
13# CONFIG_CMD_FLASH is not set
14# CONFIG_SPL_DOS_PARTITION is not set
15# CONFIG_SPL_EFI_PARTITION is not set
16CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts"
17CONFIG_SUN8I_EMAC=y
18CONFIG_USB_EHCI_HCD=y
19CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig
new file mode 100644
index 0000000000..5294dbd2eb
--- /dev/null
+++ b/configs/pinebook_defconfig
@@ -0,0 +1,22 @@
1CONFIG_ARM=y
2CONFIG_ARCH_SUNXI=y
3CONFIG_SPL=y
4CONFIG_MACH_SUN50I=y
5CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
6CONFIG_DRAM_CLK=552
7CONFIG_DRAM_ZQ=3881949
8CONFIG_MMC_SUNXI_SLOT_EXTRA=2
9CONFIG_R_I2C_ENABLE=y
10# CONFIG_CMD_FLASH is not set
11# CONFIG_SPL_DOS_PARTITION is not set
12# CONFIG_SPL_EFI_PARTITION is not set
13CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
14CONFIG_DM_REGULATOR=y
15CONFIG_DM_REGULATOR_FIXED=y
16CONFIG_DM_PWM=y
17CONFIG_PWM_SUNXI=y
18CONFIG_USB_EHCI_HCD=y
19CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
20# CONFIG_USB_GADGET is not set
21CONFIG_VIDEO_BRIDGE=y
22CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 39f15eb423..147eb9b4d5 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
99{ 99{
100 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; 100 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
101 bool new_mode = false; 101 bool new_mode = false;
102 bool calibrate = false;
102 u32 val = 0; 103 u32 val = 0;
103 104
104 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) 105 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
105 new_mode = true; 106 new_mode = true;
106 107
108#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
109 calibrate = true;
110#endif
111
107 /* 112 /*
108 * The MMC clock has an extra /2 post-divider when operating in the new 113 * The MMC clock has an extra /2 post-divider when operating in the new
109 * mode. 114 * mode.
@@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
174 val = CCM_MMC_CTRL_MODE_SEL_NEW; 179 val = CCM_MMC_CTRL_MODE_SEL_NEW;
175 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); 180 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
176#endif 181#endif
177 } else { 182 } else if (!calibrate) {
183 /*
184 * Use hardcoded delay values if controller doesn't support
185 * calibration
186 */
178 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | 187 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
179 CCM_MMC_CTRL_SCLK_DLY(sclk_dly); 188 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
180 } 189 }
@@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
228 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; 237 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
229 writel(rval, &priv->reg->clkcr); 238 writel(rval, &priv->reg->clkcr);
230 239
240#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
241 /* A64 supports calibration of delays on MMC controller and we
242 * have to set delay of zero before starting calibration.
243 * Allwinner BSP driver sets a delay only in the case of
244 * using HS400 which is not supported by mainline U-Boot or
245 * Linux at the moment
246 */
247 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
248#endif
249
231 /* Re-enable Clock */ 250 /* Re-enable Clock */
232 rval |= SUNXI_MMC_CLK_ENABLE; 251 rval |= SUNXI_MMC_CLK_ENABLE;
233 writel(rval, &priv->reg->clkcr); 252 writel(rval, &priv->reg->clkcr);
diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c
index cd4959cc71..5fecb4cfd5 100644
--- a/drivers/video/bridge/video-bridge-uclass.c
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -106,13 +106,19 @@ static int video_bridge_pre_probe(struct udevice *dev)
106int video_bridge_set_active(struct udevice *dev, bool active) 106int video_bridge_set_active(struct udevice *dev, bool active)
107{ 107{
108 struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); 108 struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
109 int ret; 109 int ret = 0;
110 110
111 debug("%s: %d\n", __func__, active); 111 debug("%s: %d\n", __func__, active);
112 ret = dm_gpio_set_value(&uc_priv->sleep, !active); 112 if (uc_priv->sleep.dev) {
113 if (ret) 113 ret = dm_gpio_set_value(&uc_priv->sleep, !active);
114 return ret; 114 if (ret)
115 if (active) { 115 return ret;
116 }
117
118 if (!active)
119 return 0;
120
121 if (uc_priv->reset.dev) {
116 ret = dm_gpio_set_value(&uc_priv->reset, true); 122 ret = dm_gpio_set_value(&uc_priv->reset, true);
117 if (ret) 123 if (ret)
118 return ret; 124 return ret;
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 63c47bf1bc..4cf3a0eb75 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -211,11 +211,17 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
211void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, 211void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
212 int *clk_div, int *clk_double, bool is_composite) 212 int *clk_div, int *clk_double, bool is_composite)
213{ 213{
214 int value, n, m, min_m, max_m, diff; 214 int value, n, m, min_m, max_m, diff, step;
215 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; 215 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
216 int best_double = 0; 216 int best_double = 0;
217 bool use_mipi_pll = false; 217 bool use_mipi_pll = false;
218 218
219#ifdef CONFIG_SUNXI_DE2
220 step = 6000;
221#else
222 step = 3000;
223#endif
224
219 if (tcon == 0) { 225 if (tcon == 0) {
220#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2) 226#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
221 min_m = 6; 227 min_m = 6;
@@ -237,10 +243,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
237 */ 243 */
238 for (m = min_m; m <= max_m; m++) { 244 for (m = min_m; m <= max_m; m++) {
239#ifndef CONFIG_SUNXI_DE2 245#ifndef CONFIG_SUNXI_DE2
240 n = (m * dotclock) / 3000; 246 n = (m * dotclock) / step;
241 247
242 if ((n >= 9) && (n <= 127)) { 248 if ((n >= 9) && (n <= 127)) {
243 value = (3000 * n) / m; 249 value = (step * n) / m;
244 diff = dotclock - value; 250 diff = dotclock - value;
245 if (diff < best_diff) { 251 if (diff < best_diff) {
246 best_diff = diff; 252 best_diff = diff;
@@ -256,9 +262,9 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
256#endif 262#endif
257 263
258 /* No double clock on DE2 */ 264 /* No double clock on DE2 */
259 n = (m * dotclock) / 6000; 265 n = (m * dotclock) / (step * 2);
260 if ((n >= 9) && (n <= 127)) { 266 if ((n >= 9) && (n <= 127)) {
261 value = (6000 * n) / m; 267 value = (step * 2 * n) / m;
262 diff = dotclock - value; 268 diff = dotclock - value;
263 if (diff < best_diff) { 269 if (diff < best_diff) {
264 best_diff = diff; 270 best_diff = diff;
@@ -287,11 +293,11 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
287 } else 293 } else
288#endif 294#endif
289 { 295 {
290 clock_set_pll3(best_n * 3000000); 296 clock_set_pll3(best_n * step * 1000);
291 debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", 297 debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
292 dotclock, 298 dotclock,
293 (best_double + 1) * clock_get_pll3() / best_m / 1000, 299 (best_double + 1) * clock_get_pll3() / best_m / 1000,
294 best_double + 1, best_n, best_m); 300 best_double + 1, step, best_n, best_m);
295 } 301 }
296 302
297 if (tcon == 0) { 303 if (tcon == 0) {