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authorTom Rini2018-11-04 07:12:21 -0600
committerTom Rini2018-11-04 07:12:21 -0600
commit5ef76e59c12c79d106ebda70b710468aa6bd8b75 (patch)
tree4e0120867b94d75ebac8b18bdc0c93a13c1c317c /arch
parent5d6fefa8051a29b26169983cbcf9378bb363f8b2 (diff)
parenta376dde1deb9cc42e3804b9c654f873c936cc8d4 (diff)
downloadu-boot-5ef76e59c12c79d106ebda70b710468aa6bd8b75.tar.gz
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Merge branch 'master' of git://git.denx.de/u-boot-sh
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-rmobile/cpu_info.c3
-rw-r--r--arch/arm/mach-rmobile/memmap-gen3.c89
2 files changed, 91 insertions, 1 deletions
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index e110737471..c9ebc9f40e 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -6,6 +6,8 @@
6#include <common.h> 6#include <common.h>
7#include <asm/io.h> 7#include <asm/io.h>
8 8
9/* R-Car Gen3 caches are enabled in memmap-gen3.c */
10#ifndef CONFIG_RCAR_GEN3
9#ifdef CONFIG_ARCH_CPU_INIT 11#ifdef CONFIG_ARCH_CPU_INIT
10int arch_cpu_init(void) 12int arch_cpu_init(void)
11{ 13{
@@ -20,6 +22,7 @@ void enable_caches(void)
20 dcache_enable(); 22 dcache_enable();
21} 23}
22#endif 24#endif
25#endif
23 26
24#ifdef CONFIG_DISPLAY_CPUINFO 27#ifdef CONFIG_DISPLAY_CPUINFO
25static u32 __rmobile_get_cpu_type(void) 28static u32 __rmobile_get_cpu_type(void)
diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c
index 92c8f2e80d..7e29ccc351 100644
--- a/arch/arm/mach-rmobile/memmap-gen3.c
+++ b/arch/arm/mach-rmobile/memmap-gen3.c
@@ -8,7 +8,9 @@
8#include <common.h> 8#include <common.h>
9#include <asm/armv8/mmu.h> 9#include <asm/armv8/mmu.h>
10 10
11static struct mm_region gen3_mem_map[] = { 11#define GEN3_NR_REGIONS 16
12
13static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
12 { 14 {
13 .virt = 0x0UL, 15 .virt = 0x0UL,
14 .phys = 0x0UL, 16 .phys = 0x0UL,
@@ -42,3 +44,88 @@ static struct mm_region gen3_mem_map[] = {
42}; 44};
43 45
44struct mm_region *mem_map = gen3_mem_map; 46struct mm_region *mem_map = gen3_mem_map;
47
48DECLARE_GLOBAL_DATA_PTR;
49
50void enable_caches(void)
51{
52 u64 start, size;
53 int bank, i = 0;
54
55 /* Create map for RPC access */
56 gen3_mem_map[i].virt = 0x0ULL;
57 gen3_mem_map[i].phys = 0x0ULL;
58 gen3_mem_map[i].size = 0x40000000ULL;
59 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
60 PTE_BLOCK_NON_SHARE |
61 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
62 i++;
63
64 /* Generate entires for DRAM in 32bit address space */
65 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
66 start = gd->bd->bi_dram[bank].start;
67 size = gd->bd->bi_dram[bank].size;
68
69 /* Skip empty DRAM banks */
70 if (!size)
71 continue;
72
73 /* Skip DRAM above 4 GiB */
74 if (start >> 32ULL)
75 continue;
76
77 /* Mark memory reserved by ATF as cacheable too. */
78 if (start == 0x48000000) {
79 start = 0x40000000ULL;
80 size += 0x08000000ULL;
81 }
82
83 gen3_mem_map[i].virt = start;
84 gen3_mem_map[i].phys = start;
85 gen3_mem_map[i].size = size;
86 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
87 PTE_BLOCK_INNER_SHARE;
88 i++;
89 }
90
91 /* Create map for register access */
92 gen3_mem_map[i].virt = 0xc0000000ULL;
93 gen3_mem_map[i].phys = 0xc0000000ULL;
94 gen3_mem_map[i].size = 0x40000000ULL;
95 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
96 PTE_BLOCK_NON_SHARE |
97 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
98 i++;
99
100 /* Generate entires for DRAM in 64bit address space */
101 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
102 start = gd->bd->bi_dram[bank].start;
103 size = gd->bd->bi_dram[bank].size;
104
105 /* Skip empty DRAM banks */
106 if (!size)
107 continue;
108
109 /* Skip DRAM below 4 GiB */
110 if (!(start >> 32ULL))
111 continue;
112
113 gen3_mem_map[i].virt = start;
114 gen3_mem_map[i].phys = start;
115 gen3_mem_map[i].size = size;
116 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
117 PTE_BLOCK_INNER_SHARE;
118 i++;
119 }
120
121 /* Zero out the remaining regions. */
122 for (; i < GEN3_NR_REGIONS; i++) {
123 gen3_mem_map[i].virt = 0;
124 gen3_mem_map[i].phys = 0;
125 gen3_mem_map[i].size = 0;
126 gen3_mem_map[i].attrs = 0;
127 }
128
129 icache_enable();
130 dcache_enable();
131}