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authorCédric Le Goater2018-10-29 01:06:41 -0500
committerJoe Hershberger2018-11-05 10:41:58 -0600
commit1e5d8aaf4f060d8f46bc53fd24b8f2679657e856 (patch)
treebfbdceabfc1d44ebe7ba031c800e67d57eb2c408 /drivers
parentf55f565d7124d815adb47c8b2de42b10b5dc25b3 (diff)
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aspeed: ast2500: fix D2-PLL clock setting in RGMII mode
The algorithm in the ast2500_calc_clock_config() routine suffers from integer rounding and the requested rate does not get the appropriate set of Numerator, Denumerator, Post Divider parameters. This is the case for the D2-PLL clock used by the MAC controllers in RGMII mode. The requested rated is 250MHz but a 251MHz is assigned. The easiest way to fix this problem is to introduce an array of clock settings defining the N, M, P parameters for well known frequencies used by the Aspeed SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/aspeed/clk_ast2500.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 2182320f60..dbee13a182 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
165 return rate; 165 return rate;
166} 166}
167 167
168struct ast2500_clock_config {
169 ulong input_rate;
170 ulong rate;
171 struct ast2500_div_config cfg;
172};
173
174static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
175 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
176};
177
178static bool ast2500_get_clock_config_default(ulong input_rate,
179 ulong requested_rate,
180 struct ast2500_div_config *cfg)
181{
182 int i;
183
184 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
185 const struct ast2500_clock_config *default_cfg =
186 &ast2500_clock_config_defaults[i];
187 if (default_cfg->input_rate == input_rate &&
188 default_cfg->rate == requested_rate) {
189 *cfg = default_cfg->cfg;
190 return true;
191 }
192 }
193
194 return false;
195}
196
168/* 197/*
169 * @input_rate - the rate of input clock in Hz 198 * @input_rate - the rate of input clock in Hz
170 * @requested_rate - desired output rate in Hz 199 * @requested_rate - desired output rate in Hz
@@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
189 ulong delta = rate_khz; 218 ulong delta = rate_khz;
190 ulong new_rate_khz = 0; 219 ulong new_rate_khz = 0;
191 220
221 /*
222 * Look for a well known frequency first.
223 */
224 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
225 return requested_rate;
226
192 for (; it.denum <= max_vals.denum; ++it.denum) { 227 for (; it.denum <= max_vals.denum; ++it.denum) {
193 for (it.post_div = 0; it.post_div <= max_vals.post_div; 228 for (it.post_div = 0; it.post_div <= max_vals.post_div;
194 ++it.post_div) { 229 ++it.post_div) {
@@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
318 /* 353 /*
319 * The values and the meaning of the next three 354 * The values and the meaning of the next three
320 * parameters are undocumented. Taken from Aspeed SDK. 355 * parameters are undocumented. Taken from Aspeed SDK.
356 *
357 * TODO(clg@kaod.org): the SIP and SIC values depend on the
358 * Numerator value
321 */ 359 */
322 const u32 d2_pll_ext_param = 0x2c; 360 const u32 d2_pll_ext_param = 0x2c;
323 const u32 d2_pll_sip = 0x11; 361 const u32 d2_pll_sip = 0x11;