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authorMarek Vasut2018-10-31 14:34:51 -0500
committerMarek Vasut2018-11-02 09:57:13 -0500
commit5dbdd3a600906f56a19c9a82a741705988851a28 (patch)
tree14f61146c3e65a29d3601432306a057e4dc8bf8c /drivers
parent0ff9e4800f21e4250ac8a6ca908de00851f896d8 (diff)
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pinctrl: renesas: Add POCCTRL handling to r8a77990
Add definition of the POCCTRL register and bits therein to R8A77990 E3 pincontrol driver. This allows the pincontrol driver to configure SDHI pin voltage according to power-source DT property. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a77990.c34
1 files changed, 32 insertions, 2 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index a99fd770f2..78bf3193d5 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -26,12 +26,12 @@
26 PORT_GP_18(0, fn, sfx), \ 26 PORT_GP_18(0, fn, sfx), \
27 PORT_GP_23(1, fn, sfx), \ 27 PORT_GP_23(1, fn, sfx), \
28 PORT_GP_26(2, fn, sfx), \ 28 PORT_GP_26(2, fn, sfx), \
29 PORT_GP_12(3, fn, sfx), \ 29 PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_1(3, 12, fn, sfx), \ 30 PORT_GP_1(3, 12, fn, sfx), \
31 PORT_GP_1(3, 13, fn, sfx), \ 31 PORT_GP_1(3, 13, fn, sfx), \
32 PORT_GP_1(3, 14, fn, sfx), \ 32 PORT_GP_1(3, 14, fn, sfx), \
33 PORT_GP_1(3, 15, fn, sfx), \ 33 PORT_GP_1(3, 15, fn, sfx), \
34 PORT_GP_11(4, fn, sfx), \ 34 PORT_GP_CFG_11(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
35 PORT_GP_20(5, fn, sfx), \ 35 PORT_GP_20(5, fn, sfx), \
36 PORT_GP_18(6, fn, sfx) 36 PORT_GP_18(6, fn, sfx)
37/* 37/*
@@ -5151,8 +5151,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5151 { }, 5151 { },
5152}; 5152};
5153 5153
5154enum ioctrl_regs {
5155 POCCTRL,
5156};
5157
5158static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5159 [POCCTRL] = { 0xe6060380, },
5160 { /* sentinel */ },
5161};
5162
5163static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5164{
5165 int bit = -EINVAL;
5166
5167 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5168
5169 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5170 bit = pin & 0x1f;
5171
5172 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5173 bit = (pin & 0x1f) + 19;
5174
5175 return bit;
5176}
5177
5178static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
5179 .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5180};
5181
5154const struct sh_pfc_soc_info r8a77990_pinmux_info = { 5182const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5155 .name = "r8a77990_pfc", 5183 .name = "r8a77990_pfc",
5184 .ops = &r8a77990_pinmux_ops,
5156 .unlock_reg = 0xe6060000, /* PMMR */ 5185 .unlock_reg = 0xe6060000, /* PMMR */
5157 5186
5158 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5187 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -5165,6 +5194,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5165 .nr_functions = ARRAY_SIZE(pinmux_functions), 5194 .nr_functions = ARRAY_SIZE(pinmux_functions),
5166 5195
5167 .cfg_regs = pinmux_config_regs, 5196 .cfg_regs = pinmux_config_regs,
5197 .ioctrl_regs = pinmux_ioctrl_regs,
5168 5198
5169 .pinmux_data = pinmux_data, 5199 .pinmux_data = pinmux_data,
5170 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5200 .pinmux_data_size = ARRAY_SIZE(pinmux_data),