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authorTom Rini2018-11-14 17:25:34 -0600
committerTom Rini2018-11-14 17:25:34 -0600
commit6f443330186676004148930b4dd77f1c2735bd36 (patch)
treef1cc00c2b5210e7bd13f527b0698bfeaf783ac86 /drivers
parent208ecbad2ea83333e8f3c9933213867addf16f4a (diff)
parent7d121a8ea4e0dbf0d7e105b57c3dbd7d8bd2e729 (diff)
downloadu-boot-6f443330186676004148930b4dd77f1c2735bd36.tar.gz
u-boot-6f443330186676004148930b4dd77f1c2735bd36.tar.xz
u-boot-6f443330186676004148930b4dd77f1c2735bd36.zip
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/sunxi_mmc.c21
-rw-r--r--drivers/video/bridge/video-bridge-uclass.c16
-rw-r--r--drivers/video/sunxi/lcdc.c22
3 files changed, 45 insertions, 14 deletions
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 39f15eb423..147eb9b4d5 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
99{ 99{
100 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; 100 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
101 bool new_mode = false; 101 bool new_mode = false;
102 bool calibrate = false;
102 u32 val = 0; 103 u32 val = 0;
103 104
104 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) 105 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
105 new_mode = true; 106 new_mode = true;
106 107
108#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
109 calibrate = true;
110#endif
111
107 /* 112 /*
108 * The MMC clock has an extra /2 post-divider when operating in the new 113 * The MMC clock has an extra /2 post-divider when operating in the new
109 * mode. 114 * mode.
@@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
174 val = CCM_MMC_CTRL_MODE_SEL_NEW; 179 val = CCM_MMC_CTRL_MODE_SEL_NEW;
175 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); 180 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
176#endif 181#endif
177 } else { 182 } else if (!calibrate) {
183 /*
184 * Use hardcoded delay values if controller doesn't support
185 * calibration
186 */
178 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | 187 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
179 CCM_MMC_CTRL_SCLK_DLY(sclk_dly); 188 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
180 } 189 }
@@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
228 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; 237 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
229 writel(rval, &priv->reg->clkcr); 238 writel(rval, &priv->reg->clkcr);
230 239
240#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
241 /* A64 supports calibration of delays on MMC controller and we
242 * have to set delay of zero before starting calibration.
243 * Allwinner BSP driver sets a delay only in the case of
244 * using HS400 which is not supported by mainline U-Boot or
245 * Linux at the moment
246 */
247 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
248#endif
249
231 /* Re-enable Clock */ 250 /* Re-enable Clock */
232 rval |= SUNXI_MMC_CLK_ENABLE; 251 rval |= SUNXI_MMC_CLK_ENABLE;
233 writel(rval, &priv->reg->clkcr); 252 writel(rval, &priv->reg->clkcr);
diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c
index cd4959cc71..5fecb4cfd5 100644
--- a/drivers/video/bridge/video-bridge-uclass.c
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -106,13 +106,19 @@ static int video_bridge_pre_probe(struct udevice *dev)
106int video_bridge_set_active(struct udevice *dev, bool active) 106int video_bridge_set_active(struct udevice *dev, bool active)
107{ 107{
108 struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); 108 struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
109 int ret; 109 int ret = 0;
110 110
111 debug("%s: %d\n", __func__, active); 111 debug("%s: %d\n", __func__, active);
112 ret = dm_gpio_set_value(&uc_priv->sleep, !active); 112 if (uc_priv->sleep.dev) {
113 if (ret) 113 ret = dm_gpio_set_value(&uc_priv->sleep, !active);
114 return ret; 114 if (ret)
115 if (active) { 115 return ret;
116 }
117
118 if (!active)
119 return 0;
120
121 if (uc_priv->reset.dev) {
116 ret = dm_gpio_set_value(&uc_priv->reset, true); 122 ret = dm_gpio_set_value(&uc_priv->reset, true);
117 if (ret) 123 if (ret)
118 return ret; 124 return ret;
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 63c47bf1bc..4cf3a0eb75 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -211,11 +211,17 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
211void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, 211void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
212 int *clk_div, int *clk_double, bool is_composite) 212 int *clk_div, int *clk_double, bool is_composite)
213{ 213{
214 int value, n, m, min_m, max_m, diff; 214 int value, n, m, min_m, max_m, diff, step;
215 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; 215 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
216 int best_double = 0; 216 int best_double = 0;
217 bool use_mipi_pll = false; 217 bool use_mipi_pll = false;
218 218
219#ifdef CONFIG_SUNXI_DE2
220 step = 6000;
221#else
222 step = 3000;
223#endif
224
219 if (tcon == 0) { 225 if (tcon == 0) {
220#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2) 226#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
221 min_m = 6; 227 min_m = 6;
@@ -237,10 +243,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
237 */ 243 */
238 for (m = min_m; m <= max_m; m++) { 244 for (m = min_m; m <= max_m; m++) {
239#ifndef CONFIG_SUNXI_DE2 245#ifndef CONFIG_SUNXI_DE2
240 n = (m * dotclock) / 3000; 246 n = (m * dotclock) / step;
241 247
242 if ((n >= 9) && (n <= 127)) { 248 if ((n >= 9) && (n <= 127)) {
243 value = (3000 * n) / m; 249 value = (step * n) / m;
244 diff = dotclock - value; 250 diff = dotclock - value;
245 if (diff < best_diff) { 251 if (diff < best_diff) {
246 best_diff = diff; 252 best_diff = diff;
@@ -256,9 +262,9 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
256#endif 262#endif
257 263
258 /* No double clock on DE2 */ 264 /* No double clock on DE2 */
259 n = (m * dotclock) / 6000; 265 n = (m * dotclock) / (step * 2);
260 if ((n >= 9) && (n <= 127)) { 266 if ((n >= 9) && (n <= 127)) {
261 value = (6000 * n) / m; 267 value = (step * 2 * n) / m;
262 diff = dotclock - value; 268 diff = dotclock - value;
263 if (diff < best_diff) { 269 if (diff < best_diff) {
264 best_diff = diff; 270 best_diff = diff;
@@ -287,11 +293,11 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
287 } else 293 } else
288#endif 294#endif
289 { 295 {
290 clock_set_pll3(best_n * 3000000); 296 clock_set_pll3(best_n * step * 1000);
291 debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", 297 debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
292 dotclock, 298 dotclock,
293 (best_double + 1) * clock_get_pll3() / best_m / 1000, 299 (best_double + 1) * clock_get_pll3() / best_m / 1000,
294 best_double + 1, best_n, best_m); 300 best_double + 1, step, best_n, best_m);
295 } 301 }
296 302
297 if (tcon == 0) { 303 if (tcon == 0) {