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authorIcenowy Zheng2018-10-28 16:26:12 -0500
committerJagan Teki2018-11-13 10:47:06 -0600
commit7d121a8ea4e0dbf0d7e105b57c3dbd7d8bd2e729 (patch)
treee04adac94441d7c3bfd329332fa61140087d8d2e /drivers
parente6b16e785234873f86b0560b5387381ae9d72762 (diff)
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sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD
DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't let PLL_VIDEO be high enough for them. Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/sunxi/lcdc.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 63c47bf1bc..4cf3a0eb75 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -211,11 +211,17 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
211void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, 211void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
212 int *clk_div, int *clk_double, bool is_composite) 212 int *clk_div, int *clk_double, bool is_composite)
213{ 213{
214 int value, n, m, min_m, max_m, diff; 214 int value, n, m, min_m, max_m, diff, step;
215 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; 215 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
216 int best_double = 0; 216 int best_double = 0;
217 bool use_mipi_pll = false; 217 bool use_mipi_pll = false;
218 218
219#ifdef CONFIG_SUNXI_DE2
220 step = 6000;
221#else
222 step = 3000;
223#endif
224
219 if (tcon == 0) { 225 if (tcon == 0) {
220#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2) 226#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
221 min_m = 6; 227 min_m = 6;
@@ -237,10 +243,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
237 */ 243 */
238 for (m = min_m; m <= max_m; m++) { 244 for (m = min_m; m <= max_m; m++) {
239#ifndef CONFIG_SUNXI_DE2 245#ifndef CONFIG_SUNXI_DE2
240 n = (m * dotclock) / 3000; 246 n = (m * dotclock) / step;
241 247
242 if ((n >= 9) && (n <= 127)) { 248 if ((n >= 9) && (n <= 127)) {
243 value = (3000 * n) / m; 249 value = (step * n) / m;
244 diff = dotclock - value; 250 diff = dotclock - value;
245 if (diff < best_diff) { 251 if (diff < best_diff) {
246 best_diff = diff; 252 best_diff = diff;
@@ -256,9 +262,9 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
256#endif 262#endif
257 263
258 /* No double clock on DE2 */ 264 /* No double clock on DE2 */
259 n = (m * dotclock) / 6000; 265 n = (m * dotclock) / (step * 2);
260 if ((n >= 9) && (n <= 127)) { 266 if ((n >= 9) && (n <= 127)) {
261 value = (6000 * n) / m; 267 value = (step * 2 * n) / m;
262 diff = dotclock - value; 268 diff = dotclock - value;
263 if (diff < best_diff) { 269 if (diff < best_diff) {
264 best_diff = diff; 270 best_diff = diff;
@@ -287,11 +293,11 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
287 } else 293 } else
288#endif 294#endif
289 { 295 {
290 clock_set_pll3(best_n * 3000000); 296 clock_set_pll3(best_n * step * 1000);
291 debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", 297 debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
292 dotclock, 298 dotclock,
293 (best_double + 1) * clock_get_pll3() / best_m / 1000, 299 (best_double + 1) * clock_get_pll3() / best_m / 1000,
294 best_double + 1, best_n, best_m); 300 best_double + 1, step, best_n, best_m);
295 } 301 }
296 302
297 if (tcon == 0) { 303 if (tcon == 0) {