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-rw-r--r--.github/pull_request_template.md3
-rw-r--r--Android.bp1
-rw-r--r--Kconfig10
-rw-r--r--MAINTAINERS20
-rw-r--r--Makefile61
-rw-r--r--api/api_storage.c5
-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/Makefile4
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch211
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/fsl-imx8mq-evk.dts414
-rw-r--r--arch/arm/dts/meson-axg-s400-u-boot.dtsi14
-rw-r--r--arch/arm/dts/omap5-u-boot.dtsi5
-rw-r--r--arch/arm/dts/rk3399-puma.dtsi5
-rw-r--r--arch/arm/dts/socfpga_arria10.dtsi1
-rw-r--r--arch/arm/dts/uniphier-ld11.dtsi52
-rw-r--r--arch/arm/dts/uniphier-ld20-global.dts4
-rw-r--r--arch/arm/dts/uniphier-ld20-ref.dts4
-rw-r--r--arch/arm/dts/uniphier-ld20.dtsi242
-rw-r--r--arch/arm/dts/uniphier-ld4.dtsi14
-rw-r--r--arch/arm/dts/uniphier-pinctrl.dtsi20
-rw-r--r--arch/arm/dts/uniphier-pro4-ace.dts8
-rw-r--r--arch/arm/dts/uniphier-pro4-sanji.dts8
-rw-r--r--arch/arm/dts/uniphier-pro4.dtsi143
-rw-r--r--arch/arm/dts/uniphier-pro5.dtsi25
-rw-r--r--arch/arm/dts/uniphier-pxs2.dtsi207
-rw-r--r--arch/arm/dts/uniphier-pxs3.dtsi267
-rw-r--r--arch/arm/dts/uniphier-sld8.dtsi14
-rw-r--r--arch/arm/dts/vf.dtsi6
-rw-r--r--arch/arm/dts/vf610-pinfunc.h810
-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h5
-rw-r--r--arch/arm/include/asm/arch-imx8m/clock.h (renamed from arch/arm/include/asm/arch-mx8m/clock.h)22
-rw-r--r--arch/arm/include/asm/arch-imx8m/crm_regs.h (renamed from arch/arm/include/asm/arch-mx8m/crm_regs.h)4
-rw-r--r--arch/arm/include/asm/arch-imx8m/ddr.h740
-rw-r--r--arch/arm/include/asm/arch-imx8m/gpio.h (renamed from arch/arm/include/asm/arch-mx8m/gpio.h)4
-rw-r--r--arch/arm/include/asm/arch-imx8m/imx-regs.h (renamed from arch/arm/include/asm/arch-mx8m/imx-regs.h)4
-rw-r--r--arch/arm/include/asm/arch-imx8m/imx8mq_pins.h (renamed from arch/arm/include/asm/arch-mx8m/mx8mq_pins.h)4
-rw-r--r--arch/arm/include/asm/arch-imx8m/lpddr4_define.h97
-rw-r--r--arch/arm/include/asm/arch-imx8m/sys_proto.h (renamed from arch/arm/include/asm/arch-mx8m/sys_proto.h)4
-rw-r--r--arch/arm/include/asm/arch-mx8m/ddr.h355
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h5
-rw-r--r--arch/arm/include/asm/arch-vf610/iomux-vf610.h2
-rw-r--r--arch/arm/include/asm/dma-mapping.h2
-rw-r--r--arch/arm/include/asm/mach-imx/iomux-v3.h2
-rw-r--r--arch/arm/include/asm/mach-imx/regs-lcdif.h6
-rw-r--r--arch/arm/include/asm/mach-imx/sys_proto.h3
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h2
-rw-r--r--arch/arm/mach-imx/Makefile37
-rw-r--r--arch/arm/mach-imx/cpu.c16
-rw-r--r--arch/arm/mach-imx/ddrmc-vf610.c6
-rw-r--r--arch/arm/mach-imx/hab.c29
-rw-r--r--arch/arm/mach-imx/imx8/cpu.c2
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig23
-rw-r--r--arch/arm/mach-imx/imx8m/Makefile (renamed from arch/arm/mach-imx/mx8m/Makefile)0
-rw-r--r--arch/arm/mach-imx/imx8m/clock.c (renamed from arch/arm/mach-imx/mx8m/clock.c)142
-rw-r--r--arch/arm/mach-imx/imx8m/clock_slice.c (renamed from arch/arm/mach-imx/mx8m/clock_slice.c)0
-rw-r--r--arch/arm/mach-imx/imx8m/imximage.cfg17
-rw-r--r--arch/arm/mach-imx/imx8m/lowlevel_init.S (renamed from arch/arm/mach-imx/mx8m/lowlevel_init.S)0
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c (renamed from arch/arm/mach-imx/mx8m/soc.c)16
-rw-r--r--arch/arm/mach-imx/imx_bootaux.c8
-rwxr-xr-xarch/arm/mach-imx/mkimage_fit_atf.sh137
-rw-r--r--arch/arm/mach-imx/mx6/Kconfig3
-rw-r--r--arch/arm/mach-imx/mx8m/Kconfig10
-rw-r--r--arch/arm/mach-imx/spl.c61
-rw-r--r--arch/arm/mach-k3/config.mk2
-rw-r--r--arch/arm/mach-mediatek/mt7629/lowlevel_init.S52
-rw-r--r--arch/arm/mach-mvebu/cpu.c6
-rw-r--r--arch/arm/mach-omap2/omap3/Kconfig5
-rw-r--r--arch/arm/mach-omap2/omap3/clock.c10
-rw-r--r--arch/arm/mach-rockchip/rk3036/sdram_rk3036.c4
-rw-r--r--arch/arm/mach-rockchip/sdram_common.c18
-rw-r--r--arch/arm/mach-socfpga/Kconfig1
-rw-r--r--arch/arm/mach-socfpga/include/mach/mailbox_s10.h9
-rw-r--r--arch/arm/mach-socfpga/include/mach/misc.h4
-rw-r--r--arch/arm/mach-socfpga/mailbox_s10.c48
-rw-r--r--arch/arm/mach-socfpga/misc.c26
-rw-r--r--arch/arm/mach-socfpga/misc_arria10.c23
-rw-r--r--arch/arm/mach-socfpga/misc_gen5.c22
-rw-r--r--arch/arm/mach-socfpga/misc_s10.c22
-rw-r--r--arch/arm/mach-uniphier/board_late_init.c8
-rw-r--r--arch/mips/Kconfig15
-rw-r--r--arch/mips/Makefile2
-rw-r--r--arch/mips/cpu/cpu.c10
-rw-r--r--arch/mips/dts/Makefile1
-rw-r--r--arch/mips/dts/ar933x.dtsi3
-rw-r--r--arch/mips/dts/brcm,bcm6318.dtsi38
-rw-r--r--arch/mips/dts/brcm,bcm63268.dtsi38
-rw-r--r--arch/mips/dts/brcm,bcm6328.dtsi30
-rw-r--r--arch/mips/dts/brcm,bcm6338.dtsi29
-rw-r--r--arch/mips/dts/brcm,bcm6348.dtsi42
-rw-r--r--arch/mips/dts/brcm,bcm6358.dtsi46
-rw-r--r--arch/mips/dts/brcm,bcm6362.dtsi32
-rw-r--r--arch/mips/dts/brcm,bcm6368.dtsi32
-rw-r--r--arch/mips/dts/ci20.dts122
-rw-r--r--arch/mips/dts/comtrend,ar-5315u.dts32
-rw-r--r--arch/mips/dts/comtrend,ar-5387un.dts32
-rw-r--r--arch/mips/dts/comtrend,ct-5361.dts12
-rw-r--r--arch/mips/dts/comtrend,vr-3032u.dts32
-rw-r--r--arch/mips/dts/comtrend,wap-5813n.dts14
-rw-r--r--arch/mips/dts/huawei,hg556a.dts12
-rw-r--r--arch/mips/dts/jz4780.dtsi164
-rw-r--r--arch/mips/dts/luton_pcb091.dts36
-rw-r--r--arch/mips/dts/mscc,luton.dtsi87
-rw-r--r--arch/mips/dts/mscc,ocelot.dtsi152
-rw-r--r--arch/mips/dts/mscc,ocelot_pcb.dtsi42
-rw-r--r--arch/mips/dts/netgear,dgnd3700v2.dts14
-rw-r--r--arch/mips/dts/nexys4ddr.dts1
-rw-r--r--arch/mips/dts/ocelot_pcb120.dts12
-rw-r--r--arch/mips/dts/ocelot_pcb123.dts12
-rw-r--r--arch/mips/dts/qca953x.dtsi3
-rw-r--r--arch/mips/dts/sagem,f@st1704.dts12
-rw-r--r--arch/mips/dts/sfr,nb4-ser.dts24
-rw-r--r--arch/mips/include/asm/cacheops.h19
-rw-r--r--arch/mips/include/asm/mipsregs.h18
-rw-r--r--arch/mips/include/asm/spl.h33
-rw-r--r--arch/mips/mach-jz47xx/Kconfig26
-rw-r--r--arch/mips/mach-jz47xx/Makefile5
-rw-r--r--arch/mips/mach-jz47xx/include/mach/jz4780.h103
-rw-r--r--arch/mips/mach-jz47xx/include/mach/jz4780_dram.h456
-rw-r--r--arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h12
-rw-r--r--arch/mips/mach-jz47xx/jz4780/Makefile3
-rw-r--r--arch/mips/mach-jz47xx/jz4780/TODO4
-rw-r--r--arch/mips/mach-jz47xx/jz4780/gpio.c39
-rw-r--r--arch/mips/mach-jz47xx/jz4780/jz4780.c83
-rw-r--r--arch/mips/mach-jz47xx/jz4780/pll.c530
-rw-r--r--arch/mips/mach-jz47xx/jz4780/reset.c53
-rw-r--r--arch/mips/mach-jz47xx/jz4780/sdram.c270
-rw-r--r--arch/mips/mach-jz47xx/jz4780/timer.c239
-rw-r--r--arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds50
-rw-r--r--arch/mips/mach-jz47xx/start.S98
-rw-r--r--arch/mips/mach-mscc/Kconfig86
-rw-r--r--arch/mips/mach-mscc/Makefile6
-rw-r--r--arch/mips/mach-mscc/cpu.c102
-rw-r--r--arch/mips/mach-mscc/dram.c73
-rw-r--r--arch/mips/mach-mscc/include/ioremap.h49
-rw-r--r--arch/mips/mach-mscc/include/mach/common.h28
-rw-r--r--arch/mips/mach-mscc/include/mach/ddr.h814
-rw-r--r--arch/mips/mach-mscc/include/mach/luton/luton.h24
-rw-r--r--arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h14
-rw-r--r--arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h245
-rw-r--r--arch/mips/mach-mscc/include/mach/ocelot/ocelot.h24
-rw-r--r--arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h21
-rw-r--r--arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h274
-rw-r--r--arch/mips/mach-mscc/include/mach/tlb.h55
-rw-r--r--arch/mips/mach-mscc/lowlevel_init.S30
-rw-r--r--arch/mips/mach-mscc/lowlevel_init_luton.S62
-rw-r--r--arch/mips/mach-mscc/reset.c30
-rw-r--r--arch/mips/mach-mt7620/cpu.c14
-rw-r--r--arch/riscv/Kconfig60
-rw-r--r--arch/riscv/Makefile9
-rw-r--r--arch/riscv/cpu/Makefile2
-rw-r--r--arch/riscv/cpu/ax25/Kconfig17
-rw-r--r--arch/riscv/cpu/ax25/cache.c12
-rw-r--r--arch/riscv/cpu/cpu.c98
-rw-r--r--arch/riscv/cpu/mtrap.S103
-rw-r--r--arch/riscv/cpu/qemu/Kconfig12
-rw-r--r--arch/riscv/cpu/qemu/cpu.c14
-rw-r--r--arch/riscv/cpu/start.S93
-rw-r--r--arch/riscv/dts/ae350.dts229
-rw-r--r--arch/riscv/include/asm/csr.h16
-rw-r--r--arch/riscv/include/asm/encoding.h236
-rw-r--r--arch/riscv/include/asm/global_data.h4
-rw-r--r--arch/riscv/include/asm/syscon.h19
-rw-r--r--arch/riscv/lib/Makefile2
-rw-r--r--arch/riscv/lib/asm-offsets.c19
-rw-r--r--arch/riscv/lib/bootm.c10
-rw-r--r--arch/riscv/lib/interrupts.c62
-rw-r--r--arch/riscv/lib/rdtime.c38
-rw-r--r--arch/riscv/lib/sifive_clint.c84
-rw-r--r--board/AndesTech/ax25-ae350/Kconfig4
-rw-r--r--board/AndesTech/ax25-ae350/MAINTAINERS5
-rw-r--r--board/embest/mx6boards/MAINTAINERS1
-rw-r--r--board/embest/mx6boards/mx6boards.c48
-rw-r--r--board/emulation/qemu-riscv/Kconfig2
-rw-r--r--board/freescale/imx8mq_evk/Kconfig12
-rw-r--r--board/freescale/imx8mq_evk/MAINTAINERS6
-rw-r--r--board/freescale/imx8mq_evk/Makefile12
-rw-r--r--board/freescale/imx8mq_evk/README36
-rw-r--r--board/freescale/imx8mq_evk/imx8mq_evk.c130
-rw-r--r--board/freescale/imx8mq_evk/lpddr4_timing.c1320
-rw-r--r--board/freescale/imx8mq_evk/lpddr4_timing_b0.c1191
-rw-r--r--board/freescale/imx8mq_evk/spl.c246
-rw-r--r--board/freescale/imx8qxp_mek/imximage.cfg1
-rw-r--r--board/ge/bx50v3/Kconfig2
-rw-r--r--board/ge/bx50v3/bx50v3.c57
-rw-r--r--board/ge/common/Kconfig14
-rw-r--r--board/ge/common/vpd_reader.c37
-rw-r--r--board/ge/common/vpd_reader.h16
-rw-r--r--board/ge/mx53ppd/Kconfig2
-rw-r--r--board/ge/mx53ppd/mx53ppd.c50
-rw-r--r--board/imgtec/ci20/Kconfig15
-rw-r--r--board/imgtec/ci20/MAINTAINERS6
-rw-r--r--board/imgtec/ci20/Makefile3
-rw-r--r--board/imgtec/ci20/README10
-rw-r--r--board/imgtec/ci20/ci20.c362
-rw-r--r--board/isee/igep003x/MAINTAINERS2
-rw-r--r--board/mscc/luton/Kconfig14
-rw-r--r--board/mscc/luton/Makefile3
-rw-r--r--board/mscc/luton/luton.c28
-rw-r--r--board/mscc/ocelot/Kconfig14
-rw-r--r--board/mscc/ocelot/Makefile4
-rw-r--r--board/mscc/ocelot/ocelot.c58
-rw-r--r--board/sunxi/board.c18
-rw-r--r--board/toradex/colibri_vf/colibri_vf.c10
-rw-r--r--cmd/cbfs.c34
-rw-r--r--common/bootm_os.c8
-rw-r--r--common/image.c1
-rw-r--r--common/spl/Kconfig5
-rw-r--r--common/spl/spl_fit.c21
-rw-r--r--configs/A20-OLinuXino-Lime2-eMMC_defconfig2
-rw-r--r--configs/A20-OLinuXino-Lime2_defconfig2
-rw-r--r--configs/MCR3000_defconfig13
-rw-r--r--configs/ae350_rv32_defconfig (renamed from configs/a25-ae350_32_defconfig)0
-rw-r--r--configs/ae350_rv64_defconfig (renamed from configs/ax25-ae350_64_defconfig)0
-rw-r--r--configs/am335x_baltos_defconfig1
-rw-r--r--configs/am335x_boneblack_defconfig3
-rw-r--r--configs/am335x_boneblack_vboot_defconfig6
-rw-r--r--configs/am335x_evm_defconfig1
-rw-r--r--configs/am335x_evm_nor_defconfig3
-rw-r--r--configs/am335x_evm_norboot_defconfig3
-rw-r--r--configs/am335x_evm_spiboot_defconfig3
-rw-r--r--configs/am335x_evm_usbspl_defconfig5
-rw-r--r--configs/am335x_igep003x_defconfig2
-rw-r--r--configs/am335x_pdu001_defconfig6
-rw-r--r--configs/am335x_shc_defconfig2
-rw-r--r--configs/am335x_shc_ict_defconfig2
-rw-r--r--configs/am335x_shc_netboot_defconfig2
-rw-r--r--configs/am335x_shc_prompt_defconfig2
-rw-r--r--configs/am335x_shc_sdboot_defconfig2
-rw-r--r--configs/am335x_shc_sdboot_prompt_defconfig2
-rw-r--r--configs/am335x_sl50_defconfig2
-rw-r--r--configs/am3517_evm_defconfig2
-rw-r--r--configs/am43xx_evm_defconfig6
-rw-r--r--configs/am43xx_evm_ethboot_defconfig3
-rw-r--r--configs/am43xx_evm_qspiboot_defconfig4
-rw-r--r--configs/am43xx_evm_rtconly_defconfig3
-rw-r--r--configs/am43xx_evm_usbhost_boot_defconfig4
-rw-r--r--configs/am43xx_hs_evm_defconfig5
-rw-r--r--configs/am57xx_evm_defconfig4
-rw-r--r--configs/am57xx_hs_evm_defconfig4
-rw-r--r--configs/apalis-tk1_defconfig1
-rw-r--r--configs/apalis_imx6_defconfig2
-rw-r--r--configs/apalis_t30_defconfig1
-rw-r--r--configs/arndale_defconfig1
-rw-r--r--configs/avnet_ultra96_rev1_defconfig1
-rw-r--r--configs/bcm968580_ram_defconfig1
-rw-r--r--configs/beaver_defconfig1
-rw-r--r--configs/birdland_bav335a_defconfig3
-rw-r--r--configs/birdland_bav335b_defconfig3
-rw-r--r--configs/brppt1_mmc_defconfig2
-rw-r--r--configs/brppt1_nand_defconfig2
-rw-r--r--configs/brppt1_spi_defconfig2
-rw-r--r--configs/bubblegum_96_defconfig1
-rw-r--r--configs/cardhu_defconfig1
-rw-r--r--configs/cei-tk1-som_defconfig1
-rw-r--r--configs/chiliboard_defconfig3
-rw-r--r--configs/chromebit_mickey_defconfig1
-rw-r--r--configs/chromebook_jerry_defconfig3
-rw-r--r--configs/chromebook_minnie_defconfig1
-rw-r--r--configs/ci20_mmc_defconfig48
-rw-r--r--configs/cl-som-am57x_defconfig3
-rw-r--r--configs/cl-som-imx7_defconfig6
-rw-r--r--configs/clearfog_defconfig1
-rw-r--r--configs/clearfog_gt_8k_defconfig3
-rw-r--r--configs/cm_fx6_defconfig1
-rw-r--r--configs/cm_t335_defconfig2
-rw-r--r--configs/cm_t3517_defconfig1
-rw-r--r--configs/cm_t35_defconfig1
-rw-r--r--configs/cm_t43_defconfig3
-rw-r--r--configs/cm_t54_defconfig1
-rw-r--r--configs/colibri-imx6ull_defconfig1
-rw-r--r--configs/colibri_imx6_defconfig2
-rw-r--r--configs/colibri_t20_defconfig1
-rw-r--r--configs/colibri_t30_defconfig1
-rw-r--r--configs/colibri_vf_defconfig3
-rw-r--r--configs/comtrend_ar5315u_ram_defconfig7
-rw-r--r--configs/comtrend_ar5387un_ram_defconfig7
-rw-r--r--configs/comtrend_ct5361_ram_defconfig8
-rw-r--r--configs/comtrend_vr3032u_ram_defconfig7
-rw-r--r--configs/comtrend_wap5813n_ram_defconfig8
-rw-r--r--configs/da850evm_defconfig1
-rw-r--r--configs/da850evm_direct_nor_defconfig1
-rw-r--r--configs/da850evm_nand_defconfig1
-rw-r--r--configs/dalmore_defconfig1
-rw-r--r--configs/db-88f6820-amc_defconfig3
-rw-r--r--configs/dh_imx6_defconfig1
-rw-r--r--configs/display5_factory_defconfig2
-rw-r--r--configs/dra7xx_evm_defconfig4
-rw-r--r--configs/dra7xx_hs_evm_defconfig4
-rw-r--r--configs/dragonboard410c_defconfig1
-rw-r--r--configs/dragonboard820c_defconfig1
-rw-r--r--configs/duovero_defconfig2
-rw-r--r--configs/e2220-1170_defconfig1
-rw-r--r--configs/edison_defconfig1
-rw-r--r--configs/elgin-rv1108_defconfig1
-rw-r--r--configs/evb-ast2500_defconfig15
-rw-r--r--configs/evb-rk3128_defconfig1
-rw-r--r--configs/evb-rk3288_defconfig1
-rw-r--r--configs/evb-rk3328_defconfig3
-rw-r--r--configs/evb-rk3399_defconfig1
-rw-r--r--configs/evb-rv1108_defconfig1
-rw-r--r--configs/fennec-rk3288_defconfig1
-rw-r--r--configs/ficus-rk3399_defconfig5
-rw-r--r--configs/firefly-rk3288_defconfig1
-rw-r--r--configs/firefly-rk3399_defconfig1
-rw-r--r--configs/gardena-smart-gateway-mt7688-ram_defconfig1
-rw-r--r--configs/gardena-smart-gateway-mt7688_defconfig1
-rw-r--r--configs/ge_bx50v3_defconfig3
-rw-r--r--configs/harmony_defconfig1
-rw-r--r--configs/helios4_defconfig6
-rw-r--r--configs/hikey_defconfig1
-rw-r--r--configs/huawei_hg556a_ram_defconfig8
-rw-r--r--configs/igep0032_defconfig1
-rw-r--r--configs/igep00x0_defconfig1
-rw-r--r--configs/imx6q_logic_defconfig2
-rw-r--r--configs/imx8mq_evk_defconfig37
-rw-r--r--configs/jetson-tk1_defconfig1
-rw-r--r--configs/k2e_evm_defconfig3
-rw-r--r--configs/k2e_hs_evm_defconfig3
-rw-r--r--configs/k2g_evm_defconfig3
-rw-r--r--configs/k2g_hs_evm_defconfig3
-rw-r--r--configs/k2hk_evm_defconfig3
-rw-r--r--configs/k2hk_hs_evm_defconfig3
-rw-r--r--configs/k2l_evm_defconfig3
-rw-r--r--configs/k2l_hs_evm_defconfig2
-rw-r--r--configs/khadas-vim2_defconfig1
-rw-r--r--configs/khadas-vim_defconfig1
-rw-r--r--configs/kp_imx6q_tpc_defconfig1
-rw-r--r--configs/kylin-rk3036_defconfig1
-rw-r--r--configs/libretech-cc_defconfig1
-rw-r--r--configs/linkit-smart-7688-ram_defconfig1
-rw-r--r--configs/linkit-smart-7688_defconfig1
-rw-r--r--configs/ls1012a2g5rdb_qspi_defconfig1
-rw-r--r--configs/ls1012a2g5rdb_tfa_defconfig1
-rw-r--r--configs/ls1012afrdm_qspi_defconfig1
-rw-r--r--configs/ls1012afrdm_tfa_defconfig1
-rw-r--r--configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1012afrwy_qspi_defconfig1
-rw-r--r--configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig4
-rw-r--r--configs/ls1012afrwy_tfa_defconfig1
-rw-r--r--configs/ls1012aqds_qspi_defconfig1
-rw-r--r--configs/ls1012aqds_tfa_SECURE_BOOT_defconfig11
-rw-r--r--configs/ls1012aqds_tfa_defconfig1
-rw-r--r--configs/ls1012ardb_qspi_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1012ardb_qspi_defconfig1
-rw-r--r--configs/ls1012ardb_tfa_SECURE_BOOT_defconfig8
-rw-r--r--configs/ls1012ardb_tfa_defconfig1
-rw-r--r--configs/ls1021atwr_nor_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1021atwr_nor_defconfig1
-rw-r--r--configs/ls1021atwr_nor_lpuart_defconfig1
-rw-r--r--configs/ls1021atwr_qspi_defconfig1
-rw-r--r--configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1021atwr_sdcard_ifc_defconfig1
-rw-r--r--configs/ls1021atwr_sdcard_qspi_defconfig1
-rw-r--r--configs/ls1043aqds_defconfig1
-rw-r--r--configs/ls1043aqds_lpuart_defconfig1
-rw-r--r--configs/ls1043aqds_nand_defconfig1
-rw-r--r--configs/ls1043aqds_nor_ddr3_defconfig1
-rw-r--r--configs/ls1043aqds_qspi_defconfig1
-rw-r--r--configs/ls1043aqds_sdcard_ifc_defconfig1
-rw-r--r--configs/ls1043aqds_sdcard_qspi_defconfig1
-rw-r--r--configs/ls1043aqds_tfa_SECURE_BOOT_defconfig10
-rw-r--r--configs/ls1043aqds_tfa_defconfig2
-rw-r--r--configs/ls1043ardb_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1043ardb_defconfig1
-rw-r--r--configs/ls1043ardb_nand_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1043ardb_nand_defconfig1
-rw-r--r--configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1043ardb_sdcard_defconfig1
-rw-r--r--configs/ls1043ardb_tfa_SECURE_BOOT_defconfig9
-rw-r--r--configs/ls1043ardb_tfa_defconfig1
-rw-r--r--configs/ls1046aqds_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1046aqds_lpuart_defconfig1
-rw-r--r--configs/ls1046aqds_nand_defconfig1
-rw-r--r--configs/ls1046aqds_qspi_defconfig1
-rw-r--r--configs/ls1046aqds_sdcard_ifc_defconfig1
-rw-r--r--configs/ls1046aqds_sdcard_qspi_defconfig1
-rw-r--r--configs/ls1046aqds_tfa_SECURE_BOOT_defconfig18
-rw-r--r--configs/ls1046aqds_tfa_defconfig9
-rw-r--r--configs/ls1046ardb_emmc_defconfig1
-rw-r--r--configs/ls1046ardb_qspi_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1046ardb_qspi_spl_defconfig1
-rw-r--r--configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1046ardb_sdcard_defconfig1
-rw-r--r--configs/ls1046ardb_tfa_SECURE_BOOT_defconfig14
-rw-r--r--configs/ls1046ardb_tfa_defconfig12
-rw-r--r--configs/ls1088aqds_qspi_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1088aqds_qspi_defconfig1
-rw-r--r--configs/ls1088aqds_sdcard_qspi_defconfig1
-rw-r--r--configs/ls1088ardb_qspi_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1088ardb_sdcard_qspi_defconfig1
-rw-r--r--configs/ls2080aqds_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls2080aqds_nand_defconfig1
-rw-r--r--configs/ls2080aqds_qspi_defconfig1
-rw-r--r--configs/ls2080aqds_sdcard_defconfig1
-rw-r--r--configs/ls2080ardb_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls2080ardb_nand_defconfig1
-rw-r--r--configs/ls2081ardb_defconfig1
-rw-r--r--configs/ls2088ardb_qspi_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls2088ardb_qspi_defconfig1
-rw-r--r--configs/lschlv2_defconfig1
-rw-r--r--configs/lsxhl_defconfig1
-rw-r--r--configs/m53menlo_defconfig8
-rw-r--r--configs/marsboard_defconfig1
-rw-r--r--configs/mccmon6_nor_defconfig1
-rw-r--r--configs/mccmon6_sd_defconfig1
-rw-r--r--configs/medcom-wide_defconfig1
-rw-r--r--configs/miqi-rk3288_defconfig1
-rw-r--r--configs/mscc_luton_defconfig64
-rw-r--r--configs/mscc_ocelot_defconfig67
-rw-r--r--configs/mscc_ocelot_pcb120_defconfig60
-rw-r--r--configs/mt7623n_bpir2_defconfig1
-rw-r--r--configs/mvebu_db-88f3720_defconfig1
-rw-r--r--configs/mvebu_db_armada8k_defconfig1
-rw-r--r--configs/mvebu_espressobin-88f3720_defconfig1
-rw-r--r--configs/mvebu_mcbin-88f8040_defconfig1
-rw-r--r--configs/mx23_olinuxino_defconfig3
-rw-r--r--configs/mx53ppd_defconfig3
-rw-r--r--configs/mx6cuboxi_defconfig1
-rw-r--r--configs/mx6memcal_defconfig2
-rw-r--r--configs/mx6qsabrelite_defconfig1
-rw-r--r--configs/mx6sabresd_defconfig2
-rw-r--r--configs/netgear_dgnd3700v2_ram_defconfig8
-rw-r--r--configs/novena_defconfig1
-rw-r--r--configs/nyan-big_defconfig1
-rw-r--r--configs/odroid-c2_defconfig1
-rw-r--r--configs/odroid-xu3_defconfig1
-rw-r--r--configs/odroid_defconfig1
-rw-r--r--configs/omap35_logic_defconfig1
-rw-r--r--configs/omap35_logic_somlv_defconfig1
-rw-r--r--configs/omap3_beagle_defconfig1
-rw-r--r--configs/omap3_logic_defconfig1
-rw-r--r--configs/omap3_logic_somlv_defconfig1
-rw-r--r--configs/omap3_overo_defconfig1
-rw-r--r--configs/omap3_zoom1_defconfig1
-rw-r--r--configs/omap4_panda_defconfig2
-rw-r--r--configs/omap4_sdp4430_defconfig1
-rw-r--r--configs/omap5_uevm_defconfig1
-rw-r--r--configs/p212_defconfig1
-rw-r--r--configs/p2371-0000_defconfig1
-rw-r--r--configs/p2371-2180_defconfig1
-rw-r--r--configs/p2571_defconfig1
-rw-r--r--configs/paz00_defconfig1
-rw-r--r--configs/pcm051_rev1_defconfig3
-rw-r--r--configs/pcm051_rev3_defconfig3
-rw-r--r--configs/peach-pi_defconfig1
-rw-r--r--configs/peach-pit_defconfig1
-rw-r--r--configs/pengwyn_defconfig3
-rw-r--r--configs/pepper_defconfig2
-rw-r--r--configs/phycore-rk3288_defconfig1
-rw-r--r--configs/pic32mzdask_defconfig1
-rw-r--r--configs/pico-hobbit-imx6ul_defconfig3
-rw-r--r--configs/pico-hobbit-imx7d_defconfig3
-rw-r--r--configs/pico-imx6ul_defconfig3
-rw-r--r--configs/pico-imx7d_defconfig3
-rw-r--r--configs/pico-pi-imx6ul_defconfig3
-rw-r--r--configs/pico-pi-imx7d_defconfig3
-rw-r--r--configs/picosam9g45_defconfig6
-rw-r--r--configs/plutux_defconfig1
-rw-r--r--configs/poplar_defconfig1
-rw-r--r--configs/popmetal-rk3288_defconfig1
-rw-r--r--configs/puma-rk3399_defconfig3
-rw-r--r--configs/pxm2_defconfig2
-rw-r--r--configs/qemu_arm64_defconfig15
-rw-r--r--configs/qemu_arm_defconfig14
-rw-r--r--configs/r8a7795_salvator-x_defconfig1
-rw-r--r--configs/r8a7795_ulcb_defconfig1
-rw-r--r--configs/r8a77965_salvator-x_defconfig1
-rw-r--r--configs/r8a7796_salvator-x_defconfig1
-rw-r--r--configs/r8a7796_ulcb_defconfig1
-rw-r--r--configs/r8a77990_ebisu_defconfig1
-rw-r--r--configs/riotboard_defconfig1
-rw-r--r--configs/riotboard_spl_defconfig47
-rw-r--r--configs/rock2_defconfig1
-rw-r--r--configs/rock960-rk3399_defconfig10
-rw-r--r--configs/rpi_0_w_defconfig1
-rw-r--r--configs/rpi_2_defconfig1
-rw-r--r--configs/rpi_3_32b_defconfig1
-rw-r--r--configs/rpi_3_defconfig1
-rw-r--r--configs/rpi_defconfig1
-rw-r--r--configs/rut_defconfig2
-rw-r--r--configs/sagem_f@st1704_ram_defconfig8
-rw-r--r--configs/sandbox64_defconfig3
-rw-r--r--configs/sandbox_defconfig9
-rw-r--r--configs/sandbox_flattree_defconfig1
-rw-r--r--configs/sandbox_noblk_defconfig1
-rw-r--r--configs/sandbox_spl_defconfig1
-rw-r--r--configs/seaboard_defconfig1
-rw-r--r--configs/sfr_nb4-ser_ram_defconfig8
-rw-r--r--configs/smartweb_defconfig4
-rw-r--r--configs/smdk5250_defconfig1
-rw-r--r--configs/smdk5420_defconfig1
-rw-r--r--configs/snow_defconfig1
-rw-r--r--configs/socfpga_arria5_defconfig1
-rw-r--r--configs/socfpga_cyclone5_defconfig1
-rw-r--r--configs/socfpga_de0_nano_soc_defconfig1
-rw-r--r--configs/socfpga_de10_nano_defconfig1
-rw-r--r--configs/socfpga_de1_soc_defconfig1
-rw-r--r--configs/socfpga_sockit_defconfig1
-rw-r--r--configs/socfpga_socrates_defconfig1
-rw-r--r--configs/socfpga_vining_fpga_defconfig1
-rw-r--r--configs/spear300_usbtty_defconfig2
-rw-r--r--configs/spear300_usbtty_nand_defconfig2
-rw-r--r--configs/spear310_usbtty_defconfig2
-rw-r--r--configs/spear310_usbtty_nand_defconfig2
-rw-r--r--configs/spear310_usbtty_pnor_defconfig2
-rw-r--r--configs/spear320_usbtty_defconfig2
-rw-r--r--configs/spear320_usbtty_nand_defconfig2
-rw-r--r--configs/spear320_usbtty_pnor_defconfig2
-rw-r--r--configs/spear600_usbtty_defconfig2
-rw-r--r--configs/spear600_usbtty_nand_defconfig2
-rw-r--r--configs/spring_defconfig1
-rw-r--r--configs/stih410-b2260_defconfig1
-rw-r--r--configs/stm32mp15_basic_defconfig1
-rw-r--r--configs/syzygy_hub_defconfig1
-rw-r--r--configs/taurus_defconfig2
-rw-r--r--configs/tbs2910_defconfig1
-rw-r--r--configs/tec-ng_defconfig1
-rw-r--r--configs/tec_defconfig1
-rw-r--r--configs/ti814x_evm_defconfig2
-rw-r--r--configs/tinker-rk3288_defconfig1
-rw-r--r--configs/topic_miami_defconfig1
-rw-r--r--configs/topic_miamilite_defconfig1
-rw-r--r--configs/topic_miamiplus_defconfig1
-rw-r--r--configs/trimslice_defconfig1
-rw-r--r--configs/turris_mox_defconfig1
-rw-r--r--configs/turris_omnia_defconfig1
-rw-r--r--configs/uniphier_ld4_sld8_defconfig2
-rw-r--r--configs/uniphier_v7_defconfig2
-rw-r--r--configs/uniphier_v8_defconfig2
-rw-r--r--configs/usbarmory_defconfig1
-rw-r--r--configs/venice2_defconfig1
-rw-r--r--configs/ventana_defconfig1
-rw-r--r--configs/vyasa-rk3288_defconfig1
-rw-r--r--configs/wandboard_defconfig1
-rw-r--r--configs/warp7_defconfig2
-rw-r--r--configs/xilinx_zynqmp_mini_qspi_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu100_revC_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu102_rev1_0_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu102_revA_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu102_revB_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu104_revA_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu104_revC_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu106_revA_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu111_revA_defconfig1
-rw-r--r--configs/zynq_cc108_defconfig1
-rw-r--r--configs/zynq_cse_nand_defconfig1
-rw-r--r--configs/zynq_cse_nor_defconfig1
-rw-r--r--configs/zynq_cse_qspi_defconfig1
-rw-r--r--configs/zynq_dlc20_rev1_0_defconfig1
-rw-r--r--configs/zynq_microzed_defconfig1
-rw-r--r--configs/zynq_minized_defconfig1
-rw-r--r--configs/zynq_picozed_defconfig1
-rw-r--r--configs/zynq_z_turn_defconfig1
-rw-r--r--configs/zynq_zc702_defconfig1
-rw-r--r--configs/zynq_zc706_defconfig1
-rw-r--r--configs/zynq_zed_defconfig1
-rw-r--r--configs/zynq_zybo_defconfig1
-rw-r--r--configs/zynq_zybo_z7_defconfig1
-rw-r--r--doc/README.ae3502
-rw-r--r--doc/README.commands38
-rw-r--r--doc/README.odroid7
-rw-r--r--doc/README.video20
-rw-r--r--doc/device-tree-bindings/w1/mxc-w1.txt37
-rw-r--r--doc/driver-model/MIGRATION.txt28
-rw-r--r--doc/imx/mkimage/imximage.txt2
-rw-r--r--doc/imx/mkimage/mxsimage.txt4
-rw-r--r--drivers/Makefile7
-rw-r--r--drivers/clk/imx/clk-imx8.c2
-rw-r--r--drivers/clk/uniphier/clk-uniphier-sys.c8
-rw-r--r--drivers/cpu/Kconfig6
-rw-r--r--drivers/cpu/Makefile1
-rw-r--r--drivers/cpu/riscv_cpu.c116
-rw-r--r--drivers/ddr/Kconfig1
-rw-r--r--drivers/ddr/imx/Kconfig1
-rw-r--r--drivers/ddr/imx/imx8m/Kconfig22
-rw-r--r--drivers/ddr/imx/imx8m/Makefile11
-rw-r--r--drivers/ddr/imx/imx8m/ddr4_init.c113
-rw-r--r--drivers/ddr/imx/imx8m/ddrphy_csr.c732
-rw-r--r--drivers/ddr/imx/imx8m/ddrphy_train.c86
-rw-r--r--drivers/ddr/imx/imx8m/ddrphy_utils.c186
-rw-r--r--drivers/ddr/imx/imx8m/helper.c170
-rw-r--r--drivers/ddr/imx/imx8m/lpddr4_init.c188
-rw-r--r--drivers/dma/Kconfig9
-rw-r--r--drivers/dma/Makefile1
-rw-r--r--drivers/dma/bcm6348-iudma.c642
-rw-r--r--drivers/fpga/Kconfig11
-rw-r--r--drivers/fpga/Makefile1
-rw-r--r--drivers/fpga/altera.c6
-rw-r--r--drivers/fpga/stratix10.c288
-rw-r--r--drivers/gpio/Kconfig7
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-mscc-bitbang-spi.c122
-rw-r--r--drivers/gpio/mxc_gpio.c18
-rw-r--r--drivers/gpio/stm32f7_gpio.c22
-rw-r--r--drivers/misc/Kconfig6
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/imx8/scu.c26
-rw-r--r--drivers/misc/imx8/scu_api.c4
-rw-r--r--drivers/misc/jz4780_efuse.c103
-rw-r--r--drivers/misc/mxc_ocotp.c6
-rw-r--r--drivers/mmc/Kconfig6
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/fsl_esdhc.c18
-rw-r--r--drivers/mmc/jz_mmc.c488
-rw-r--r--drivers/mmc/mmc.c4
-rw-r--r--drivers/mmc/sunxi_mmc.c50
-rw-r--r--drivers/mtd/nand/raw/Kconfig11
-rw-r--r--drivers/mtd/nand/raw/denali.c53
-rw-r--r--drivers/mtd/nand/raw/denali.h1
-rw-r--r--drivers/mtd/nand/raw/denali_dt.c40
-rw-r--r--drivers/mtd/nand/raw/nand_ids.c4
-rw-r--r--drivers/mtd/nand/raw/vf610_nfc.c49
-rw-r--r--drivers/net/Kconfig18
-rw-r--r--drivers/net/Makefile2
-rw-r--r--drivers/net/bcm6348-eth.c537
-rw-r--r--drivers/net/bcm6368-eth.c625
-rw-r--r--drivers/net/fec_mxc.c2
-rw-r--r--drivers/net/phy/phy.c3
-rw-r--r--drivers/pinctrl/Kconfig11
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/mscc/Kconfig22
-rw-r--r--drivers/pinctrl/mscc/Makefile5
-rw-r--r--drivers/pinctrl/mscc/mscc-common.c236
-rw-r--r--drivers/pinctrl/mscc/mscc-common.h51
-rw-r--r--drivers/pinctrl/mscc/pinctrl-luton.c172
-rw-r--r--drivers/pinctrl/mscc/pinctrl-ocelot.c188
-rw-r--r--drivers/pinctrl/nxp/Kconfig14
-rw-r--r--drivers/pinctrl/nxp/Makefile1
-rw-r--r--drivers/pinctrl/nxp/pinctrl-vf610.c40
-rw-r--r--drivers/pinctrl/pinctrl-uclass.c22
-rw-r--r--drivers/pinctrl/rockchip/pinctrl_rk3399.c237
-rw-r--r--drivers/power/regulator/Kconfig7
-rw-r--r--drivers/power/regulator/Makefile2
-rw-r--r--drivers/power/regulator/regulator-uclass.c2
-rw-r--r--drivers/ram/rockchip/sdram_rk3128.c2
-rw-r--r--drivers/ram/rockchip/sdram_rk3188.c2
-rw-r--r--drivers/ram/rockchip/sdram_rk322x.c2
-rw-r--r--drivers/ram/rockchip/sdram_rk3288.c2
-rw-r--r--drivers/ram/rockchip/sdram_rk3328.c2
-rw-r--r--drivers/ram/rockchip/sdram_rk3399.c2
-rw-r--r--drivers/serial/Kconfig13
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial_sifive.c215
-rw-r--r--drivers/spi/designware_spi.c8
-rw-r--r--drivers/spi/sun4i_spi.c3
-rw-r--r--drivers/timer/Kconfig7
-rw-r--r--drivers/timer/Makefile1
-rw-r--r--drivers/timer/riscv_timer.c56
-rw-r--r--drivers/usb/gadget/Makefile2
-rw-r--r--drivers/usb/gadget/udc/Makefile3
-rw-r--r--drivers/usb/gadget/udc/udc-uclass.c7
-rw-r--r--drivers/usb/host/xhci-mem.c3
-rw-r--r--drivers/video/fonts/Kconfig1
-rw-r--r--drivers/w1/Kconfig14
-rw-r--r--drivers/w1/Makefile1
-rw-r--r--drivers/w1/mxc_w1.c232
-rw-r--r--drivers/watchdog/Kconfig6
-rw-r--r--drivers/watchdog/Makefile2
-rw-r--r--drivers/watchdog/imx_watchdog.c9
-rw-r--r--env/env.c3
-rw-r--r--env/sata.c2
-rw-r--r--fs/cbfs/cbfs.c7
-rw-r--r--fs/fat/fat.c5
-rw-r--r--include/altera.h8
-rw-r--r--include/bootm.h2
-rw-r--r--include/cbfs.h14
-rw-r--r--include/configs/bmips_common.h6
-rw-r--r--include/configs/ci20.h72
-rw-r--r--include/configs/edison.h10
-rw-r--r--include/configs/embestmx6boards.h13
-rw-r--r--include/configs/helios4.h2
-rw-r--r--include/configs/imx8mq_evk.h246
-rw-r--r--include/configs/m53menlo.h3
-rw-r--r--include/configs/mt7623.h2
-rw-r--r--include/configs/odroid.h4
-rw-r--r--include/configs/odroid_xu3.h5
-rw-r--r--include/configs/omap3_igep00x0.h4
-rw-r--r--include/configs/pcm058.h1
-rw-r--r--include/configs/pico-imx7d.h14
-rw-r--r--include/configs/poplar.h6
-rw-r--r--include/configs/s5p_goni.h4
-rw-r--r--include/configs/s5pc210_universal.h4
-rw-r--r--include/configs/tbs2910.h2
-rw-r--r--include/configs/trats.h4
-rw-r--r--include/configs/trats2.h4
-rw-r--r--include/configs/uniphier.h26
-rw-r--r--include/configs/vcoreiii.h82
-rw-r--r--include/cpu.h3
-rw-r--r--include/dm/pinctrl.h12
-rw-r--r--include/dt-bindings/clock/bcm6318-clock.h11
-rw-r--r--include/dt-bindings/clock/jz4780-cgu.h89
-rw-r--r--include/dt-bindings/dma/bcm6318-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm63268-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6328-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6338-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6348-dma.h16
-rw-r--r--include/dt-bindings/dma/bcm6358-dma.h16
-rw-r--r--include/dt-bindings/dma/bcm6362-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6368-dma.h14
-rw-r--r--include/environment/ti/boot.h7
-rw-r--r--include/imximage.h17
-rw-r--r--include/linux/kernel.h12
-rw-r--r--include/spl.h13
-rw-r--r--include/vxworks.h1
-rw-r--r--lib/crc32.c3
-rw-r--r--lib/efi_loader/efi_runtime.c34
-rw-r--r--lib/efi_selftest/efi_selftest_block_device.c10
-rw-r--r--scripts/Makefile.spl2
-rwxr-xr-xscripts/check-config.sh9
-rw-r--r--scripts/config_whitelist.txt10
-rw-r--r--test/dm/video.c6
-rw-r--r--test/overlay/Kconfig7
-rw-r--r--tools/Makefile1
-rw-r--r--tools/imagetool.h1
-rw-r--r--tools/imx8image.c2
-rwxr-xr-xtools/imx8m_image.sh43
-rw-r--r--tools/imx8mimage.c623
-rwxr-xr-xtools/imx_cntr_image.sh2
-rw-r--r--tools/mkimage.c7
724 files changed, 21969 insertions, 1767 deletions
diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
new file mode 100644
index 0000000000..23599b97c0
--- /dev/null
+++ b/.github/pull_request_template.md
@@ -0,0 +1,3 @@
1Please do not submit a Pull Request via github. Our project makes use of
2mailing lists for patch submission and review. For more details please
3see https://www.denx.de/wiki/U-Boot/Patches
diff --git a/Android.bp b/Android.bp
index 5bb58e7ae5..25c6d9af5a 100644
--- a/Android.bp
+++ b/Android.bp
@@ -57,6 +57,7 @@ cc_binary_host {
57 "tools/image-host.c", 57 "tools/image-host.c",
58 "tools/imagetool.c", 58 "tools/imagetool.c",
59 "tools/imx8image.c", 59 "tools/imx8image.c",
60 "tools/imx8mimage.c",
60 "tools/imximage.c", 61 "tools/imximage.c",
61 "tools/kwbimage.c", 62 "tools/kwbimage.c",
62 "tools/libfdt/fdt.c", 63 "tools/libfdt/fdt.c",
diff --git a/Kconfig b/Kconfig
index 9e0b8af40a..aff7b2e00a 100644
--- a/Kconfig
+++ b/Kconfig
@@ -251,6 +251,16 @@ config FIT
251 251
252if FIT 252if FIT
253 253
254config FIT_EXTERNAL_OFFSET
255 hex "Text Base"
256 default 0x0
257 help
258 This specifies a data offset in fit image.
259 The offset is from data payload offset to the beginning of
260 fit image header. When specifies a offset, specific data
261 could be put in the hole between data payload and fit image
262 header, such as CSF data on i.MX platform.
263
254config FIT_ENABLE_SHA256_SUPPORT 264config FIT_ENABLE_SHA256_SUPPORT
255 bool "Support SHA256 checksum of FIT image contents" 265 bool "Support SHA256 checksum of FIT image contents"
256 default y 266 default y
diff --git a/MAINTAINERS b/MAINTAINERS
index 0fb089807c..f86fdf9c33 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -123,7 +123,7 @@ F: drivers/spi/bcmstb_spi.c
123ARM FREESCALE IMX 123ARM FREESCALE IMX
124M: Stefano Babic <sbabic@denx.de> 124M: Stefano Babic <sbabic@denx.de>
125M: Fabio Estevam <fabio.estevam@nxp.com> 125M: Fabio Estevam <fabio.estevam@nxp.com>
126R: NXP Linux Team <linux-imx@nxp.com> 126R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
127S: Maintained 127S: Maintained
128T: git git://git.denx.de/u-boot-imx.git 128T: git git://git.denx.de/u-boot-imx.git
129F: arch/arm/cpu/arm1136/mx*/ 129F: arch/arm/cpu/arm1136/mx*/
@@ -512,6 +512,24 @@ S: Maintained
512T: git git://git.denx.de/u-boot-mips.git 512T: git git://git.denx.de/u-boot-mips.git
513F: arch/mips/ 513F: arch/mips/
514 514
515MIPS MSCC
516M: Gregory CLEMENT <gregory.clement@bootlin.com>
517M: Lars Povlsen <lars.povlsen@microchip.com>
518M: Horatiu Vultur <horatiu.vultur@microchip.com>
519S: Maintained
520F: arch/mips/mach-mscc/
521F: arch/mips/dts/luton*
522F: arch/mips/dts/mscc*
523F: arch/mips/dts/ocelot*
524F: board/mscc/
525F: configs/mscc*
526F: include/configs/vcoreiii.h
527
528MIPS JZ4780
529M: Ezequiel Garcia <ezequiel@collabora.com>
530S: Maintained
531F: arch/mips/mach-jz47xx/
532
515MMC 533MMC
516M: Jaehoon Chung <jh80.chung@samsung.com> 534M: Jaehoon Chung <jh80.chung@samsung.com>
517S: Maintained 535S: Maintained
diff --git a/Makefile b/Makefile
index a8461dd611..6aa08964ff 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
3VERSION = 2019 3VERSION = 2019
4PATCHLEVEL = 01 4PATCHLEVEL = 01
5SUBLEVEL = 5SUBLEVEL =
6EXTRAVERSION = -rc2 6EXTRAVERSION =
7NAME = 7NAME =
8 8
9# *DOCUMENTATION* 9# *DOCUMENTATION*
@@ -712,8 +712,8 @@ libs-y += drivers/usb/dwc3/
712libs-y += drivers/usb/common/ 712libs-y += drivers/usb/common/
713libs-y += drivers/usb/emul/ 713libs-y += drivers/usb/emul/
714libs-y += drivers/usb/eth/ 714libs-y += drivers/usb/eth/
715libs-y += drivers/usb/gadget/ 715libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
716libs-y += drivers/usb/gadget/udc/ 716libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
717libs-y += drivers/usb/host/ 717libs-y += drivers/usb/host/
718libs-y += drivers/usb/musb/ 718libs-y += drivers/usb/musb/
719libs-y += drivers/usb/musb-new/ 719libs-y += drivers/usb/musb-new/
@@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
893 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) 893 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
894 894
895quiet_cmd_mkfitimage = MKIMAGE $@ 895quiet_cmd_mkfitimage = MKIMAGE $@
896cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \ 896cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
897 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) 897 >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
898 898
899quiet_cmd_cat = CAT $@ 899quiet_cmd_cat = CAT $@
@@ -938,7 +938,8 @@ ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
938 @echo >&2 "====================================================" 938 @echo >&2 "===================================================="
939endif 939endif
940endif 940endif
941ifeq ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y) 941ifeq ($(CONFIG_LIBATA)$(CONFIG_MVSATA_IDE),y)
942ifneq ($(CONFIG_DM_SCSI),y)
942 @echo >&2 "===================== WARNING ======================" 943 @echo >&2 "===================== WARNING ======================"
943 @echo >&2 "This board does not use CONFIG_DM_SCSI. Please update" 944 @echo >&2 "This board does not use CONFIG_DM_SCSI. Please update"
944 @echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release." 945 @echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release."
@@ -946,6 +947,27 @@ ifeq ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y)
946 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." 947 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
947 @echo >&2 "====================================================" 948 @echo >&2 "===================================================="
948endif 949endif
950endif
951ifeq ($(CONFIG_PCI),y)
952ifneq ($(CONFIG_DM_PCI),y)
953 @echo >&2 "===================== WARNING ======================"
954 @echo >&2 "This board does not use CONFIG_DM_PCI Please update"
955 @echo >&2 "the board to use CONFIG_DM_PCI before the v2019.07 release."
956 @echo >&2 "Failure to update by the deadline may result in board removal."
957 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
958 @echo >&2 "===================================================="
959endif
960endif
961ifneq ($(CONFIG_LCD)$(CONFIG_VIDEO),)
962ifneq ($(CONFIG_DM_VIDEO),y)
963 @echo >&2 "===================== WARNING ======================"
964 @echo >&2 "This board does not use CONFIG_DM_VIDEO Please update"
965 @echo >&2 "the board to use CONFIG_DM_VIDEO before the v2019.07 release."
966 @echo >&2 "Failure to update by the deadline may result in board removal."
967 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
968 @echo >&2 "===================================================="
969endif
970endif
949ifeq ($(CONFIG_OF_EMBED),y) 971ifeq ($(CONFIG_OF_EMBED),y)
950 @echo >&2 "===================== WARNING ======================" 972 @echo >&2 "===================== WARNING ======================"
951 @echo >&2 "CONFIG_OF_EMBED is enabled. This option should only" 973 @echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
@@ -954,6 +976,27 @@ ifeq ($(CONFIG_OF_EMBED),y)
954 @echo >&2 "See doc/README.fdt-control for more info." 976 @echo >&2 "See doc/README.fdt-control for more info."
955 @echo >&2 "====================================================" 977 @echo >&2 "===================================================="
956endif 978endif
979ifeq ($(CONFIG_SPI),y)
980ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
981 @echo >&2 "===================== WARNING ======================"
982 @echo >&2 "This board does not use CONFIG_DM_SPI. Please update"
983 @echo >&2 "the board before v2019.04 for no dm conversion"
984 @echo >&2 "and v2019.07 for partially dm converted drivers."
985 @echo >&2 "Failure to update can lead to driver/board removal"
986 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
987 @echo >&2 "===================================================="
988endif
989endif
990ifeq ($(CONFIG_SPI_FLASH),y)
991ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy)
992 @echo >&2 "===================== WARNING ======================"
993 @echo >&2 "This board does not use CONFIG_DM_SPI_FLASH. Please update"
994 @echo >&2 "the board to use CONFIG_SPI_FLASH before the v2019.07 release."
995 @echo >&2 "Failure to update by the deadline may result in board removal."
996 @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
997 @echo >&2 "===================================================="
998endif
999endif
957 @# Check that this build does not use CONFIG options that we do not 1000 @# Check that this build does not use CONFIG options that we do not
958 @# know about unless they are in Kconfig. All the existing CONFIG 1001 @# know about unless they are in Kconfig. All the existing CONFIG
959 @# options are whitelisted, so new ones should not be added. 1002 @# options are whitelisted, so new ones should not be added.
@@ -1112,6 +1155,9 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
1112else 1155else
1113ifneq ($(CONFIG_SPL_FIT_GENERATOR),"") 1156ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
1114U_BOOT_ITS := u-boot.its 1157U_BOOT_ITS := u-boot.its
1158ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
1159U_BOOT_ITS_DEPS += u-boot-nodtb.bin
1160endif
1115ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py") 1161ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
1116U_BOOT_ITS_DEPS += u-boot 1162U_BOOT_ITS_DEPS += u-boot
1117endif 1163endif
@@ -1207,6 +1253,11 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
1207SPL: spl/u-boot-spl.bin FORCE 1253SPL: spl/u-boot-spl.bin FORCE
1208 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ 1254 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
1209 1255
1256ifeq ($(CONFIG_ARCH_IMX8M), y)
1257flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
1258 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
1259endif
1260
1210u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE 1261u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
1211 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ 1262 $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
1212 1263
diff --git a/api/api_storage.c b/api/api_storage.c
index 8aeeda2715..2b90c18aae 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -99,6 +99,7 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
99{ 99{
100 struct blk_desc *dd; 100 struct blk_desc *dd;
101 int found = 0; 101 int found = 0;
102 int found_last = 0;
102 int i = 0; 103 int i = 0;
103 104
104 /* Wasn't configured for this type, return 0 directly */ 105 /* Wasn't configured for this type, return 0 directly */
@@ -111,9 +112,13 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
111 if (di->cookie == 112 if (di->cookie ==
112 (void *)blk_get_dev(specs[type].name, i)) { 113 (void *)blk_get_dev(specs[type].name, i)) {
113 i += 1; 114 i += 1;
115 found_last = 1;
114 break; 116 break;
115 } 117 }
116 } 118 }
119
120 if (!found_last)
121 i = 0;
117 } 122 }
118 123
119 for (; i < specs[type].max_dev; i++) { 124 for (; i < specs[type].max_dev; i++) {
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cb7ec58079..d6b1629a00 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -607,6 +607,7 @@ config ARCH_EXYNOS
607 select DM_SPI 607 select DM_SPI
608 select DM_SPI_FLASH 608 select DM_SPI_FLASH
609 select SPI 609 select SPI
610 imply SYS_THUMB_BUILD
610 imply CMD_DM 611 imply CMD_DM
611 imply FAT_WRITE 612 imply FAT_WRITE
612 613
@@ -694,7 +695,7 @@ config ARCH_IMX8
694 select DM 695 select DM
695 select OF_CONTROL 696 select OF_CONTROL
696 697
697config ARCH_MX8M 698config ARCH_IMX8M
698 bool "NXP i.MX8M platform" 699 bool "NXP i.MX8M platform"
699 select ARM64 700 select ARM64
700 select DM 701 select DM
@@ -874,7 +875,6 @@ config ARCH_SUNXI
874 imply PRE_CONSOLE_BUFFER 875 imply PRE_CONSOLE_BUFFER
875 imply SPL_GPIO_SUPPORT 876 imply SPL_GPIO_SUPPORT
876 imply SPL_LIBCOMMON_SUPPORT 877 imply SPL_LIBCOMMON_SUPPORT
877 imply SPL_LIBDISK_SUPPORT
878 imply SPL_LIBGENERIC_SUPPORT 878 imply SPL_LIBGENERIC_SUPPORT
879 imply SPL_MMC_SUPPORT if MMC 879 imply SPL_MMC_SUPPORT if MMC
880 imply SPL_POWER_SUPPORT 880 imply SPL_POWER_SUPPORT
@@ -1451,7 +1451,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig"
1451 1451
1452source "arch/arm/mach-imx/imx8/Kconfig" 1452source "arch/arm/mach-imx/imx8/Kconfig"
1453 1453
1454source "arch/arm/mach-imx/mx8m/Kconfig" 1454source "arch/arm/mach-imx/imx8m/Kconfig"
1455 1455
1456source "arch/arm/mach-imx/mxs/Kconfig" 1456source "arch/arm/mach-imx/mxs/Kconfig"
1457 1457
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c38ef3cb69..87d9d4b9f7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -103,11 +103,11 @@ libs-y += arch/arm/cpu/
103libs-y += arch/arm/lib/ 103libs-y += arch/arm/lib/
104 104
105ifeq ($(CONFIG_SPL_BUILD),y) 105ifeq ($(CONFIG_SPL_BUILD),y)
106ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) 106ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
107libs-y += arch/arm/mach-imx/ 107libs-y += arch/arm/mach-imx/
108endif 108endif
109else 109else
110ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) 110ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
111libs-y += arch/arm/mach-imx/ 111libs-y += arch/arm/mach-imx/
112endif 112endif
113endif 113endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
index a6ef830069..9583bf743e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
@@ -8,3 +8,14 @@ Freescale LayerScape with Chassis Generation 2
8 8
9This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, 9This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
10for example LS1043A. 10for example LS1043A.
11
12Watchdog support Overview
13-------------------
14Support watchdog driver for LSCH2. The driver is disabled in default.
15You can enable it by setting CONFIG_IMX_WATCHDOG.
16Use following config to set watchdog timeout, if this config is not defined,
17the default timeout value is 128s which is the maximum. Set 10 seconds for
18example:
19 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000
20Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the
21watchdog will not be fed in u-boot.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dc6f6b233a..dda4e59491 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -466,6 +466,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
466 466
467dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb 467dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
468 468
469dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
470
469dtb-$(CONFIG_RCAR_GEN3) += \ 471dtb-$(CONFIG_RCAR_GEN3) += \
470 r8a7795-h3ulcb-u-boot.dtb \ 472 r8a7795-h3ulcb-u-boot.dtb \
471 r8a7795-salvator-x-u-boot.dtb \ 473 r8a7795-salvator-x-u-boot.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
new file mode 100644
index 0000000000..4a08099b3c
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -0,0 +1,414 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6/dts-v1/;
7
8/* First 128KB is for PSCI ATF. */
9/memreserve/ 0x40000000 0x00020000;
10
11#include "fsl-imx8mq.dtsi"
12
13/ {
14 model = "Freescale i.MX8MQ EVK";
15 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16
17 chosen {
18 bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 reg_usdhc2_vmmc: usdhc2_vmmc {
27 compatible = "regulator-fixed";
28 regulator-name = "VSD_3V3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32 enable-active-high;
33 };
34 };
35
36 pwmleds {
37 compatible = "pwm-leds";
38
39 ledpwm2 {
40 label = "PWM2";
41 pwms = <&pwm2 0 50000>;
42 max-brightness = <255>;
43 };
44 };
45};
46
47&iomuxc {
48 pinctrl-names = "default";
49
50 imx8mq-evk {
51 pinctrl_fec1: fec1grp {
52 fsl,pins = <
53 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
54 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
55 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
56 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
57 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
58 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
59 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
60 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
61 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
62 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
63 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
64 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
65 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
66 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
67 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
68 >;
69 };
70
71 pinctrl_i2c1: i2c1grp {
72 fsl,pins = <
73 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
74 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
75 >;
76 };
77
78 pinctrl_i2c2: i2c2grp {
79 fsl,pins = <
80 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
81 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
82 >;
83 };
84
85 pinctrl_pwm2: pwm2grp {
86 fsl,pins = <
87 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
88 >;
89 };
90
91 pinctrl_qspi: qspigrp {
92 fsl,pins = <
93 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
94 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
95 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
96 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
97 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
98 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
99
100 >;
101 };
102
103 pinctrl_usdhc1: usdhc1grp {
104 fsl,pins = <
105 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
106 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
107 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
108 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
109 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
110 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
111 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
112 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
113 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
114 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
115 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
116 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
117 >;
118 };
119
120 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
121 fsl,pins = <
122 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
123 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
124 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
125 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
126 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
127 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
128 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
129 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
130 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
131 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
132 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
133 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
134 >;
135 };
136
137 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
138 fsl,pins = <
139 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
140 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
141 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
142 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
143 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
144 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
145 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
146 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
147 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
148 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
149 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
150 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
151 >;
152 };
153
154 pinctrl_usdhc2_gpio: usdhc2grpgpio {
155 fsl,pins = <
156 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
157 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
158 >;
159 };
160
161 pinctrl_usdhc2: usdhc2grp {
162 fsl,pins = <
163 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
164 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
165 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
166 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
167 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
168 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
169 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
170 >;
171 };
172
173 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
174 fsl,pins = <
175 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
176 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
177 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
178 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
179 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
180 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
181 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
182 >;
183 };
184
185 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
186 fsl,pins = <
187 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
188 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
189 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
190 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
191 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
192 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
193 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
194 >;
195 };
196
197 pinctrl_sai2: sai2grp {
198 fsl,pins = <
199 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
200 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
201 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
202 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
203 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
204 >;
205 };
206
207 pinctrl_wdog: wdoggrp {
208 fsl,pins = <
209 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
210 >;
211 };
212 };
213};
214
215&fec1 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_fec1>;
218 phy-mode = "rgmii-id";
219 phy-handle = <&ethphy0>;
220 fsl,magic-packet;
221 status = "okay";
222
223 mdio {
224 #address-cells = <1>;
225 #size-cells = <0>;
226
227 ethphy0: ethernet-phy@0 {
228 compatible = "ethernet-phy-ieee802.3-c22";
229 reg = <0>;
230 at803x,led-act-blind-workaround;
231 at803x,eee-disabled;
232 };
233 };
234};
235
236&i2c1 {
237 clock-frequency = <100000>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c1>;
240 status = "okay";
241
242 pmic: pfuze100@08 {
243 compatible = "fsl,pfuze100";
244 reg = <0x08>;
245
246 regulators {
247 sw1a_reg: sw1ab {
248 regulator-min-microvolt = <300000>;
249 regulator-max-microvolt = <1875000>;
250 regulator-always-on;
251 };
252
253 sw1c_reg: sw1c {
254 regulator-min-microvolt = <300000>;
255 regulator-max-microvolt = <1875000>;
256 regulator-always-on;
257 };
258
259 sw2_reg: sw2 {
260 regulator-min-microvolt = <800000>;
261 regulator-max-microvolt = <3300000>;
262 regulator-always-on;
263 };
264
265 sw3a_reg: sw3ab {
266 regulator-min-microvolt = <400000>;
267 regulator-max-microvolt = <1975000>;
268 regulator-always-on;
269 };
270
271 sw4_reg: sw4 {
272 regulator-min-microvolt = <800000>;
273 regulator-max-microvolt = <3300000>;
274 regulator-always-on;
275 };
276
277 swbst_reg: swbst {
278 regulator-min-microvolt = <5000000>;
279 regulator-max-microvolt = <5150000>;
280 };
281
282 snvs_reg: vsnvs {
283 regulator-min-microvolt = <1000000>;
284 regulator-max-microvolt = <3000000>;
285 regulator-always-on;
286 };
287
288 vref_reg: vrefddr {
289 regulator-always-on;
290 };
291
292 vgen1_reg: vgen1 {
293 regulator-min-microvolt = <800000>;
294 regulator-max-microvolt = <1550000>;
295 };
296
297 vgen2_reg: vgen2 {
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1550000>;
300 regulator-always-on;
301 };
302
303 vgen3_reg: vgen3 {
304 regulator-min-microvolt = <1800000>;
305 regulator-max-microvolt = <3300000>;
306 regulator-always-on;
307 };
308
309 vgen4_reg: vgen4 {
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-always-on;
313 };
314
315 vgen5_reg: vgen5 {
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3300000>;
318 regulator-always-on;
319 };
320
321 vgen6_reg: vgen6 {
322 regulator-min-microvolt = <1800000>;
323 regulator-max-microvolt = <3300000>;
324 };
325 };
326 };
327};
328
329&i2c2 {
330 clock-frequency = <100000>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_i2c2>;
333 status = "disabled";
334};
335
336&pwm2 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_pwm2>;
339 status = "okay";
340};
341
342&lcdif {
343 status = "okay";
344 disp-dev = "mipi_dsi_northwest";
345 display = <&display0>;
346
347 display0: display@0 {
348 bits-per-pixel = <24>;
349 bus-width = <24>;
350
351 display-timings {
352 native-mode = <&timing0>;
353 timing0: timing0 {
354 clock-frequency = <9200000>;
355 hactive = <480>;
356 vactive = <272>;
357 hfront-porch = <8>;
358 hback-porch = <4>;
359 hsync-len = <41>;
360 vback-porch = <2>;
361 vfront-porch = <4>;
362 vsync-len = <10>;
363
364 hsync-active = <0>;
365 vsync-active = <0>;
366 de-active = <1>;
367 pixelclk-active = <0>;
368 };
369 };
370 };
371};
372
373&qspi {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_qspi>;
376 status = "okay";
377
378 flash0: n25q256a@0 {
379 reg = <0>;
380 #address-cells = <1>;
381 #size-cells = <1>;
382 compatible = "micron,n25q256a";
383 spi-max-frequency = <29000000>;
384 spi-nor,ddr-quad-read-dummy = <6>;
385 };
386};
387
388&usdhc1 {
389 pinctrl-names = "default", "state_100mhz", "state_200mhz";
390 pinctrl-0 = <&pinctrl_usdhc1>;
391 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
392 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
393 bus-width = <8>;
394 non-removable;
395 status = "okay";
396};
397
398&usdhc2 {
399 pinctrl-names = "default", "state_100mhz", "state_200mhz";
400 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
401 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
402 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
403 bus-width = <4>;
404 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
405 vmmc-supply = <&reg_usdhc2_vmmc>;
406 status = "okay";
407};
408
409&wdog1 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_wdog>;
412 fsl,ext-reset-output;
413 status = "okay";
414};
diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
new file mode 100644
index 0000000000..c46eb3f38d
--- /dev/null
+++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6/* wifi module */
7&sd_emmc_b {
8 status = "disabled";
9};
10
11/* emmc storage */
12&sd_emmc_c {
13 status = "okay";
14};
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index 1eb50cd438..54a7285e6e 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -12,6 +12,11 @@
12 tick-timer = &timer2; 12 tick-timer = &timer2;
13 }; 13 };
14 14
15 aliases {
16 usb0 = &usb1;
17 usb1 = &usb2;
18 };
19
15 ocp { 20 ocp {
16 u-boot,dm-spl; 21 u-boot,dm-spl;
17 22
diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi
index 9a61fbb453..8304f67192 100644
--- a/arch/arm/dts/rk3399-puma.dtsi
+++ b/arch/arm/dts/rk3399-puma.dtsi
@@ -172,10 +172,7 @@
172 regulator-max-microvolt = <1400000>; 172 regulator-max-microvolt = <1400000>;
173 regulator-always-on; 173 regulator-always-on;
174 regulator-boot-on; 174 regulator-boot-on;
175 175 regulator-init-microvolt = <950000>;
176 /* for rockchip boot on */
177 rockchip,pwm_id= <2>;
178 rockchip,pwm_voltage = <1000000>;
179 }; 176 };
180}; 177};
181 178
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 2c5249c1eb..c11a5c0cc1 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -660,6 +660,7 @@
660 fifo-depth = <0x400>; 660 fifo-depth = <0x400>;
661 clocks = <&l4_mp_clk>, <&sdmmc_clk>; 661 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
662 clock-names = "biu", "ciu"; 662 clock-names = "biu", "ciu";
663 resets = <&rst SDMMC_RESET>;
663 status = "disabled"; 664 status = "disabled";
664 }; 665 };
665 666
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index d63b56e944..31ba52b14e 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -116,6 +116,28 @@
116 #size-cells = <1>; 116 #size-cells = <1>;
117 ranges = <0 0 0 0xffffffff>; 117 ranges = <0 0 0 0xffffffff>;
118 118
119 spi0: spi@54006000 {
120 compatible = "socionext,uniphier-scssi";
121 status = "disabled";
122 reg = <0x54006000 0x100>;
123 interrupts = <0 39 4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_spi0>;
126 clocks = <&peri_clk 11>;
127 resets = <&peri_rst 11>;
128 };
129
130 spi1: spi@54006100 {
131 compatible = "socionext,uniphier-scssi";
132 status = "disabled";
133 reg = <0x54006100 0x100>;
134 interrupts = <0 216 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_spi1>;
137 clocks = <&peri_clk 11>;
138 resets = <&peri_rst 11>;
139 };
140
119 serial0: serial@54006800 { 141 serial0: serial@54006800 {
120 compatible = "socionext,uniphier-uart"; 142 compatible = "socionext,uniphier-uart";
121 status = "disabled"; 143 status = "disabled";
@@ -432,6 +454,8 @@
432 <&mio_clk 12>; 454 <&mio_clk 12>;
433 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 455 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
434 <&mio_rst 12>; 456 <&mio_rst 12>;
457 phy-names = "usb";
458 phys = <&usb_phy0>;
435 has-transaction-translator; 459 has-transaction-translator;
436 }; 460 };
437 461
@@ -446,6 +470,8 @@
446 <&mio_clk 13>; 470 <&mio_clk 13>;
447 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 471 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
448 <&mio_rst 13>; 472 <&mio_rst 13>;
473 phy-names = "usb";
474 phys = <&usb_phy1>;
449 has-transaction-translator; 475 has-transaction-translator;
450 }; 476 };
451 477
@@ -460,6 +486,8 @@
460 <&mio_clk 14>; 486 <&mio_clk 14>;
461 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 487 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
462 <&mio_rst 14>; 488 <&mio_rst 14>;
489 phy-names = "usb";
490 phys = <&usb_phy2>;
463 has-transaction-translator; 491 has-transaction-translator;
464 }; 492 };
465 493
@@ -488,6 +516,27 @@
488 pinctrl: pinctrl { 516 pinctrl: pinctrl {
489 compatible = "socionext,uniphier-ld11-pinctrl"; 517 compatible = "socionext,uniphier-ld11-pinctrl";
490 }; 518 };
519
520 usb-phy {
521 compatible = "socionext,uniphier-ld11-usb2-phy";
522 #address-cells = <1>;
523 #size-cells = <0>;
524
525 usb_phy0: phy@0 {
526 reg = <0>;
527 #phy-cells = <0>;
528 };
529
530 usb_phy1: phy@1 {
531 reg = <1>;
532 #phy-cells = <0>;
533 };
534
535 usb_phy2: phy@2 {
536 reg = <2>;
537 #phy-cells = <0>;
538 };
539 };
491 }; 540 };
492 541
493 soc-glue@5f900000 { 542 soc-glue@5f900000 {
@@ -571,7 +620,8 @@
571 interrupts = <0 65 4>; 620 interrupts = <0 65 4>;
572 pinctrl-names = "default"; 621 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_nand>; 622 pinctrl-0 = <&pinctrl_nand>;
574 clocks = <&sys_clk 2>; 623 clock-names = "nand", "nand_x", "ecc";
624 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
575 resets = <&sys_rst 2>; 625 resets = <&sys_rst 2>;
576 }; 626 };
577 }; 627 };
diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts
index 1a5e7c24b9..9ca692ed1b 100644
--- a/arch/arm/dts/uniphier-ld20-global.dts
+++ b/arch/arm/dts/uniphier-ld20-global.dts
@@ -145,6 +145,10 @@
145 }; 145 };
146}; 146};
147 147
148&usb {
149 status = "okay";
150};
151
148&nand { 152&nand {
149 status = "okay"; 153 status = "okay";
150}; 154};
diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts
index 440c2e6a63..406244a5c8 100644
--- a/arch/arm/dts/uniphier-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ld20-ref.dts
@@ -75,3 +75,7 @@
75 drive-strength = <9>; 75 drive-strength = <9>;
76 }; 76 };
77}; 77};
78
79&usb {
80 status = "okay";
81};
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 9970497039..b9ed613ace 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -224,6 +224,50 @@
224 #size-cells = <1>; 224 #size-cells = <1>;
225 ranges = <0 0 0 0xffffffff>; 225 ranges = <0 0 0 0xffffffff>;
226 226
227 spi0: spi@54006000 {
228 compatible = "socionext,uniphier-scssi";
229 status = "disabled";
230 reg = <0x54006000 0x100>;
231 interrupts = <0 39 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_spi0>;
234 clocks = <&peri_clk 11>;
235 resets = <&peri_rst 11>;
236 };
237
238 spi1: spi@54006100 {
239 compatible = "socionext,uniphier-scssi";
240 status = "disabled";
241 reg = <0x54006100 0x100>;
242 interrupts = <0 216 4>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_spi1>;
245 clocks = <&peri_clk 11>;
246 resets = <&peri_rst 11>;
247 };
248
249 spi2: spi@54006200 {
250 compatible = "socionext,uniphier-scssi";
251 status = "disabled";
252 reg = <0x54006200 0x100>;
253 interrupts = <0 229 4>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_spi2>;
256 clocks = <&peri_clk 11>;
257 resets = <&peri_rst 11>;
258 };
259
260 spi3: spi@54006300 {
261 compatible = "socionext,uniphier-scssi";
262 status = "disabled";
263 reg = <0x54006300 0x100>;
264 interrupts = <0 230 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_spi3>;
267 clocks = <&peri_clk 11>;
268 resets = <&peri_rst 11>;
269 };
270
227 serial0: serial@54006800 { 271 serial0: serial@54006800 {
228 compatible = "socionext,uniphier-uart"; 272 compatible = "socionext,uniphier-uart";
229 status = "disabled"; 273 status = "disabled";
@@ -567,6 +611,50 @@
567 efuse@200 { 611 efuse@200 {
568 compatible = "socionext,uniphier-efuse"; 612 compatible = "socionext,uniphier-efuse";
569 reg = <0x200 0x68>; 613 reg = <0x200 0x68>;
614 #address-cells = <1>;
615 #size-cells = <1>;
616
617 /* USB cells */
618 usb_rterm0: trim@54,4 {
619 reg = <0x54 1>;
620 bits = <4 2>;
621 };
622 usb_rterm1: trim@55,4 {
623 reg = <0x55 1>;
624 bits = <4 2>;
625 };
626 usb_rterm2: trim@58,4 {
627 reg = <0x58 1>;
628 bits = <4 2>;
629 };
630 usb_rterm3: trim@59,4 {
631 reg = <0x59 1>;
632 bits = <4 2>;
633 };
634 usb_sel_t0: trim@54,0 {
635 reg = <0x54 1>;
636 bits = <0 4>;
637 };
638 usb_sel_t1: trim@55,0 {
639 reg = <0x55 1>;
640 bits = <0 4>;
641 };
642 usb_sel_t2: trim@58,0 {
643 reg = <0x58 1>;
644 bits = <0 4>;
645 };
646 usb_sel_t3: trim@59,0 {
647 reg = <0x59 1>;
648 bits = <0 4>;
649 };
650 usb_hs_i0: trim@56,0 {
651 reg = <0x56 1>;
652 bits = <0 4>;
653 };
654 usb_hs_i2: trim@5a,0 {
655 reg = <0x5a 1>;
656 bits = <0 4>;
657 };
570 }; 658 };
571 }; 659 };
572 660
@@ -634,6 +722,157 @@
634 }; 722 };
635 }; 723 };
636 724
725 _usb: usb@65a00000 {
726 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
727 status = "disabled";
728 reg = <0x65a00000 0xcd00>;
729 interrupt-names = "host";
730 interrupts = <0 134 4>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
733 <&pinctrl_usb2>, <&pinctrl_usb3>;
734 clock-names = "ref", "bus_early", "suspend";
735 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
736 resets = <&usb_rst 15>;
737 phys = <&usb_hsphy0>, <&usb_hsphy1>,
738 <&usb_hsphy2>, <&usb_hsphy3>,
739 <&usb_ssphy0>, <&usb_ssphy1>;
740 dr_mode = "host";
741 };
742
743 usb-glue@65b00000 {
744 compatible = "socionext,uniphier-ld20-dwc3-glue",
745 "simple-mfd";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 ranges = <0 0x65b00000 0x400>;
749
750 usb_rst: reset@0 {
751 compatible = "socionext,uniphier-ld20-usb3-reset";
752 reg = <0x0 0x4>;
753 #reset-cells = <1>;
754 clock-names = "link";
755 clocks = <&sys_clk 14>;
756 reset-names = "link";
757 resets = <&sys_rst 14>;
758 };
759
760 usb_vbus0: regulator@100 {
761 compatible = "socionext,uniphier-ld20-usb3-regulator";
762 reg = <0x100 0x10>;
763 clock-names = "link";
764 clocks = <&sys_clk 14>;
765 reset-names = "link";
766 resets = <&sys_rst 14>;
767 };
768
769 usb_vbus1: regulator@110 {
770 compatible = "socionext,uniphier-ld20-usb3-regulator";
771 reg = <0x110 0x10>;
772 clock-names = "link";
773 clocks = <&sys_clk 14>;
774 reset-names = "link";
775 resets = <&sys_rst 14>;
776 };
777
778 usb_vbus2: regulator@120 {
779 compatible = "socionext,uniphier-ld20-usb3-regulator";
780 reg = <0x120 0x10>;
781 clock-names = "link";
782 clocks = <&sys_clk 14>;
783 reset-names = "link";
784 resets = <&sys_rst 14>;
785 };
786
787 usb_vbus3: regulator@130 {
788 compatible = "socionext,uniphier-ld20-usb3-regulator";
789 reg = <0x130 0x10>;
790 clock-names = "link";
791 clocks = <&sys_clk 14>;
792 reset-names = "link";
793 resets = <&sys_rst 14>;
794 };
795
796 usb_hsphy0: hs-phy@200 {
797 compatible = "socionext,uniphier-ld20-usb3-hsphy";
798 reg = <0x200 0x10>;
799 #phy-cells = <0>;
800 clock-names = "link", "phy";
801 clocks = <&sys_clk 14>, <&sys_clk 16>;
802 reset-names = "link", "phy";
803 resets = <&sys_rst 14>, <&sys_rst 16>;
804 vbus-supply = <&usb_vbus0>;
805 nvmem-cell-names = "rterm", "sel_t", "hs_i";
806 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
807 <&usb_hs_i0>;
808 };
809
810 usb_hsphy1: hs-phy@210 {
811 compatible = "socionext,uniphier-ld20-usb3-hsphy";
812 reg = <0x210 0x10>;
813 #phy-cells = <0>;
814 clock-names = "link", "phy";
815 clocks = <&sys_clk 14>, <&sys_clk 16>;
816 reset-names = "link", "phy";
817 resets = <&sys_rst 14>, <&sys_rst 16>;
818 vbus-supply = <&usb_vbus1>;
819 nvmem-cell-names = "rterm", "sel_t", "hs_i";
820 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
821 <&usb_hs_i0>;
822 };
823
824 usb_hsphy2: hs-phy@220 {
825 compatible = "socionext,uniphier-ld20-usb3-hsphy";
826 reg = <0x220 0x10>;
827 #phy-cells = <0>;
828 clock-names = "link", "phy";
829 clocks = <&sys_clk 14>, <&sys_clk 17>;
830 reset-names = "link", "phy";
831 resets = <&sys_rst 14>, <&sys_rst 17>;
832 vbus-supply = <&usb_vbus2>;
833 nvmem-cell-names = "rterm", "sel_t", "hs_i";
834 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
835 <&usb_hs_i2>;
836 };
837
838 usb_hsphy3: hs-phy@230 {
839 compatible = "socionext,uniphier-ld20-usb3-hsphy";
840 reg = <0x230 0x10>;
841 #phy-cells = <0>;
842 clock-names = "link", "phy";
843 clocks = <&sys_clk 14>, <&sys_clk 17>;
844 reset-names = "link", "phy";
845 resets = <&sys_rst 14>, <&sys_rst 17>;
846 vbus-supply = <&usb_vbus3>;
847 nvmem-cell-names = "rterm", "sel_t", "hs_i";
848 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
849 <&usb_hs_i2>;
850 };
851
852 usb_ssphy0: ss-phy@300 {
853 compatible = "socionext,uniphier-ld20-usb3-ssphy";
854 reg = <0x300 0x10>;
855 #phy-cells = <0>;
856 clock-names = "link", "phy";
857 clocks = <&sys_clk 14>, <&sys_clk 18>;
858 reset-names = "link", "phy";
859 resets = <&sys_rst 14>, <&sys_rst 18>;
860 vbus-supply = <&usb_vbus0>;
861 };
862
863 usb_ssphy1: ss-phy@310 {
864 compatible = "socionext,uniphier-ld20-usb3-ssphy";
865 reg = <0x310 0x10>;
866 #phy-cells = <0>;
867 clock-names = "link", "phy";
868 clocks = <&sys_clk 14>, <&sys_clk 19>;
869 reset-names = "link", "phy";
870 resets = <&sys_rst 14>, <&sys_rst 19>;
871 vbus-supply = <&usb_vbus1>;
872 };
873 };
874
875 /* FIXME: U-Boot own node */
637 usb: usb@65b00000 { 876 usb: usb@65b00000 {
638 compatible = "socionext,uniphier-ld20-dwc3"; 877 compatible = "socionext,uniphier-ld20-dwc3";
639 reg = <0x65b00000 0x1000>; 878 reg = <0x65b00000 0x1000>;
@@ -660,7 +899,8 @@
660 interrupts = <0 65 4>; 899 interrupts = <0 65 4>;
661 pinctrl-names = "default"; 900 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_nand>; 901 pinctrl-0 = <&pinctrl_nand>;
663 clocks = <&sys_clk 2>; 902 clock-names = "nand", "nand_x", "ecc";
903 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
664 resets = <&sys_rst 2>; 904 resets = <&sys_rst 2>;
665 }; 905 };
666 }; 906 };
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index f505f643f7..b73d594b6d 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -63,6 +63,17 @@
63 cache-level = <2>; 63 cache-level = <2>;
64 }; 64 };
65 65
66 spi: spi@54006000 {
67 compatible = "socionext,uniphier-scssi";
68 status = "disabled";
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_spi0>;
73 clocks = <&peri_clk 11>;
74 resets = <&peri_rst 11>;
75 };
76
66 serial0: serial@54006800 { 77 serial0: serial@54006800 {
67 compatible = "socionext,uniphier-uart"; 78 compatible = "socionext,uniphier-uart";
68 status = "disabled"; 79 status = "disabled";
@@ -381,7 +392,8 @@
381 interrupts = <0 65 4>; 392 interrupts = <0 65 4>;
382 pinctrl-names = "default"; 393 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_nand2cs>; 394 pinctrl-0 = <&pinctrl_nand2cs>;
384 clocks = <&sys_clk 2>; 395 clock-names = "nand", "nand_x", "ecc";
396 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
385 resets = <&sys_rst 2>; 397 resets = <&sys_rst 2>;
386 }; 398 };
387 }; 399 };
diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi
index aeb47b0ffe..1fee5ffbfb 100644
--- a/arch/arm/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/dts/uniphier-pinctrl.dtsi
@@ -131,6 +131,26 @@
131 function = "sd1"; 131 function = "sd1";
132 }; 132 };
133 133
134 pinctrl_spi0: spi0 {
135 groups = "spi0";
136 function = "spi0";
137 };
138
139 pinctrl_spi1: spi1 {
140 groups = "spi1";
141 function = "spi1";
142 };
143
144 pinctrl_spi2: spi2 {
145 groups = "spi2";
146 function = "spi2";
147 };
148
149 pinctrl_spi3: spi3 {
150 groups = "spi3";
151 function = "spi3";
152 };
153
134 pinctrl_system_bus: system-bus { 154 pinctrl_system_bus: system-bus {
135 groups = "system_bus", "system_bus_cs1"; 155 groups = "system_bus", "system_bus_cs1";
136 function = "system_bus"; 156 function = "system_bus";
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts
index bff90c256b..ce8ea7b79b 100644
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -73,11 +73,11 @@
73 status = "okay"; 73 status = "okay";
74}; 74};
75 75
76&usb0 { 76&usb2 {
77 status = "okay"; 77 status = "okay";
78}; 78};
79 79
80&usb1 { 80&usb3 {
81 status = "okay"; 81 status = "okay";
82}; 82};
83 83
@@ -92,10 +92,10 @@
92 }; 92 };
93}; 93};
94 94
95&usb2 { 95&usb0 {
96 status = "okay"; 96 status = "okay";
97}; 97};
98 98
99&usb3 { 99&usb1 {
100 status = "okay"; 100 status = "okay";
101}; 101};
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts
index 7f5b957f98..686dd3af7e 100644
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -68,11 +68,11 @@
68 status = "okay"; 68 status = "okay";
69}; 69};
70 70
71&usb0 { 71&usb2 {
72 status = "okay"; 72 status = "okay";
73}; 73};
74 74
75&usb1 { 75&usb3 {
76 status = "okay"; 76 status = "okay";
77}; 77};
78 78
@@ -87,10 +87,10 @@
87 }; 87 };
88}; 88};
89 89
90&usb2 { 90&usb0 {
91 status = "okay"; 91 status = "okay";
92}; 92};
93 93
94&usb3 { 94&usb1 {
95 status = "okay"; 95 status = "okay";
96}; 96};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 8974844541..ef342088e1 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -71,6 +71,17 @@
71 cache-level = <2>; 71 cache-level = <2>;
72 }; 72 };
73 73
74 spi0: spi@54006000 {
75 compatible = "socionext,uniphier-scssi";
76 status = "disabled";
77 reg = <0x54006000 0x100>;
78 interrupts = <0 39 4>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_spi0>;
81 clocks = <&peri_clk 11>;
82 resets = <&peri_rst 11>;
83 };
84
74 serial0: serial@54006800 { 85 serial0: serial@54006800 {
75 compatible = "socionext,uniphier-uart"; 86 compatible = "socionext,uniphier-uart";
76 status = "disabled"; 87 status = "disabled";
@@ -317,6 +328,8 @@
317 <&mio_clk 12>; 328 <&mio_clk 12>;
318 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 329 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
319 <&mio_rst 12>; 330 <&mio_rst 12>;
331 phy-names = "usb";
332 phys = <&usb_phy0>;
320 has-transaction-translator; 333 has-transaction-translator;
321 }; 334 };
322 335
@@ -331,6 +344,8 @@
331 <&mio_clk 13>; 344 <&mio_clk 13>;
332 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 345 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
333 <&mio_rst 13>; 346 <&mio_rst 13>;
347 phy-names = "usb";
348 phys = <&usb_phy1>;
334 has-transaction-translator; 349 has-transaction-translator;
335 }; 350 };
336 351
@@ -342,6 +357,34 @@
342 pinctrl: pinctrl { 357 pinctrl: pinctrl {
343 compatible = "socionext,uniphier-pro4-pinctrl"; 358 compatible = "socionext,uniphier-pro4-pinctrl";
344 }; 359 };
360
361 usb-phy {
362 compatible = "socionext,uniphier-pro4-usb2-phy";
363 #address-cells = <1>;
364 #size-cells = <0>;
365
366 usb_phy0: phy@0 {
367 reg = <0>;
368 #phy-cells = <0>;
369 };
370
371 usb_phy1: phy@1 {
372 reg = <1>;
373 #phy-cells = <0>;
374 };
375
376 usb_phy2: phy@2 {
377 reg = <2>;
378 #phy-cells = <0>;
379 vbus-supply = <&usb0_vbus>;
380 };
381
382 usb_phy3: phy@3 {
383 reg = <3>;
384 #phy-cells = <0>;
385 vbus-supply = <&usb1_vbus>;
386 };
387 };
345 }; 388 };
346 389
347 soc-glue@5f900000 { 390 soc-glue@5f900000 {
@@ -434,6 +477,60 @@
434 }; 477 };
435 }; 478 };
436 479
480 _usb0: usb@65a00000 {
481 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
482 status = "disabled";
483 reg = <0x65a00000 0xcd00>;
484 interrupt-names = "host", "peripheral";
485 interrupts = <0 134 4>, <0 135 4>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_usb0>;
488 clock-names = "ref", "bus_early", "suspend";
489 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
490 resets = <&usb0_rst 4>;
491 phys = <&usb_phy2>, <&usb0_ssphy>;
492 dr_mode = "host";
493 };
494
495 usb-glue@65b00000 {
496 compatible = "socionext,uniphier-pro4-dwc3-glue",
497 "simple-mfd";
498 #address-cells = <1>;
499 #size-cells = <1>;
500 ranges = <0 0x65b00000 0x100>;
501
502 usb0_vbus: regulator@0 {
503 compatible = "socionext,uniphier-pro4-usb3-regulator";
504 reg = <0 0x10>;
505 clock-names = "gio", "link";
506 clocks = <&sys_clk 12>, <&sys_clk 14>;
507 reset-names = "gio", "link";
508 resets = <&sys_rst 12>, <&sys_rst 14>;
509 };
510
511 usb0_ssphy: ss-phy@10 {
512 compatible = "socionext,uniphier-pro4-usb3-ssphy";
513 reg = <0x10 0x10>;
514 #phy-cells = <0>;
515 clock-names = "gio", "link";
516 clocks = <&sys_clk 12>, <&sys_clk 14>;
517 reset-names = "gio", "link";
518 resets = <&sys_rst 12>, <&sys_rst 14>;
519 vbus-supply = <&usb0_vbus>;
520 };
521
522 usb0_rst: reset@40 {
523 compatible = "socionext,uniphier-pro4-usb3-reset";
524 reg = <0x40 0x4>;
525 #reset-cells = <1>;
526 clock-names = "gio", "link";
527 clocks = <&sys_clk 12>, <&sys_clk 14>;
528 reset-names = "gio", "link";
529 resets = <&sys_rst 12>, <&sys_rst 14>;
530 };
531 };
532
533 /* FIXME: U-Boot own node */
437 usb0: usb@65b00000 { 534 usb0: usb@65b00000 {
438 compatible = "socionext,uniphier-pro4-dwc3"; 535 compatible = "socionext,uniphier-pro4-dwc3";
439 status = "disabled"; 536 status = "disabled";
@@ -452,6 +549,49 @@
452 }; 549 };
453 }; 550 };
454 551
552 _usb1: usb@65c00000 {
553 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
554 status = "disabled";
555 reg = <0x65c00000 0xcd00>;
556 interrupt-names = "host", "peripheral";
557 interrupts = <0 137 4>, <0 138 4>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_usb1>;
560 clock-names = "ref", "bus_early", "suspend";
561 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
562 resets = <&usb1_rst 4>;
563 phys = <&usb_phy3>;
564 dr_mode = "host";
565 };
566
567 usb-glue@65d00000 {
568 compatible = "socionext,uniphier-pro4-dwc3-glue",
569 "simple-mfd";
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges = <0 0x65d00000 0x100>;
573
574 usb1_vbus: regulator@0 {
575 compatible = "socionext,uniphier-pro4-usb3-regulator";
576 reg = <0 0x10>;
577 clock-names = "gio", "link";
578 clocks = <&sys_clk 12>, <&sys_clk 15>;
579 reset-names = "gio", "link";
580 resets = <&sys_rst 12>, <&sys_rst 15>;
581 };
582
583 usb1_rst: reset@40 {
584 compatible = "socionext,uniphier-pro4-usb3-reset";
585 reg = <0x40 0x4>;
586 #reset-cells = <1>;
587 clock-names = "gio", "link";
588 clocks = <&sys_clk 12>, <&sys_clk 15>;
589 reset-names = "gio", "link";
590 resets = <&sys_rst 12>, <&sys_rst 15>;
591 };
592 };
593
594 /* FIXME: U-Boot own node */
455 usb1: usb@65d00000 { 595 usb1: usb@65d00000 {
456 compatible = "socionext,uniphier-pro4-dwc3"; 596 compatible = "socionext,uniphier-pro4-dwc3";
457 status = "disabled"; 597 status = "disabled";
@@ -478,7 +618,8 @@
478 interrupts = <0 65 4>; 618 interrupts = <0 65 4>;
479 pinctrl-names = "default"; 619 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_nand>; 620 pinctrl-0 = <&pinctrl_nand>;
481 clocks = <&sys_clk 2>; 621 clock-names = "nand", "nand_x", "ecc";
622 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
482 resets = <&sys_rst 2>; 623 resets = <&sys_rst 2>;
483 }; 624 };
484 }; 625 };
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 6e0ea7976e..9cad79d086 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -156,6 +156,28 @@
156 cache-level = <3>; 156 cache-level = <3>;
157 }; 157 };
158 158
159 spi0: spi@54006000 {
160 compatible = "socionext,uniphier-scssi";
161 status = "disabled";
162 reg = <0x54006000 0x100>;
163 interrupts = <0 39 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_spi0>;
166 clocks = <&peri_clk 11>;
167 resets = <&peri_rst 11>;
168 };
169
170 spi1: spi@54006100 {
171 compatible = "socionext,uniphier-scssi";
172 status = "disabled";
173 reg = <0x54006100 0x100>;
174 interrupts = <0 216 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi1>;
177 clocks = <&peri_clk 11>;
178 resets = <&peri_rst 11>;
179 };
180
159 serial0: serial@54006800 { 181 serial0: serial@54006800 {
160 compatible = "socionext,uniphier-uart"; 182 compatible = "socionext,uniphier-uart";
161 status = "disabled"; 183 status = "disabled";
@@ -475,7 +497,8 @@
475 interrupts = <0 65 4>; 497 interrupts = <0 65 4>;
476 pinctrl-names = "default"; 498 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_nand2cs>; 499 pinctrl-0 = <&pinctrl_nand2cs>;
478 clocks = <&sys_clk 2>; 500 clock-names = "nand", "nand_x", "ecc";
501 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
479 resets = <&sys_rst 2>; 502 resets = <&sys_rst 2>;
480 }; 503 };
481 504
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 63c1c2ce60..fa25ffd97f 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -167,6 +167,28 @@
167 cache-level = <2>; 167 cache-level = <2>;
168 }; 168 };
169 169
170 spi0: spi@54006000 {
171 compatible = "socionext,uniphier-scssi";
172 status = "disabled";
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi0>;
177 clocks = <&peri_clk 11>;
178 resets = <&peri_rst 11>;
179 };
180
181 spi1: spi@54006100 {
182 compatible = "socionext,uniphier-scssi";
183 status = "disabled";
184 reg = <0x54006100 0x100>;
185 interrupts = <0 216 4>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_spi1>;
188 clocks = <&peri_clk 11>;
189 resets = <&peri_rst 11>;
190 };
191
170 serial0: serial@54006800 { 192 serial0: serial@54006800 {
171 compatible = "socionext,uniphier-uart"; 193 compatible = "socionext,uniphier-uart";
172 status = "disabled"; 194 status = "disabled";
@@ -557,6 +579,103 @@
557 }; 579 };
558 }; 580 };
559 581
582 _usb0: usb@65a00000 {
583 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
584 status = "disabled";
585 reg = <0x65a00000 0xcd00>;
586 interrupt-names = "host", "peripheral";
587 interrupts = <0 134 4>, <0 135 4>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
590 clock-names = "ref", "bus_early", "suspend";
591 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
592 resets = <&usb0_rst 15>;
593 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
594 <&usb0_ssphy0>, <&usb0_ssphy1>;
595 dr_mode = "host";
596 };
597
598 usb-glue@65b00000 {
599 compatible = "socionext,uniphier-pxs2-dwc3-glue",
600 "simple-mfd";
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges = <0 0x65b00000 0x400>;
604
605 usb0_rst: reset@0 {
606 compatible = "socionext,uniphier-pxs2-usb3-reset";
607 reg = <0x0 0x4>;
608 #reset-cells = <1>;
609 clock-names = "link";
610 clocks = <&sys_clk 14>;
611 reset-names = "link";
612 resets = <&sys_rst 14>;
613 };
614
615 usb0_vbus0: regulator@100 {
616 compatible = "socionext,uniphier-pxs2-usb3-regulator";
617 reg = <0x100 0x10>;
618 clock-names = "link";
619 clocks = <&sys_clk 14>;
620 reset-names = "link";
621 resets = <&sys_rst 14>;
622 };
623
624 usb0_vbus1: regulator@110 {
625 compatible = "socionext,uniphier-pxs2-usb3-regulator";
626 reg = <0x110 0x10>;
627 clock-names = "link";
628 clocks = <&sys_clk 14>;
629 reset-names = "link";
630 resets = <&sys_rst 14>;
631 };
632
633 usb0_hsphy0: hs-phy@200 {
634 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
635 reg = <0x200 0x10>;
636 #phy-cells = <0>;
637 clock-names = "link", "phy";
638 clocks = <&sys_clk 14>, <&sys_clk 16>;
639 reset-names = "link", "phy";
640 resets = <&sys_rst 14>, <&sys_rst 16>;
641 vbus-supply = <&usb0_vbus0>;
642 };
643
644 usb0_hsphy1: hs-phy@210 {
645 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
646 reg = <0x210 0x10>;
647 #phy-cells = <0>;
648 clock-names = "link", "phy";
649 clocks = <&sys_clk 14>, <&sys_clk 16>;
650 reset-names = "link", "phy";
651 resets = <&sys_rst 14>, <&sys_rst 16>;
652 vbus-supply = <&usb0_vbus1>;
653 };
654
655 usb0_ssphy0: ss-phy@300 {
656 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
657 reg = <0x300 0x10>;
658 #phy-cells = <0>;
659 clock-names = "link", "phy";
660 clocks = <&sys_clk 14>, <&sys_clk 17>;
661 reset-names = "link", "phy";
662 resets = <&sys_rst 14>, <&sys_rst 17>;
663 vbus-supply = <&usb0_vbus0>;
664 };
665
666 usb0_ssphy1: ss-phy@310 {
667 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
668 reg = <0x310 0x10>;
669 #phy-cells = <0>;
670 clock-names = "link", "phy";
671 clocks = <&sys_clk 14>, <&sys_clk 18>;
672 reset-names = "link", "phy";
673 resets = <&sys_rst 14>, <&sys_rst 18>;
674 vbus-supply = <&usb0_vbus1>;
675 };
676 };
677
678 /* FIXME: U-Boot own node */
560 usb0: usb@65b00000 { 679 usb0: usb@65b00000 {
561 compatible = "socionext,uniphier-pxs2-dwc3"; 680 compatible = "socionext,uniphier-pxs2-dwc3";
562 status = "disabled"; 681 status = "disabled";
@@ -575,6 +694,91 @@
575 }; 694 };
576 }; 695 };
577 696
697 _usb1: usb@65c00000 {
698 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
699 status = "disabled";
700 reg = <0x65c00000 0xcd00>;
701 interrupt-names = "host", "peripheral";
702 interrupts = <0 137 4>, <0 138 4>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
705 clock-names = "ref", "bus_early", "suspend";
706 clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
707 resets = <&usb1_rst 15>;
708 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
709 dr_mode = "host";
710 };
711
712 usb-glue@65d00000 {
713 compatible = "socionext,uniphier-pxs2-dwc3-glue",
714 "simple-mfd";
715 #address-cells = <1>;
716 #size-cells = <1>;
717 ranges = <0 0x65d00000 0x400>;
718
719 usb1_rst: reset@0 {
720 compatible = "socionext,uniphier-pxs2-usb3-reset";
721 reg = <0x0 0x4>;
722 #reset-cells = <1>;
723 clock-names = "link";
724 clocks = <&sys_clk 15>;
725 reset-names = "link";
726 resets = <&sys_rst 15>;
727 };
728
729 usb1_vbus0: regulator@100 {
730 compatible = "socionext,uniphier-pxs2-usb3-regulator";
731 reg = <0x100 0x10>;
732 clock-names = "link";
733 clocks = <&sys_clk 15>;
734 reset-names = "link";
735 resets = <&sys_rst 15>;
736 };
737
738 usb1_vbus1: regulator@110 {
739 compatible = "socionext,uniphier-pxs2-usb3-regulator";
740 reg = <0x110 0x10>;
741 clock-names = "link";
742 clocks = <&sys_clk 15>;
743 reset-names = "link";
744 resets = <&sys_rst 15>;
745 };
746
747 usb1_hsphy0: hs-phy@200 {
748 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
749 reg = <0x200 0x10>;
750 #phy-cells = <0>;
751 clock-names = "link", "phy";
752 clocks = <&sys_clk 15>, <&sys_clk 20>;
753 reset-names = "link", "phy";
754 resets = <&sys_rst 15>, <&sys_rst 20>;
755 vbus-supply = <&usb1_vbus0>;
756 };
757
758 usb1_hsphy1: hs-phy@210 {
759 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
760 reg = <0x210 0x10>;
761 #phy-cells = <0>;
762 clock-names = "link", "phy";
763 clocks = <&sys_clk 15>, <&sys_clk 20>;
764 reset-names = "link", "phy";
765 resets = <&sys_rst 15>, <&sys_rst 20>;
766 vbus-supply = <&usb1_vbus1>;
767 };
768
769 usb1_ssphy0: ss-phy@300 {
770 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
771 reg = <0x300 0x10>;
772 #phy-cells = <0>;
773 clock-names = "link", "phy";
774 clocks = <&sys_clk 15>, <&sys_clk 21>;
775 reset-names = "link", "phy";
776 resets = <&sys_rst 15>, <&sys_rst 21>;
777 vbus-supply = <&usb1_vbus0>;
778 };
779 };
780
781 /* FIXME: U-Boot own node */
578 usb1: usb@65d00000 { 782 usb1: usb@65d00000 {
579 compatible = "socionext,uniphier-pxs2-dwc3"; 783 compatible = "socionext,uniphier-pxs2-dwc3";
580 status = "disabled"; 784 status = "disabled";
@@ -601,7 +805,8 @@
601 interrupts = <0 65 4>; 805 interrupts = <0 65 4>;
602 pinctrl-names = "default"; 806 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_nand2cs>; 807 pinctrl-0 = <&pinctrl_nand2cs>;
604 clocks = <&sys_clk 2>; 808 clock-names = "nand", "nand_x", "ecc";
809 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
605 resets = <&sys_rst 2>; 810 resets = <&sys_rst 2>;
606 }; 811 };
607 }; 812 };
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index daf74531e4..f629c6a862 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -144,6 +144,28 @@
144 #size-cells = <1>; 144 #size-cells = <1>;
145 ranges = <0 0 0 0xffffffff>; 145 ranges = <0 0 0 0xffffffff>;
146 146
147 spi0: spi@54006000 {
148 compatible = "socionext,uniphier-scssi";
149 status = "disabled";
150 reg = <0x54006000 0x100>;
151 interrupts = <0 39 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_spi0>;
154 clocks = <&peri_clk 11>;
155 resets = <&peri_rst 11>;
156 };
157
158 spi1: spi@54006100 {
159 compatible = "socionext,uniphier-scssi";
160 status = "disabled";
161 reg = <0x54006100 0x100>;
162 interrupts = <0 216 4>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_spi1>;
165 clocks = <&peri_clk 11>;
166 resets = <&peri_rst 11>;
167 };
168
147 serial0: serial@54006800 { 169 serial0: serial@54006800 {
148 compatible = "socionext,uniphier-uart"; 170 compatible = "socionext,uniphier-uart";
149 status = "disabled"; 171 status = "disabled";
@@ -384,6 +406,50 @@
384 efuse@200 { 406 efuse@200 {
385 compatible = "socionext,uniphier-efuse"; 407 compatible = "socionext,uniphier-efuse";
386 reg = <0x200 0x68>; 408 reg = <0x200 0x68>;
409 #address-cells = <1>;
410 #size-cells = <1>;
411
412 /* USB cells */
413 usb_rterm0: trim@54,4 {
414 reg = <0x54 1>;
415 bits = <4 2>;
416 };
417 usb_rterm1: trim@55,4 {
418 reg = <0x55 1>;
419 bits = <4 2>;
420 };
421 usb_rterm2: trim@58,4 {
422 reg = <0x58 1>;
423 bits = <4 2>;
424 };
425 usb_rterm3: trim@59,4 {
426 reg = <0x59 1>;
427 bits = <4 2>;
428 };
429 usb_sel_t0: trim@54,0 {
430 reg = <0x54 1>;
431 bits = <0 4>;
432 };
433 usb_sel_t1: trim@55,0 {
434 reg = <0x55 1>;
435 bits = <0 4>;
436 };
437 usb_sel_t2: trim@58,0 {
438 reg = <0x58 1>;
439 bits = <0 4>;
440 };
441 usb_sel_t3: trim@59,0 {
442 reg = <0x59 1>;
443 bits = <0 4>;
444 };
445 usb_hs_i0: trim@56,0 {
446 reg = <0x56 1>;
447 bits = <0 4>;
448 };
449 usb_hs_i2: trim@5a,0 {
450 reg = <0x5a 1>;
451 bits = <0 4>;
452 };
387 }; 453 };
388 }; 454 };
389 455
@@ -465,6 +531,109 @@
465 }; 531 };
466 }; 532 };
467 533
534 _usb0: usb@65a00000 {
535 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
536 status = "disabled";
537 reg = <0x65a00000 0xcd00>;
538 interrupt-names = "host", "peripheral";
539 interrupts = <0 134 4>, <0 135 4>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
542 clock-names = "ref", "bus_early", "suspend";
543 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
544 resets = <&usb0_rst 15>;
545 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
546 <&usb0_ssphy0>, <&usb0_ssphy1>;
547 dr_mode = "host";
548 };
549
550 usb-glue@65b00000 {
551 compatible = "socionext,uniphier-pxs3-dwc3-glue",
552 "simple-mfd";
553 #address-cells = <1>;
554 #size-cells = <1>;
555 ranges = <0 0x65b00000 0x400>;
556
557 usb0_rst: reset@0 {
558 compatible = "socionext,uniphier-pxs3-usb3-reset";
559 reg = <0x0 0x4>;
560 #reset-cells = <1>;
561 clock-names = "link";
562 clocks = <&sys_clk 12>;
563 reset-names = "link";
564 resets = <&sys_rst 12>;
565 };
566
567 usb0_vbus0: regulator@100 {
568 compatible = "socionext,uniphier-pxs3-usb3-regulator";
569 reg = <0x100 0x10>;
570 clock-names = "link";
571 clocks = <&sys_clk 12>;
572 reset-names = "link";
573 resets = <&sys_rst 12>;
574 };
575
576 usb0_vbus1: regulator@110 {
577 compatible = "socionext,uniphier-pxs3-usb3-regulator";
578 reg = <0x110 0x10>;
579 clock-names = "link";
580 clocks = <&sys_clk 12>;
581 reset-names = "link";
582 resets = <&sys_rst 12>;
583 };
584
585 usb0_hsphy0: hs-phy@200 {
586 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
587 reg = <0x200 0x10>;
588 #phy-cells = <0>;
589 clock-names = "link", "phy";
590 clocks = <&sys_clk 12>, <&sys_clk 16>;
591 reset-names = "link", "phy";
592 resets = <&sys_rst 12>, <&sys_rst 16>;
593 vbus-supply = <&usb0_vbus0>;
594 nvmem-cell-names = "rterm", "sel_t", "hs_i";
595 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
596 <&usb_hs_i0>;
597 };
598
599 usb0_hsphy1: hs-phy@210 {
600 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
601 reg = <0x210 0x10>;
602 #phy-cells = <0>;
603 clock-names = "link", "phy";
604 clocks = <&sys_clk 12>, <&sys_clk 16>;
605 reset-names = "link", "phy";
606 resets = <&sys_rst 12>, <&sys_rst 16>;
607 vbus-supply = <&usb0_vbus1>;
608 nvmem-cell-names = "rterm", "sel_t", "hs_i";
609 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
610 <&usb_hs_i0>;
611 };
612
613 usb0_ssphy0: ss-phy@300 {
614 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
615 reg = <0x300 0x10>;
616 #phy-cells = <0>;
617 clock-names = "link", "phy";
618 clocks = <&sys_clk 12>, <&sys_clk 17>;
619 reset-names = "link", "phy";
620 resets = <&sys_rst 12>, <&sys_rst 17>;
621 vbus-supply = <&usb0_vbus0>;
622 };
623
624 usb0_ssphy1: ss-phy@310 {
625 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
626 reg = <0x310 0x10>;
627 #phy-cells = <0>;
628 clock-names = "link", "phy";
629 clocks = <&sys_clk 12>, <&sys_clk 18>;
630 reset-names = "link", "phy";
631 resets = <&sys_rst 12>, <&sys_rst 18>;
632 vbus-supply = <&usb0_vbus1>;
633 };
634 };
635
636 /* FIXME: U-Boot own node */
468 usb0: usb@65b00000 { 637 usb0: usb@65b00000 {
469 compatible = "socionext,uniphier-pxs3-dwc3"; 638 compatible = "socionext,uniphier-pxs3-dwc3";
470 status = "disabled"; 639 status = "disabled";
@@ -483,6 +652,101 @@
483 }; 652 };
484 }; 653 };
485 654
655 _usb1: usb@65c00000 {
656 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
657 status = "disabled";
658 reg = <0x65c00000 0xcd00>;
659 interrupt-names = "host", "peripheral";
660 interrupts = <0 137 4>, <0 138 4>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
663 clock-names = "ref", "bus_early", "suspend";
664 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
665 resets = <&usb1_rst 15>;
666 phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
667 <&usb1_ssphy0>;
668 dr_mode = "host";
669 };
670
671 usb-glue@65d00000 {
672 compatible = "socionext,uniphier-pxs3-dwc3-glue",
673 "simple-mfd";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 ranges = <0 0x65d00000 0x400>;
677
678 usb1_rst: reset@0 {
679 compatible = "socionext,uniphier-pxs3-usb3-reset";
680 reg = <0x0 0x4>;
681 #reset-cells = <1>;
682 clock-names = "link";
683 clocks = <&sys_clk 13>;
684 reset-names = "link";
685 resets = <&sys_rst 13>;
686 };
687
688 usb1_vbus0: regulator@100 {
689 compatible = "socionext,uniphier-pxs3-usb3-regulator";
690 reg = <0x100 0x10>;
691 clock-names = "link";
692 clocks = <&sys_clk 13>;
693 reset-names = "link";
694 resets = <&sys_rst 13>;
695 };
696
697 usb1_vbus1: regulator@110 {
698 compatible = "socionext,uniphier-pxs3-usb3-regulator";
699 reg = <0x110 0x10>;
700 clock-names = "link";
701 clocks = <&sys_clk 13>;
702 reset-names = "link";
703 resets = <&sys_rst 13>;
704 };
705
706 usb1_hsphy0: hs-phy@200 {
707 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
708 reg = <0x200 0x10>;
709 #phy-cells = <0>;
710 clock-names = "link", "phy", "phy-ext";
711 clocks = <&sys_clk 13>, <&sys_clk 20>,
712 <&sys_clk 14>;
713 reset-names = "link", "phy";
714 resets = <&sys_rst 13>, <&sys_rst 20>;
715 vbus-supply = <&usb1_vbus0>;
716 nvmem-cell-names = "rterm", "sel_t", "hs_i";
717 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
718 <&usb_hs_i2>;
719 };
720
721 usb1_hsphy1: hs-phy@210 {
722 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
723 reg = <0x210 0x10>;
724 #phy-cells = <0>;
725 clock-names = "link", "phy", "phy-ext";
726 clocks = <&sys_clk 13>, <&sys_clk 20>,
727 <&sys_clk 14>;
728 reset-names = "link", "phy";
729 resets = <&sys_rst 13>, <&sys_rst 20>;
730 vbus-supply = <&usb1_vbus1>;
731 nvmem-cell-names = "rterm", "sel_t", "hs_i";
732 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
733 <&usb_hs_i2>;
734 };
735
736 usb1_ssphy0: ss-phy@300 {
737 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
738 reg = <0x300 0x10>;
739 #phy-cells = <0>;
740 clock-names = "link", "phy", "phy-ext";
741 clocks = <&sys_clk 13>, <&sys_clk 21>,
742 <&sys_clk 14>;
743 reset-names = "link", "phy";
744 resets = <&sys_rst 13>, <&sys_rst 21>;
745 vbus-supply = <&usb1_vbus0>;
746 };
747 };
748
749 /* FIXME: U-Boot own node */
486 usb1: usb@65d00000 { 750 usb1: usb@65d00000 {
487 compatible = "socionext,uniphier-pxs3-dwc3"; 751 compatible = "socionext,uniphier-pxs3-dwc3";
488 status = "disabled"; 752 status = "disabled";
@@ -509,7 +773,8 @@
509 interrupts = <0 65 4>; 773 interrupts = <0 65 4>;
510 pinctrl-names = "default"; 774 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_nand>; 775 pinctrl-0 = <&pinctrl_nand>;
512 clocks = <&sys_clk 2>; 776 clock-names = "nand", "nand_x", "ecc";
777 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
513 resets = <&sys_rst 2>; 778 resets = <&sys_rst 2>;
514 }; 779 };
515 }; 780 };
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index 437265bb73..f7fcf6b459 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -63,6 +63,17 @@
63 cache-level = <2>; 63 cache-level = <2>;
64 }; 64 };
65 65
66 spi: spi@54006000 {
67 compatible = "socionext,uniphier-scssi";
68 status = "disabled";
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_spi0>;
73 clocks = <&peri_clk 11>;
74 resets = <&peri_rst 11>;
75 };
76
66 serial0: serial@54006800 { 77 serial0: serial@54006800 {
67 compatible = "socionext,uniphier-uart"; 78 compatible = "socionext,uniphier-uart";
68 status = "disabled"; 79 status = "disabled";
@@ -385,7 +396,8 @@
385 interrupts = <0 65 4>; 396 interrupts = <0 65 4>;
386 pinctrl-names = "default"; 397 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_nand2cs>; 398 pinctrl-0 = <&pinctrl_nand2cs>;
388 clocks = <&sys_clk 2>; 399 clock-names = "nand", "nand_x", "ecc";
400 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
389 resets = <&sys_rst 2>; 401 resets = <&sys_rst 2>;
390 }; 402 };
391 }; 403 };
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 5198eee024..ad30059b9a 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -89,6 +89,12 @@
89 status = "disabled"; 89 status = "disabled";
90 }; 90 };
91 91
92 iomuxc: iomuxc@40048000 {
93 compatible = "fsl,vf610-iomuxc";
94 reg = <0x40048000 0x1000>;
95 fsl,mux_mask = <0x700000>;
96 };
97
92 gpio0: gpio@40049000 { 98 gpio0: gpio@40049000 {
93 compatible = "fsl,vf610-gpio"; 99 compatible = "fsl,vf610-gpio";
94 reg = <0x400ff000 0x40>; 100 reg = <0x400ff000 0x40>;
diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
new file mode 100644
index 0000000000..fcad7132c8
--- /dev/null
+++ b/arch/arm/dts/vf610-pinfunc.h
@@ -0,0 +1,810 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_VF610_PINFUNC_H
11#define __DTS_VF610_PINFUNC_H
12
13/*
14 * The pin function ID for VF610 is a tuple of:
15 * <mux_reg input_reg mux_mode input_val>
16 */
17
18#define ALT0 0x0
19#define ALT1 0x1
20#define ALT2 0x2
21#define ALT3 0x3
22#define ALT4 0x4
23#define ALT5 0x5
24#define ALT6 0x6
25#define ALT7 0x7
26
27
28#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
29#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
30#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0
31#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0
32#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0
33#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0
34#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
35#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0
36#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0
37#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0
38#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
39#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0
40#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1
41#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0
42#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0
43#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0
44#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
45#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0
46#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0
47#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0
48#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0
49#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0
50#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
51#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0
52#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0
53#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0
54#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
55#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1
56#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0
57#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0
58#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0
59#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
60#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0
61#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0
62#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0
63#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0
64#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0
65#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0
66#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0
67#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
68#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0
69#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0
70#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0
71#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0
72#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0
73#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0
74#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0
75#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
76#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0
77#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0
78#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0
79#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0
80#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0
81#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0
82#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0
83#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
84#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0
85#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0
86#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0
87#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0
88#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0
89#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0
90#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0
91#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
92#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0
93#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0
94#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0
95#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0
96#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
97#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0
98#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0
99#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0
100#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0
101#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0
102#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0
103#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0
104#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0
105#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0
106#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0
107#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0
108#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0
109#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0
110#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0
111#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0
112#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0
113#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0
114#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0
115#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0
116#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0
117#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0
118#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0
119#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0
120#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0
121#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0
122#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0
123#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0
124#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0
125#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0
126#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0
127#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0
128#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0
129#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0
130#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0
131#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0
132#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0
133#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0
134#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0
135#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0
136#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0
137#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0
138#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0
139#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0
140#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0
141#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0
142#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0
143#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0
144#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0
145#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0
146#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0
147#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0
148#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0
149#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0
150#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0
151#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1
152#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0
153#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0
154#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0
155#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0
156#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0
157#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0
158#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1
159#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0
160#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0
161#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0
162#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0
163#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0
164#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1
165#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0
166#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0
167#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0
168#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0
169#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0
170#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0
171#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0
172#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1
173#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0
174#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0
175#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0
176#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0
177#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0
178#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0
179#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0
180#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1
181#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0
182#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0
183#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0
184#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0
185#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0
186#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0
187#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0
188#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0
189#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0
190#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0
191#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0
192#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0
193#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0
194#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0
195#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0
196#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0
197#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0
198#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0
199#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0
200#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0
201#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0
202#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0
203#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0
204#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0
205#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0
206#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0
207#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0
208#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0
209#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0
210#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0
211#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0
212#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0
213#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0
214#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0
215#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0
216#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0
217#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0
218#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0
219#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0
220#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0
221#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0
222#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1
223#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1
224#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0
225#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0
226#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0
227#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1
228#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0
229#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0
230#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0
231#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0
232#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2
233#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0
234#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1
235#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0
236#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0
237#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0
238#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0
239#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0
240#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0
241#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0
242#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0
243#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0
244#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0
245#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0
246#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0
247#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0
248#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0
249#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0
250#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0
251#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0
252#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0
253#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0
254#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0
255#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0
256#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1
257#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0
258#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0
259#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0
260#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0
261#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1
262#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0
263#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0
264#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0
265#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0
266#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1
267#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0
268#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0
269#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0
270#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1
271#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0
272#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0
273#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0
274#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2
275#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0
276#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0
277#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0
278#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0
279#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0
280#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0
281#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0
282#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0
283#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0
284#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0
285#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0
286#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0
287#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0
288#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0
289#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0
290#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0
291#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1
292#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0
293#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0
294#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1
295#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0
296#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0
297#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0
298#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0
299#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0
300#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0
301#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0
302#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1
303#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0
304#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0
305#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0
306#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0
307#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0
308#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0
309#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0
310#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1
311#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0
312#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0
313#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0
314#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0
315#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0
316#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0
317#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1
318#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0
319#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0
320#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0
321#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0
322#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0
323#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0
324#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0
325#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0
326#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0
327#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0
328#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0
329#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0
330#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0
331#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0
332#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1
333#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0
334#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0
335#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0
336#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0
337#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0
338#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0
339#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0
340#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0
341#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0
342#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0
343#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0
344#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0
345#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0
346#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0
347#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0
348#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0
349#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0
350#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0
351#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0
352#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0
353#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0
354#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0
355#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0
356#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0
357#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0
358#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1
359#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1
360#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0
361#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0
362#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0
363#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1
364#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1
365#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0
366#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0
367#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0
368#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1
369#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1
370#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0
371#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0
372#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0
373#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1
374#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1
375#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0
376#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0
377#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0
378#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1
379#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2
380#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0
381#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0
382#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0
383#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1
384#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0
385#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2
386#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0
387#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0
388#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0
389#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0
390#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1
391#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0
392#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0
393#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0
394#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0
395#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0
396#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0
397#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1
398#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0
399#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2
400#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0
401#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0
402#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0
403#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0
404#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0
405#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0
406#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1
407#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0
408#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0
409#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0
410#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0
411#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0
412#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0
413#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0
414#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0
415#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0
416#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0
417#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0
418#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0
419#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0
420#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0
421#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0
422#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0
423#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0
424#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
425#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
426#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
427#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
428#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
429#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
430#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
431#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0
432#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0
433#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0
434#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0
435#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0
436#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0
437#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1
438#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0
439#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0
440#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0
441#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0
442#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0
443#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0
444#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0
445#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0
446#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0
447#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0
448#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0
449#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0
450#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0
451#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0
452#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0
453#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0
454#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0
455#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0
456#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0
457#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0
458#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0
459#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0
460#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0
461#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1
462#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0
463#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1
464#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0
465#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0
466#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0
467#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0
468#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0
469#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1
470#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0
471#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1
472#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0
473#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0
474#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0
475#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0
476#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0
477#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0
478#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0
479#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0
480#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0
481#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0
482#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0
483#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0
484#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0
485#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0
486#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0
487#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0
488#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0
489#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0
490#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0
491#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2
492#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0
493#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0
494#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0
495#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0
496#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0
497#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0
498#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2
499#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0
500#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0
501#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0
502#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0
503#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0
504#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0
505#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2
506#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0
507#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0
508#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0
509#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0
510#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0
511#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2
512#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0
513#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0
514#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0
515#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2
516#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0
517#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0
518#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0
519#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0
520#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0
521#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2
522#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0
523#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0
524#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0
525#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0
526#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0
527#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0
528#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0
529#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0
530#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0
531#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0
532#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0
533#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0
534#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1
535#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0
536#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0
537#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0
538#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0
539#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0
540#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0
541#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0
542#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0
543#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0
544#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0
545#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0
546#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0
547#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1
548#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0
549#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0
550#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0
551#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0
552#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1
553#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0
554#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0
555#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0
556#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0
557#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0
558#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0
559#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0
560#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0
561#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0
562#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0
563#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1
564#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0
565#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0
566#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0
567#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0
568#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0
569#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0
570#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0
571#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0
572#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0
573#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0
574#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0
575#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0
576#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0
577#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0
578#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0
579#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0
580#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0
581#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0
582#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0
583#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0
584#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0
585#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0
586#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0
587#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0
588#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0
589#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0
590#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0
591#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0
592#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0
593#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0
594#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2
595#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1
596#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0
597#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0
598#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0
599#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0
600#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0
601#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0
602#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2
603#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1
604#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0
605#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0
606#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0
607#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0
608#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0
609#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0
610#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0
611#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1
612#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0
613#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0
614#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0
615#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0
616#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0
617#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2
618#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0
619#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0
620#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0
621#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0
622#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0
623#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0
624#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0
625#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0
626#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0
627#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0
628#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0
629#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0
630#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0
631#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0
632#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0
633#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0
634#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0
635#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0
636#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0
637#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0
638#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0
639#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0
640#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0
641#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0
642#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0
643#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0
644#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0
645#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0
646#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0
647#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0
648#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0
649#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0
650#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0
651#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0
652#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0
653#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0
654#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0
655#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0
656#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0
657#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0
658#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0
659#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0
660#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0
661#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0
662#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0
663#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0
664#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0
665#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0
666#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0
667#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0
668#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0
669#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0
670#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0
671#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0
672#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0
673#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1
674#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0
675#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0
676#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0
677#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0
678#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0
679#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0
680#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0
681#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0
682#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0
683#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0
684#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0
685#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0
686#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0
687#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0
688#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0
689#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0
690#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0
691#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0
692#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0
693#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0
694#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0
695#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0
696#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0
697#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0
698#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0
699#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0
700#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0
701#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0
702#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0
703#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0
704#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0
705#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0
706#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0
707#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0
708#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0
709#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0
710#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0
711#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0
712#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0
713#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0
714#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0
715#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0
716#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0
717#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0
718#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0
719#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0
720#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0
721#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0
722#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0
723#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0
724#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0
725#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0
726#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0
727#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0
728#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0
729#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0
730#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0
731#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0
732#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0
733#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0
734#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0
735#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0
736#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0
737#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0
738#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0
739#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0
740#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0
741#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0
742#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0
743#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0
744#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0
745#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0
746#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0
747#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0
748#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0
749#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0
750#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0
751#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0
752#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0
753#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0
754#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0
755#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0
756#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0
757#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0
758#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0
759#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0
760#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0
761#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0
762#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0
763#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0
764#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0
765#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0
766#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0
767#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3
768#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0
769#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0
770#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0
771#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0
772#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3
773#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0
774#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0
775#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0
776#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0
777#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0
778#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0
779#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0
780#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0
781#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0
782#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0
783#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0
784#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0
785#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0
786#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0
787#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0
788#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0
789#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0
790#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0
791#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0
792#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0
793#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0
794#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0
795#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0
796#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0
797#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0
798#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0
799#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0
800#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3
801#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0
802#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0
803#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0
804#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0
805#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3
806#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0
807#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
808#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
809
810#endif
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 2af79659d2..667badbc06 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -24,7 +24,7 @@
24#define MXC_CPU_MX6QP 0x69 24#define MXC_CPU_MX6QP 0x69
25#define MXC_CPU_MX7S 0x71 /* dummy ID */ 25#define MXC_CPU_MX7S 0x71 /* dummy ID */
26#define MXC_CPU_MX7D 0x72 26#define MXC_CPU_MX7D 0x72
27#define MXC_CPU_MX8MQ 0x82 27#define MXC_CPU_IMX8MQ 0x82
28#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ 28#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
29#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ 29#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
30#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ 30#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
@@ -32,7 +32,7 @@
32 32
33#define MXC_SOC_MX6 0x60 33#define MXC_SOC_MX6 0x60
34#define MXC_SOC_MX7 0x70 34#define MXC_SOC_MX7 0x70
35#define MXC_SOC_MX8M 0x80 35#define MXC_SOC_IMX8M 0x80
36#define MXC_SOC_IMX8 0x90 /* dummy */ 36#define MXC_SOC_IMX8 0x90 /* dummy */
37#define MXC_SOC_MX7ULP 0xE0 /* dummy */ 37#define MXC_SOC_MX7ULP 0xE0 /* dummy */
38 38
@@ -41,6 +41,7 @@
41#define CHIP_REV_1_2 0x12 41#define CHIP_REV_1_2 0x12
42#define CHIP_REV_1_5 0x15 42#define CHIP_REV_1_5 0x15
43#define CHIP_REV_2_0 0x20 43#define CHIP_REV_2_0 0x20
44#define CHIP_REV_2_1 0x21
44#define CHIP_REV_2_5 0x25 45#define CHIP_REV_2_5 0x25
45#define CHIP_REV_3_0 0x30 46#define CHIP_REV_3_0 0x30
46 47
diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index 45cfea3018..e7c1670f6b 100644
--- a/arch/arm/include/asm/arch-mx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -10,6 +10,8 @@
10 10
11#include <linux/bitops.h> 11#include <linux/bitops.h>
12 12
13#define MHZ(X) ((X) * 1000000UL)
14
13enum pll_clocks { 15enum pll_clocks {
14 ANATOP_ARM_PLL, 16 ANATOP_ARM_PLL,
15 ANATOP_GPU_PLL, 17 ANATOP_GPU_PLL,
@@ -631,6 +633,26 @@ enum frac_pll_out_val {
631 FRAC_PLL_OUT_1600M, 633 FRAC_PLL_OUT_1600M,
632}; 634};
633 635
636#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
637 { \
638 .clk = (_rate), \
639 .alt_root_sel = (_m), \
640 .alt_pre_div = (_p), \
641 .apb_root_sel = (_s), \
642 .apb_pre_div = (_k), \
643 }
644
645struct dram_bypass_clk_setting {
646 ulong clk;
647 int alt_root_sel;
648 enum root_pre_div alt_pre_div;
649 int apb_root_sel;
650 enum root_pre_div apb_pre_div;
651};
652
653void dram_pll_init(ulong pll_val);
654void dram_enable_bypass(ulong clk_val);
655void dram_disable_bypass(void);
634u32 imx_get_fecclk(void); 656u32 imx_get_fecclk(void);
635u32 imx_get_uartclk(void); 657u32 imx_get_uartclk(void);
636int clock_init(void); 658int clock_init(void);
diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h
index c128931289..c42e6685de 100644
--- a/arch/arm/include/asm/arch-mx8m/crm_regs.h
+++ b/arch/arm/include/asm/arch-imx8m/crm_regs.h
@@ -3,7 +3,7 @@
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 */ 4 */
5 5
6#ifndef _ASM_ARCH_MX8M_CRM_REGS_H 6#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
7#define _ASM_ARCH_MX8M_CRM_REGS_H 7#define _ASM_ARCH_IMX8M_CRM_REGS_H
8/* Dummy header, some imx-common code needs this file */ 8/* Dummy header, some imx-common code needs this file */
9#endif 9#endif
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
new file mode 100644
index 0000000000..53d46256d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -0,0 +1,740 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2017 NXP
4 */
5
6#ifndef __ASM_ARCH_IMX8M_DDR_H
7#define __ASM_ARCH_IMX8M_DDR_H
8
9#include <asm/io.h>
10#include <asm/types.h>
11#include <asm/arch/ddr.h>
12
13#define DDRC_DDR_SS_GPR0 0x3d000000
14#define DDRC_IPS_BASE_ADDR_0 0x3f400000
15#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
16#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
17
18struct ddrc_freq {
19 u32 res0[8];
20 u32 derateen;
21 u32 derateint;
22 u32 res1[10];
23 u32 rfshctl0;
24 u32 res2[4];
25 u32 rfshtmg;
26 u32 rfshtmg1;
27 u32 res3[28];
28 u32 init3;
29 u32 init4;
30 u32 res;
31 u32 init6;
32 u32 init7;
33 u32 res4[4];
34 u32 dramtmg0;
35 u32 dramtmg1;
36 u32 dramtmg2;
37 u32 dramtmg3;
38 u32 dramtmg4;
39 u32 dramtmg5;
40 u32 dramtmg6;
41 u32 dramtmg7;
42 u32 dramtmg8;
43 u32 dramtmg9;
44 u32 dramtmg10;
45 u32 dramtmg11;
46 u32 dramtmg12;
47 u32 dramtmg13;
48 u32 dramtmg14;
49 u32 dramtmg15;
50 u32 dramtmg16;
51 u32 dramtmg17;
52 u32 res5[10];
53 u32 mramtmg0;
54 u32 mramtmg1;
55 u32 mramtmg4;
56 u32 mramtmg9;
57 u32 zqctl0;
58 u32 res6[3];
59 u32 dfitmg0;
60 u32 dfitmg1;
61 u32 res7[7];
62 u32 dfitmg2;
63 u32 dfitmg3;
64 u32 res8[33];
65 u32 odtcfg;
66};
67
68struct imx8m_ddrc_regs {
69 u32 mstr;
70 u32 stat;
71 u32 mstr1;
72 u32 res1;
73 u32 mrctrl0;
74 u32 mrctrl1;
75 u32 mrstat;
76 u32 mrctrl2;
77 u32 derateen;
78 u32 derateint;
79 u32 mstr2;
80 u32 res2;
81 u32 pwrctl;
82 u32 pwrtmg;
83 u32 hwlpctl;
84 u32 hwffcctl;
85 u32 hwffcstat;
86 u32 res3[3];
87 u32 rfshctl0;
88 u32 rfshctl1;
89 u32 rfshctl2;
90 u32 rfshctl4;
91 u32 rfshctl3;
92 u32 rfshtmg;
93 u32 rfshtmg1;
94 u32 res4;
95 u32 ecccfg0;
96 u32 ecccfg1;
97 u32 eccstat;
98 u32 eccclr;
99 u32 eccerrcnt;
100 u32 ecccaddr0;
101 u32 ecccaddr1;
102 u32 ecccsyn0;
103 u32 ecccsyn1;
104 u32 ecccsyn2;
105 u32 eccbitmask0;
106 u32 eccbitmask1;
107 u32 eccbitmask2;
108 u32 eccuaddr0;
109 u32 eccuaddr1;
110 u32 eccusyn0;
111 u32 eccusyn1;
112 u32 eccusyn2;
113 u32 eccpoisonaddr0;
114 u32 eccpoisonaddr1;
115 u32 crcparctl0;
116 u32 crcparctl1;
117 u32 crcparctl2;
118 u32 crcparstat;
119 u32 init0;
120 u32 init1;
121 u32 init2;
122 u32 init3;
123 u32 init4;
124 u32 init5;
125 u32 init6;
126 u32 init7;
127 u32 dimmctl;
128 u32 rankctl;
129 u32 res5;
130 u32 chctl;
131 u32 dramtmg0;
132 u32 dramtmg1;
133 u32 dramtmg2;
134 u32 dramtmg3;
135 u32 dramtmg4;
136 u32 dramtmg5;
137 u32 dramtmg6;
138 u32 dramtmg7;
139 u32 dramtmg8;
140 u32 dramtmg9;
141 u32 dramtmg10;
142 u32 dramtmg11;
143 u32 dramtmg12;
144 u32 dramtmg13;
145 u32 dramtmg14;
146 u32 dramtmg15;
147 u32 dramtmg16;
148 u32 dramtmg17;
149 u32 res6[10];
150 u32 mramtmg0;
151 u32 mramtmg1;
152 u32 mramtmg4;
153 u32 mramtmg9;
154 u32 zqctl0;
155 u32 zqctl1;
156 u32 zqctl2;
157 u32 zqstat;
158 u32 dfitmg0;
159 u32 dfitmg1;
160 u32 dfilpcfg0;
161 u32 dfilpcfg1;
162 u32 dfiupd0;
163 u32 dfiupd1;
164 u32 dfiupd2;
165 u32 res7;
166 u32 dfimisc;
167 u32 dfitmg2;
168 u32 dfitmg3;
169 u32 dfistat;
170 u32 dbictl;
171 u32 dfiphymstr;
172 u32 res8[14];
173 u32 addrmap0;
174 u32 addrmap1;
175 u32 addrmap2;
176 u32 addrmap3;
177 u32 addrmap4;
178 u32 addrmap5;
179 u32 addrmap6;
180 u32 addrmap7;
181 u32 addrmap8;
182 u32 addrmap9;
183 u32 addrmap10;
184 u32 addrmap11;
185 u32 res9[4];
186 u32 odtcfg;
187 u32 odtmap;
188 u32 res10[2];
189 u32 sched;
190 u32 sched1;
191 u32 sched2;
192 u32 perfhpr1;
193 u32 res11;
194 u32 perflpr1;
195 u32 res12;
196 u32 perfwr1;
197 u32 res13[4];
198 u32 dqmap0;
199 u32 dqmap1;
200 u32 dqmap2;
201 u32 dqmap3;
202 u32 dqmap4;
203 u32 dqmap5;
204 u32 res14[26];
205 u32 dbg0;
206 u32 dbg1;
207 u32 dbgcam;
208 u32 dbgcmd;
209 u32 dbgstat;
210 u32 res15[3];
211 u32 swctl;
212 u32 swstat;
213 u32 res16[2];
214 u32 ocparcfg0;
215 u32 ocparcfg1;
216 u32 ocparcfg2;
217 u32 ocparcfg3;
218 u32 ocparstat0;
219 u32 ocparstat1;
220 u32 ocparwlog0;
221 u32 ocparwlog1;
222 u32 ocparwlog2;
223 u32 ocparawlog0;
224 u32 ocparawlog1;
225 u32 ocparrlog0;
226 u32 ocparrlog1;
227 u32 ocpararlog0;
228 u32 ocpararlog1;
229 u32 poisoncfg;
230 u32 poisonstat;
231 u32 adveccindex;
232 union {
233 u32 adveccstat;
234 u32 eccapstat;
235 };
236 u32 eccpoisonpat0;
237 u32 eccpoisonpat1;
238 u32 eccpoisonpat2;
239 u32 res17[6];
240 u32 caparpoisonctl;
241 u32 caparpoisonstat;
242 u32 res18[2];
243 u32 dynbsmstat;
244 u32 res19[18];
245 u32 pstat;
246 u32 pccfg;
247 struct {
248 u32 pcfgr;
249 u32 pcfgw;
250 u32 pcfgc;
251 struct {
252 u32 pcfgidmaskch0;
253 u32 pcfidvaluech0;
254 } pcfgid[16];
255 u32 pctrl;
256 u32 pcfgqos0;
257 u32 pcfgqos1;
258 u32 pcfgwqos0;
259 u32 pcfgwqos1;
260 u32 res[4];
261 } pcfg[16];
262 struct {
263 u32 sarbase;
264 u32 sarsize;
265 } sar[4];
266 u32 sbrctl;
267 u32 sbrstat;
268 u32 sbrwdata0;
269 u32 sbrwdata1;
270 u32 pdch;
271 u32 res20[755];
272 /* umctl2_regs_dch1 */
273 u32 ch1_stat;
274 u32 res21[2];
275 u32 ch1_mrctrl0;
276 u32 ch1_mrctrl1;
277 u32 ch1_mrstat;
278 u32 ch1_mrctrl2;
279 u32 res22[4];
280 u32 ch1_pwrctl;
281 u32 ch1_pwrtmg;
282 u32 ch1_hwlpctl;
283 u32 res23[15];
284 u32 ch1_eccstat;
285 u32 ch1_eccclr;
286 u32 ch1_eccerrcnt;
287 u32 ch1_ecccaddr0;
288 u32 ch1_ecccaddr1;
289 u32 ch1_ecccsyn0;
290 u32 ch1_ecccsyn1;
291 u32 ch1_ecccsyn2;
292 u32 ch1_eccbitmask0;
293 u32 ch1_eccbitmask1;
294 u32 ch1_eccbitmask2;
295 u32 ch1_eccuaddr0;
296 u32 ch1_eccuaddr1;
297 u32 ch1_eccusyn0;
298 u32 ch1_eccusyn1;
299 u32 ch1_eccusyn2;
300 u32 res24[2];
301 u32 ch1_crcparctl0;
302 u32 res25[2];
303 u32 ch1_crcparstat;
304 u32 res26[46];
305 u32 ch1_zqctl2;
306 u32 ch1_zqstat;
307 u32 res27[11];
308 u32 ch1_dfistat;
309 u32 res28[33];
310 u32 ch1_odtmap;
311 u32 res29[47];
312 u32 ch1_dbg1;
313 u32 ch1_dbgcam;
314 u32 ch1_dbgcmd;
315 u32 ch1_dbgstat;
316 u32 res30[123];
317 /* umctl2_regs_freq1 */
318 struct ddrc_freq freq1;
319 u32 res31[109];
320 /* umctl2_regs_addrmap_alt */
321 u32 addrmap0_alt;
322 u32 addrmap1_alt;
323 u32 addrmap2_alt;
324 u32 addrmap3_alt;
325 u32 addrmap4_alt;
326 u32 addrmap5_alt;
327 u32 addrmap6_alt;
328 u32 addrmap7_alt;
329 u32 addrmap8_alt;
330 u32 addrmap9_alt;
331 u32 addrmap10_alt;
332 u32 addrmap11_alt;
333 u32 res32[758];
334 /* umctl2_regs_freq2 */
335 struct ddrc_freq freq2;
336 u32 res33[879];
337 /* umctl2_regs_freq3 */
338 struct ddrc_freq freq3;
339};
340
341struct imx8m_ddrphy_regs {
342 u32 reg[0xf0000];
343};
344
345/* PHY State */
346enum pstate {
347 PS0,
348 PS1,
349 PS2,
350 PS3,
351};
352
353enum msg_response {
354 TRAIN_SUCCESS = 0x7,
355 TRAIN_STREAM_START = 0x8,
356 TRAIN_FAIL = 0xff,
357};
358
359#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
360#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
361#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
362#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
363#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
364#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
365#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
366#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
367#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
368#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
369#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
370#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
371#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
372#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
373#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
374#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
375#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
376#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
377#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
378#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
379#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
380#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
381#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
382#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
383#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
384#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
385#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
386#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
387#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
388#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
389#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
390#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
391#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
392#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
393#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
394#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
395#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
396#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
397#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
398#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
399#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
400#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
401#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
402#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
403#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
404#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
405#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
406#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
407#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
408#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
409#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
410#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
411#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
412#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
413#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
414#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
415#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
416#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
417#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
418#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
419#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
420#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
421#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
422#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
423#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
424#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
425#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
426#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
427#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
428#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
429#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
430#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
431#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
432#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
433#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
434#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
435#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
436#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
437#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
438#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
439#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
440#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
441#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
442#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
443#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
444#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
445#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
446#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
447#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
448#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
449#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
450#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
451#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
452#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
453#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
454#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
455#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
456#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
457#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
458#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
459#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
460#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
461#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
462#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
463#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
464#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
465#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
466#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
467#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
468#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
469#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
470#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
471#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
472#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
473#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
474#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
475#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
476#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
477#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
478#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
479#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
480#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
481#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
482#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
483#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
484#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
485#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
486#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
487#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
488#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
489#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
490#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
491#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
492#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
493#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
494#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
495#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
496#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
497#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
498#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
499#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
500#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
501#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
502#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
503
504#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
505#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
506#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
507#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
508#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
509#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
510#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
511#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
512#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
513#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
514#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
515#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
516#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
517#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
518#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
519#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
520#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
521#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
522#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
523#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
524#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
525#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
526#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
527#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
528#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
529#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
530#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
531#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
532
533#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
534#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
535#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
536#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
537#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
538#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
539#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
540#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
541#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
542#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
543#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
544#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
545#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
546#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
547#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
548#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
549#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
550#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
551#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
552#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
553#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
554#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
555#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
556#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
557#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
558#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
559#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
560#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
561#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
562#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
563#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
564#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
565
566#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
567#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
568#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
569#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
570#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
571#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
572#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
573#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
574#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
575#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
576#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
577#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
578#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
579#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
580#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
581#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
582#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
583#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
584#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
585#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
586#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
587#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
588#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
589#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
590#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
591#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
592#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
593#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
594#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
595#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
596#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
597#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
598
599#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
600#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
601#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
602#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
603#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
604#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
605#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
606#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
607#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
608#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
609#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
610#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
611#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
612#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
613#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
614#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
615#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
616#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
617#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
618#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
619#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
620#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
621#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
622#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
623#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
624
625#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
626#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
627#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
628#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
629#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
630#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
631#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
632#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
633#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
634#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
635#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
636
637#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
638
639#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000))
640#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
641#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
642#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
643#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
644#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
645#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
646#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
647#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
648#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
649#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
650#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
651#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
652#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
653#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
654#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
655#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
656#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
657#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
658#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
659#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
660#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
661#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
662#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
663#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
664
665/* user data type */
666enum fw_type {
667 FW_1D_IMAGE,
668 FW_2D_IMAGE,
669};
670
671struct dram_cfg_param {
672 unsigned int reg;
673 unsigned int val;
674};
675
676struct dram_fsp_msg {
677 unsigned int drate;
678 enum fw_type fw_type;
679 struct dram_cfg_param *fsp_cfg;
680 unsigned int fsp_cfg_num;
681};
682
683struct dram_timing_info {
684 /* umctl2 config */
685 struct dram_cfg_param *ddrc_cfg;
686 unsigned int ddrc_cfg_num;
687 /* ddrphy config */
688 struct dram_cfg_param *ddrphy_cfg;
689 unsigned int ddrphy_cfg_num;
690 /* ddr fsp train info */
691 struct dram_fsp_msg *fsp_msg;
692 unsigned int fsp_msg_num;
693 /* ddr phy trained CSR */
694 struct dram_cfg_param *ddrphy_trained_csr;
695 unsigned int ddrphy_trained_csr_num;
696 /* ddr phy PIE */
697 struct dram_cfg_param *ddrphy_pie;
698 unsigned int ddrphy_pie_num;
699 /* initialized drate table */
700 unsigned int fsp_table[4];
701};
702
703extern struct dram_timing_info dram_timing;
704
705void ddr_load_train_firmware(enum fw_type type);
706void ddr_init(struct dram_timing_info *timing_info);
707void ddr_cfg_phy(struct dram_timing_info *timing_info);
708void load_lpddr4_phy_pie(void);
709void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
710void dram_config_save(struct dram_timing_info *info, unsigned long base);
711
712/* utils function for ddr phy training */
713void wait_ddrphy_training_complete(void);
714void ddrphy_init_set_dfi_clk(unsigned int drate);
715void ddrphy_init_read_msg_block(enum fw_type type);
716
717static inline void reg32_write(unsigned long addr, u32 val)
718{
719 writel(val, addr);
720}
721
722static inline u32 reg32_read(unsigned long addr)
723{
724 return readl(addr);
725}
726
727static inline void reg32setbit(unsigned long addr, u32 bit)
728{
729 setbits_le32(addr, (1 << bit));
730}
731
732#define dwc_ddrphy_apb_wr(addr, data) \
733 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
734#define dwc_ddrphy_apb_rd(addr) \
735 reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
736
737extern struct dram_cfg_param ddrphy_trained_csr[];
738extern uint32_t ddrphy_trained_csr_num;
739
740#endif
diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h
index 2ba5643d05..2d9fbcb0e4 100644
--- a/arch/arm/include/asm/arch-mx8m/gpio.h
+++ b/arch/arm/include/asm/arch-imx8m/gpio.h
@@ -3,8 +3,8 @@
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 */ 4 */
5 5
6#ifndef __ASM_ARCH_MX8M_GPIO_H 6#ifndef __ASM_ARCH_IMX8M_GPIO_H
7#define __ASM_ARCH_MX8M_GPIO_H 7#define __ASM_ARCH_IMX8M_GPIO_H
8 8
9#include <asm/mach-imx/gpio.h> 9#include <asm/mach-imx/gpio.h>
10 10
diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index a3b06282b0..3facd5450c 100644
--- a/arch/arm/include/asm/arch-mx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -3,8 +3,8 @@
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 */ 4 */
5 5
6#ifndef __ASM_ARCH_MX8M_REGS_H__ 6#ifndef __ASM_ARCH_IMX8M_REGS_H__
7#define __ASM_ARCH_MX8M_REGS_H__ 7#define __ASM_ARCH_IMX8M_REGS_H__
8 8
9#include <asm/mach-imx/regs-lcdif.h> 9#include <asm/mach-imx/regs-lcdif.h>
10 10
diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
index 3ba4d15a2a..c71913f209 100644
--- a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
+++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
@@ -3,8 +3,8 @@
3 * Copyright (C) 2017 NXP 3 * Copyright (C) 2017 NXP
4 */ 4 */
5 5
6#ifndef __ASM_ARCH_MX8MQ_PINS_H__ 6#ifndef __ASM_ARCH_IMX8MQ_PINS_H__
7#define __ASM_ARCH_MX8MQ_PINS_H__ 7#define __ASM_ARCH_IMX8MQ_PINS_H__
8 8
9#include <asm/mach-imx/iomux-v3.h> 9#include <asm/mach-imx/iomux-v3.h>
10 10
diff --git a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h
new file mode 100644
index 0000000000..caf5bafb6d
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h
@@ -0,0 +1,97 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __LPDDR4_DEFINE_H_
7#define __LPDDR4_DEFINE_H_
8
9#define LPDDR4_DVFS_DBI
10#define DDR_ONE_RANK
11/* #define LPDDR4_DBI_ON */
12#define DFI_BUG_WR
13#define M845S_4GBx2
14#define PRETRAIN
15
16/* DRAM MR setting */
17#ifdef LPDDR4_DBI_ON
18#define LPDDR4_MR3 0xf1
19#define LPDDR4_PHY_DMIPinPresent 0x1
20#else
21#define LPDDR4_MR3 0x31
22#define LPDDR4_PHY_DMIPinPresent 0x0
23#endif
24
25#ifdef DDR_ONE_RANK
26#define LPDDR4_CS 0x1
27#else
28#define LPDDR4_CS 0x3
29#endif
30
31/* PHY training feature */
32#define LPDDR4_HDT_CTL_2D 0xC8
33#define LPDDR4_HDT_CTL_3200_1D 0xC8
34#define LPDDR4_HDT_CTL_400_1D 0xC8
35#define LPDDR4_HDT_CTL_100_1D 0xC8
36
37/* 400/100 training seq */
38#define LPDDR4_TRAIN_SEQ_P2 0x121f
39#define LPDDR4_TRAIN_SEQ_P1 0x121f
40#define LPDDR4_TRAIN_SEQ_P0 0x121f
41#define LPDDR4_TRAIN_SEQ_100 0x121f
42#define LPDDR4_TRAIN_SEQ_400 0x121f
43
44/* 2D share & weight */
45#define LPDDR4_2D_WEIGHT 0x1f7f
46#define LPDDR4_2D_SHARE 1
47#define LPDDR4_CATRAIN_3200_1d 0
48#define LPDDR4_CATRAIN_400 0
49#define LPDDR4_CATRAIN_100 0
50#define LPDDR4_CATRAIN_3200_2d 0
51
52/* MRS parameter */
53/* for LPDDR4 Rtt */
54#define LPDDR4_RTT40 6
55#define LPDDR4_RTT48 5
56#define LPDDR4_RTT60 4
57#define LPDDR4_RTT80 3
58#define LPDDR4_RTT120 2
59#define LPDDR4_RTT240 1
60#define LPDDR4_RTT_DIS 0
61
62/* for LPDDR4 Ron */
63#define LPDDR4_RON34 7
64#define LPDDR4_RON40 6
65#define LPDDR4_RON48 5
66#define LPDDR4_RON60 4
67#define LPDDR4_RON80 3
68
69#define LPDDR4_PHY_ADDR_RON60 0x1
70#define LPDDR4_PHY_ADDR_RON40 0x3
71#define LPDDR4_PHY_ADDR_RON30 0x7
72#define LPDDR4_PHY_ADDR_RON24 0xf
73#define LPDDR4_PHY_ADDR_RON20 0x1f
74
75/* for read channel */
76#define LPDDR4_RON LPDDR4_RON40
77#define LPDDR4_PHY_RTT 30
78#define LPDDR4_PHY_VREF_VALUE 17
79
80/* for write channel */
81#define LPDDR4_PHY_RON 30
82#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
83#define LPDDR4_RTT_DQ LPDDR4_RTT40
84#define LPDDR4_RTT_CA LPDDR4_RTT40
85#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40
86#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40
87#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd))
88#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd))
89#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd))
90#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \
91 (LPDDR4_RTT40))
92#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \
93 (LPDDR4_RTT40))
94
95#define LPDDR4_MR3_PU_CAL 1
96
97#endif /* __LPDDR4_DEFINE_H__ */
diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index 01d6cd76c1..d328542ece 100644
--- a/arch/arm/include/asm/arch-mx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -3,8 +3,8 @@
3 * Copyright (C) 2017 NXP 3 * Copyright (C) 2017 NXP
4 */ 4 */
5 5
6#ifndef __ARCH_MX8M_SYS_PROTO_H 6#ifndef __ARCH_IMX8M_SYS_PROTO_H
7#define __ARCH_MX8M_SYS_PROTO_H 7#define __ARCH_NMX8M_SYS_PROTO_H
8 8
9#include <asm/mach-imx/sys_proto.h> 9#include <asm/mach-imx/sys_proto.h>
10 10
diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-mx8m/ddr.h
deleted file mode 100644
index 7e4f6fbb64..0000000000
--- a/arch/arm/include/asm/arch-mx8m/ddr.h
+++ /dev/null
@@ -1,355 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2017 NXP
4 */
5
6#ifndef __ASM_ARCH_MX8M_DDR_H
7#define __ASM_ARCH_MX8M_DDR_H
8
9#define DDRC_DDR_SS_GPR0 0x3d000000
10#define DDRC_IPS_BASE_ADDR_0 0x3f400000
11#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
12#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
13
14struct ddrc_freq {
15 u32 res0[8];
16 u32 derateen;
17 u32 derateint;
18 u32 res1[10];
19 u32 rfshctl0;
20 u32 res2[4];
21 u32 rfshtmg;
22 u32 rfshtmg1;
23 u32 res3[28];
24 u32 init3;
25 u32 init4;
26 u32 res;
27 u32 init6;
28 u32 init7;
29 u32 res4[4];
30 u32 dramtmg0;
31 u32 dramtmg1;
32 u32 dramtmg2;
33 u32 dramtmg3;
34 u32 dramtmg4;
35 u32 dramtmg5;
36 u32 dramtmg6;
37 u32 dramtmg7;
38 u32 dramtmg8;
39 u32 dramtmg9;
40 u32 dramtmg10;
41 u32 dramtmg11;
42 u32 dramtmg12;
43 u32 dramtmg13;
44 u32 dramtmg14;
45 u32 dramtmg15;
46 u32 dramtmg16;
47 u32 dramtmg17;
48 u32 res5[10];
49 u32 mramtmg0;
50 u32 mramtmg1;
51 u32 mramtmg4;
52 u32 mramtmg9;
53 u32 zqctl0;
54 u32 res6[3];
55 u32 dfitmg0;
56 u32 dfitmg1;
57 u32 res7[7];
58 u32 dfitmg2;
59 u32 dfitmg3;
60 u32 res8[33];
61 u32 odtcfg;
62};
63
64struct imx8m_ddrc_regs {
65 u32 mstr;
66 u32 stat;
67 u32 mstr1;
68 u32 res1;
69 u32 mrctrl0;
70 u32 mrctrl1;
71 u32 mrstat;
72 u32 mrctrl2;
73 u32 derateen;
74 u32 derateint;
75 u32 mstr2;
76 u32 res2;
77 u32 pwrctl;
78 u32 pwrtmg;
79 u32 hwlpctl;
80 u32 hwffcctl;
81 u32 hwffcstat;
82 u32 res3[3];
83 u32 rfshctl0;
84 u32 rfshctl1;
85 u32 rfshctl2;
86 u32 rfshctl4;
87 u32 rfshctl3;
88 u32 rfshtmg;
89 u32 rfshtmg1;
90 u32 res4;
91 u32 ecccfg0;
92 u32 ecccfg1;
93 u32 eccstat;
94 u32 eccclr;
95 u32 eccerrcnt;
96 u32 ecccaddr0;
97 u32 ecccaddr1;
98 u32 ecccsyn0;
99 u32 ecccsyn1;
100 u32 ecccsyn2;
101 u32 eccbitmask0;
102 u32 eccbitmask1;
103 u32 eccbitmask2;
104 u32 eccuaddr0;
105 u32 eccuaddr1;
106 u32 eccusyn0;
107 u32 eccusyn1;
108 u32 eccusyn2;
109 u32 eccpoisonaddr0;
110 u32 eccpoisonaddr1;
111 u32 crcparctl0;
112 u32 crcparctl1;
113 u32 crcparctl2;
114 u32 crcparstat;
115 u32 init0;
116 u32 init1;
117 u32 init2;
118 u32 init3;
119 u32 init4;
120 u32 init5;
121 u32 init6;
122 u32 init7;
123 u32 dimmctl;
124 u32 rankctl;
125 u32 res5;
126 u32 chctl;
127 u32 dramtmg0;
128 u32 dramtmg1;
129 u32 dramtmg2;
130 u32 dramtmg3;
131 u32 dramtmg4;
132 u32 dramtmg5;
133 u32 dramtmg6;
134 u32 dramtmg7;
135 u32 dramtmg8;
136 u32 dramtmg9;
137 u32 dramtmg10;
138 u32 dramtmg11;
139 u32 dramtmg12;
140 u32 dramtmg13;
141 u32 dramtmg14;
142 u32 dramtmg15;
143 u32 dramtmg16;
144 u32 dramtmg17;
145 u32 res6[10];
146 u32 mramtmg0;
147 u32 mramtmg1;
148 u32 mramtmg4;
149 u32 mramtmg9;
150 u32 zqctl0;
151 u32 zqctl1;
152 u32 zqctl2;
153 u32 zqstat;
154 u32 dfitmg0;
155 u32 dfitmg1;
156 u32 dfilpcfg0;
157 u32 dfilpcfg1;
158 u32 dfiupd0;
159 u32 dfiupd1;
160 u32 dfiupd2;
161 u32 res7;
162 u32 dfimisc;
163 u32 dfitmg2;
164 u32 dfitmg3;
165 u32 dfistat;
166 u32 dbictl;
167 u32 dfiphymstr;
168 u32 res8[14];
169 u32 addrmap0;
170 u32 addrmap1;
171 u32 addrmap2;
172 u32 addrmap3;
173 u32 addrmap4;
174 u32 addrmap5;
175 u32 addrmap6;
176 u32 addrmap7;
177 u32 addrmap8;
178 u32 addrmap9;
179 u32 addrmap10;
180 u32 addrmap11;
181 u32 res9[4];
182 u32 odtcfg;
183 u32 odtmap;
184 u32 res10[2];
185 u32 sched;
186 u32 sched1;
187 u32 sched2;
188 u32 perfhpr1;
189 u32 res11;
190 u32 perflpr1;
191 u32 res12;
192 u32 perfwr1;
193 u32 res13[4];
194 u32 dqmap0;
195 u32 dqmap1;
196 u32 dqmap2;
197 u32 dqmap3;
198 u32 dqmap4;
199 u32 dqmap5;
200 u32 res14[26];
201 u32 dbg0;
202 u32 dbg1;
203 u32 dbgcam;
204 u32 dbgcmd;
205 u32 dbgstat;
206 u32 res15[3];
207 u32 swctl;
208 u32 swstat;
209 u32 res16[2];
210 u32 ocparcfg0;
211 u32 ocparcfg1;
212 u32 ocparcfg2;
213 u32 ocparcfg3;
214 u32 ocparstat0;
215 u32 ocparstat1;
216 u32 ocparwlog0;
217 u32 ocparwlog1;
218 u32 ocparwlog2;
219 u32 ocparawlog0;
220 u32 ocparawlog1;
221 u32 ocparrlog0;
222 u32 ocparrlog1;
223 u32 ocpararlog0;
224 u32 ocpararlog1;
225 u32 poisoncfg;
226 u32 poisonstat;
227 u32 adveccindex;
228 union {
229 u32 adveccstat;
230 u32 eccapstat;
231 };
232 u32 eccpoisonpat0;
233 u32 eccpoisonpat1;
234 u32 eccpoisonpat2;
235 u32 res17[6];
236 u32 caparpoisonctl;
237 u32 caparpoisonstat;
238 u32 res18[2];
239 u32 dynbsmstat;
240 u32 res19[18];
241 u32 pstat;
242 u32 pccfg;
243 struct {
244 u32 pcfgr;
245 u32 pcfgw;
246 u32 pcfgc;
247 struct {
248 u32 pcfgidmaskch0;
249 u32 pcfidvaluech0;
250 } pcfgid[16];
251 u32 pctrl;
252 u32 pcfgqos0;
253 u32 pcfgqos1;
254 u32 pcfgwqos0;
255 u32 pcfgwqos1;
256 u32 res[4];
257 } pcfg[16];
258 struct {
259 u32 sarbase;
260 u32 sarsize;
261 } sar[4];
262 u32 sbrctl;
263 u32 sbrstat;
264 u32 sbrwdata0;
265 u32 sbrwdata1;
266 u32 pdch;
267 u32 res20[755];
268 /* umctl2_regs_dch1 */
269 u32 ch1_stat;
270 u32 res21[2];
271 u32 ch1_mrctrl0;
272 u32 ch1_mrctrl1;
273 u32 ch1_mrstat;
274 u32 ch1_mrctrl2;
275 u32 res22[4];
276 u32 ch1_pwrctl;
277 u32 ch1_pwrtmg;
278 u32 ch1_hwlpctl;
279 u32 res23[15];
280 u32 ch1_eccstat;
281 u32 ch1_eccclr;
282 u32 ch1_eccerrcnt;
283 u32 ch1_ecccaddr0;
284 u32 ch1_ecccaddr1;
285 u32 ch1_ecccsyn0;
286 u32 ch1_ecccsyn1;
287 u32 ch1_ecccsyn2;
288 u32 ch1_eccbitmask0;
289 u32 ch1_eccbitmask1;
290 u32 ch1_eccbitmask2;
291 u32 ch1_eccuaddr0;
292 u32 ch1_eccuaddr1;
293 u32 ch1_eccusyn0;
294 u32 ch1_eccusyn1;
295 u32 ch1_eccusyn2;
296 u32 res24[2];
297 u32 ch1_crcparctl0;
298 u32 res25[2];
299 u32 ch1_crcparstat;
300 u32 res26[46];
301 u32 ch1_zqctl2;
302 u32 ch1_zqstat;
303 u32 res27[11];
304 u32 ch1_dfistat;
305 u32 res28[33];
306 u32 ch1_odtmap;
307 u32 res29[47];
308 u32 ch1_dbg1;
309 u32 ch1_dbgcam;
310 u32 ch1_dbgcmd;
311 u32 ch1_dbgstat;
312 u32 res30[123];
313 /* umctl2_regs_freq1 */
314 struct ddrc_freq freq1;
315 u32 res31[109];
316 /* umctl2_regs_addrmap_alt */
317 u32 addrmap0_alt;
318 u32 addrmap1_alt;
319 u32 addrmap2_alt;
320 u32 addrmap3_alt;
321 u32 addrmap4_alt;
322 u32 addrmap5_alt;
323 u32 addrmap6_alt;
324 u32 addrmap7_alt;
325 u32 addrmap8_alt;
326 u32 addrmap9_alt;
327 u32 addrmap10_alt;
328 u32 addrmap11_alt;
329 u32 res32[758];
330 /* umctl2_regs_freq2 */
331 struct ddrc_freq freq2;
332 u32 res33[879];
333 /* umctl2_regs_freq3 */
334 struct ddrc_freq freq3;
335};
336
337struct imx8m_ddrphy_regs {
338 u32 reg[0xf0000];
339};
340
341/* PHY State */
342enum pstate {
343 PS0,
344 PS1,
345 PS2,
346 PS3,
347};
348
349enum msg_response {
350 TRAIN_SUCCESS = 0x7,
351 TRAIN_STREAM_START = 0x8,
352 TRAIN_FAIL = 0xff,
353};
354
355#endif
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 08ba8e94f8..f71fbf4e73 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -200,7 +200,8 @@
200#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) 200#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24)
201#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) 201#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
202#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) 202#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
203#define DDRMC_CR82_INT_MASK 0x10000000 203#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8)
204#define DDRMC_CR82_INT_MASK (1 << 28)
204#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24) 205#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
205#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16) 206#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
206#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) 207#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
@@ -239,7 +240,7 @@
239#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) 240#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
240#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) 241#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16)
241#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) 242#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16)
242#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) 243#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8)
243#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) 244#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
244#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) 245#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
245#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) 246#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index c0eeaa7e7d..01bc2998b8 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -244,6 +244,8 @@ enum {
244 VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), 244 VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
245 VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), 245 VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
246 VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), 246 VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
247 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
248 VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
247}; 249};
248 250
249#endif /* __IOMUX_VF610_H__ */ 251#endif /* __IOMUX_VF610_H__ */
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 0883b7ea75..fc5b8f634d 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -13,7 +13,7 @@
13 13
14static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) 14static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
15{ 15{
16 *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); 16 *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
17 return (void *)*handle; 17 return (void *)*handle;
18} 18}
19 19
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index 63f4b33aeb..b899a4ff6f 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;
86#define IOMUX_CONFIG_LPSR 0x20 86#define IOMUX_CONFIG_LPSR 0x20
87#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ 87#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
88 MUX_MODE_SHIFT) 88 MUX_MODE_SHIFT)
89#ifdef CONFIG_MX8M 89#ifdef CONFIG_IMX8M
90#define PAD_CTL_DSE0 (0x0 << 0) 90#define PAD_CTL_DSE0 (0x0 << 0)
91#define PAD_CTL_DSE1 (0x1 << 0) 91#define PAD_CTL_DSE1 (0x1 << 0)
92#define PAD_CTL_DSE2 (0x2 << 0) 92#define PAD_CTL_DSE2 (0x2 << 0)
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index d294c90646..b4c430a35c 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
22 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ 22 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
23 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ 23 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
24 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ 24 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
25 defined(CONFIG_MX8M) 25 defined(CONFIG_IMX8M)
26 mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ 26 mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
27#endif 27#endif
28 mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ 28 mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
61 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ 61 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
62 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ 62 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
63 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ 63 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
64 defined(CONFIG_MX8M) 64 defined(CONFIG_IMX8M)
65 mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ 65 mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
66#endif 66#endif
67 mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ 67 mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -73,7 +73,7 @@ struct mxs_lcdif_regs {
73 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ 73 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
74 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ 74 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
75 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ 75 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
76 defined(CONFIG_MX8M) 76 defined(CONFIG_IMX8M)
77 mxs_reg_32(hw_lcdif_thres) 77 mxs_reg_32(hw_lcdif_thres)
78 mxs_reg_32(hw_lcdif_as_ctrl) 78 mxs_reg_32(hw_lcdif_as_ctrl)
79 mxs_reg_32(hw_lcdif_as_buf) 79 mxs_reg_32(hw_lcdif_as_buf)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index f8890b57da..8d6832a331 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -26,7 +26,7 @@
26 26
27#define is_mx6() (is_soc_type(MXC_SOC_MX6)) 27#define is_mx6() (is_soc_type(MXC_SOC_MX6))
28#define is_mx7() (is_soc_type(MXC_SOC_MX7)) 28#define is_mx7() (is_soc_type(MXC_SOC_MX7))
29#define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) 29#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
30#define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 30#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
31 31
32#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 32#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -42,6 +42,7 @@
42 42
43#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 43#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
44 44
45#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
45#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 46#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
46 47
47#ifdef CONFIG_MX6 48#ifdef CONFIG_MX6
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 4837781957..48f13c7648 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -58,7 +58,7 @@ struct exynos5_sysreg {
58/* Move 0xd3 value to CPSR register to enable SVC mode */ 58/* Move 0xd3 value to CPSR register to enable SVC mode */
59#define svc32_mode_en() __asm__ __volatile__ \ 59#define svc32_mode_en() __asm__ __volatile__ \
60 ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ 60 ("@ I&F disable, Mode: 0x13 - SVC\n\t" \
61 "msr cpsr_c, #0x13|0xC0\n\t" : : ) 61 "msr cpsr_c, %0\n\t" : : "r"(0x13|0xC0))
62 62
63/* Set program counter with the given value */ 63/* Set program counter with the given value */
64#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) 64#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 53d9e5f42b..d236e40510 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,12 +5,14 @@
5# 5#
6# (C) Copyright 2011 Freescale Semiconductor, Inc. 6# (C) Copyright 2011 Freescale Semiconductor, Inc.
7 7
8ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610)) 8ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
9obj-y = iomux-v3.o 9obj-y = iomux-v3.o
10endif 10endif
11 11
12ifeq ($(SOC),$(filter $(SOC),mx8m)) 12ifeq ($(SOC),$(filter $(SOC),imx8m))
13ifneq ($(CONFIG_SPL_BUILD),y)
13obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o 14obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
15endif
14obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o 16obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
15obj-$(CONFIG_FEC_MXC) += mac.o 17obj-$(CONFIG_FEC_MXC) += mac.o
16obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o 18obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
@@ -22,7 +24,7 @@ obj-y += cpu.o speed.o
22obj-$(CONFIG_GPT_TIMER) += timer.o 24obj-$(CONFIG_GPT_TIMER) += timer.o
23obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o 25obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
24endif 26endif
25ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m)) 27ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m))
26obj-y += misc.o 28obj-y += misc.o
27obj-$(CONFIG_SPL_BUILD) += spl.o 29obj-$(CONFIG_SPL_BUILD) += spl.o
28endif 30endif
@@ -104,7 +106,11 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
104ifeq ($(CONFIG_ARCH_IMX8), y) 106ifeq ($(CONFIG_ARCH_IMX8), y)
105CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh 107CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
106IMAGE_TYPE := imx8image 108IMAGE_TYPE := imx8image
107DEPFILE_EXISTS := $(shell if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) 109DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
110else ifeq ($(CONFIG_ARCH_IMX8M), y)
111IMAGE_TYPE := imx8mimage
112IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
113DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
108else 114else
109IMAGE_TYPE := imximage 115IMAGE_TYPE := imximage
110DEPFILE_EXISTS := 0 116DEPFILE_EXISTS := 0
@@ -129,6 +135,26 @@ ifeq ($(DEPFILE_EXISTS),0)
129endif 135endif
130endif 136endif
131 137
138ifdef CONFIG_ARM64
139ifeq ($(CONFIG_ARCH_IMX8M), y)
140SPL:
141
142MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
143 -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
144flash.bin: MKIMAGEOUTPUT = flash.log
145
146spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
147ifeq ($(DEPFILE_EXISTS),0)
148 $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
149endif
150
151flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
152ifeq ($(DEPFILE_EXISTS),0)
153 $(call if_changed,mkimage)
154endif
155endif
156
157else
132MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ 158MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
133 -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) 159 -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
134SPL: MKIMAGEOUTPUT = SPL.log 160SPL: MKIMAGEOUTPUT = SPL.log
@@ -160,6 +186,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
160 186
161spl/u-boot-nand-spl.imx: SPL FORCE 187spl/u-boot-nand-spl.imx: SPL FORCE
162 $(call if_changed,u-boot-nand-spl_imx) 188 $(call if_changed,u-boot-nand-spl_imx)
189endif
163 190
164targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) 191targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
165 192
@@ -169,5 +196,5 @@ obj-$(CONFIG_MX5) += mx5/
169obj-$(CONFIG_MX6) += mx6/ 196obj-$(CONFIG_MX6) += mx6/
170obj-$(CONFIG_MX7) += mx7/ 197obj-$(CONFIG_MX7) += mx7/
171obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ 198obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
172obj-$(CONFIG_MX8M) += mx8m/ 199obj-$(CONFIG_IMX8M) += imx8m/
173obj-$(CONFIG_ARCH_IMX8) += imx8/ 200obj-$(CONFIG_ARCH_IMX8) += imx8/
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index dcdaced991..80d9ff48a4 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -62,7 +62,7 @@ static char *get_reset_cause(void)
62 return "WDOG4"; 62 return "WDOG4";
63 case 0x00200: 63 case 0x00200:
64 return "TEMPSENSE"; 64 return "TEMPSENSE";
65#elif defined(CONFIG_MX8M) 65#elif defined(CONFIG_IMX8M)
66 case 0x00100: 66 case 0x00100:
67 return "WDOG2"; 67 return "WDOG2";
68 case 0x00200: 68 case 0x00200:
@@ -142,8 +142,8 @@ unsigned imx_ddr_size(void)
142const char *get_imx_type(u32 imxtype) 142const char *get_imx_type(u32 imxtype)
143{ 143{
144 switch (imxtype) { 144 switch (imxtype) {
145 case MXC_CPU_MX8MQ: 145 case MXC_CPU_IMX8MQ:
146 return "8MQ"; /* Quad-core version of the mx8m */ 146 return "8MQ"; /* Quad-core version of the imx8m */
147 case MXC_CPU_MX7S: 147 case MXC_CPU_MX7S:
148 return "7S"; /* Single-core version of the mx7 */ 148 return "7S"; /* Single-core version of the mx7 */
149 case MXC_CPU_MX7D: 149 case MXC_CPU_MX7D:
@@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
266} 266}
267#endif 267#endif
268 268
269#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) 269#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
270u32 get_ahb_clk(void) 270u32 get_ahb_clk(void)
271{ 271{
272 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 272 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -300,7 +300,7 @@ void arch_preboot_os(void)
300#endif 300#endif
301} 301}
302 302
303#ifndef CONFIG_MX8M 303#ifndef CONFIG_IMX8M
304void set_chipselect_size(int const cs_size) 304void set_chipselect_size(int const cs_size)
305{ 305{
306 unsigned int reg; 306 unsigned int reg;
@@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size)
333} 333}
334#endif 334#endif
335 335
336#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) 336#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
337/* 337/*
338 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) 338 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
339 * defines a 2-bit SPEED_GRADING 339 * defines a 2-bit SPEED_GRADING
@@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
409} 409}
410#endif 410#endif
411 411
412#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) 412#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
413enum boot_device get_boot_device(void) 413enum boot_device get_boot_device(void)
414{ 414{
415 struct bootrom_sw_info **p = 415 struct bootrom_sw_info **p =
@@ -438,7 +438,7 @@ enum boot_device get_boot_device(void)
438 case BOOT_TYPE_SPINOR: 438 case BOOT_TYPE_SPINOR:
439 boot_dev = SPI_NOR_BOOT; 439 boot_dev = SPI_NOR_BOOT;
440 break; 440 break;
441#ifdef CONFIG_MX8M 441#ifdef CONFIG_IMX8M
442 case BOOT_TYPE_USB: 442 case BOOT_TYPE_USB:
443 boot_dev = USB_BOOT; 443 boot_dev = USB_BOOT;
444 break; 444 break;
diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index 3d7da1c25e..fa948f7812 100644
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -61,6 +61,8 @@ void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
61 VF610_PAD_DDR_WE__DDR_WE_B, 61 VF610_PAD_DDR_WE__DDR_WE_B,
62 VF610_PAD_DDR_ODT1__DDR_ODT_0, 62 VF610_PAD_DDR_ODT1__DDR_ODT_0,
63 VF610_PAD_DDR_ODT0__DDR_ODT_1, 63 VF610_PAD_DDR_ODT0__DDR_ODT_1,
64 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
65 VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
64 VF610_PAD_DDR_RESETB, 66 VF610_PAD_DDR_RESETB,
65 }; 67 };
66 68
@@ -188,7 +190,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
188 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); 190 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
189 writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) | 191 writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
190 DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); 192 DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
191 writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
192 193
193 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); 194 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
194 195
@@ -231,6 +232,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
231 /* all inits done, start the DDR controller */ 232 /* all inits done, start the DDR controller */
232 writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); 233 writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
233 234
234 while (!(readl(&ddrmr->cr[80]) && 0x100)) 235 while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
235 udelay(10); 236 udelay(10);
237 writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
236} 238}
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index b88acd13da..dbfd692fa3 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -6,6 +6,8 @@
6#include <common.h> 6#include <common.h>
7#include <config.h> 7#include <config.h>
8#include <fuse.h> 8#include <fuse.h>
9#include <mapmem.h>
10#include <image.h>
9#include <asm/io.h> 11#include <asm/io.h>
10#include <asm/system.h> 12#include <asm/system.h>
11#include <asm/arch/clock.h> 13#include <asm/arch/clock.h>
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc,
302 return 0; 304 return 0;
303} 305}
304 306
307static ulong get_image_ivt_offset(ulong img_addr)
308{
309 const void *buf;
310
311 buf = map_sysmem(img_addr, 0);
312 switch (genimg_get_format(buf)) {
313#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
314 case IMAGE_FORMAT_LEGACY:
315 return (image_get_image_size((image_header_t *)img_addr)
316 + 0x1000 - 1) & ~(0x1000 - 1);
317#endif
318#if IMAGE_ENABLE_FIT
319 case IMAGE_FORMAT_FIT:
320 return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1);
321#endif
322 default:
323 return 0;
324 }
325}
326
305static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc, 327static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
306 char * const argv[]) 328 char * const argv[])
307{ 329{
308 ulong addr, length, ivt_offset; 330 ulong addr, length, ivt_offset;
309 int rcode = 0; 331 int rcode = 0;
310 332
311 if (argc < 4) 333 if (argc < 3)
312 return CMD_RET_USAGE; 334 return CMD_RET_USAGE;
313 335
314 addr = simple_strtoul(argv[1], NULL, 16); 336 addr = simple_strtoul(argv[1], NULL, 16);
315 length = simple_strtoul(argv[2], NULL, 16); 337 length = simple_strtoul(argv[2], NULL, 16);
316 ivt_offset = simple_strtoul(argv[3], NULL, 16); 338 if (argc == 3)
339 ivt_offset = get_image_ivt_offset(addr);
340 else
341 ivt_offset = simple_strtoul(argv[3], NULL, 16);
317 342
318 rcode = imx_hab_authenticate_image(addr, length, ivt_offset); 343 rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
319 if (rcode == 0) 344 if (rcode == 0)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index f093f34ca5..7599afe720 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -573,7 +573,7 @@ int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
573 if (size < 100) 573 if (size < 100)
574 return -ENOSPC; 574 return -ENOSPC;
575 575
576 snprintf(buf, size, "CPU: Freescale i.MX8%s Rev%s %s at %u MHz\n", 576 snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
577 plat->type, plat->rev, plat->name, plat->freq_mhz); 577 plat->type, plat->rev, plat->name, plat->freq_mhz);
578 578
579 return 0; 579 return 0;
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
new file mode 100644
index 0000000000..317dee9bc1
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -0,0 +1,23 @@
1if ARCH_IMX8M
2
3config IMX8M
4 bool
5 select ROM_UNIFIED_SECTIONS
6
7config SYS_SOC
8 default "imx8m"
9
10choice
11 prompt "NXP i.MX8M board select"
12 optional
13
14config TARGET_IMX8MQ_EVK
15 bool "imx8mq_evk"
16 select IMX8M
17 select IMX8M_LPDDR4
18
19endchoice
20
21source "board/freescale/imx8mq_evk/Kconfig"
22
23endif
diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index feff4941c1..feff4941c1 100644
--- a/arch/arm/mach-imx/mx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/imx8m/clock.c
index fe32e1c3f1..289b9417aa 100644
--- a/arch/arm/mach-imx/mx8m/clock.c
+++ b/arch/arm/mach-imx/imx8m/clock.c
@@ -250,9 +250,9 @@ static u32 get_root_src_clk(enum clk_root_src root_src)
250 case OSC_25M_CLK: 250 case OSC_25M_CLK:
251 return 25000000; 251 return 25000000;
252 case OSC_27M_CLK: 252 case OSC_27M_CLK:
253 return 25000000; 253 return 27000000;
254 case OSC_32K_CLK: 254 case OSC_32K_CLK:
255 return 32000; 255 return 32768;
256 case ARM_PLL_CLK: 256 case ARM_PLL_CLK:
257 return decode_frac_pll(root_src); 257 return decode_frac_pll(root_src);
258 case SYSTEM_PLL1_800M_CLK: 258 case SYSTEM_PLL1_800M_CLK:
@@ -525,41 +525,127 @@ u32 imx_get_fecclk(void)
525 return get_root_clk(ENET_AXI_CLK_ROOT); 525 return get_root_clk(ENET_AXI_CLK_ROOT);
526} 526}
527 527
528#ifdef CONFIG_SPL_BUILD 528static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
529void dram_pll_init(void) 529 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
530 CLK_ROOT_PRE_DIV2),
531 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
532 CLK_ROOT_PRE_DIV2),
533 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
534 CLK_ROOT_PRE_DIV2),
535};
536
537void dram_enable_bypass(ulong clk_val)
530{ 538{
531 struct src *src = (struct src *)SRC_BASE_ADDR; 539 int i;
532 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; 540 struct dram_bypass_clk_setting *config;
533 u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0; 541
534 u32 val; 542 for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
535 int ret; 543 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
544 break;
545 }
536 546
537 setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7)); 547 if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
538 setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5)); 548 printf("No matched freq table %lu\n", clk_val);
549 return;
550 }
539 551
540 pwdn_mask = SSCG_PLL_PD_MASK; 552 config = &imx8mq_dram_bypass_tbl[i];
541 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
542 bypass1 = SSCG_PLL_BYPASS1_MASK;
543 bypass2 = SSCG_PLL_BYPASS2_MASK;
544 553
545 /* Enable DDR1 and DDR2 domain */ 554 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
546 writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr); 555 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
547 writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr); 556 CLK_ROOT_PRE_DIV(config->alt_pre_div));
557 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
558 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
559 CLK_ROOT_PRE_DIV(config->apb_pre_div));
560 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
561 CLK_ROOT_SOURCE_SEL(1));
562}
563
564void dram_disable_bypass(void)
565{
566 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
567 CLK_ROOT_SOURCE_SEL(0));
568 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
569 CLK_ROOT_SOURCE_SEL(4) |
570 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
571}
572
573#ifdef CONFIG_SPL_BUILD
574void dram_pll_init(ulong pll_val)
575{
576 u32 val;
577 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
578 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
579
580 /* Bypass */
581 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
582 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
583
584 switch (pll_val) {
585 case MHZ(800):
586 val = readl(pll_cfg_reg2);
587 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
588 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
589 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
590 SSCG_PLL_REF_DIVR2_MASK);
591 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
592 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
593 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
594 val |= SSCG_PLL_REF_DIVR2_VAL(29);
595 writel(val, pll_cfg_reg2);
596 break;
597 case MHZ(600):
598 val = readl(pll_cfg_reg2);
599 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
600 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
601 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
602 SSCG_PLL_REF_DIVR2_MASK);
603 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
604 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
605 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
606 val |= SSCG_PLL_REF_DIVR2_VAL(29);
607 writel(val, pll_cfg_reg2);
608 break;
609 case MHZ(400):
610 val = readl(pll_cfg_reg2);
611 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
612 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
613 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
614 SSCG_PLL_REF_DIVR2_MASK);
615 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
616 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
617 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
618 val |= SSCG_PLL_REF_DIVR2_VAL(29);
619 writel(val, pll_cfg_reg2);
620 break;
621 case MHZ(167):
622 val = readl(pll_cfg_reg2);
623 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
624 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
625 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
626 SSCG_PLL_REF_DIVR2_MASK);
627 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
628 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
629 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
630 val |= SSCG_PLL_REF_DIVR2_VAL(30);
631 writel(val, pll_cfg_reg2);
632 break;
633 default:
634 break;
635 }
548 636
549 /* Clear power down bit */ 637 /* Clear power down bit */
550 clrbits_le32(pll_control_reg, pwdn_mask); 638 clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
551 /* Eanble ARM_PLL/SYS_PLL */ 639 /* Eanble ARM_PLL/SYS_PLL */
552 setbits_le32(pll_control_reg, pll_clke); 640 setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
553 641
554 /* Clear bypass */ 642 /* Clear bypass */
555 clrbits_le32(pll_control_reg, bypass1); 643 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
556 __udelay(100); 644 __udelay(100);
557 clrbits_le32(pll_control_reg, bypass2); 645 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
558 /* Wait lock */ 646 /* Wait lock */
559 ret = readl_poll_timeout(pll_control_reg, val, 647 while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
560 val & SSCG_PLL_LOCK_MASK, 1); 648 ;
561 if (ret)
562 printf("%s timeout\n", __func__);
563} 649}
564 650
565int frac_pll_init(u32 pll, enum frac_pll_out_val val) 651int frac_pll_init(u32 pll, enum frac_pll_out_val val)
@@ -730,7 +816,7 @@ int clock_init(void)
730 * Dump some clockes. 816 * Dump some clockes.
731 */ 817 */
732#ifndef CONFIG_SPL_BUILD 818#ifndef CONFIG_SPL_BUILD
733int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, 819int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
734 char * const argv[]) 820 char * const argv[])
735{ 821{
736 u32 freq; 822 u32 freq;
@@ -785,7 +871,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
785} 871}
786 872
787U_BOOT_CMD( 873U_BOOT_CMD(
788 clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks, 874 clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
789 "display clocks", 875 "display clocks",
790 "" 876 ""
791); 877);
diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 1a67c626f1..1a67c626f1 100644
--- a/arch/arm/mach-imx/mx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
diff --git a/arch/arm/mach-imx/imx8m/imximage.cfg b/arch/arm/mach-imx/imx8m/imximage.cfg
new file mode 100644
index 0000000000..714b24273b
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imximage.cfg
@@ -0,0 +1,17 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#define __ASSEMBLY__
7
8FIT
9BOOT_FROM sd
10SIGNED_HDMI signed_hdmi_imx8m.bin
11LOADER spl/u-boot-spl-ddr.bin 0x7E1000
12SECOND_LOADER u-boot.itb 0x40200000 0x60000
13
14DDR_FW lpddr4_pmu_train_1d_imem.bin
15DDR_FW lpddr4_pmu_train_1d_dmem.bin
16DDR_FW lpddr4_pmu_train_2d_imem.bin
17DDR_FW lpddr4_pmu_train_2d_dmem.bin
diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/imx8m/lowlevel_init.S
index a4c6466ca9..a4c6466ca9 100644
--- a/arch/arm/mach-imx/mx8m/lowlevel_init.S
+++ b/arch/arm/mach-imx/imx8m/lowlevel_init.S
diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 46873aa8dd..11251c5f9a 100644
--- a/arch/arm/mach-imx/mx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -78,6 +78,22 @@ static struct mm_region imx8m_mem_map[] = {
78 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 78 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
79 PTE_BLOCK_OUTER_SHARE 79 PTE_BLOCK_OUTER_SHARE
80 }, { 80 }, {
81 /* CAAM */
82 .virt = 0x100000UL,
83 .phys = 0x100000UL,
84 .size = 0x8000UL,
85 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
86 PTE_BLOCK_NON_SHARE |
87 PTE_BLOCK_PXN | PTE_BLOCK_UXN
88 }, {
89 /* TCM */
90 .virt = 0x7C0000UL,
91 .phys = 0x7C0000UL,
92 .size = 0x80000UL,
93 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
94 PTE_BLOCK_NON_SHARE |
95 PTE_BLOCK_PXN | PTE_BLOCK_UXN
96 }, {
81 /* OCRAM */ 97 /* OCRAM */
82 .virt = 0x900000UL, 98 .virt = 0x900000UL,
83 .phys = 0x900000UL, 99 .phys = 0x900000UL,
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index a1ea5c13f1..18d7e6819c 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -17,15 +17,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
17 if (!boot_private_data) 17 if (!boot_private_data)
18 return -EINVAL; 18 return -EINVAL;
19 19
20 stack = *(ulong *)boot_private_data; 20 stack = *(u32 *)boot_private_data;
21 pc = *(ulong *)(boot_private_data + 4); 21 pc = *(u32 *)(boot_private_data + 4);
22 22
23 /* Set the stack and pc to M4 bootROM */ 23 /* Set the stack and pc to M4 bootROM */
24 writel(stack, M4_BOOTROM_BASE_ADDR); 24 writel(stack, M4_BOOTROM_BASE_ADDR);
25 writel(pc, M4_BOOTROM_BASE_ADDR + 4); 25 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
26 26
27 /* Enable M4 */ 27 /* Enable M4 */
28#ifdef CONFIG_MX8M 28#ifdef CONFIG_IMX8M
29 call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); 29 call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
30#else 30#else
31 clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, 31 clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
37 37
38int arch_auxiliary_core_check_up(u32 core_id) 38int arch_auxiliary_core_check_up(u32 core_id)
39{ 39{
40#ifdef CONFIG_MX8M 40#ifdef CONFIG_IMX8M
41 return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); 41 return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
42#else 42#else
43 unsigned int val; 43 unsigned int val;
diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh
new file mode 100755
index 0000000000..77f7143263
--- /dev/null
+++ b/arch/arm/mach-imx/mkimage_fit_atf.sh
@@ -0,0 +1,137 @@
1#!/bin/sh
2# SPDX-License-Identifier: GPL-2.0+
3#
4# script to generate FIT image source for i.MX8MQ boards with
5# ARM Trusted Firmware and multiple device trees (given on the command line)
6#
7# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
8
9[ -z "$BL31" ] && BL31="bl31.bin"
10[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
11[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
12
13if [ ! -f $BL31 ]; then
14 echo "ERROR: BL31 file $BL31 NOT found" >&2
15 exit 0
16else
17 echo "$BL31 size: " >&2
18 ls -lct $BL31 | awk '{print $5}' >&2
19fi
20
21BL32="tee.bin"
22
23if [ ! -f $BL32 ]; then
24 BL32=/dev/null
25else
26 echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
27 echo "$BL32 size: " >&2
28 ls -lct $BL32 | awk '{print $5}' >&2
29fi
30
31BL33="u-boot-nodtb.bin"
32
33if [ ! -f $BL33 ]; then
34 echo "ERROR: $BL33 file NOT found" >&2
35 exit 0
36else
37 echo "u-boot-nodtb.bin size: " >&2
38 ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2
39fi
40
41for dtname in $*
42do
43 echo "$dtname size: " >&2
44 ls -lct $dtname | awk '{print $5}' >&2
45done
46
47
48cat << __HEADER_EOF
49/dts-v1/;
50
51/ {
52 description = "Configuration to load ATF before U-Boot";
53
54 images {
55 uboot@1 {
56 description = "U-Boot (64-bit)";
57 data = /incbin/("$BL33");
58 type = "standalone";
59 arch = "arm64";
60 compression = "none";
61 load = <0x40200000>;
62 };
63 atf@1 {
64 description = "ARM Trusted Firmware";
65 data = /incbin/("$BL31");
66 type = "firmware";
67 arch = "arm64";
68 compression = "none";
69 load = <$ATF_LOAD_ADDR>;
70 entry = <$ATF_LOAD_ADDR>;
71 };
72__HEADER_EOF
73
74if [ -f $BL32 ]; then
75cat << __HEADER_EOF
76 tee@1 {
77 description = "TEE firmware";
78 data = /incbin/("$BL32");
79 type = "firmware";
80 arch = "arm64";
81 compression = "none";
82 load = <$TEE_LOAD_ADDR>;
83 entry = <$TEE_LOAD_ADDR>;
84 };
85__HEADER_EOF
86fi
87
88cnt=1
89for dtname in $*
90do
91 cat << __FDT_IMAGE_EOF
92 fdt@$cnt {
93 description = "$(basename $dtname .dtb)";
94 data = /incbin/("$dtname");
95 type = "flat_dt";
96 compression = "none";
97 };
98__FDT_IMAGE_EOF
99cnt=$((cnt+1))
100done
101
102cat << __CONF_HEADER_EOF
103 };
104 configurations {
105 default = "config@1";
106
107__CONF_HEADER_EOF
108
109cnt=1
110for dtname in $*
111do
112if [ -f $BL32 ]; then
113cat << __CONF_SECTION_EOF
114 config@$cnt {
115 description = "$(basename $dtname .dtb)";
116 firmware = "uboot@1";
117 loadables = "atf@1", "tee@1";
118 fdt = "fdt@$cnt";
119 };
120__CONF_SECTION_EOF
121else
122cat << __CONF_SECTION1_EOF
123 config@$cnt {
124 description = "$(basename $dtname .dtb)";
125 firmware = "uboot@1";
126 loadables = "atf@1";
127 fdt = "fdt@$cnt";
128 };
129__CONF_SECTION1_EOF
130fi
131cnt=$((cnt+1))
132done
133
134cat << __ITS_EOF
135 };
136};
137__ITS_EOF
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 06c25bae36..3d56346ccb 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -182,6 +182,7 @@ config TARGET_DISPLAY5
182config TARGET_EMBESTMX6BOARDS 182config TARGET_EMBESTMX6BOARDS
183 bool "embestmx6boards" 183 bool "embestmx6boards"
184 select BOARD_LATE_INIT 184 select BOARD_LATE_INIT
185 select SUPPORT_SPL
185 186
186config TARGET_GE_BX50V3 187config TARGET_GE_BX50V3
187 bool "General Electric Bx50v3" 188 bool "General Electric Bx50v3"
@@ -262,7 +263,7 @@ config TARGET_MX6DL_MAMOJ
262 select SPL_PINCTRL if SPL 263 select SPL_PINCTRL if SPL
263 select SPL_SEPARATE_BSS if SPL 264 select SPL_SEPARATE_BSS if SPL
264 select SPL_SERIAL_SUPPORT if SPL 265 select SPL_SERIAL_SUPPORT if SPL
265 select SPL_USB_GADGET_SUPPORT if SPL 266 select SPL_USB_GADGET if SPL
266 select SPL_USB_HOST_SUPPORT if SPL 267 select SPL_USB_HOST_SUPPORT if SPL
267 select SPL_USB_SDP_SUPPORT if SPL 268 select SPL_USB_SDP_SUPPORT if SPL
268 select SPL_WATCHDOG_SUPPORT if SPL 269 select SPL_WATCHDOG_SUPPORT if SPL
diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
deleted file mode 100644
index 3a84c2f2b0..0000000000
--- a/arch/arm/mach-imx/mx8m/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
1if ARCH_MX8M
2
3config MX8M
4 bool
5 select ROM_UNIFIED_SECTIONS
6
7config SYS_SOC
8 default "mx8m"
9
10endif
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index a20b30d154..397d6d4a91 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -96,8 +96,8 @@ u32 spl_boot_device(void)
96 return BOOT_DEVICE_NONE; 96 return BOOT_DEVICE_NONE;
97} 97}
98 98
99#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) 99#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
100/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ 100/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
101u32 spl_boot_device(void) 101u32 spl_boot_device(void)
102{ 102{
103#if defined(CONFIG_MX7) 103#if defined(CONFIG_MX7)
@@ -126,6 +126,7 @@ u32 spl_boot_device(void)
126 enum boot_device boot_device_spl = get_boot_device(); 126 enum boot_device boot_device_spl = get_boot_device();
127 127
128 switch (boot_device_spl) { 128 switch (boot_device_spl) {
129#if defined(CONFIG_MX7)
129 case SD1_BOOT: 130 case SD1_BOOT:
130 case MMC1_BOOT: 131 case MMC1_BOOT:
131 case SD2_BOOT: 132 case SD2_BOOT:
@@ -133,6 +134,14 @@ u32 spl_boot_device(void)
133 case SD3_BOOT: 134 case SD3_BOOT:
134 case MMC3_BOOT: 135 case MMC3_BOOT:
135 return BOOT_DEVICE_MMC1; 136 return BOOT_DEVICE_MMC1;
137#elif defined(CONFIG_IMX8M)
138 case SD1_BOOT:
139 case MMC1_BOOT:
140 return BOOT_DEVICE_MMC1;
141 case SD2_BOOT:
142 case MMC2_BOOT:
143 return BOOT_DEVICE_MMC2;
144#endif
136 case NAND_BOOT: 145 case NAND_BOOT:
137 return BOOT_DEVICE_NAND; 146 return BOOT_DEVICE_NAND;
138 case SPI_NOR_BOOT: 147 case SPI_NOR_BOOT:
@@ -143,9 +152,9 @@ u32 spl_boot_device(void)
143 return BOOT_DEVICE_NONE; 152 return BOOT_DEVICE_NONE;
144 } 153 }
145} 154}
146#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ 155#endif /* CONFIG_MX7 || CONFIG_IMX8M */
147 156
148#ifdef CONFIG_SPL_USB_GADGET_SUPPORT 157#ifdef CONFIG_SPL_USB_GADGET
149int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) 158int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
150{ 159{
151 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct); 160 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct);
@@ -220,14 +229,46 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
220 229
221 debug("image entry point: 0x%lX\n", spl_image->entry_point); 230 debug("image entry point: 0x%lX\n", spl_image->entry_point);
222 231
223 /* HAB looks for the CSF at the end of the authenticated data therefore, 232 if (spl_image->flags & SPL_FIT_FOUND) {
224 * we need to subtract the size of the CSF from the actual filesize */
225 offset = spl_image->size - CONFIG_CSF_SIZE;
226 if (!imx_hab_authenticate_image(spl_image->load_addr,
227 offset + IVT_SIZE + CSF_PAD_SIZE,
228 offset)) {
229 image_entry(); 233 image_entry();
230 } else { 234 } else {
235 /*
236 * HAB looks for the CSF at the end of the authenticated
237 * data therefore, we need to subtract the size of the
238 * CSF from the actual filesize
239 */
240 offset = spl_image->size - CONFIG_CSF_SIZE;
241 if (!imx_hab_authenticate_image(spl_image->load_addr,
242 offset + IVT_SIZE +
243 CSF_PAD_SIZE, offset)) {
244 image_entry();
245 } else {
246 puts("spl: ERROR: image authentication fail\n");
247 hang();
248 }
249 }
250}
251
252ulong board_spl_fit_size_align(ulong size)
253{
254 /*
255 * HAB authenticate_image requests the IVT offset is
256 * aligned to 0x1000
257 */
258
259 size = ALIGN(size, 0x1000);
260 size += CONFIG_CSF_SIZE;
261
262 return size;
263}
264
265void board_spl_fit_post_load(ulong load_addr, size_t length)
266{
267 u32 offset = length - CONFIG_CSF_SIZE;
268
269 if (imx_hab_authenticate_image(load_addr,
270 offset + IVT_SIZE + CSF_PAD_SIZE,
271 offset)) {
231 puts("spl: ERROR: image authentication unsuccessful\n"); 272 puts("spl: ERROR: image authentication unsuccessful\n");
232 hang(); 273 hang();
233 } 274 }
diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 7fc0b3f357..be00d79fb0 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -37,7 +37,7 @@ cmd_gencert = cat $(srctree)/tools/k3_x509template.txt | sed $(SED_OPTS) > u-boo
37ifeq ($(CONFIG_SYS_K3_KEY), "") 37ifeq ($(CONFIG_SYS_K3_KEY), "")
38KEY=u-boot-spl-eckey.pem 38KEY=u-boot-spl-eckey.pem
39else 39else
40KEY=$(patsubst "%",%,$(CONFIG_SYS_K3_KEY)) 40KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
41endif 41endif
42 42
43u-boot-spl-eckey.pem: FORCE 43u-boot-spl-eckey.pem: FORCE
diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
index 90dd4ea48e..3375796b79 100644
--- a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
+++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
@@ -5,6 +5,14 @@
5 5
6#include <linux/linkage.h> 6#include <linux/linkage.h>
7 7
8#define WAIT_CODE_SRAM_BASE 0x0010ff00
9
10#define SLAVE_JUMP_REG 0x10202034
11#define SLAVE1_MAGIC_REG 0x10202038
12#define SLAVE1_MAGIC_NUM 0x534c4131
13
14#define GIC_CPU_BASE 0x10320000
15
8ENTRY(lowlevel_init) 16ENTRY(lowlevel_init)
9 17
10#ifndef CONFIG_SPL_BUILD 18#ifndef CONFIG_SPL_BUILD
@@ -28,6 +36,7 @@ ENTRY(lowlevel_init)
28 mrc p15, 0, r0, c0, c0, 5 36 mrc p15, 0, r0, c0, c0, 5
29 ands r1, r0, #0x40000000 37 ands r1, r0, #0x40000000
30 bne go @ Go if UP 38 bne go @ Go if UP
39 /* read slave CPU number */
31 ands r0, r0, #0x0f 40 ands r0, r0, #0x0f
32 beq go @ Go if core0 on primary core tile 41 beq go @ Go if core0 on primary core tile
33 b secondary 42 b secondary
@@ -37,14 +46,41 @@ go:
37 mov pc, lr 46 mov pc, lr
38 47
39secondary: 48secondary:
40 /* read slave CPU number into r0 firstly */ 49 /* enable GIC as cores will be waken up by IPI */
41 mrc p15, 0, r0, c0, c0, 5 50 ldr r2, =GIC_CPU_BASE
42 and r0, r0, #0x0f 51 mov r1, #0xf0
52 str r1, [r2, #4]
53 mov r1, #1
54 str r1, [r2, #0]
55
56 ldr r1, [r2]
57 orr r1, #1
58 str r1, [r2]
59
60 /* copy wait code into SRAM */
61 ldr r0, =slave_cpu_wait
62 ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
63 ldr r0, =WAIT_CODE_SRAM_BASE
64 stm r0, {r1 - r8}
65
66 /* pass args to slave_cpu_wait */
67 ldr r0, =SLAVE1_MAGIC_REG
68 ldr r1, =SLAVE1_MAGIC_NUM
69
70 /* jump to wait code in SRAM */
71 ldr pc, =WAIT_CODE_SRAM_BASE
43 72
44loop:
45 dsb
46 isb
47 wfi @Zzz...
48 b loop
49#endif 73#endif
50ENDPROC(lowlevel_init) 74ENDPROC(lowlevel_init)
75
76/* This function will be copied into SRAM */
77ENTRY(slave_cpu_wait)
78 wfi
79 ldr r2, [r0]
80 cmp r2, r1
81 bne slave_cpu_wait
82 movw r0, #:lower16:SLAVE_JUMP_REG
83 movt r0, #:upper16:SLAVE_JUMP_REG
84 ldr r1, [r0]
85 mov pc, r1
86ENDPROC(slave_cpu_wait)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index aa1be8ebab..919d05c88c 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -283,10 +283,8 @@ int print_cpuinfo(void)
283 * and sets the correct windows sizes and base addresses accordingly. 283 * and sets the correct windows sizes and base addresses accordingly.
284 * 284 *
285 * These values are set in the scratch registers by the Marvell 285 * These values are set in the scratch registers by the Marvell
286 * DDR3 training code, which is executed by the BootROM before the 286 * DDR3 training code, which is executed by the SPL before the
287 * main payload (U-Boot) is executed. This training code is currently 287 * main payload (U-Boot) is executed.
288 * only available in the Marvell U-Boot version. It needs to be
289 * ported to mainline U-Boot SPL at some point.
290 */ 288 */
291static void update_sdram_window_sizes(void) 289static void update_sdram_window_sizes(void)
292{ 290{
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index e0d02fb4e5..0286b0daa3 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -3,18 +3,23 @@ if OMAP34XX
3# We only enable the clocks for the GPIO banks that a given board requies. 3# We only enable the clocks for the GPIO banks that a given board requies.
4config OMAP3_GPIO_2 4config OMAP3_GPIO_2
5 bool 5 bool
6 default y if CMD_GPIO
6 7
7config OMAP3_GPIO_3 8config OMAP3_GPIO_3
8 bool 9 bool
10 default y if CMD_GPIO
9 11
10config OMAP3_GPIO_4 12config OMAP3_GPIO_4
11 bool 13 bool
14 default y if CMD_GPIO
12 15
13config OMAP3_GPIO_5 16config OMAP3_GPIO_5
14 bool 17 bool
18 default y if CMD_GPIO
15 19
16config OMAP3_GPIO_6 20config OMAP3_GPIO_6
17 bool 21 bool
22 default y if CMD_GPIO
18 23
19choice 24choice
20 prompt "OMAP3 board select" 25 prompt "OMAP3 board select"
diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c
index 9a03bfa9d3..cb9e91ebc3 100644
--- a/arch/arm/mach-omap2/omap3/clock.c
+++ b/arch/arm/mach-omap2/omap3/clock.c
@@ -750,23 +750,23 @@ void per_clocks_enable(void)
750 setbits_le32(&prcm_base->iclken_per, 0x00000800); 750 setbits_le32(&prcm_base->iclken_per, 0x00000800);
751#endif 751#endif
752 752
753#if (CONFIG_IS_ENABLED(OMAP3_GPIO_2) || CONFIG_IS_ENABLED(CMD_GPIO)) 753#if defined(CONFIG_OMAP3_GPIO_2)
754 setbits_le32(&prcm_base->fclken_per, 0x00002000); 754 setbits_le32(&prcm_base->fclken_per, 0x00002000);
755 setbits_le32(&prcm_base->iclken_per, 0x00002000); 755 setbits_le32(&prcm_base->iclken_per, 0x00002000);
756#endif 756#endif
757#if (CONFIG_IS_ENABLED(OMAP3_GPIO_3) || CONFIG_IS_ENABLED(CMD_GPIO)) 757#if defined(CONFIG_OMAP3_GPIO_3)
758 setbits_le32(&prcm_base->fclken_per, 0x00004000); 758 setbits_le32(&prcm_base->fclken_per, 0x00004000);
759 setbits_le32(&prcm_base->iclken_per, 0x00004000); 759 setbits_le32(&prcm_base->iclken_per, 0x00004000);
760#endif 760#endif
761#if (CONFIG_IS_ENABLED(OMAP3_GPIO_4) || CONFIG_IS_ENABLED(CMD_GPIO)) 761#if defined(CONFIG_OMAP3_GPIO_4)
762 setbits_le32(&prcm_base->fclken_per, 0x00008000); 762 setbits_le32(&prcm_base->fclken_per, 0x00008000);
763 setbits_le32(&prcm_base->iclken_per, 0x00008000); 763 setbits_le32(&prcm_base->iclken_per, 0x00008000);
764#endif 764#endif
765#if (CONFIG_IS_ENABLED(OMAP3_GPIO_5) || CONFIG_IS_ENABLED(CMD_GPIO)) 765#if defined(CONFIG_OMAP3_GPIO_5)
766 setbits_le32(&prcm_base->fclken_per, 0x00010000); 766 setbits_le32(&prcm_base->fclken_per, 0x00010000);
767 setbits_le32(&prcm_base->iclken_per, 0x00010000); 767 setbits_le32(&prcm_base->iclken_per, 0x00010000);
768#endif 768#endif
769#if (CONFIG_IS_ENABLED(OMAP3_GPIO_6) || CONFIG_IS_ENABLED(CMD_GPIO)) 769#if defined(CONFIG_OMAP3_GPIO_6)
770 setbits_le32(&prcm_base->fclken_per, 0x00020000); 770 setbits_le32(&prcm_base->fclken_per, 0x00020000);
771 setbits_le32(&prcm_base->iclken_per, 0x00020000); 771 setbits_le32(&prcm_base->iclken_per, 0x00020000);
772#endif 772#endif
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 4e5690eae3..2012d9fe04 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0+ 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/* 2/*
3 * (C) Copyright 2015 Google, Inc 3 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
4 */ 4 */
5#include <common.h> 5#include <common.h>
6#include <asm/io.h> 6#include <asm/io.h>
diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 650d53e4d9..a27138083a 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -48,6 +48,24 @@ size_t rockchip_sdram_size(phys_addr_t reg)
48 rank, col, bk, cs0_row, bw, row_3_4); 48 rank, col, bk, cs0_row, bw, row_3_4);
49 } 49 }
50 50
51 /*
52 * This is workaround for issue we can't get correct size for 4GB ram
53 * in 32bit system and available before we really need ram space
54 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
55 * The size of 4GB is '0x1 00000000', and this value will be truncated
56 * to 0 in 32bit system, and system can not get correct ram size.
57 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
58 * and we are now setting SDRAM_MAX_SIZE as max available space for
59 * ram in 4GB, so we can use this directly to workaround the issue.
60 * TODO:
61 * 1. update correct value for SDRAM_MAX_SIZE as what dram
62 * controller sees.
63 * 2. update board_get_usable_ram_top() and dram_init_banksize()
64 * to reserve memory for peripheral space after previous update.
65 */
66 if (size_mb > (SDRAM_MAX_SIZE >> 20))
67 size_mb = (SDRAM_MAX_SIZE >> 20);
68
51 return (size_t)size_mb << 20; 69 return (size_t)size_mb << 20;
52} 70}
53 71
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 06f8527aa4..5e87371f8c 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -35,6 +35,7 @@ config TARGET_SOCFPGA_STRATIX10
35 select ARMV8_MULTIENTRY 35 select ARMV8_MULTIENTRY
36 select ARMV8_SET_SMPEN 36 select ARMV8_SET_SMPEN
37 select ARMV8_SPIN_TABLE 37 select ARMV8_SPIN_TABLE
38 select FPGA_STRATIX10
38 39
39choice 40choice
40 prompt "Altera SOCFPGA board select" 41 prompt "Altera SOCFPGA board select"
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 81a609d2f8..ae728a5df5 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -107,6 +107,12 @@ enum ALT_SDM_MBOX_RESP_CODE {
107#define RECONFIG_STATUS_PIN_STATUS 2 107#define RECONFIG_STATUS_PIN_STATUS 2
108#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 108#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
109 109
110/* Macros for specifying number of arguments in mailbox command */
111#define MBOX_NUM_ARGS(n, b) (((n) & 0xFF) << (b))
112#define MBOX_DIRECT_COUNT(n) MBOX_NUM_ARGS((n), 0)
113#define MBOX_ARG_DESC_COUNT(n) MBOX_NUM_ARGS((n), 8)
114#define MBOX_RESP_DESC_COUNT(n) MBOX_NUM_ARGS((n), 16)
115
110#define MBOX_CFGSTAT_STATE_IDLE 0x00000000 116#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
111#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 117#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
112#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 118#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
@@ -140,5 +146,6 @@ int mbox_qspi_open(void);
140#endif 146#endif
141 147
142int mbox_reset_cold(void); 148int mbox_reset_cold(void);
143 149int mbox_get_fpga_config_status(u32 cmd);
150int mbox_get_fpga_config_status_psci(u32 cmd);
144#endif /* _MAILBOX_S10_H_ */ 151#endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 26609927c8..86d5d2b62b 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -18,9 +18,9 @@ struct bsel {
18extern struct bsel bsel_str[]; 18extern struct bsel bsel_str[];
19 19
20#ifdef CONFIG_FPGA 20#ifdef CONFIG_FPGA
21void socfpga_fpga_add(void); 21void socfpga_fpga_add(void *fpga_desc);
22#else 22#else
23static inline void socfpga_fpga_add(void) {} 23inline void socfpga_fpga_add(void *fpga_desc) {}
24#endif 24#endif
25 25
26#ifdef CONFIG_TARGET_SOCFPGA_GEN5 26#ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 0d906c3480..3c33223936 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -342,6 +342,54 @@ int mbox_reset_cold(void)
342 return 0; 342 return 0;
343} 343}
344 344
345/* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
346static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
347{
348 u32 reconfig_status_resp_len;
349 u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
350 int ret;
351
352 reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
353 ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
354 MBOX_CMD_DIRECT, 0, NULL, 0,
355 &reconfig_status_resp_len,
356 reconfig_status_resp);
357
358 if (ret)
359 return ret;
360
361 /* Check for any error */
362 ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
363 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
364 return ret;
365
366 /* Make sure nStatus is not 0 */
367 ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
368 if (!(ret & RCF_PIN_STATUS_NSTATUS))
369 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
370
371 ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
372 if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
373 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
374
375 if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
376 (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
377 !reconfig_status_resp[RECONFIG_STATUS_STATE])
378 return 0; /* configuration success */
379
380 return MBOX_CFGSTAT_STATE_CONFIG;
381}
382
383int mbox_get_fpga_config_status(u32 cmd)
384{
385 return mbox_get_fpga_config_status_common(cmd);
386}
387
388int __secure mbox_get_fpga_config_status_psci(u32 cmd)
389{
390 return mbox_get_fpga_config_status_common(cmd);
391}
392
345int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, 393int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
346 u8 urgent, u32 *resp_buf_len, u32 *resp_buf) 394 u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
347{ 395{
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index a4f6d5c1ac..78fbe28724 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -88,33 +88,11 @@ int overwrite_console(void)
88#endif 88#endif
89 89
90#ifdef CONFIG_FPGA 90#ifdef CONFIG_FPGA
91/*
92 * FPGA programming support for SoC FPGA Cyclone V
93 */
94static Altera_desc altera_fpga[] = {
95 {
96 /* Family */
97 Altera_SoCFPGA,
98 /* Interface type */
99 fast_passive_parallel,
100 /* No limitation as additional data will be ignored */
101 -1,
102 /* No device function table */
103 NULL,
104 /* Base interface address specified in driver */
105 NULL,
106 /* No cookie implementation */
107 0
108 },
109};
110
111/* add device descriptor to FPGA device table */ 91/* add device descriptor to FPGA device table */
112void socfpga_fpga_add(void) 92void socfpga_fpga_add(void *fpga_desc)
113{ 93{
114 int i;
115 fpga_init(); 94 fpga_init();
116 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 95 fpga_add(fpga_altera, fpga_desc);
117 fpga_add(fpga_altera, &altera_fpga[i]);
118} 96}
119#endif 97#endif
120 98
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index f347ae857e..63b8c75d31 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -30,6 +30,27 @@
30 30
31static struct socfpga_system_manager *sysmgr_regs = 31static struct socfpga_system_manager *sysmgr_regs =
32 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 32 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
33
34/*
35 * FPGA programming support for SoC FPGA Arria 10
36 */
37static Altera_desc altera_fpga[] = {
38 {
39 /* Family */
40 Altera_SoCFPGA,
41 /* Interface type */
42 fast_passive_parallel,
43 /* No limitation as additional data will be ignored */
44 -1,
45 /* No device function table */
46 NULL,
47 /* Base interface address specified in driver */
48 NULL,
49 /* No cookie implementation */
50 0
51 },
52};
53
33#if defined(CONFIG_SPL_BUILD) 54#if defined(CONFIG_SPL_BUILD)
34static struct pl310_regs *const pl310 = 55static struct pl310_regs *const pl310 =
35 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 56 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -73,7 +94,7 @@ void socfpga_sdram_remap_zero(void)
73int arch_early_init_r(void) 94int arch_early_init_r(void)
74{ 95{
75 /* Add device descriptor to FPGA device table */ 96 /* Add device descriptor to FPGA device table */
76 socfpga_fpga_add(); 97 socfpga_fpga_add(&altera_fpga[0]);
77 98
78 return 0; 99 return 0;
79} 100}
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 5fa40937c4..04f237d100 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -35,6 +35,26 @@ static struct scu_registers *scu_regs =
35 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 35 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
36 36
37/* 37/*
38 * FPGA programming support for SoC FPGA Cyclone V
39 */
40static Altera_desc altera_fpga[] = {
41 {
42 /* Family */
43 Altera_SoCFPGA,
44 /* Interface type */
45 fast_passive_parallel,
46 /* No limitation as additional data will be ignored */
47 -1,
48 /* No device function table */
49 NULL,
50 /* Base interface address specified in driver */
51 NULL,
52 /* No cookie implementation */
53 0
54 },
55};
56
57/*
38 * DesignWare Ethernet initialization 58 * DesignWare Ethernet initialization
39 */ 59 */
40#ifdef CONFIG_ETH_DESIGNWARE 60#ifdef CONFIG_ETH_DESIGNWARE
@@ -221,7 +241,7 @@ int arch_early_init_r(void)
221 socfpga_sdram_remap_zero(); 241 socfpga_sdram_remap_zero();
222 242
223 /* Add device descriptor to FPGA device table */ 243 /* Add device descriptor to FPGA device table */
224 socfpga_fpga_add(); 244 socfpga_fpga_add(&altera_fpga[0]);
225 245
226#ifdef CONFIG_DESIGNWARE_SPI 246#ifdef CONFIG_DESIGNWARE_SPI
227 /* Get Designware SPI controller out of reset */ 247 /* Get Designware SPI controller out of reset */
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index e599362f14..113eace650 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -25,6 +25,26 @@ static struct socfpga_system_manager *sysmgr_regs =
25 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 25 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
26 26
27/* 27/*
28 * FPGA programming support for SoC FPGA Stratix 10
29 */
30static Altera_desc altera_fpga[] = {
31 {
32 /* Family */
33 Intel_FPGA_Stratix10,
34 /* Interface type */
35 secure_device_manager_mailbox,
36 /* No limitation as additional data will be ignored */
37 -1,
38 /* No device function table */
39 NULL,
40 /* Base interface address specified in driver */
41 NULL,
42 /* No cookie implementation */
43 0
44 },
45};
46
47/*
28 * DesignWare Ethernet initialization 48 * DesignWare Ethernet initialization
29 */ 49 */
30#ifdef CONFIG_ETH_DESIGNWARE 50#ifdef CONFIG_ETH_DESIGNWARE
@@ -125,6 +145,8 @@ int arch_misc_init(void)
125 145
126int arch_early_init_r(void) 146int arch_early_init_r(void)
127{ 147{
148 socfpga_fpga_add(&altera_fpga[0]);
149
128 return 0; 150 return 0;
129} 151}
130 152
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 1b871c62ce..972dbe8ae5 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -66,20 +66,20 @@ int board_late_init(void)
66 switch (uniphier_boot_device_raw()) { 66 switch (uniphier_boot_device_raw()) {
67 case BOOT_DEVICE_MMC1: 67 case BOOT_DEVICE_MMC1:
68 printf("eMMC Boot"); 68 printf("eMMC Boot");
69 env_set("bootcmd", "run bootcmd_mmc0; run distro_bootcmd"); 69 env_set("bootdev", "emmc");
70 break; 70 break;
71 case BOOT_DEVICE_NAND: 71 case BOOT_DEVICE_NAND:
72 printf("NAND Boot"); 72 printf("NAND Boot");
73 env_set("bootcmd", "run bootcmd_ubifs0; run distro_bootcmd"); 73 env_set("bootdev", "nand");
74 nand_denali_wp_disable(); 74 nand_denali_wp_disable();
75 break; 75 break;
76 case BOOT_DEVICE_NOR: 76 case BOOT_DEVICE_NOR:
77 printf("NOR Boot"); 77 printf("NOR Boot");
78 env_set("bootcmd", "run tftpboot; run distro_bootcmd"); 78 env_set("bootdev", "nor");
79 break; 79 break;
80 case BOOT_DEVICE_USB: 80 case BOOT_DEVICE_USB:
81 printf("USB Boot"); 81 printf("USB Boot");
82 env_set("bootcmd", "run bootcmd_usb0; run distro_bootcmd"); 82 env_set("bootdev", "usb");
83 break; 83 break;
84 default: 84 default:
85 printf("Unknown"); 85 printf("Unknown");
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b1b1d7d00..194f4f349e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -59,6 +59,11 @@ config ARCH_ATH79
59 select OF_CONTROL 59 select OF_CONTROL
60 imply CMD_DM 60 imply CMD_DM
61 61
62config ARCH_MSCC
63 bool "Support MSCC VCore-III"
64 select OF_CONTROL
65 select DM
66
62config ARCH_BMIPS 67config ARCH_BMIPS
63 bool "Support BMIPS SoCs" 68 bool "Support BMIPS SoCs"
64 select CLK 69 select CLK
@@ -79,7 +84,7 @@ config ARCH_MT7620
79 select DM_SERIAL 84 select DM_SERIAL
80 imply DM_SPI 85 imply DM_SPI
81 imply DM_SPI_FLASH 86 imply DM_SPI_FLASH
82 select ARCH_MISC_INIT if WATCHDOG 87 select ARCH_MISC_INIT
83 select MIPS_TUNE_24KC 88 select MIPS_TUNE_24KC
84 select OF_CONTROL 89 select OF_CONTROL
85 select ROM_EXCEPTION_VECTORS 90 select ROM_EXCEPTION_VECTORS
@@ -88,6 +93,12 @@ config ARCH_MT7620
88 select SUPPORTS_LITTLE_ENDIAN 93 select SUPPORTS_LITTLE_ENDIAN
89 select SYSRESET 94 select SYSRESET
90 95
96config ARCH_JZ47XX
97 bool "Support Ingenic JZ47xx"
98 select SUPPORT_SPL
99 select OF_CONTROL
100 select DM
101
91config MACH_PIC32 102config MACH_PIC32
92 bool "Support Microchip PIC32" 103 bool "Support Microchip PIC32"
93 select DM 104 select DM
@@ -138,7 +149,9 @@ source "board/imgtec/xilfpga/Kconfig"
138source "board/micronas/vct/Kconfig" 149source "board/micronas/vct/Kconfig"
139source "board/qemu-mips/Kconfig" 150source "board/qemu-mips/Kconfig"
140source "arch/mips/mach-ath79/Kconfig" 151source "arch/mips/mach-ath79/Kconfig"
152source "arch/mips/mach-mscc/Kconfig"
141source "arch/mips/mach-bmips/Kconfig" 153source "arch/mips/mach-bmips/Kconfig"
154source "arch/mips/mach-jz47xx/Kconfig"
142source "arch/mips/mach-pic32/Kconfig" 155source "arch/mips/mach-pic32/Kconfig"
143source "arch/mips/mach-mt7620/Kconfig" 156source "arch/mips/mach-mt7620/Kconfig"
144 157
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 802244a06e..029d290f1e 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -13,8 +13,10 @@ libs-y += arch/mips/lib/
13 13
14machine-$(CONFIG_ARCH_ATH79) += ath79 14machine-$(CONFIG_ARCH_ATH79) += ath79
15machine-$(CONFIG_ARCH_BMIPS) += bmips 15machine-$(CONFIG_ARCH_BMIPS) += bmips
16machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
16machine-$(CONFIG_MACH_PIC32) += pic32 17machine-$(CONFIG_MACH_PIC32) += pic32
17machine-$(CONFIG_ARCH_MT7620) += mt7620 18machine-$(CONFIG_ARCH_MT7620) += mt7620
19machine-$(CONFIG_ARCH_MSCC) += mscc
18 20
19machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) 21machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
20libs-y += $(machdirs) 22libs-y += $(machdirs)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 5c56ab0289..a403ff729b 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
28} 28}
29#endif 29#endif
30 30
31void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
32{
33 write_c0_entrylo0(low0);
34 write_c0_pagemask(pagemask);
35 write_c0_entrylo1(low1);
36 write_c0_entryhi(hi);
37 write_c0_index(index);
38 tlb_write_indexed();
39}
40
41int arch_cpu_init(void) 31int arch_cpu_init(void)
42{ 32{
43 mips_cache_probe(); 33 mips_cache_probe();
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b447141f87..647d2bf0d5 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
16dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb 16dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
17dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb 17dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
18dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb 18dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
19dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
19 20
20targets += $(dtb-y) 21targets += $(dtb-y)
21 22
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
index 85fb14b13b..37354324fe 100644
--- a/arch/mips/dts/ar933x.dtsi
+++ b/arch/mips/dts/ar933x.dtsi
@@ -3,7 +3,6 @@
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 */ 4 */
5 5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include "skeleton.dtsi" 6#include "skeleton.dtsi"
8 7
9/ { 8/ {
@@ -68,7 +67,6 @@
68 uart0: uart@18020000 { 67 uart0: uart@18020000 {
69 compatible = "qca,ar9330-uart"; 68 compatible = "qca,ar9330-uart";
70 reg = <0x18020000 0x20>; 69 reg = <0x18020000 0x20>;
71 interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
72 70
73 status = "disabled"; 71 status = "disabled";
74 }; 72 };
@@ -103,7 +101,6 @@
103 spi0: spi@1f000000 { 101 spi0: spi@1f000000 {
104 compatible = "qca,ar7100-spi"; 102 compatible = "qca,ar7100-spi";
105 reg = <0x1f000000 0x10>; 103 reg = <0x1f000000 0x10>;
106 interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
107 104
108 status = "disabled"; 105 status = "disabled";
109 106
diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi
index f75988be12..d678dab242 100644
--- a/arch/mips/dts/brcm,bcm6318.dtsi
+++ b/arch/mips/dts/brcm,bcm6318.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm6318-clock.h> 6#include <dt-bindings/clock/bcm6318-clock.h>
7#include <dt-bindings/dma/bcm6318-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/power-domain/bcm6318-power-domain.h> 9#include <dt-bindings/power-domain/bcm6318-power-domain.h>
9#include <dt-bindings/reset/bcm6318-reset.h> 10#include <dt-bindings/reset/bcm6318-reset.h>
@@ -54,6 +55,12 @@
54 reg = <0x10000004 0x4>; 55 reg = <0x10000004 0x4>;
55 #clock-cells = <1>; 56 #clock-cells = <1>;
56 }; 57 };
58
59 ubus_clk: ubus-clk {
60 compatible = "brcm,bcm6345-clk";
61 reg = <0x10000008 0x4>;
62 #clock-cells = <1>;
63 };
57 }; 64 };
58 65
59 ubus { 66 ubus {
@@ -182,5 +189,36 @@
182 189
183 status = "disabled"; 190 status = "disabled";
184 }; 191 };
192
193 enet: ethernet@10080000 {
194 compatible = "brcm,bcm6368-enet";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 reg = <0x10080000 0x8000>;
198 clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
199 <&periph_clk BCM6318_CLK_ROBOSW025>,
200 <&ubus_clk BCM6318_UCLK_ROBOSW>;
201 resets = <&periph_rst BCM6318_RST_ENETSW>,
202 <&periph_rst BCM6318_RST_EPHY>;
203 dmas = <&iudma BCM6318_DMA_ENETSW_RX>,
204 <&iudma BCM6318_DMA_ENETSW_TX>;
205 dma-names = "rx",
206 "tx";
207 brcm,num-ports = <5>;
208
209 status = "disabled";
210 };
211
212 iudma: dma-controller@10088000 {
213 compatible = "brcm,bcm6368-iudma";
214 reg = <0x10088000 0x80>,
215 <0x10088200 0x80>,
216 <0x10088400 0x80>;
217 reg-names = "dma",
218 "dma-channels",
219 "dma-sram";
220 #dma-cells = <1>;
221 dma-channels = <8>;
222 };
185 }; 223 };
186}; 224};
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 62c440e675..f8a72ef535 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm63268-clock.h> 6#include <dt-bindings/clock/bcm63268-clock.h>
7#include <dt-bindings/dma/bcm63268-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/power-domain/bcm63268-power-domain.h> 9#include <dt-bindings/power-domain/bcm63268-power-domain.h>
9#include <dt-bindings/reset/bcm63268-reset.h> 10#include <dt-bindings/reset/bcm63268-reset.h>
@@ -217,5 +218,42 @@
217 reg = <0x10003000 0x894>; 218 reg = <0x10003000 0x894>;
218 u-boot,dm-pre-reloc; 219 u-boot,dm-pre-reloc;
219 }; 220 };
221
222 iudma: dma-controller@1000d800 {
223 compatible = "brcm,bcm6368-iudma";
224 reg = <0x1000d800 0x80>,
225 <0x1000da00 0x80>,
226 <0x1000dc00 0x80>;
227 reg-names = "dma",
228 "dma-channels",
229 "dma-sram";
230 #dma-cells = <1>;
231 dma-channels = <8>;
232 };
233
234 enet: ethernet@10700000 {
235 compatible = "brcm,bcm6368-enet";
236 #address-cells = <1>;
237 #size-cells = <0>;
238 reg = <0x10700000 0x10000>;
239 clocks = <&periph_clk BCM63268_CLK_GMAC>,
240 <&periph_clk BCM63268_CLK_ROBOSW>,
241 <&periph_clk BCM63268_CLK_ROBOSW250>,
242 <&timer_clk BCM63268_TCLK_EPHY1>,
243 <&timer_clk BCM63268_TCLK_EPHY2>,
244 <&timer_clk BCM63268_TCLK_EPHY3>,
245 <&timer_clk BCM63268_TCLK_GPHY>;
246 resets = <&periph_rst BCM63268_RST_ENETSW>,
247 <&periph_rst BCM63268_RST_EPHY>,
248 <&periph_rst BCM63268_RST_GPHY>;
249 dmas = <&iudma BCM63268_DMA_ENETSW_RX>,
250 <&iudma BCM63268_DMA_ENETSW_TX>;
251 dma-names = "rx",
252 "tx";
253 brcm,rgmii-override;
254 brcm,rgmii-timing;
255
256 status = "disabled";
257 };
220 }; 258 };
221}; 259};
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index e00a2950e2..50beed4171 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm6328-clock.h> 6#include <dt-bindings/clock/bcm6328-clock.h>
7#include <dt-bindings/dma/bcm6328-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/power-domain/bcm6328-power-domain.h> 9#include <dt-bindings/power-domain/bcm6328-power-domain.h>
9#include <dt-bindings/reset/bcm6328-reset.h> 10#include <dt-bindings/reset/bcm6328-reset.h>
@@ -187,5 +188,34 @@
187 reg = <0x10003000 0x864>; 188 reg = <0x10003000 0x864>;
188 u-boot,dm-pre-reloc; 189 u-boot,dm-pre-reloc;
189 }; 190 };
191
192 iudma: dma-controller@1000d800 {
193 compatible = "brcm,bcm6368-iudma";
194 reg = <0x1000d800 0x80>,
195 <0x1000da00 0x80>,
196 <0x1000dc00 0x80>;
197 reg-names = "dma",
198 "dma-channels",
199 "dma-sram";
200 #dma-cells = <1>;
201 dma-channels = <8>;
202 };
203
204 enet: ethernet@10e00000 {
205 compatible = "brcm,bcm6368-enet";
206 #address-cells = <1>;
207 #size-cells = <0>;
208 reg = <0x10e00000 0x10000>;
209 clocks = <&periph_clk BCM6328_CLK_ROBOSW>;
210 resets = <&periph_rst BCM6328_RST_ENETSW>,
211 <&periph_rst BCM6328_RST_EPHY>;
212 dmas = <&iudma BCM6328_DMA_ENETSW_RX>,
213 <&iudma BCM6328_DMA_ENETSW_TX>;
214 dma-names = "rx",
215 "tx";
216 brcm,num-ports = <5>;
217
218 status = "disabled";
219 };
190 }; 220 };
191}; 221};
diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi
index bbd58cf803..c547e949dd 100644
--- a/arch/mips/dts/brcm,bcm6338.dtsi
+++ b/arch/mips/dts/brcm,bcm6338.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm6338-clock.h> 6#include <dt-bindings/clock/bcm6338-clock.h>
7#include <dt-bindings/dma/bcm6338-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/reset/bcm6338-reset.h> 9#include <dt-bindings/reset/bcm6338-reset.h>
9#include "skeleton.dtsi" 10#include "skeleton.dtsi"
@@ -130,5 +131,33 @@
130 reg = <0xfffe3100 0x38>; 131 reg = <0xfffe3100 0x38>;
131 u-boot,dm-pre-reloc; 132 u-boot,dm-pre-reloc;
132 }; 133 };
134
135 iudma: dma-controller@fffe2400 {
136 compatible = "brcm,bcm6348-iudma";
137 reg = <0xfffe2400 0x1c>,
138 <0xfffe2500 0x60>,
139 <0xfffe2600 0x60>;
140 reg-names = "dma",
141 "dma-channels",
142 "dma-sram";
143 #dma-cells = <1>;
144 dma-channels = <6>;
145 resets = <&periph_rst BCM6338_RST_DMAMEM>;
146 };
147
148 enet: ethernet@fffe2800 {
149 compatible = "brcm,bcm6348-enet";
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0xfffe2800 0x2dc>;
153 clocks = <&periph_clk BCM6338_CLK_ENET>;
154 resets = <&periph_rst BCM6338_RST_ENET>;
155 dmas = <&iudma BCM6338_DMA_ENET_RX>,
156 <&iudma BCM6338_DMA_ENET_TX>;
157 dma-names = "rx",
158 "tx";
159
160 status = "disabled";
161 };
133 }; 162 };
134}; 163};
diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
index cc80bbc808..79e7bd892b 100644
--- a/arch/mips/dts/brcm,bcm6348.dtsi
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm6348-clock.h> 6#include <dt-bindings/clock/bcm6348-clock.h>
7#include <dt-bindings/dma/bcm6348-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/reset/bcm6348-reset.h> 9#include <dt-bindings/reset/bcm6348-reset.h>
9#include "skeleton.dtsi" 10#include "skeleton.dtsi"
@@ -159,5 +160,46 @@
159 reg = <0xfffe2300 0x38>; 160 reg = <0xfffe2300 0x38>;
160 u-boot,dm-pre-reloc; 161 u-boot,dm-pre-reloc;
161 }; 162 };
163
164 enet0: ethernet@fffe6000 {
165 compatible = "brcm,bcm6348-enet";
166 #address-cells = <1>;
167 #size-cells = <0>;
168 reg = <0xfffe6000 0x2dc>;
169 dmas = <&iudma BCM6348_DMA_ENET0_RX>,
170 <&iudma BCM6348_DMA_ENET0_TX>;
171 dma-names = "rx",
172 "tx";
173
174 status = "disabled";
175 };
176
177 enet1: ethernet@fffe6800 {
178 compatible = "brcm,bcm6348-enet";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 reg = <0xfffe6800 0x2dc>;
182 dmas = <&iudma BCM6348_DMA_ENET1_RX>,
183 <&iudma BCM6348_DMA_ENET1_TX>;
184 dma-names = "rx",
185 "tx";
186
187 status = "disabled";
188 };
189
190 iudma: dma-controller@fffe7000 {
191 compatible = "brcm,bcm6348-iudma";
192 reg = <0xfffe7000 0x1c>,
193 <0xfffe7100 0x40>,
194 <0xfffe7200 0x40>;
195 reg-names = "dma",
196 "dma-channels",
197 "dma-sram";
198 #dma-cells = <1>;
199 dma-channels = <4>;
200 clocks = <&periph_clk BCM6348_CLK_ENET>;
201 resets = <&periph_rst BCM6348_RST_ENET>,
202 <&periph_rst BCM6348_RST_DMAMEM>;
203 };
162 }; 204 };
163}; 205};
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
index 0617b46e92..5e9c9ad769 100644
--- a/arch/mips/dts/brcm,bcm6358.dtsi
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm6358-clock.h> 6#include <dt-bindings/clock/bcm6358-clock.h>
7#include <dt-bindings/dma/bcm6358-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/reset/bcm6358-reset.h> 9#include <dt-bindings/reset/bcm6358-reset.h>
9#include "skeleton.dtsi" 10#include "skeleton.dtsi"
@@ -190,5 +191,50 @@
190 191
191 status = "disabled"; 192 status = "disabled";
192 }; 193 };
194
195 enet0: ethernet@fffe4000 {
196 compatible = "brcm,bcm6348-enet";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 reg = <0xfffe4000 0x2dc>;
200 clocks = <&periph_clk BCM6358_CLK_ENET0>;
201 dmas = <&iudma BCM6358_DMA_ENET0_RX>,
202 <&iudma BCM6358_DMA_ENET0_TX>;
203 dma-names = "rx",
204 "tx";
205
206 status = "disabled";
207 };
208
209 enet1: ethernet@fffe4800 {
210 compatible = "brcm,bcm6348-enet";
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <0xfffe4800 0x2dc>;
214 clocks = <&periph_clk BCM6358_CLK_ENET1>;
215 dmas = <&iudma BCM6358_DMA_ENET1_RX>,
216 <&iudma BCM6358_DMA_ENET1_TX>;
217 dma-names = "rx",
218 "tx";
219
220 status = "disabled";
221 };
222
223 iudma: dma-controller@fffe5000 {
224 compatible = "brcm,bcm6348-iudma";
225 reg = <0xfffe5000 0x24>,
226 <0xfffe5100 0x80>,
227 <0xfffe5200 0x80>;
228 reg-names = "dma",
229 "dma-channels",
230 "dma-sram";
231 #dma-cells = <1>;
232 dma-channels = <8>;
233 clocks = <&periph_clk BCM6358_CLK_EMUSB>,
234 <&periph_clk BCM6358_CLK_USBSU>,
235 <&periph_clk BCM6358_CLK_EPHY>;
236 resets = <&periph_rst BCM6358_RST_ENET>,
237 <&periph_rst BCM6358_RST_EPHY>;
238 };
193 }; 239 };
194}; 240};
diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi
index 3047b82b21..c77b80a4cc 100644
--- a/arch/mips/dts/brcm,bcm6362.dtsi
+++ b/arch/mips/dts/brcm,bcm6362.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm6362-clock.h> 6#include <dt-bindings/clock/bcm6362-clock.h>
7#include <dt-bindings/dma/bcm6362-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/power-domain/bcm6362-power-domain.h> 9#include <dt-bindings/power-domain/bcm6362-power-domain.h>
9#include <dt-bindings/reset/bcm6362-reset.h> 10#include <dt-bindings/reset/bcm6362-reset.h>
@@ -211,5 +212,36 @@
211 reg = <0x10003000 0x864>; 212 reg = <0x10003000 0x864>;
212 u-boot,dm-pre-reloc; 213 u-boot,dm-pre-reloc;
213 }; 214 };
215
216 iudma: dma-controller@1000d800 {
217 compatible = "brcm,bcm6368-iudma";
218 reg = <0x1000d800 0x80>,
219 <0x1000da00 0x80>,
220 <0x1000dc00 0x80>;
221 reg-names = "dma",
222 "dma-channels",
223 "dma-sram";
224 #dma-cells = <1>;
225 dma-channels = <8>;
226 };
227
228 enet: ethernet@10e00000 {
229 compatible = "brcm,bcm6368-enet";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <0x10e00000 0x10000>;
233 clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
234 <&periph_clk BCM6362_CLK_SWPKT_SAR>,
235 <&periph_clk BCM6362_CLK_ROBOSW>;
236 resets = <&periph_rst BCM6362_RST_ENETSW>,
237 <&periph_rst BCM6362_RST_EPHY>;
238 dmas = <&iudma BCM6362_DMA_ENETSW_RX>,
239 <&iudma BCM6362_DMA_ENETSW_TX>;
240 dma-names = "rx",
241 "tx";
242 brcm,num-ports = <6>;
243
244 status = "disabled";
245 };
214 }; 246 };
215}; 247};
diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi
index 65d769ab4f..89590d6ff9 100644
--- a/arch/mips/dts/brcm,bcm6368.dtsi
+++ b/arch/mips/dts/brcm,bcm6368.dtsi
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <dt-bindings/clock/bcm6368-clock.h> 6#include <dt-bindings/clock/bcm6368-clock.h>
7#include <dt-bindings/dma/bcm6368-dma.h>
7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/reset/bcm6368-reset.h> 9#include <dt-bindings/reset/bcm6368-reset.h>
9#include "skeleton.dtsi" 10#include "skeleton.dtsi"
@@ -192,5 +193,36 @@
192 193
193 status = "disabled"; 194 status = "disabled";
194 }; 195 };
196
197 iudma: dma-controller@10006800 {
198 compatible = "brcm,bcm6368-iudma";
199 reg = <0x10006800 0x80>,
200 <0x10006a00 0x80>,
201 <0x10006c00 0x80>;
202 reg-names = "dma",
203 "dma-channels",
204 "dma-sram";
205 #dma-cells = <1>;
206 dma-channels = <8>;
207 };
208
209 enet: ethernet@10f00000 {
210 compatible = "brcm,bcm6368-enet";
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <0x10f00000 0x10000>;
214 clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
215 <&periph_clk BCM6368_CLK_SWPKT_SAR>,
216 <&periph_clk BCM6368_CLK_ROBOSW>;
217 resets = <&periph_rst BCM6368_RST_SWITCH>,
218 <&periph_rst BCM6368_RST_EPHY>;
219 dmas = <&iudma BCM6368_DMA_ENETSW_RX>,
220 <&iudma BCM6368_DMA_ENETSW_TX>;
221 dma-names = "rx",
222 "tx";
223 brcm,num-ports = <6>;
224
225 status = "disabled";
226 };
195 }; 227 };
196}; 228};
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index 0000000000..8d6417af73
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,122 @@
1// SPDX-License-Identifier: GPL-2.0+
2
3/dts-v1/;
4
5#include "jz4780.dtsi"
6
7/ {
8 compatible = "img,ci20", "ingenic,jz4780";
9
10 aliases {
11 serial0 = &uart0;
12 serial1 = &uart1;
13 serial3 = &uart3;
14 serial4 = &uart4;
15 };
16
17 chosen {
18 stdout-path = "serial4:115200n8";
19 };
20
21 memory {
22 device_type = "memory";
23 reg = <0x0 0x10000000
24 0x30000000 0x30000000>;
25 };
26};
27
28&ext {
29 clock-frequency = <48000000>;
30};
31
32&uart0 {
33 status = "okay";
34};
35
36&uart1 {
37 status = "okay";
38};
39
40&uart3 {
41 status = "okay";
42};
43
44&uart4 {
45 status = "okay";
46};
47
48&nemc {
49 status = "okay";
50
51 nandc: nand-controller@1 {
52 compatible = "ingenic,jz4780-nand";
53 reg = <1 0 0x1000000>;
54
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 ingenic,bch-controller = <&bch>;
59
60 ingenic,nemc-tAS = <10>;
61 ingenic,nemc-tAH = <5>;
62 ingenic,nemc-tBP = <10>;
63 ingenic,nemc-tAW = <15>;
64 ingenic,nemc-tSTRV = <100>;
65
66 nand@1 {
67 reg = <1>;
68
69 nand-ecc-step-size = <1024>;
70 nand-ecc-strength = <24>;
71 nand-ecc-mode = "hw";
72 nand-on-flash-bbt;
73
74 partitions {
75 compatible = "fixed-partitions";
76 #address-cells = <2>;
77 #size-cells = <2>;
78
79 partition@0 {
80 label = "u-boot-spl";
81 reg = <0x0 0x0 0x0 0x800000>;
82 };
83
84 partition@0x800000 {
85 label = "u-boot";
86 reg = <0x0 0x800000 0x0 0x200000>;
87 };
88
89 partition@0xa00000 {
90 label = "u-boot-env";
91 reg = <0x0 0xa00000 0x0 0x200000>;
92 };
93
94 partition@0xc00000 {
95 label = "boot";
96 reg = <0x0 0xc00000 0x0 0x4000000>;
97 };
98
99 partition@0x8c00000 {
100 label = "system";
101 reg = <0x0 0x4c00000 0x1 0xfb400000>;
102 };
103 };
104 };
105 };
106};
107
108&bch {
109 status = "okay";
110};
111
112&mmc0 {
113 bus-width = <4>;
114 max-frequency = <50000000>;
115 status = "okay";
116};
117
118&mmc1 {
119 bus-width = <4>;
120 max-frequency = <50000000>;
121 status = "okay";
122};
diff --git a/arch/mips/dts/comtrend,ar-5315u.dts b/arch/mips/dts/comtrend,ar-5315u.dts
index 45570189d0..eb60aaa8d5 100644
--- a/arch/mips/dts/comtrend,ar-5315u.dts
+++ b/arch/mips/dts/comtrend,ar-5315u.dts
@@ -24,6 +24,38 @@
24 status = "okay"; 24 status = "okay";
25}; 25};
26 26
27&enet {
28 status = "okay";
29
30 port@0 {
31 compatible = "brcm,enetsw-port";
32 reg = <0>;
33 label = "fe4";
34 brcm,phy-id = <1>;
35 };
36
37 port@1 {
38 compatible = "brcm,enetsw-port";
39 reg = <1>;
40 label = "fe3";
41 brcm,phy-id = <2>;
42 };
43
44 port@2 {
45 compatible = "brcm,enetsw-port";
46 reg = <2>;
47 label = "fe2";
48 brcm,phy-id = <3>;
49 };
50
51 port@3 {
52 compatible = "brcm,enetsw-port";
53 reg = <3>;
54 label = "fe1";
55 brcm,phy-id = <4>;
56 };
57};
58
27&leds { 59&leds {
28 status = "okay"; 60 status = "okay";
29 61
diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts
index e993b5cd89..03e3851ab1 100644
--- a/arch/mips/dts/comtrend,ar-5387un.dts
+++ b/arch/mips/dts/comtrend,ar-5387un.dts
@@ -24,6 +24,38 @@
24 status = "okay"; 24 status = "okay";
25}; 25};
26 26
27&enet {
28 status = "okay";
29
30 port@0 {
31 compatible = "brcm,enetsw-port";
32 reg = <0>;
33 label = "fe1";
34 brcm,phy-id = <1>;
35 };
36
37 port@1 {
38 compatible = "brcm,enetsw-port";
39 reg = <1>;
40 label = "fe2";
41 brcm,phy-id = <2>;
42 };
43
44 port@2 {
45 compatible = "brcm,enetsw-port";
46 reg = <2>;
47 label = "fe3";
48 brcm,phy-id = <3>;
49 };
50
51 port@3 {
52 compatible = "brcm,enetsw-port";
53 reg = <3>;
54 label = "fe4";
55 brcm,phy-id = <4>;
56 };
57};
58
27&leds { 59&leds {
28 status = "okay"; 60 status = "okay";
29 61
diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
index 25747ca95d..f6b8a94e25 100644
--- a/arch/mips/dts/comtrend,ct-5361.dts
+++ b/arch/mips/dts/comtrend,ct-5361.dts
@@ -34,6 +34,18 @@
34 }; 34 };
35}; 35};
36 36
37&enet1 {
38 status = "okay";
39 phy = <&enet1phy>;
40 phy-mode = "mii";
41
42 enet1phy: fixed-link {
43 reg = <1>;
44 speed = <100>;
45 full-duplex;
46 };
47};
48
37&gpio0 { 49&gpio0 {
38 status = "okay"; 50 status = "okay";
39}; 51};
diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts
index 8c6a4a1eac..512cb52de3 100644
--- a/arch/mips/dts/comtrend,vr-3032u.dts
+++ b/arch/mips/dts/comtrend,vr-3032u.dts
@@ -24,6 +24,38 @@
24 status = "okay"; 24 status = "okay";
25}; 25};
26 26
27&enet {
28 status = "okay";
29
30 port@0 {
31 compatible = "brcm,enetsw-port";
32 reg = <0>;
33 label = "fe2";
34 brcm,phy-id = <1>;
35 };
36
37 port@1 {
38 compatible = "brcm,enetsw-port";
39 reg = <1>;
40 label = "fe3";
41 brcm,phy-id = <2>;
42 };
43
44 port@2 {
45 compatible = "brcm,enetsw-port";
46 reg = <2>;
47 label = "fe4";
48 brcm,phy-id = <3>;
49 };
50
51 port@3 {
52 compatible = "brcm,enetsw-port";
53 reg = <3>;
54 label = "fe1";
55 brcm,phy-id = <4>;
56 };
57};
58
27&leds { 59&leds {
28 status = "okay"; 60 status = "okay";
29 brcm,serial-leds; 61 brcm,serial-leds;
diff --git a/arch/mips/dts/comtrend,wap-5813n.dts b/arch/mips/dts/comtrend,wap-5813n.dts
index bd41dab9f8..7e835b28d2 100644
--- a/arch/mips/dts/comtrend,wap-5813n.dts
+++ b/arch/mips/dts/comtrend,wap-5813n.dts
@@ -54,6 +54,20 @@
54 status = "okay"; 54 status = "okay";
55}; 55};
56 56
57&enet {
58 status = "okay";
59
60 port@4 {
61 compatible = "brcm,enetsw-port";
62 reg = <4>;
63 label = "rgmii";
64 brcm,phy-id = <0xff>;
65 speed = <1000>;
66 full-duplex;
67 bypass-link;
68 };
69};
70
57&gpio0 { 71&gpio0 {
58 status = "okay"; 72 status = "okay";
59}; 73};
diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts
index 60455c2ff8..6a7fc1df4b 100644
--- a/arch/mips/dts/huawei,hg556a.dts
+++ b/arch/mips/dts/huawei,hg556a.dts
@@ -93,6 +93,18 @@
93 status = "okay"; 93 status = "okay";
94}; 94};
95 95
96&enet1 {
97 status = "okay";
98 phy = <&enet1phy>;
99 phy-mode = "mii";
100
101 enet1phy: fixed-link {
102 reg = <1>;
103 speed = <100>;
104 full-duplex;
105 };
106};
107
96&gpio0 { 108&gpio0 {
97 status = "okay"; 109 status = "okay";
98}; 110};
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index 0000000000..f62a7a95f8
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,164 @@
1// SPDX-License-Identifier: GPL-2.0+
2
3#include <dt-bindings/clock/jz4780-cgu.h>
4
5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "ingenic,jz4780";
9
10 cpuintc: interrupt-controller {
11 #address-cells = <0>;
12 #interrupt-cells = <1>;
13 interrupt-controller;
14 compatible = "mti,cpu-interrupt-controller";
15 };
16
17 intc: interrupt-controller@10001000 {
18 compatible = "ingenic,jz4780-intc";
19 reg = <0x10001000 0x50>;
20
21 interrupt-controller;
22 #interrupt-cells = <1>;
23
24 interrupt-parent = <&cpuintc>;
25 interrupts = <2>;
26 };
27
28 ext: ext {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 };
32
33 rtc: rtc {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32768>;
37 };
38
39 cgu: jz4780-cgu@10000000 {
40 compatible = "ingenic,jz4780-cgu";
41 reg = <0x10000000 0x100>;
42
43 clocks = <&ext>, <&rtc>;
44 clock-names = "ext", "rtc";
45
46 #clock-cells = <1>;
47 };
48
49 mmc0: mmc@13450000 {
50 compatible = "ingenic,jz4780-mmc";
51 reg = <0x13450000 0x1000>;
52
53 status = "disabled";
54
55 clocks = <&cgu JZ4780_CLK_MSC0>;
56 clock-names = "mmc";
57 };
58
59 mmc1: mmc@13460000 {
60 compatible = "ingenic,jz4780-mmc";
61 reg = <0x13460000 0x1000>;
62
63 clocks = <&cgu JZ4780_CLK_MSC1>;
64 clock-names = "mmc";
65
66 status = "disabled";
67 };
68
69 uart0: serial@10030000 {
70 compatible = "ingenic,jz4780-uart";
71 reg = <0x10030000 0x100>;
72 reg-shift = <2>;
73
74 interrupt-parent = <&intc>;
75 interrupts = <51>;
76
77 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
78 clock-names = "baud", "module";
79
80 status = "disabled";
81 };
82
83 uart1: serial@10031000 {
84 compatible = "ingenic,jz4780-uart";
85 reg = <0x10031000 0x100>;
86 reg-shift = <2>;
87
88 interrupt-parent = <&intc>;
89 interrupts = <50>;
90
91 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
92 clock-names = "baud", "module";
93
94 status = "disabled";
95 };
96
97 uart2: serial@10032000 {
98 compatible = "ingenic,jz4780-uart";
99 reg = <0x10032000 0x100>;
100 reg-shift = <2>;
101
102 interrupt-parent = <&intc>;
103 interrupts = <49>;
104
105 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
106 clock-names = "baud", "module";
107
108 status = "disabled";
109 };
110
111 uart3: serial@10033000 {
112 compatible = "ingenic,jz4780-uart";
113 reg = <0x10033000 0x100>;
114 reg-shift = <2>;
115
116 interrupt-parent = <&intc>;
117 interrupts = <48>;
118
119 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
120 clock-names = "baud", "module";
121
122 status = "disabled";
123 };
124
125 uart4: serial@10034000 {
126 compatible = "ingenic,jz4780-uart";
127 reg = <0x10034000 0x100>;
128 reg-shift = <2>;
129
130 interrupt-parent = <&intc>;
131 interrupts = <34>;
132
133 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
134 clock-names = "baud", "module";
135
136 status = "disabled";
137 };
138
139 nemc: nemc@13410000 {
140 compatible = "ingenic,jz4780-nemc";
141 reg = <0x13410000 0x10000>;
142 #address-cells = <2>;
143 #size-cells = <1>;
144 ranges = <1 0 0x1b000000 0x1000000
145 2 0 0x1a000000 0x1000000
146 3 0 0x19000000 0x1000000
147 4 0 0x18000000 0x1000000
148 5 0 0x17000000 0x1000000
149 6 0 0x16000000 0x1000000>;
150
151 clocks = <&cgu JZ4780_CLK_NEMC>;
152
153 status = "disabled";
154 };
155
156 bch: bch@134d0000 {
157 compatible = "ingenic,jz4780-bch";
158 reg = <0x134d0000 0x10000>;
159
160 clocks = <&cgu JZ4780_CLK_BCH>;
161
162 status = "disabled";
163 };
164};
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644
index 0000000000..74f9274c21
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,36 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,luton.dtsi"
8
9/ {
10 model = "Luton10 PCB091 Reference Board";
11 compatible = "mscc,luton-pcb091", "mscc,luton";
12
13 aliases {
14 serial0 = &uart0;
15 spi0 = &spi0;
16 };
17
18 chosen {
19 stdout-path = "serial0:115200n8";
20 };
21};
22
23&uart0 {
24 status = "okay";
25};
26
27&spi0 {
28 status = "okay";
29 spi-flash@0 {
30 compatible = "spi-flash";
31 spi-max-frequency = <18000000>; /* input clock */
32 reg = <0>; /* CS0 */
33 spi-cs-high;
34 };
35};
36
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644
index 0000000000..6a4ad2a5be
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 compatible = "mscc,luton";
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 compatible = "mips,mips24KEc";
19 device_type = "cpu";
20 reg = <0>;
21 };
22 };
23
24 aliases {
25 serial0 = &uart0;
26 };
27
28 ahb_clk: ahb-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <208333333>;
32 };
33
34 ahb {
35 compatible = "simple-bus";
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges = <0 0x60000000 0x10200000>;
39
40 uart0: serial@10100000 {
41 pinctrl-0 = <&uart_pins>;
42 pinctrl-names = "default";
43
44 compatible = "ns16550a";
45 reg = <0x10100000 0x20>;
46 clocks = <&ahb_clk>;
47 reg-io-width = <4>;
48 reg-shift = <2>;
49
50 status = "disabled";
51 };
52
53 gpio: pinctrl@70068 {
54 compatible = "mscc,luton-pinctrl";
55 reg = <0x70068 0x68>;
56 gpio-controller;
57 #gpio-cells = <2>;
58 gpio-ranges = <&gpio 0 0 32>;
59
60 uart_pins: uart-pins {
61 pins = "GPIO_30", "GPIO_31";
62 function = "uart";
63 };
64
65 };
66
67 gpio_spi_bitbang: gpio@10000064 {
68 compatible = "mscc,spi-bitbang-gpio";
69 reg = <0x10000064 0x4>;
70 gpio-controller;
71 #gpio-cells = <2>;
72
73 };
74
75 spi0: spi-bitbang {
76 compatible = "spi-gpio";
77 status = "okay";
78 gpio-sck = <&gpio_spi_bitbang 6 0>;
79 gpio-miso = <&gpio_spi_bitbang 0 0>;
80 gpio-mosi = <&gpio_spi_bitbang 5 0>;
81 cs-gpios = <&gpio_spi_bitbang 1 0>;
82 num-chipselects = <1>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85 };
86 };
87};
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
new file mode 100644
index 0000000000..87b4736285
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -0,0 +1,152 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "mscc,ocelot";
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu@0 {
16 compatible = "mips,mips24KEc";
17 device_type = "cpu";
18 clocks = <&cpu_clk>;
19 reg = <0>;
20 };
21 };
22
23 aliases {
24 serial0 = &uart0;
25 };
26
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
32 };
33
34 cpu_clk: cpu-clock {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <500000000>;
38 };
39
40 ahb_clk: ahb-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <250000000>;
44 };
45
46 ahb {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges = <0 0x70000000 0x2000000>;
51
52 interrupt-parent = <&intc>;
53
54 cpu_ctrl: syscon@0 {
55 compatible = "mscc,ocelot-cpu-syscon", "syscon";
56 reg = <0x0 0x2c>;
57 };
58
59 intc: interrupt-controller@70 {
60 compatible = "mscc,ocelot-icpu-intr";
61 reg = <0x70 0x70>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 interrupt-parent = <&cpuintc>;
65 interrupts = <2>;
66 };
67
68 uart0: serial@100000 {
69 pinctrl-0 = <&uart_pins>;
70 pinctrl-names = "default";
71 compatible = "ns16550a";
72 reg = <0x100000 0x20>;
73 interrupts = <6>;
74 clocks = <&ahb_clk>;
75 reg-io-width = <4>;
76 reg-shift = <2>;
77
78 status = "disabled";
79 };
80
81 uart2: serial@100800 {
82 pinctrl-0 = <&uart2_pins>;
83 pinctrl-names = "default";
84 compatible = "ns16550a";
85 reg = <0x100800 0x20>;
86 interrupts = <7>;
87 clocks = <&ahb_clk>;
88 reg-io-width = <4>;
89 reg-shift = <2>;
90
91 status = "disabled";
92 };
93
94 spi0: spi-master@101000 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 compatible = "snps,dw-apb-ssi";
98 reg = <0x101000 0x40>;
99 num-chipselect = <4>;
100 bus-num = <0>;
101 reg-io-width = <4>;
102 reg-shift = <2>;
103 spi-max-frequency = <18000000>; /* input clock */
104 clocks = <&ahb_clk>;
105
106 status = "disabled";
107 };
108
109 reset@1070008 {
110 compatible = "mscc,ocelot-chip-reset";
111 reg = <0x1070008 0x4>;
112 };
113
114 gpio: pinctrl@1070034 {
115 compatible = "mscc,ocelot-pinctrl";
116 reg = <0x1070034 0x68>;
117 gpio-controller;
118 #gpio-cells = <2>;
119 gpio-ranges = <&gpio 0 0 22>;
120
121 uart_pins: uart-pins {
122 pins = "GPIO_6", "GPIO_7";
123 function = "uart";
124 };
125
126 uart2_pins: uart2-pins {
127 pins = "GPIO_12", "GPIO_13";
128 function = "uart2";
129 };
130
131 spi_cs1_pin: spi-cs1-pin {
132 pins = "GPIO_8";
133 function = "si";
134 };
135
136 spi_cs2_pin: spi-cs2-pin {
137 pins = "GPIO_9";
138 function = "si";
139 };
140
141 spi_cs3_pin: spi-cs3-pin {
142 pins = "GPIO_16";
143 function = "si";
144 };
145
146 spi_cs4_pin: spi-cs4-pin {
147 pins = "GPIO_17";
148 function = "si";
149 };
150 };
151 };
152};
diff --git a/arch/mips/dts/mscc,ocelot_pcb.dtsi b/arch/mips/dts/mscc,ocelot_pcb.dtsi
new file mode 100644
index 0000000000..90725d3b94
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot_pcb.dtsi
@@ -0,0 +1,42 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,ocelot.dtsi"
8
9/ {
10 compatible = "mscc,ocelot";
11
12 aliases {
13 spi0 = &spi0;
14 serial0 = &uart0;
15 };
16
17 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20};
21
22&uart0 {
23 status = "okay";
24};
25
26&spi0 {
27 status = "okay";
28 pinctrl-0 = <&spi_cs1_pin>;
29 pinctrl-names = "default";
30
31 spi-flash@0 {
32 compatible = "spi-flash";
33 spi-max-frequency = <18000000>; /* input clock */
34 reg = <0>; /* CS0 */
35 };
36
37 spi-nand@1 {
38 compatible = "spi-nand";
39 spi-max-frequency = <18000000>; /* input clock */
40 reg = <1>; /* CS1 */
41 };
42};
diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts
index 322d1567ff..2b72491f0b 100644
--- a/arch/mips/dts/netgear,dgnd3700v2.dts
+++ b/arch/mips/dts/netgear,dgnd3700v2.dts
@@ -43,6 +43,20 @@
43 status = "okay"; 43 status = "okay";
44}; 44};
45 45
46&enet {
47 status = "okay";
48
49 port@4 {
50 compatible = "brcm,enetsw-port";
51 reg = <4>;
52 label = "rgmii";
53 brcm,phy-id = <0xff>;
54 speed = <1000>;
55 full-duplex;
56 bypass-link;
57 };
58};
59
46&gpio0 { 60&gpio0 {
47 status = "okay"; 61 status = "okay";
48}; 62};
diff --git a/arch/mips/dts/nexys4ddr.dts b/arch/mips/dts/nexys4ddr.dts
index e254ab1eaa..6de8584ea7 100644
--- a/arch/mips/dts/nexys4ddr.dts
+++ b/arch/mips/dts/nexys4ddr.dts
@@ -40,7 +40,6 @@
40 #address-cells = <1>; 40 #address-cells = <1>;
41 #size-cells = <0>; 41 #size-cells = <0>;
42 phy0: phy@1 { 42 phy0: phy@1 {
43 compatible = <0x0007c0f0 0xfffffff0>;
44 device_type = "ethernet-phy"; 43 device_type = "ethernet-phy";
45 reg = <1>; 44 reg = <1>;
46 } ; 45 } ;
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
new file mode 100644
index 0000000000..47d305a614
--- /dev/null
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -0,0 +1,12 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,ocelot_pcb.dtsi"
8
9/ {
10 model = "Ocelot PCB120 Reference Board";
11 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
12};
diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts
new file mode 100644
index 0000000000..17d8d326ce
--- /dev/null
+++ b/arch/mips/dts/ocelot_pcb123.dts
@@ -0,0 +1,12 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,ocelot_pcb.dtsi"
8
9/ {
10 model = "Ocelot PCB123 Reference Board";
11 compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
12};
diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi
index 599e809c47..ba29ea287e 100644
--- a/arch/mips/dts/qca953x.dtsi
+++ b/arch/mips/dts/qca953x.dtsi
@@ -3,7 +3,6 @@
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 */ 4 */
5 5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include "skeleton.dtsi" 6#include "skeleton.dtsi"
8 7
9/ { 8/ {
@@ -63,7 +62,6 @@
63 reg = <0x18020000 0x20>; 62 reg = <0x18020000 0x20>;
64 reg-shift = <2>; 63 reg-shift = <2>;
65 clock-frequency = <25000000>; 64 clock-frequency = <25000000>;
66 interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
67 65
68 status = "disabled"; 66 status = "disabled";
69 }; 67 };
@@ -72,7 +70,6 @@
72 spi0: spi@1f000000 { 70 spi0: spi@1f000000 {
73 compatible = "qca,ar7100-spi"; 71 compatible = "qca,ar7100-spi";
74 reg = <0x1f000000 0x10>; 72 reg = <0x1f000000 0x10>;
75 interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
76 73
77 status = "disabled"; 74 status = "disabled";
78 75
diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts
index 5300f8b6df..ec6846dd9f 100644
--- a/arch/mips/dts/sagem,f@st1704.dts
+++ b/arch/mips/dts/sagem,f@st1704.dts
@@ -39,6 +39,18 @@
39 }; 39 };
40}; 40};
41 41
42&enet {
43 status = "okay";
44 phy = <&enetphy>;
45 phy-mode = "mii";
46
47 enetphy: fixed-link {
48 reg = <1>;
49 speed = <100>;
50 full-duplex;
51 };
52};
53
42&gpio { 54&gpio {
43 status = "okay"; 55 status = "okay";
44}; 56};
diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts
index bdc6f8ae45..dfbc4148dc 100644
--- a/arch/mips/dts/sfr,nb4-ser.dts
+++ b/arch/mips/dts/sfr,nb4-ser.dts
@@ -53,6 +53,30 @@
53 status = "okay"; 53 status = "okay";
54}; 54};
55 55
56&enet0 {
57 status = "okay";
58 phy = <&enet0phy>;
59 phy-mode = "internal";
60
61 enet0phy: fixed-link {
62 reg = <1>;
63 speed = <100>;
64 full-duplex;
65 };
66};
67
68&enet1 {
69 status = "okay";
70 phy = <&enet1phy>;
71 phy-mode = "mii";
72
73 enet1phy: fixed-link {
74 reg = <1>;
75 speed = <100>;
76 full-duplex;
77 };
78};
79
56&gpio0 { 80&gpio0 {
57 status = "okay"; 81 status = "okay";
58}; 82};
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 3161875441..98b67ccc8e 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr)
19#endif 19#endif
20} 20}
21 21
22#define MIPS32_WHICH_ICACHE 0x0
23#define MIPS32_FETCH_AND_LOCK 0x7
24
25#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
26
27/* Prefetch and lock instructions into cache */
28static inline void icache_lock(void *func, size_t len)
29{
30 int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
31
32 for (i = 0; i < lines; i++) {
33 asm volatile (" cache %0, %1(%2)"
34 : /* No Output */
35 : "I" ICACHE_LOAD_LOCK,
36 "n" (i * ARCH_DMA_MINALIGN),
37 "r" (func)
38 : /* No Clobbers */);
39 }
40}
22#endif /* !__ASSEMBLY__ */ 41#endif /* !__ASSEMBLY__ */
23 42
24/* 43/*
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 48fa1f1f7f..f80311e64e 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1013,9 +1013,7 @@ do { \
1013#define __read_64bit_c0_split(source, sel) \ 1013#define __read_64bit_c0_split(source, sel) \
1014({ \ 1014({ \
1015 unsigned long long __val; \ 1015 unsigned long long __val; \
1016 unsigned long __flags; \
1017 \ 1016 \
1018 local_irq_save(__flags); \
1019 if (sel == 0) \ 1017 if (sel == 0) \
1020 __asm__ __volatile__( \ 1018 __asm__ __volatile__( \
1021 ".set\tmips64\n\t" \ 1019 ".set\tmips64\n\t" \
@@ -1034,16 +1032,12 @@ do { \
1034 "dsra\t%L0, %L0, 32\n\t" \ 1032 "dsra\t%L0, %L0, 32\n\t" \
1035 ".set\tmips0" \ 1033 ".set\tmips0" \
1036 : "=r" (__val)); \ 1034 : "=r" (__val)); \
1037 local_irq_restore(__flags); \
1038 \ 1035 \
1039 __val; \ 1036 __val; \
1040}) 1037})
1041 1038
1042#define __write_64bit_c0_split(source, sel, val) \ 1039#define __write_64bit_c0_split(source, sel, val) \
1043do { \ 1040do { \
1044 unsigned long __flags; \
1045 \
1046 local_irq_save(__flags); \
1047 if (sel == 0) \ 1041 if (sel == 0) \
1048 __asm__ __volatile__( \ 1042 __asm__ __volatile__( \
1049 ".set\tmips64\n\t" \ 1043 ".set\tmips64\n\t" \
@@ -1064,7 +1058,6 @@ do { \
1064 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 1058 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1065 ".set\tmips0" \ 1059 ".set\tmips0" \
1066 : : "r" (val)); \ 1060 : : "r" (val)); \
1067 local_irq_restore(__flags); \
1068} while (0) 1061} while (0)
1069 1062
1070#define __readx_32bit_c0_register(source) \ 1063#define __readx_32bit_c0_register(source) \
@@ -2005,6 +1998,17 @@ static inline unsigned int get_ebase_cpunum(void)
2005 return read_c0_ebase() & 0x3ff; 1998 return read_c0_ebase() & 0x3ff;
2006} 1999}
2007 2000
2001static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
2002 u32 low1)
2003{
2004 write_c0_entrylo0(low0);
2005 write_c0_pagemask(pagemask);
2006 write_c0_entrylo1(low1);
2007 write_c0_entryhi(hi);
2008 write_c0_index(index);
2009 tlb_write_indexed();
2010}
2011
2008#endif /* !__ASSEMBLY__ */ 2012#endif /* !__ASSEMBLY__ */
2009 2013
2010#endif /* _ASM_MIPSREGS_H */ 2014#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index 0000000000..0a847edec8
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,33 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2012
4 * Texas Instruments, <www.ti.com>
5 */
6#ifndef _ASM_SPL_H_
7#define _ASM_SPL_H_
8
9enum {
10 BOOT_DEVICE_RAM,
11 BOOT_DEVICE_MMC1,
12 BOOT_DEVICE_MMC2,
13 BOOT_DEVICE_MMC2_2,
14 BOOT_DEVICE_NAND,
15 BOOT_DEVICE_ONENAND,
16 BOOT_DEVICE_NOR,
17 BOOT_DEVICE_UART,
18 BOOT_DEVICE_SPI,
19 BOOT_DEVICE_USB,
20 BOOT_DEVICE_SATA,
21 BOOT_DEVICE_I2C,
22 BOOT_DEVICE_BOARD,
23 BOOT_DEVICE_DFU,
24 BOOT_DEVICE_XIP,
25 BOOT_DEVICE_BOOTROM,
26 BOOT_DEVICE_NONE
27};
28
29#ifndef CONFIG_DM
30extern gd_t gdata;
31#endif
32
33#endif
diff --git a/arch/mips/mach-jz47xx/Kconfig b/arch/mips/mach-jz47xx/Kconfig
new file mode 100644
index 0000000000..dcaac01628
--- /dev/null
+++ b/arch/mips/mach-jz47xx/Kconfig
@@ -0,0 +1,26 @@
1menu "Ingenic JZ47xx platforms"
2 depends on ARCH_JZ47XX
3
4config SYS_SOC
5 default "jz47xx"
6
7config SOC_JZ4780
8 bool
9 select SUPPORTS_LITTLE_ENDIAN
10 select SUPPORTS_CPU_MIPS32_R1
11 select SUPPORTS_CPU_MIPS32_R2
12 help
13 Support for Ingenic JZ4780 family SoCs.
14
15choice
16 prompt "Board select"
17
18config TARGET_JZ4780_CI20
19 bool "Creator CI20 Reference Board"
20 select SOC_JZ4780
21
22endchoice
23
24source "board/imgtec/ci20/Kconfig"
25
26endmenu
diff --git a/arch/mips/mach-jz47xx/Makefile b/arch/mips/mach-jz47xx/Makefile
new file mode 100644
index 0000000000..dbb8229f78
--- /dev/null
+++ b/arch/mips/mach-jz47xx/Makefile
@@ -0,0 +1,5 @@
1# SPDX-License-Identifier: GPL-2.0+
2
3extra-$(CONFIG_SPL_BUILD) := start.o
4
5obj-$(CONFIG_SOC_JZ4780) += jz4780/
diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780.h b/arch/mips/mach-jz47xx/include/mach/jz4780.h
new file mode 100644
index 0000000000..4422e503ed
--- /dev/null
+++ b/arch/mips/mach-jz47xx/include/mach/jz4780.h
@@ -0,0 +1,103 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * JZ4780 definitions
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#ifndef __JZ4780_H__
10#define __JZ4780_H__
11
12/* AHB0 BUS Devices */
13#define DDRC_BASE 0xb3010000
14
15/* AHB2 BUS Devices */
16#define NEMC_BASE 0xb3410000
17#define BCH_BASE 0xb34d0000
18
19/* APB BUS Devices */
20#define CPM_BASE 0xb0000000
21#define TCU_BASE 0xb0002000
22#define WDT_BASE 0xb0002000
23#define GPIO_BASE 0xb0010000
24#define UART0_BASE 0xb0030000
25#define UART1_BASE 0xb0031000
26#define UART2_BASE 0xb0032000
27#define UART3_BASE 0xb0033000
28#define MSC0_BASE 0xb3450000
29#define MSC1_BASE 0xb3460000
30#define MSC2_BASE 0xb3470000
31
32/*
33 * GPIO
34 */
35/* n = 0,1,2,3,4,5 */
36#define GPIO_PXPIN(n) (0x00 + (n) * 0x100)
37#define GPIO_PXINT(n) (0x10 + (n) * 0x100)
38#define GPIO_PXINTS(n) (0x14 + (n) * 0x100)
39#define GPIO_PXINTC(n) (0x18 + (n) * 0x100)
40#define GPIO_PXMASK(n) (0x20 + (n) * 0x100)
41#define GPIO_PXMASKS(n) (0x24 + (n) * 0x100)
42#define GPIO_PXMASKC(n) (0x28 + (n) * 0x100)
43#define GPIO_PXPAT1(n) (0x30 + (n) * 0x100)
44#define GPIO_PXPAT1S(n) (0x34 + (n) * 0x100)
45#define GPIO_PXPAT1C(n) (0x38 + (n) * 0x100)
46#define GPIO_PXPAT0(n) (0x40 + (n) * 0x100)
47#define GPIO_PXPAT0S(n) (0x44 + (n) * 0x100)
48#define GPIO_PXPAT0C(n) (0x48 + (n) * 0x100)
49#define GPIO_PXFLG(n) (0x50 + (n) * 0x100)
50#define GPIO_PXFLGC(n) (0x54 + (n) * 0x100)
51#define GPIO_PXOEN(n) (0x60 + (n) * 0x100)
52#define GPIO_PXOENS(n) (0x64 + (n) * 0x100)
53#define GPIO_PXOENC(n) (0x68 + (n) * 0x100)
54#define GPIO_PXPEN(n) (0x70 + (n) * 0x100)
55#define GPIO_PXPENS(n) (0x74 + (n) * 0x100)
56#define GPIO_PXPENC(n) (0x78 + (n) * 0x100)
57#define GPIO_PXDS(n) (0x80 + (n) * 0x100)
58#define GPIO_PXDSS(n) (0x84 + (n) * 0x100)
59#define GPIO_PXDSC(n) (0x88 + (n) * 0x100)
60
61/* PLL setup */
62#define JZ4780_SYS_EXTAL 48000000
63#define JZ4780_SYS_MEM_SPEED (CONFIG_SYS_MHZ * 1000000)
64#define JZ4780_SYS_MEM_DIV 3
65#define JZ4780_SYS_AUDIO_SPEED (768 * 1000000)
66
67#define JZ4780_APLL_M 1
68#define JZ4780_APLL_N 1
69#define JZ4780_APLL_OD 1
70
71#define JZ4780_MPLL_M (JZ4780_SYS_MEM_SPEED / JZ4780_SYS_EXTAL * 2)
72#define JZ4780_MPLL_N 2
73#define JZ4780_MPLL_OD 1
74
75#define JZ4780_EPLL_M (JZ4780_SYS_AUDIO_SPEED * 2 / JZ4780_SYS_EXTAL)
76#define JZ4780_EPLL_N 1
77#define JZ4780_EPLL_OD 2
78
79#define JZ4780_VPLL_M ((888 * 1000000) * 2 / JZ4780_SYS_EXTAL)
80#define JZ4780_VPLL_N 1
81#define JZ4780_VPLL_OD 2
82
83#ifndef __ASSEMBLY__
84
85u32 sdram_size(int bank);
86
87const u32 jz4780_clk_get_efuse_clk(void);
88void jz4780_clk_ungate_ethernet(void);
89void jz4780_clk_ungate_mmc(void);
90void jz4780_clk_ungate_uart(const unsigned int uart);
91
92void jz4780_efuse_read(size_t addr, size_t count, u8 *buf);
93void jz4780_efuse_init(u32 ahb2_rate);
94
95void jz4780_tcu_wdt_start(void);
96
97#ifdef CONFIG_SPL_BUILD
98int jz_mmc_init(void __iomem *base);
99#endif
100
101#endif /* __ASSEMBLY__ */
102
103#endif /* __JZ4780_H__ */
diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h b/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
new file mode 100644
index 0000000000..92d431bd04
--- /dev/null
+++ b/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
@@ -0,0 +1,456 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * JZ4780 DDR initialization - parameters definitions
4 *
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Matt Redfearn <matt.redfearn.com>
7 */
8
9#ifndef __JZ4780_DRAM_H__
10#define __JZ4780_DRAM_H__
11
12/*
13 * DDR
14 */
15#define DDRC_ST 0x0
16#define DDRC_CFG 0x4
17#define DDRC_CTRL 0x8
18#define DDRC_LMR 0xc
19#define DDRC_REFCNT 0x18
20#define DDRC_DQS 0x1c
21#define DDRC_DQS_ADJ 0x20
22#define DDRC_MMAP0 0x24
23#define DDRC_MMAP1 0x28
24#define DDRC_MDELAY 0x2c
25#define DDRC_CKEL 0x30
26#define DDRC_PMEMCTRL0 0x54
27#define DDRC_PMEMCTRL1 0x50
28#define DDRC_PMEMCTRL2 0x58
29#define DDRC_PMEMCTRL3 0x5c
30
31#define DDRC_TIMING(n) (0x60 + 4 * (n))
32#define DDRC_REMMAP(n) (0x9c + 4 * (n))
33
34/*
35 * DDR PHY
36 */
37#define DDR_MEM_PHY_BASE 0x20000000
38#define DDR_PHY_OFFSET 0x1000
39
40#define DDRP_PIR 0x4
41#define DDRP_PGCR 0x8
42#define DDRP_PGSR 0xc
43
44#define DDRP_PTR0 0x18
45#define DDRP_PTR1 0x1c
46#define DDRP_PTR2 0x20
47
48#define DDRP_ACIOCR 0x24
49#define DDRP_DXCCR 0x28
50#define DDRP_DSGCR 0x2c
51#define DDRP_DCR 0x30
52
53#define DDRP_DTPR0 0x34
54#define DDRP_DTPR1 0x38
55#define DDRP_DTPR2 0x3c
56#define DDRP_MR0 0x40
57#define DDRP_MR1 0x44
58#define DDRP_MR2 0x48
59#define DDRP_MR3 0x4c
60
61#define DDRP_ODTCR 0x50
62#define DDRP_DTAR 0x54
63#define DDRP_DTDR0 0x58
64#define DDRP_DTDR1 0x5c
65
66#define DDRP_DCUAR 0xc0
67#define DDRP_DCUDR 0xc4
68#define DDRP_DCURR 0xc8
69#define DDRP_DCULR 0xcc
70#define DDRP_DCUGCR 0xd0
71#define DDRP_DCUTPR 0xd4
72#define DDRP_DCUSR0 0xd8
73#define DDRP_DCUSR1 0xdc
74
75#define DDRP_ZQXCR0(n) (0x180 + ((n) * 0x10))
76#define DDRP_ZQXCR1(n) (0x184 + ((n) * 0x10))
77#define DDRP_ZQXSR0(n) (0x188 + ((n) * 0x10))
78#define DDRP_ZQXSR1(n) (0x18c + ((n) * 0x10))
79
80#define DDRP_DXGCR(n) (0x1c0 + ((n) * 0x40))
81#define DDRP_DXGSR0(n) (0x1c4 + ((n) * 0x40))
82#define DDRP_DXGSR1(n) (0x1c8 + ((n) * 0x40))
83#define DDRP_DXDQSTR(n) (0x1d4 + ((n) * 0x40))
84
85/* DDRC Status Register */
86#define DDRC_ST_ENDIAN BIT(7)
87#define DDRC_ST_DPDN BIT(5)
88#define DDRC_ST_PDN BIT(4)
89#define DDRC_ST_AREF BIT(3)
90#define DDRC_ST_SREF BIT(2)
91#define DDRC_ST_CKE1 BIT(1)
92#define DDRC_ST_CKE0 BIT(0)
93
94/* DDRC Configure Register */
95#define DDRC_CFG_ROW1_BIT 27
96#define DDRC_CFG_ROW1_MASK (0x7 << DDRC_CFG_ROW1_BIT)
97#define DDRC_CFG_COL1_BIT 24
98#define DDRC_CFG_COL1_MASK (0x7 << DDRC_CFG_COL1_BIT)
99#define DDRC_CFG_BA1 BIT(23)
100#define DDRC_CFG_IMBA BIT(22)
101#define DDRC_CFG_BL_8 BIT(21)
102
103#define DDRC_CFG_TYPE_BIT 17
104#define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT)
105#define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT)
106#define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT)
107#define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT)
108#define DDRC_CFG_TYPE_LPDDR2 (5 << DDRC_CFG_TYPE_BIT)
109#define DDRC_CFG_TYPE_DDR3 (6 << DDRC_CFG_TYPE_BIT)
110
111#define DDRC_CFG_ODT_EN BIT(16)
112
113#define DDRC_CFG_MPRT BIT(15)
114
115#define DDRC_CFG_ROW_BIT 11
116#define DDRC_CFG_ROW_MASK (0x7 << DDRC_CFG_ROW_BIT)
117#define DDRC_CFG_ROW_12 (0 << DDRC_CFG_ROW_BIT)
118#define DDRC_CFG_ROW_13 (1 << DDRC_CFG_ROW_BIT)
119#define DDRC_CFG_ROW_14 (2 << DDRC_CFG_ROW_BIT)
120
121#define DDRC_CFG_COL_BIT 8
122#define DDRC_CFG_COL_MASK (0x7 << DDRC_CFG_COL_BIT)
123#define DDRC_CFG_COL_8 (0 << DDRC_CFG_COL_BIT)
124#define DDRC_CFG_COL_9 (1 << DDRC_CFG_COL_BIT)
125#define DDRC_CFG_COL_10 (2 << DDRC_CFG_COL_BIT)
126#define DDRC_CFG_COL_11 (3 << DDRC_CFG_COL_BIT)
127
128#define DDRC_CFG_CS1EN BIT(7)
129#define DDRC_CFG_CS0EN BIT(6)
130#define DDRC_CFG_CL_BIT 2
131#define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT)
132#define DDRC_CFG_CL_3 (0 << DDRC_CFG_CL_BIT)
133#define DDRC_CFG_CL_4 (1 << DDRC_CFG_CL_BIT)
134#define DDRC_CFG_CL_5 (2 << DDRC_CFG_CL_BIT)
135#define DDRC_CFG_CL_6 (3 << DDRC_CFG_CL_BIT)
136
137#define DDRC_CFG_BA BIT(1)
138#define DDRC_CFG_DW BIT(0)
139
140/* DDRC Control Register */
141#define DDRC_CTRL_DFI_RST BIT(23)
142#define DDRC_CTRL_DLL_RST BIT(22)
143#define DDRC_CTRL_CTL_RST BIT(21)
144#define DDRC_CTRL_CFG_RST BIT(20)
145#define DDRC_CTRL_ACTPD BIT(15)
146#define DDRC_CTRL_PDT_BIT 12
147#define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT)
148#define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT)
149#define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT)
150#define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT)
151#define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT)
152#define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT)
153#define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT)
154
155#define DDRC_CTRL_PRET_BIT 8
156#define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT)
157#define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT)
158#define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT)
159#define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT)
160#define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT)
161#define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT)
162#define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT)
163
164#define DDRC_CTRL_DPD BIT(6)
165#define DDRC_CTRL_SR BIT(5)
166#define DDRC_CTRL_UNALIGN BIT(4)
167#define DDRC_CTRL_ALH BIT(3)
168#define DDRC_CTRL_RDC BIT(2)
169#define DDRC_CTRL_CKE BIT(1)
170#define DDRC_CTRL_RESET BIT(0)
171
172/* DDRC Load-Mode-Register */
173#define DDRC_LMR_DDR_ADDR_BIT 16
174#define DDRC_LMR_DDR_ADDR_MASK (0x3fff << DDRC_LMR_DDR_ADDR_BIT)
175
176#define DDRC_LMR_BA_BIT 8
177#define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT)
178/* For DDR2 */
179#define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT)
180#define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT)
181#define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT)
182#define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT)
183/* For mobile DDR */
184#define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT)
185#define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT)
186#define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT)
187/* For Normal DDR1 */
188#define DDRC_LMR_BA_N_MRS (0 << DDRC_LMR_BA_BIT)
189#define DDRC_LMR_BA_N_EMRS (1 << DDRC_LMR_BA_BIT)
190
191#define DDRC_LMR_CMD_BIT 4
192#define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT)
193#define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT)
194#define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT)
195#define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT)
196
197#define DDRC_LMR_START BIT(0)
198
199/* DDRC Timing Config Register 1 */
200#define DDRC_TIMING1_TRTP_BIT 24
201#define DDRC_TIMING1_TRTP_MASK (0x3f << DDRC_TIMING1_TRTP_BIT)
202#define DDRC_TIMING1_TWTR_BIT 16
203#define DDRC_TIMING1_TWTR_MASK (0x3f << DDRC_TIMING1_TWTR_BIT)
204#define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT)
205#define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT)
206#define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT)
207#define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT)
208#define DDRC_TIMING1_TWR_BIT 8
209#define DDRC_TIMING1_TWR_MASK (0x3f << DDRC_TIMING1_TWR_BIT)
210#define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT)
211#define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT)
212#define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT)
213#define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT)
214#define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT)
215#define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT)
216#define DDRC_TIMING1_TWL_BIT 0
217#define DDRC_TIMING1_TWL_MASK (0x3f << DDRC_TIMING1_TWL_BIT)
218
219/* DDRC Timing Config Register 2 */
220#define DDRC_TIMING2_TCCD_BIT 24
221#define DDRC_TIMING2_TCCD_MASK (0x3f << DDRC_TIMING2_TCCD_BIT)
222#define DDRC_TIMING2_TRAS_BIT 16
223#define DDRC_TIMING2_TRAS_MASK (0x3f << DDRC_TIMING2_TRAS_BIT)
224#define DDRC_TIMING2_TRCD_BIT 8
225#define DDRC_TIMING2_TRCD_MASK (0x3f << DDRC_TIMING2_TRCD_BIT)
226#define DDRC_TIMING2_TRL_BIT 0
227#define DDRC_TIMING2_TRL_MASK (0x3f << DDRC_TIMING2_TRL_BIT)
228
229/* DDRC Timing Config Register 3 */
230#define DDRC_TIMING3_ONUM 27
231#define DDRC_TIMING3_TCKSRE_BIT 24
232#define DDRC_TIMING3_TCKSRE_MASK (0x3f << DDRC_TIMING3_TCKSRE_BIT)
233#define DDRC_TIMING3_TRP_BIT 16
234#define DDRC_TIMING3_TRP_MASK (0x3f << DDRC_TIMING3_TRP_BIT)
235#define DDRC_TIMING3_TRRD_BIT 8
236#define DDRC_TIMING3_TRRD_MASK (0x3f << DDRC_TIMING3_TRRD_BIT)
237#define DDRC_TIMING3_TRRD_DISABLE (0 << DDRC_TIMING3_TRRD_BIT)
238#define DDRC_TIMING3_TRRD_2 (1 << DDRC_TIMING3_TRRD_BIT)
239#define DDRC_TIMING3_TRRD_3 (2 << DDRC_TIMING3_TRRD_BIT)
240#define DDRC_TIMING3_TRRD_4 (3 << DDRC_TIMING3_TRRD_BIT)
241#define DDRC_TIMING3_TRC_BIT 0
242#define DDRC_TIMING3_TRC_MASK (0x3f << DDRC_TIMING3_TRC_BIT)
243
244/* DDRC Timing Config Register 4 */
245#define DDRC_TIMING4_TRFC_BIT 24
246#define DDRC_TIMING4_TRFC_MASK (0x3f << DDRC_TIMING4_TRFC_BIT)
247#define DDRC_TIMING4_TEXTRW_BIT 21
248#define DDRC_TIMING4_TEXTRW_MASK (0x7 << DDRC_TIMING4_TEXTRW_BIT)
249#define DDRC_TIMING4_TRWCOV_BIT 19
250#define DDRC_TIMING4_TRWCOV_MASK (0x3 << DDRC_TIMING4_TRWCOV_BIT)
251#define DDRC_TIMING4_TCKE_BIT 16
252#define DDRC_TIMING4_TCKE_MASK (0x7 << DDRC_TIMING4_TCKE_BIT)
253#define DDRC_TIMING4_TMINSR_BIT 8
254#define DDRC_TIMING4_TMINSR_MASK (0xf << DDRC_TIMING4_TMINSR_BIT)
255#define DDRC_TIMING4_TXP_BIT 4
256#define DDRC_TIMING4_TXP_MASK (0x7 << DDRC_TIMING4_TXP_BIT)
257#define DDRC_TIMING4_TMRD_BIT 0
258#define DDRC_TIMING4_TMRD_MASK (0x3 << DDRC_TIMING4_TMRD_BIT)
259
260/* DDRC Timing Config Register 5 */
261#define DDRC_TIMING5_TCTLUPD_BIT 24
262#define DDRC_TIMING4_TCTLUPD_MASK (0x3f << DDRC_TIMING5_TCTLUDP_BIT)
263#define DDRC_TIMING5_TRTW_BIT 16
264#define DDRC_TIMING5_TRTW_MASK (0x3f << DDRC_TIMING5_TRTW_BIT)
265#define DDRC_TIMING5_TRDLAT_BIT 8
266#define DDRC_TIMING5_TRDLAT_MASK (0x3f << DDRC_TIMING5_TRDLAT_BIT)
267#define DDRC_TIMING5_TWDLAT_BIT 0
268#define DDRC_TIMING5_TWDLAT_MASK (0x3f << DDRC_TIMING5_TWDLAT_BIT)
269
270/* DDRC Timing Config Register 6 */
271#define DDRC_TIMING6_TXSRD_BIT 24
272#define DDRC_TIMING6_TXSRD_MASK (0x3f << DDRC_TIMING6_TXSRD_BIT)
273#define DDRC_TIMING6_TFAW_BIT 16
274#define DDRC_TIMING6_TFAW_MASK (0x3f << DDRC_TIMING6_TFAW_BIT)
275#define DDRC_TIMING6_TCFGW_BIT 8
276#define DDRC_TIMING6_TCFGW_MASK (0x3f << DDRC_TIMING6_TCFGW_BIT)
277#define DDRC_TIMING6_TCFGR_BIT 0
278#define DDRC_TIMING6_TCFGR_MASK (0x3f << DDRC_TIMING6_TCFGR_BIT)
279
280/* DDRC Auto-Refresh Counter */
281#define DDRC_REFCNT_CON_BIT 16
282#define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT)
283#define DDRC_REFCNT_CNT_BIT 8
284#define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT)
285#define DDRC_REFCNT_CLKDIV_BIT 1
286#define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT)
287#define DDRC_REFCNT_REF_EN BIT(0)
288
289/* DDRC DQS Delay Control Register */
290#define DDRC_DQS_ERROR BIT(29)
291#define DDRC_DQS_READY BIT(28)
292#define DDRC_DQS_AUTO BIT(23)
293#define DDRC_DQS_DET BIT(24)
294#define DDRC_DQS_SRDET BIT(25)
295#define DDRC_DQS_CLKD_BIT 16
296#define DDRC_DQS_CLKD_MASK (0x3f << DDRC_DQS_CLKD_BIT)
297#define DDRC_DQS_WDQS_BIT 8
298#define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT)
299#define DDRC_DQS_RDQS_BIT 0
300#define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT)
301
302/* DDRC DQS Delay Adjust Register */
303#define DDRC_DQS_ADJWDQS_BIT 8
304#define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT)
305#define DDRC_DQS_ADJRDQS_BIT 0
306#define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT)
307
308/* DDRC Memory Map Config Register */
309#define DDRC_MMAP_BASE_BIT 8
310#define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT)
311#define DDRC_MMAP_MASK_BIT 0
312#define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT)
313
314#define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT)
315#define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT)
316#define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT)
317#define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT)
318
319#define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT)
320#define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT)
321#define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT)
322
323/* DDRP PHY Initialization Register */
324#define DDRP_PIR_INIT BIT(0)
325#define DDRP_PIR_DLLSRST BIT(1)
326#define DDRP_PIR_DLLLOCK BIT(2)
327#define DDRP_PIR_ZCAL BIT(3)
328#define DDRP_PIR_ITMSRST BIT(4)
329#define DDRP_PIR_DRAMRST BIT(5)
330#define DDRP_PIR_DRAMINT BIT(6)
331#define DDRP_PIR_QSTRN BIT(7)
332#define DDRP_PIR_EYETRN BIT(8)
333#define DDRP_PIR_DLLBYP BIT(17)
334/* DDRP PHY General Configurate Register */
335#define DDRP_PGCR_ITMDMD BIT(0)
336#define DDRP_PGCR_DQSCFG BIT(1)
337#define DDRP_PGCR_DFTCMP BIT(2)
338#define DDRP_PGCR_DFTLMT_BIT 3
339#define DDRP_PGCR_DTOSEL_BIT 5
340#define DDRP_PGCR_CKEN_BIT 9
341#define DDRP_PGCR_CKDV_BIT 12
342#define DDRP_PGCR_CKINV BIT(14)
343#define DDRP_PGCR_RANKEN_BIT 18
344#define DDRP_PGCR_ZCKSEL_32 (2 << 22)
345#define DDRP_PGCR_PDDISDX BIT(24)
346/* DDRP PHY General Status Register */
347#define DDRP_PGSR_IDONE BIT(0)
348#define DDRP_PGSR_DLDONE BIT(1)
349#define DDRP_PGSR_ZCDONE BIT(2)
350#define DDRP_PGSR_DIDONE BIT(3)
351#define DDRP_PGSR_DTDONE BIT(4)
352#define DDRP_PGSR_DTERR BIT(5)
353#define DDRP_PGSR_DTIERR BIT(6)
354#define DDRP_PGSR_DFTEERR BIT(7)
355/* DDRP DRAM Configuration Register */
356#define DDRP_DCR_TYPE_BIT 0
357#define DDRP_DCR_TYPE_MASK (0x7 << DDRP_DCR_TYPE_BIT)
358#define DDRP_DCR_TYPE_MDDR (0 << DDRP_DCR_TYPE_BIT)
359#define DDRP_DCR_TYPE_DDR (1 << DDRP_DCR_TYPE_BIT)
360#define DDRP_DCR_TYPE_DDR2 (2 << DDRP_DCR_TYPE_BIT)
361#define DDRP_DCR_TYPE_DDR3 (3 << DDRP_DCR_TYPE_BIT)
362#define DDRP_DCR_TYPE_LPDDR2 (4 << DDRP_DCR_TYPE_BIT)
363#define DDRP_DCR_DDR8BNK_BIT 3
364#define DDRP_DCR_DDR8BNK_MASK (1 << DDRP_DCR_DDR8BNK_BIT)
365#define DDRP_DCR_DDR8BNK (1 << DDRP_DCR_DDR8BNK_BIT)
366#define DDRP_DCR_DDR8BNK_DIS (0 << DDRP_DCR_DDR8BNK_BIT)
367
368#define DRP_DTRP1_RTODT BIT(11)
369
370#define DDRP_DXGCR_DXEN BIT(0)
371
372#define DDRP_ZQXCR_ZDEN_BIT 28
373#define DDRP_ZQXCR_ZDEN (1 << DDRP_ZQXCR_ZDEN_BIT)
374#define DDRP_ZQXCR_PULLUP_IMPE_BIT 5
375#define DDRP_ZQXCR_PULLDOWN_IMPE_BIT 0
376
377/* DDR3 Mode Register Set */
378#define DDR3_MR0_BL_BIT 0
379#define DDR3_MR0_BL_MASK (3 << DDR3_MR0_BL_BIT)
380#define DDR3_MR0_BL_8 (0 << DDR3_MR0_BL_BIT)
381#define DDR3_MR0_BL_fly (1 << DDR3_MR0_BL_BIT)
382#define DDR3_MR0_BL_4 (2 << DDR3_MR0_BL_BIT)
383#define DDR3_MR0_BT_BIT 3
384#define DDR3_MR0_BT_MASK (1 << DDR3_MR0_BT_BIT)
385#define DDR3_MR0_BT_SEQ (0 << DDR3_MR0_BT_BIT)
386#define DDR3_MR0_BT_INTER (1 << DDR3_MR0_BT_BIT)
387#define DDR3_MR0_WR_BIT 9
388
389#define DDR3_MR1_DLL_DISABLE 1
390#define DDR3_MR1_DIC_6 (0 << 5 | 0 << 1)
391#define DDR3_MR1_DIC_7 (0 << 5 | BIT(1))
392#define DDR3_MR1_RTT_DIS (0 << 9 | 0 << 6 | 0 << 2)
393#define DDR3_MR1_RTT_4 (0 << 9 | 0 << 6 | BIT(2))
394#define DDR3_MR1_RTT_2 (0 << 9 | BIT(6) | 0 << 2)
395#define DDR3_MR1_RTT_6 (0 << 9 | BIT(6) | BIT(2))
396#define DDR3_MR1_RTT_12 (BIT(9) | 0 << 6 | 0 << 2)
397#define DDR3_MR1_RTT_8 (BIT(9) | 0 << 6 | BIT(2))
398
399#define DDR3_MR2_CWL_BIT 3
400
401/* Parameters common to all RAM devices used */
402
403/* Chip Select */
404/* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */
405#define DDR_CS0EN 1
406/* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */
407#define DDR_CS1EN 0
408
409/* ROW : 12 to 18 row address, 1G only 512MB */
410#define DDR_ROW 15
411/* COL : 8 to 14 column address */
412#define DDR_COL 10
413/* Banks each chip: 0-4bank, 1-8bank */
414#define DDR_BANK8 1
415/* 0 - 16-bit data width, 1 - 32-bit data width */
416#define DDR_DW32 1
417
418/* Refresh period: 64ms / 32768 = 1.95 us , 2 ^ 15 = 32768 */
419#define DDR_tREFI 7800
420/* Clock Divider */
421#define DDR_CLK_DIV 1
422
423/* DDR3 Burst length: 0 - 8 burst, 2 - 4 burst , 1 - 4 or 8 (on the fly) */
424#define DDR_BL 8
425
426/* CAS latency: 5 to 14, tCK */
427#define DDR_CL 6
428/* DDR3 only: CAS Write Latency, 5 to 8 */
429#define DDR_tCWL (DDR_CL - 1)
430
431/* Structure representing per-RAM type configuration */
432
433struct jz4780_ddr_config {
434 u32 timing[6]; /* Timing1..6 register value */
435
436 /* DDR PHY control */
437 u16 mr0; /* Mode Register 0 */
438 u16 mr1; /* Mode Register 1 */
439
440 u32 ptr0; /* PHY Timing Register 0 */
441 u32 ptr1; /* PHY Timing Register 1 */
442 u32 ptr2; /* PHY Timing Register 1 */
443
444 u32 dtpr0; /* DRAM Timing Parameters Register 0 */
445 u32 dtpr1; /* DRAM Timing Parameters Register 1 */
446 u32 dtpr2; /* DRAM Timing Parameters Register 2 */
447
448 u8 pullup; /* PHY pullup impedance */
449 u8 pulldn; /* PHY pulldown impedance */
450};
451
452void pll_init(void);
453void sdram_init(void);
454
455#endif /* __JZ4780_DRAM_H__ */
456
diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h b/arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h
new file mode 100644
index 0000000000..37f0892f7b
--- /dev/null
+++ b/arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h
@@ -0,0 +1,12 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __JZ4780_GPIO_H__
4#define __JZ4780_GPIO_H__
5
6#define JZ_GPIO(bank, pin) ((32 * (bank)) + (pin))
7
8int jz47xx_gpio_get_value(unsigned int gpio);
9void jz47xx_gpio_direction_input(unsigned int gpio);
10void jz47xx_gpio_direction_output(unsigned int gpio, int value);
11
12#endif
diff --git a/arch/mips/mach-jz47xx/jz4780/Makefile b/arch/mips/mach-jz47xx/jz4780/Makefile
new file mode 100644
index 0000000000..5b3c354327
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/Makefile
@@ -0,0 +1,3 @@
1# SPDX-License-Identifier: GPL-2.0+
2
3obj-y := gpio.o jz4780.o pll.o reset.o sdram.o timer.o
diff --git a/arch/mips/mach-jz47xx/jz4780/TODO b/arch/mips/mach-jz47xx/jz4780/TODO
new file mode 100644
index 0000000000..99ad6225b0
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/TODO
@@ -0,0 +1,4 @@
1- dm gpio driver
2- ethernet driver for the dm9000
3- reduce the hundreds of definitions of register addresses to the ones really needed in assembly or SPL.
4- define the remaining register base addresses as physical addresses and establish a mapping with ioremap_nocache()
diff --git a/arch/mips/mach-jz47xx/jz4780/gpio.c b/arch/mips/mach-jz47xx/jz4780/gpio.c
new file mode 100644
index 0000000000..cee2328ab1
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/gpio.c
@@ -0,0 +1,39 @@
1// SPDX-License-Identifier: GPL-2.0+
2
3#include <config.h>
4#include <common.h>
5#include <asm/io.h>
6#include <mach/jz4780.h>
7
8int jz47xx_gpio_get_value(unsigned int gpio)
9{
10 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
11 int port = gpio / 32;
12 int pin = gpio % 32;
13
14 return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
15}
16
17void jz47xx_gpio_direction_input(unsigned int gpio)
18{
19 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
20 int port = gpio / 32;
21 int pin = gpio % 32;
22
23 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
24 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
25 writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
26}
27
28void jz47xx_gpio_direction_output(unsigned int gpio, int value)
29{
30 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
31 int port = gpio / 32;
32 int pin = gpio % 32;
33
34 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
35 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
36 writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port));
37 writel(BIT(pin), gpio_regs +
38 (value ? GPIO_PXPAT0S(port) : GPIO_PXPAT0C(port)));
39}
diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c
new file mode 100644
index 0000000000..dbd328cb49
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c
@@ -0,0 +1,83 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * JZ4780 common routines
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#include <config.h>
10#include <common.h>
11#include <asm/io.h>
12#include <asm/sections.h>
13#include <mach/jz4780.h>
14#include <mach/jz4780_dram.h>
15#include <mmc.h>
16#include <spl.h>
17
18#ifdef CONFIG_SPL_BUILD
19/* Pointer to the global data structure for SPL */
20DECLARE_GLOBAL_DATA_PTR;
21gd_t gdata __attribute__ ((section(".bss")));
22
23void board_init_f(ulong dummy)
24{
25 typedef void __noreturn (*image_entry_noargs_t)(void);
26 struct mmc *mmc;
27 unsigned long count;
28 struct image_header *header;
29 int ret;
30
31 /* Set global data pointer */
32 gd = &gdata;
33
34 timer_init();
35 pll_init();
36 sdram_init();
37 enable_caches();
38
39 /* Clear the BSS */
40 memset(__bss_start, 0, (char *)&__bss_end - __bss_start);
41
42 gd->flags |= GD_FLG_SPL_INIT;
43
44 ret = mmc_initialize(NULL);
45 if (ret)
46 hang();
47
48 mmc = find_mmc_device(BOOT_DEVICE_MMC1);
49 if (ret)
50 hang();
51
52 ret = mmc_init(mmc);
53 if (ret)
54 hang();
55
56 header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
57 sizeof(struct image_header));
58
59 count = blk_dread(mmc_get_blk_desc(mmc),
60 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
61 0x800, header);
62 if (count == 0)
63 hang();
64
65 image_entry_noargs_t image_entry =
66 (image_entry_noargs_t)CONFIG_SYS_TEXT_BASE;
67
68 image_entry();
69
70 hang();
71}
72#endif /* CONFIG_SPL_BUILD */
73
74ulong board_get_usable_ram_top(ulong total_size)
75{
76 return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
77}
78
79int print_cpuinfo(void)
80{
81 printf("CPU: Ingenic JZ4780\n");
82 return 0;
83}
diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c
new file mode 100644
index 0000000000..9a46198f36
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/pll.c
@@ -0,0 +1,530 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * JZ4780 PLL setup
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#include <config.h>
10#include <common.h>
11#include <asm/io.h>
12#include <mach/jz4780.h>
13
14#define CPM_CPCCR 0x00
15#define CPM_LCR 0x04
16#define CPM_RSR 0x08
17#define CPM_CPPCR 0x0c
18#define CPM_CPAPCR 0x10
19#define CPM_CPMPCR 0x14
20#define CPM_CPEPCR 0x18
21#define CPM_CPVPCR 0x1c
22#define CPM_CLKGR0 0x20
23#define CPM_OPCR 0x24
24#define CPM_CLKGR1 0x28
25#define CPM_DDCDR 0x2c
26#define CPM_VPUCDR 0x30
27#define CPM_CPSPR 0x34
28#define CPM_CPSPPR 0x38
29#define CPM_USBPCR 0x3c
30#define CPM_USBRDT 0x40
31#define CPM_USBVBFIL 0x44
32#define CPM_USBPCR1 0x48
33#define CPM_USBCDR 0x50
34#define CPM_LPCDR 0x54
35#define CPM_I2SCDR 0x60
36#define CPM_LPCDR1 0x64
37#define CPM_MSCCDR 0x68
38#define CPM_UHCCDR 0x6c
39#define CPM_SSICDR 0x74
40#define CPM_CIMCDR 0x7c
41#define CPM_PCMCDR 0x84
42#define CPM_GPUCDR 0x88
43#define CPM_HDMICDR 0x8c
44#define CPM_I2S1CDR 0xa0
45#define CPM_MSCCDR1 0xa4
46#define CPM_MSCCDR2 0xa8
47#define CPM_BCHCDR 0xac
48#define CPM_SPCR0 0xb8
49#define CPM_SPCR1 0xbc
50#define CPM_CPCSR 0xd4
51#define CPM_PSWCST(n) ((0x4 * (n)) + 0x90)
52
53/* Clock control register */
54#define CPM_CPCCR_SEL_SRC_BIT 30
55#define CPM_CPCCR_SEL_SRC_MASK (0x3 << CPM_CPCCR_SEL_SRC_BIT)
56#define CPM_SRC_SEL_STOP 0
57#define CPM_SRC_SEL_APLL 1
58#define CPM_SRC_SEL_EXCLK 2
59#define CPM_SRC_SEL_RTCLK 3
60#define CPM_CPCCR_SEL_CPLL_BIT 28
61#define CPM_CPCCR_SEL_CPLL_MASK (0x3 << CPM_CPCCR_SEL_CPLL_BIT)
62#define CPM_CPCCR_SEL_H0PLL_BIT 26
63#define CPM_CPCCR_SEL_H0PLL_MASK (0x3 << CPM_CPCCR_SEL_H0PLL_BIT)
64#define CPM_CPCCR_SEL_H2PLL_BIT 24
65#define CPM_CPCCR_SEL_H2PLL_MASK (0x3 << CPM_CPCCR_SEL_H2PLL_BIT)
66#define CPM_PLL_SEL_STOP 0
67#define CPM_PLL_SEL_SRC 1
68#define CPM_PLL_SEL_MPLL 2
69#define CPM_PLL_SEL_EPLL 3
70#define CPM_CPCCR_CE_CPU (0x1 << 22)
71#define CPM_CPCCR_CE_AHB0 (0x1 << 21)
72#define CPM_CPCCR_CE_AHB2 (0x1 << 20)
73#define CPM_CPCCR_PDIV_BIT 16
74#define CPM_CPCCR_PDIV_MASK (0xf << CPM_CPCCR_PDIV_BIT)
75#define CPM_CPCCR_H2DIV_BIT 12
76#define CPM_CPCCR_H2DIV_MASK (0xf << CPM_CPCCR_H2DIV_BIT)
77#define CPM_CPCCR_H0DIV_BIT 8
78#define CPM_CPCCR_H0DIV_MASK (0x0f << CPM_CPCCR_H0DIV_BIT)
79#define CPM_CPCCR_L2DIV_BIT 4
80#define CPM_CPCCR_L2DIV_MASK (0x0f << CPM_CPCCR_L2DIV_BIT)
81#define CPM_CPCCR_CDIV_BIT 0
82#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
83
84/* Clock Status register */
85#define CPM_CPCSR_H2DIV_BUSY BIT(2)
86#define CPM_CPCSR_H0DIV_BUSY BIT(1)
87#define CPM_CPCSR_CDIV_BUSY BIT(0)
88
89/* PLL control register */
90#define CPM_CPPCR_PLLST_BIT 0
91#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
92
93/* XPLL control register */
94#define CPM_CPXPCR_XPLLM_BIT 19
95#define CPM_CPXPCR_XPLLM_MASK (0x1fff << CPM_CPXPCR_XPLLM_BIT)
96#define CPM_CPXPCR_XPLLN_BIT 13
97#define CPM_CPXPCR_XPLLN_MASK (0x3f << CPM_CPXPCR_XPLLN_BIT)
98#define CPM_CPXPCR_XPLLOD_BIT 9
99#define CPM_CPXPCR_XPLLOD_MASK (0xf << CPM_CPXPCR_XPLLOD_BIT)
100#define CPM_CPXPCR_XLOCK BIT(6)
101#define CPM_CPXPCR_XPLL_ON BIT(4)
102#define CPM_CPXPCR_XF_MODE BIT(3)
103#define CPM_CPXPCR_XPLLBP BIT(1)
104#define CPM_CPXPCR_XPLLEN BIT(0)
105
106/* CPM scratch protected register */
107#define CPM_CPSPPR_BIT 0
108#define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT)
109
110/* USB parameter control register */
111#define CPM_USBPCR_USB_MODE BIT(31) /* 1: OTG, 0: UDC*/
112#define CPM_USBPCR_AVLD_REG BIT(30)
113#define CPM_USBPCR_IDPULLUP_MASK_BIT 28
114#define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT)
115#define CPM_USBPCR_INCR_MASK BIT(27)
116#define CPM_USBPCR_CLK12_EN BIT(26)
117#define CPM_USBPCR_COMMONONN BIT(25)
118#define CPM_USBPCR_VBUSVLDEXT BIT(24)
119#define CPM_USBPCR_VBUSVLDEXTSEL BIT(23)
120#define CPM_USBPCR_POR BIT(22)
121#define CPM_USBPCR_SIDDQ BIT(21)
122#define CPM_USBPCR_OTG_DISABLE BIT(20)
123#define CPM_USBPCR_COMPDISTUNE_BIT 17
124#define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT)
125#define CPM_USBPCR_OTGTUNE_BIT 14
126#define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT)
127#define CPM_USBPCR_SQRXTUNE_BIT 11
128#define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT)
129#define CPM_USBPCR_TXFSLSTUNE_BIT 7
130#define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT)
131#define CPM_USBPCR_TXPREEMPHTUNE BIT(6)
132#define CPM_USBPCR_TXRISETUNE_BIT 4
133#define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT)
134#define CPM_USBPCR_TXVREFTUNE_BIT 0
135#define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT)
136
137/* DDR memory clock divider register */
138#define CPM_DDRCDR_DCS_BIT 30
139#define CPM_DDRCDR_DCS_MASK (0x3 << CPM_DDRCDR_DCS_BIT)
140#define CPM_DDRCDR_DCS_STOP (0x0 << CPM_DDRCDR_DCS_BIT)
141#define CPM_DDRCDR_DCS_SRC (0x1 << CPM_DDRCDR_DCS_BIT)
142#define CPM_DDRCDR_DCS_MPLL (0x2 << CPM_DDRCDR_DCS_BIT)
143#define CPM_DDRCDR_CE_DDR BIT(29)
144#define CPM_DDRCDR_DDR_BUSY BIT(28)
145#define CPM_DDRCDR_DDR_STOP BIT(27)
146#define CPM_DDRCDR_DDRDIV_BIT 0
147#define CPM_DDRCDR_DDRDIV_MASK (0xf << CPM_DDRCDR_DDRDIV_BIT)
148
149/* USB reset detect timer register */
150#define CPM_USBRDT_VBFIL_LD_EN BIT(25)
151#define CPM_USBRDT_IDDIG_EN BIT(24)
152#define CPM_USBRDT_IDDIG_REG BIT(23)
153#define CPM_USBRDT_USBRDT_BIT 0
154#define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT)
155
156/* USB OTG PHY clock divider register */
157#define CPM_USBCDR_UCS BIT(31)
158#define CPM_USBCDR_UPCS BIT(30)
159#define CPM_USBCDR_CEUSB BIT(29)
160#define CPM_USBCDR_USB_BUSY BIT(28)
161#define CPM_USBCDR_OTGDIV_BIT 0
162#define CPM_USBCDR_OTGDIV_MASK (0xff << CPM_USBCDR_OTGDIV_BIT)
163
164/* I2S device clock divider register */
165#define CPM_I2SCDR_I2CS BIT(31)
166#define CPM_I2SCDR_I2PCS BIT(30)
167#define CPM_I2SCDR_I2SDIV_BIT 0
168#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
169
170/* LCD0 pix clock divider register */
171#define CPM_LPCDR_LPCS_BIT 30
172#define CPM_LPCDR_LPCS_MASK (0x3 << CPM_LPCDR_LPCS_BIT)
173#define CPM_LPCDR_CELCD BIT(28)
174#define CPM_LPCDR_LCD_BUSY BIT(27)
175#define CPM_LPCDR_LCD_STOP BIT(26)
176#define CPM_LPCDR_PIXDIV_BIT 0
177#define CPM_LPCDR_PIXDIV_MASK (0xff << CPM_LPCDR_PIXDIV_BIT)
178
179/* MSC clock divider register */
180#define CPM_MSCCDR_MPCS_BIT 30
181#define CPM_MSCCDR_MPCS_MASK (3 << CPM_MSCCDR_MPCS_BIT)
182#define CPM_MSCCDR_MPCS_STOP (0x0 << CPM_MSCCDR_MPCS_BIT)
183#define CPM_MSCCDR_MPCS_SRC (0x1 << CPM_MSCCDR_MPCS_BIT)
184#define CPM_MSCCDR_MPCS_MPLL (0x2 << CPM_MSCCDR_MPCS_BIT)
185#define CPM_MSCCDR_CE BIT(29)
186#define CPM_MSCCDR_MSC_BUSY BIT(28)
187#define CPM_MSCCDR_MSC_STOP BIT(27)
188#define CPM_MSCCDR_MSC_CLK0_SEL BIT(15)
189#define CPM_MSCCDR_MSCDIV_BIT 0
190#define CPM_MSCCDR_MSCDIV_MASK (0xff << CPM_MSCCDR_MSCDIV_BIT)
191
192/* UHC 48M clock divider register */
193#define CPM_UHCCDR_UHCS_BIT 30
194#define CPM_UHCCDR_UHCS_MASK (0x3 << CPM_UHCCDR_UHCS_BIT)
195#define CPM_UHCCDR_UHCS_SRC (0x0 << CPM_UHCCDR_UHCS_BIT)
196#define CPM_UHCCDR_UHCS_MPLL (0x1 << CPM_UHCCDR_UHCS_BIT)
197#define CPM_UHCCDR_UHCS_EPLL (0x2 << CPM_UHCCDR_UHCS_BIT)
198#define CPM_UHCCDR_UHCS_OTG (0x3 << CPM_UHCCDR_UHCS_BIT)
199#define CPM_UHCCDR_CE_UHC BIT(29)
200#define CPM_UHCCDR_UHC_BUSY BIT(28)
201#define CPM_UHCCDR_UHC_STOP BIT(27)
202#define CPM_UHCCDR_UHCDIV_BIT 0
203#define CPM_UHCCDR_UHCDIV_MASK (0xff << CPM_UHCCDR_UHCDIV_BIT)
204
205/* SSI clock divider register */
206#define CPM_SSICDR_SCS BIT(31)
207#define CPM_SSICDR_SSIDIV_BIT 0
208#define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT)
209
210/* CIM MCLK clock divider register */
211#define CPM_CIMCDR_CIMDIV_BIT 0
212#define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT)
213
214/* GPS clock divider register */
215#define CPM_GPSCDR_GPCS BIT(31)
216#define CPM_GPSCDR_GPSDIV_BIT 0
217#define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT)
218
219/* PCM device clock divider register */
220#define CPM_PCMCDR_PCMS BIT(31)
221#define CPM_PCMCDR_PCMPCS BIT(30)
222#define CPM_PCMCDR_PCMDIV_BIT 0
223#define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT)
224
225/* GPU clock divider register */
226#define CPM_GPUCDR_GPCS BIT(31)
227#define CPM_GPUCDR_GPUDIV_BIT 0
228#define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT)
229
230/* HDMI clock divider register */
231#define CPM_HDMICDR_HPCS_BIT 30
232#define CPM_HDMICDR_HPCS_MASK (0x3 << CPM_HDMICDR_HPCS_BIT)
233#define CPM_HDMICDR_CEHDMI BIT(29)
234#define CPM_HDMICDR_HDMI_BUSY BIT(28)
235#define CPM_HDMICDR_HDMI_STOP BIT(26)
236#define CPM_HDMICDR_HDMIDIV_BIT 0
237#define CPM_HDMICDR_HDMIDIV_MASK (0xff << CPM_HDMICDR_HDMIDIV_BIT)
238
239/* Low Power Control Register */
240#define CPM_LCR_PD_SCPU BIT(31)
241#define CPM_LCR_PD_VPU BIT(30)
242#define CPM_LCR_PD_GPU BIT(29)
243#define CPM_LCR_PD_GPS BIT(28)
244#define CPM_LCR_SCPUS BIT(27)
245#define CPM_LCR_VPUS BIT(26)
246#define CPM_LCR_GPUS BIT(25)
247#define CPM_LCR_GPSS BIT(24)
248#define CPM_LCR_GPU_IDLE BIT(20)
249#define CPM_LCR_PST_BIT 8
250#define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT)
251#define CPM_LCR_DOZE_DUTY_BIT 3
252#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
253#define CPM_LCR_DOZE_ON BIT(2)
254#define CPM_LCR_LPM_BIT 0
255#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
256#define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
257#define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
258
259/* Clock Gate Register0 */
260#define CPM_CLKGR0_DDR1 BIT(31)
261#define CPM_CLKGR0_DDR0 BIT(30)
262#define CPM_CLKGR0_IPU BIT(29)
263#define CPM_CLKGR0_LCD1 BIT(28)
264#define CPM_CLKGR0_LCD BIT(27)
265#define CPM_CLKGR0_CIM BIT(26)
266#define CPM_CLKGR0_I2C2 BIT(25)
267#define CPM_CLKGR0_UHC BIT(24)
268#define CPM_CLKGR0_MAC BIT(23)
269#define CPM_CLKGR0_GPS BIT(22)
270#define CPM_CLKGR0_PDMAC BIT(21)
271#define CPM_CLKGR0_SSI2 BIT(20)
272#define CPM_CLKGR0_SSI1 BIT(19)
273#define CPM_CLKGR0_UART3 BIT(18)
274#define CPM_CLKGR0_UART2 BIT(17)
275#define CPM_CLKGR0_UART1 BIT(16)
276#define CPM_CLKGR0_UART0 BIT(15)
277#define CPM_CLKGR0_SADC BIT(14)
278#define CPM_CLKGR0_KBC BIT(13)
279#define CPM_CLKGR0_MSC2 BIT(12)
280#define CPM_CLKGR0_MSC1 BIT(11)
281#define CPM_CLKGR0_OWI BIT(10)
282#define CPM_CLKGR0_TSSI BIT(9)
283#define CPM_CLKGR0_AIC BIT(8)
284#define CPM_CLKGR0_SCC BIT(7)
285#define CPM_CLKGR0_I2C1 BIT(6)
286#define CPM_CLKGR0_I2C0 BIT(5)
287#define CPM_CLKGR0_SSI0 BIT(4)
288#define CPM_CLKGR0_MSC0 BIT(3)
289#define CPM_CLKGR0_OTG BIT(2)
290#define CPM_CLKGR0_BCH BIT(1)
291#define CPM_CLKGR0_NEMC BIT(0)
292
293/* Clock Gate Register1 */
294#define CPM_CLKGR1_P1 BIT(15)
295#define CPM_CLKGR1_X2D BIT(14)
296#define CPM_CLKGR1_DES BIT(13)
297#define CPM_CLKGR1_I2C4 BIT(12)
298#define CPM_CLKGR1_AHB BIT(11)
299#define CPM_CLKGR1_UART4 BIT(10)
300#define CPM_CLKGR1_HDMI BIT(9)
301#define CPM_CLKGR1_OTG1 BIT(8)
302#define CPM_CLKGR1_GPVLC BIT(7)
303#define CPM_CLKGR1_AIC1 BIT(6)
304#define CPM_CLKGR1_COMPRES BIT(5)
305#define CPM_CLKGR1_GPU BIT(4)
306#define CPM_CLKGR1_PCM BIT(3)
307#define CPM_CLKGR1_VPU BIT(2)
308#define CPM_CLKGR1_TSSI1 BIT(1)
309#define CPM_CLKGR1_I2C3 BIT(0)
310
311/* Oscillator and Power Control Register */
312#define CPM_OPCR_O1ST_BIT 8
313#define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT)
314#define CPM_OPCR_SPENDN BIT(7)
315#define CPM_OPCR_GPSEN BIT(6)
316#define CPM_OPCR_SPENDH BIT(5)
317#define CPM_OPCR_O1SE BIT(4)
318#define CPM_OPCR_ERCS BIT(2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
319#define CPM_OPCR_USBM BIT(0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
320
321/* Reset Status Register */
322#define CPM_RSR_P0R BIT(2)
323#define CPM_RSR_WR BIT(1)
324#define CPM_RSR_PR BIT(0)
325
326/* BCH clock divider register */
327#define CPM_BCHCDR_BPCS_BIT 30
328#define CPM_BCHCDR_BPCS_MASK (0x3 << CPM_BCHCDR_BPCS_BIT)
329#define CPM_BCHCDR_BPCS_STOP (0X0 << CPM_BCHCDR_BPCS_BIT)
330#define CPM_BCHCDR_BPCS_SRC_CLK (0x1 << CPM_BCHCDR_BPCS_BIT)
331#define CPM_BCHCDR_BPCS_MPLL (0x2 << CPM_BCHCDR_BPCS_BIT)
332#define CPM_BCHCDR_BPCS_EPLL (0x3 << CPM_BCHCDR_BPCS_BIT)
333#define CPM_BCHCDR_CE_BCH BIT(29)
334#define CPM_BCHCDR_BCH_BUSY BIT(28)
335#define CPM_BCHCDR_BCH_STOP BIT(27)
336#define CPM_BCHCDR_BCHCDR_BIT 0
337#define CPM_BCHCDR_BCHCDR_MASK (0x7 << CPM_BCHCDR_BCHCDR_BIT)
338
339/* CPM scratch pad protected register(CPSPPR) */
340#define CPSPPR_CPSPR_WRITABLE 0x00005a5a
341#define RECOVERY_SIGNATURE 0x1a1a /* means "RECY" */
342#define RECOVERY_SIGNATURE_SEC 0x800 /* means "RECY" */
343
344#define REBOOT_SIGNATURE 0x3535 /* means reboot */
345
346/* XPLL control register */
347#define XLOCK (1 << 6)
348#define XPLL_ON (1 << 4)
349#define XF_MODE (1 << 3)
350#define XPLLBP (1 << 1)
351#define XPLLEN (1 << 0)
352
353enum PLLS {
354 EXTCLK = 0,
355 APLL,
356 MPLL,
357 EPLL,
358 VPLL,
359};
360
361#define M_N_OD(m, n, od) \
362 ((((m) - 1) << 19) | (((n) - 1) << 13) | (((od) - 1) << 9))
363
364struct cgu_pll_select {
365 u8 reg;
366 u8 pll;
367 u8 pll_shift;
368};
369
370static void pll_init_one(int pll, int m, int n, int od)
371{
372 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
373 void __iomem *pll_reg = cpm_regs + CPM_CPAPCR + ((pll - 1) * 4);
374
375 setbits_le32(pll_reg, M_N_OD(m, n, od) | XPLLEN);
376
377 /* FIXME */
378 while (!(readl(pll_reg) & XPLL_ON))
379 ;
380}
381
382static void cpu_mux_select(int pll)
383{
384 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
385 u32 clk_ctrl;
386 unsigned int selectplls[] = {
387 CPM_PLL_SEL_STOP,
388 CPM_PLL_SEL_SRC,
389 CPM_PLL_SEL_MPLL,
390 CPM_PLL_SEL_EPLL
391 };
392
393 /* Init CPU, L2CACHE, AHB0, AHB2, APB clock */
394 clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 |
395 ((6 - 1) << CPM_CPCCR_H2DIV_BIT) |
396 ((3 - 1) << CPM_CPCCR_H0DIV_BIT) |
397 ((2 - 1) << CPM_CPCCR_L2DIV_BIT) |
398 ((1 - 1) << CPM_CPCCR_CDIV_BIT);
399
400 if (CONFIG_SYS_MHZ >= 1000)
401 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
402 else
403 clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT;
404
405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
406
407 while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY |
408 CPM_CPCSR_H0DIV_BUSY | CPM_CPCSR_H2DIV_BUSY))
409 ;
410
411 clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) |
412 (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) |
413 (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT);
414 if (pll == APLL)
415 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT;
416 else
417 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT;
418
419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl);
420}
421
422static void ddr_mux_select(int pll)
423{
424 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
425 int selectplls[] = { CPM_DDRCDR_DCS_STOP,
426 CPM_DDRCDR_DCS_SRC,
427 CPM_DDRCDR_DCS_MPLL};
428
429 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1),
430 cpm_regs + CPM_DDCDR);
431
432 while (readl(cpm_regs + CPM_DDCDR) & CPM_DDRCDR_DDR_BUSY)
433 ;
434
435 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_DDR0);
436
437 mdelay(200);
438}
439
440static void cgu_mux_init(struct cgu_pll_select *cgu, unsigned int num)
441{
442 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
443 unsigned int selectplls[] = {0, 1, 2, 3, 2, 6};
444 int i;
445
446 for (i = 0; i < num; i++)
447 writel(selectplls[cgu[i].pll] << cgu[i].pll_shift,
448 cpm_regs + cgu[i].reg);
449}
450
451void pll_init(void)
452{
453 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
454 struct cgu_pll_select cgu_mux[] = {
455 { CPM_MSCCDR, MPLL, 30 },
456 { CPM_LPCDR, VPLL, 30 },
457 { CPM_LPCDR1, VPLL, 30 },
458 { CPM_GPUCDR, MPLL, 30 },
459 { CPM_HDMICDR, VPLL, 30 },
460 { CPM_I2SCDR, EPLL, 30 },
461 { CPM_BCHCDR, MPLL, 30 },
462 { CPM_VPUCDR, 0x1, 30 },
463 { CPM_UHCCDR, 0x3, 30 },
464 { CPM_CIMCDR, 0x1, 31 },
465 { CPM_PCMCDR, 0x5, 29 },
466 { CPM_SSICDR, 0x3, 30 },
467 };
468
469 /* PLL stable time set to default -- 1ms */
470 clrsetbits_le32(cpm_regs + CPM_CPPCR, 0xfffff, (16 << 8) | 0x20);
471
472 pll_init_one(APLL, JZ4780_APLL_M, JZ4780_APLL_N, JZ4780_APLL_OD);
473 pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD);
474 pll_init_one(VPLL, JZ4780_VPLL_M, JZ4780_VPLL_N, JZ4780_VPLL_OD);
475 pll_init_one(EPLL, JZ4780_EPLL_M, JZ4780_EPLL_N, JZ4780_EPLL_OD);
476
477 cpu_mux_select(MPLL);
478 ddr_mux_select(MPLL);
479 cgu_mux_init(cgu_mux, ARRAY_SIZE(cgu_mux));
480}
481
482const u32 jz4780_clk_get_efuse_clk(void)
483{
484 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
485 u32 cpccr = readl(cpm_regs + CPM_CPCCR);
486 u32 ahb2_div = ((cpccr & CPM_CPCCR_H2DIV_MASK) >>
487 CPM_CPCCR_H2DIV_BIT) + 1;
488 return JZ4780_SYS_MEM_SPEED / ahb2_div;
489}
490
491void jz4780_clk_ungate_ethernet(void)
492{
493 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
494
495 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_MAC);
496 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_NEMC);
497}
498
499void jz4780_clk_ungate_mmc(void)
500{
501 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
502 u32 msc_cdr = JZ4780_SYS_MEM_SPEED / 24000000 / 2 - 1;
503
504 msc_cdr |= CPM_MSCCDR_MPCS_MPLL | CPM_MSCCDR_CE;
505 writel(msc_cdr, cpm_regs + CPM_MSCCDR);
506 writel(msc_cdr, cpm_regs + CPM_MSCCDR1);
507 writel(msc_cdr, cpm_regs + CPM_MSCCDR2);
508
509 /* The wait_for_bit() won't fit, thus unbounded loop here. */
510 while (readl(cpm_regs + CPM_MSCCDR1) & CPM_MSCCDR_MSC_BUSY)
511 ;
512}
513
514void jz4780_clk_ungate_uart(const unsigned int uart)
515{
516 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
517
518 if (uart == 0)
519 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART0);
520 else if (uart == 1)
521 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART1);
522 else if (uart == 2)
523 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART2);
524 else if (uart == 3)
525 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART3);
526 else if (uart == 4)
527 clrbits_le32(cpm_regs + CPM_CLKGR1, CPM_CLKGR1_UART4);
528 else
529 printf("%s[%i]: Invalid UART %d\n", __func__, __LINE__, uart);
530}
diff --git a/arch/mips/mach-jz47xx/jz4780/reset.c b/arch/mips/mach-jz47xx/jz4780/reset.c
new file mode 100644
index 0000000000..73af34721f
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/reset.c
@@ -0,0 +1,53 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * JZ4780 common routines
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#include <config.h>
10#include <common.h>
11#include <asm/io.h>
12#include <mach/jz4780.h>
13
14/* WDT */
15#define WDT_TDR 0x00
16#define WDT_TCER 0x04
17#define WDT_TCNT 0x08
18#define WDT_TCSR 0x0C
19
20/* Register definition */
21#define WDT_TCSR_PRESCALE_BIT 3
22#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
23 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
24 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
25 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
26 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
27 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
28 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
29#define WDT_TCSR_EXT_EN BIT(2)
30#define WDT_TCSR_RTC_EN BIT(1)
31#define WDT_TCSR_PCK_EN BIT(0)
32
33#define WDT_TCER_TCEN BIT(0)
34
35void _machine_restart(void)
36{
37 void __iomem *wdt_regs = (void __iomem *)WDT_BASE;
38
39 /* EXTAL as the timer clock input. */
40 writew(WDT_TCSR_PRESCALE1 | WDT_TCSR_EXT_EN, wdt_regs + WDT_TCSR);
41
42 /* Reset the WDT counter and timeout. */
43 writew(0, wdt_regs + WDT_TCNT);
44 writew(0, wdt_regs + WDT_TDR);
45
46 jz4780_tcu_wdt_start();
47
48 /* WDT start */
49 writeb(WDT_TCER_TCEN, wdt_regs + WDT_TCER);
50
51 for (;;)
52 ;
53}
diff --git a/arch/mips/mach-jz47xx/jz4780/sdram.c b/arch/mips/mach-jz47xx/jz4780/sdram.c
new file mode 100644
index 0000000000..5b25c8d002
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/sdram.c
@@ -0,0 +1,270 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * JZ4780 DDR initialization
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 *
8 * Based on spl/common/{jz4780_ddr,jz_ddr3_init}.c from X-Boot
9 * Copyright (c) 2006-2013 Ingenic Semiconductor
10 */
11
12#include <common.h>
13#include <asm/io.h>
14#include <mach/jz4780.h>
15#include <mach/jz4780_dram.h>
16
17static const u32 get_mem_clk(void)
18{
19 const u32 mpll_out = ((u64)JZ4780_SYS_EXTAL * JZ4780_MPLL_M) /
20 (JZ4780_MPLL_N * JZ4780_MPLL_OD);
21 return mpll_out / JZ4780_SYS_MEM_DIV;
22}
23
24u32 sdram_size(int cs)
25{
26 u32 dw = DDR_DW32 ? 4 : 2;
27 u32 banks = DDR_BANK8 ? 8 : 4;
28 u32 size = 0;
29
30 if ((cs == 0) && DDR_CS0EN) {
31 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
32 if (DDR_CS1EN && (size > 0x20000000))
33 size = 0x20000000;
34 } else if ((cs == 1) && DDR_CS1EN) {
35 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
36 }
37
38 return size;
39}
40
41static void ddr_cfg_init(void)
42{
43 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
44 u32 ddrc_cfg, tmp;
45
46 tmp = DDR_CL;
47 if (tmp)
48 tmp--;
49 if (tmp > 4)
50 tmp = 4;
51
52 ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA |
53 DDR_DW32 | DDRC_CFG_MPRT | ((tmp | 0x8) << 2) |
54 ((DDR_ROW - 12) << 11) | ((DDR_COL - 8) << 8) |
55 (DDR_CS0EN << 6) | (DDR_BANK8 << 1) |
56 ((DDR_ROW - 12) << 27) | ((DDR_COL - 8) << 24) |
57 (DDR_CS1EN << 7) | (DDR_BANK8 << 23);
58
59 if (DDR_BL > 4)
60 ddrc_cfg |= BIT(21);
61
62 writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG);
63}
64
65static void ddr_phy_init(const struct jz4780_ddr_config *ddr_config)
66{
67 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
68 void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
69 unsigned int count = 0, i;
70 u32 reg, mask;
71
72 writel(DDRP_DCR_TYPE_DDR3 | (DDR_BANK8 << 3), ddr_phy_regs + DDRP_DCR);
73
74 writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0);
75 writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1);
76 writel(0, ddr_phy_regs + DDRP_ODTCR);
77 writel(0, ddr_phy_regs + DDRP_MR2);
78
79 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0);
80 writel(ddr_config->ptr1, ddr_phy_regs + DDRP_PTR1);
81 writel(ddr_config->ptr2, ddr_phy_regs + DDRP_PTR2);
82
83 writel(ddr_config->dtpr0, ddr_phy_regs + DDRP_DTPR0);
84 writel(ddr_config->dtpr1, ddr_phy_regs + DDRP_DTPR1);
85 writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2);
86
87 writel(DDRP_PGCR_DQSCFG | (7 << DDRP_PGCR_CKEN_BIT) |
88 (2 << DDRP_PGCR_CKDV_BIT) |
89 (DDR_CS0EN | (DDR_CS1EN << 1)) << DDRP_PGCR_RANKEN_BIT |
90 DDRP_PGCR_ZCKSEL_32 | DDRP_PGCR_PDDISDX,
91 ddr_phy_regs + DDRP_PGCR);
92
93 for (i = 0; i < 8; i++)
94 clrbits_le32(ddr_phy_regs + DDRP_DXGCR(i), 0x3 << 9);
95
96 count = 0;
97 mask = DDRP_PGSR_IDONE | DDRP_PGSR_DLDONE | DDRP_PGSR_ZCDONE;
98 for (;;) {
99 reg = readl(ddr_phy_regs + DDRP_PGSR);
100 if ((reg == mask) || (reg == 0x1f))
101 break;
102 if (count++ == 10000)
103 hang();
104 }
105
106 /* DQS extension and early set to 1 */
107 clrsetbits_le32(ddr_phy_regs + DDRP_DSGCR, 0x7E << 4, 0x12 << 4);
108
109 /* 500 pull up and 500 pull down */
110 clrsetbits_le32(ddr_phy_regs + DDRP_DXCCR, 0xFF << 4, 0xC4 << 4);
111
112 /* Initialise phy */
113 writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST,
114 ddr_phy_regs + DDRP_PIR);
115
116 count = 0;
117 mask |= DDRP_PGSR_DIDONE;
118 for (;;) {
119 reg = readl(ddr_phy_regs + DDRP_PGSR);
120 if ((reg == mask) || (reg == 0x1f))
121 break;
122 if (count++ == 20000)
123 hang();
124 }
125
126 writel(DDRP_PIR_INIT | DDRP_PIR_QSTRN, ddr_phy_regs + DDRP_PIR);
127
128 count = 0;
129 mask |= DDRP_PGSR_DTDONE;
130 for (;;) {
131 reg = readl(ddr_phy_regs + DDRP_PGSR);
132 if (reg == mask)
133 break;
134 if (count++ != 50000)
135 continue;
136 reg &= DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR;
137 if (reg)
138 hang();
139 count = 0;
140 }
141
142 /* Override impedance */
143 clrsetbits_le32(ddr_phy_regs + DDRP_ZQXCR0(0), 0x3ff,
144 ((ddr_config->pullup & 0x1f) << DDRP_ZQXCR_PULLUP_IMPE_BIT) |
145 ((ddr_config->pulldn & 0x1f) << DDRP_ZQXCR_PULLDOWN_IMPE_BIT) |
146 DDRP_ZQXCR_ZDEN);
147}
148
149#define JZBIT(bit) ((bit % 4) * 8)
150#define JZMASK(bit) (0x1f << JZBIT(bit))
151
152static void remap_swap(int a, int b)
153{
154 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
155 u32 remmap[2], tmp[2];
156
157 remmap[0] = readl(ddr_ctl_regs + DDRC_REMMAP(a / 4));
158 remmap[1] = readl(ddr_ctl_regs + DDRC_REMMAP(b / 4));
159
160 tmp[0] = (remmap[0] & JZMASK(a)) >> JZBIT(a);
161 tmp[1] = (remmap[1] & JZMASK(b)) >> JZBIT(b);
162
163 remmap[0] &= ~JZMASK(a);
164 remmap[1] &= ~JZMASK(b);
165
166 writel(remmap[0] | (tmp[1] << JZBIT(a)),
167 ddr_ctl_regs + DDRC_REMMAP(a / 4));
168 writel(remmap[1] | (tmp[0] << JZBIT(b)),
169 ddr_ctl_regs + DDRC_REMMAP(b / 4));
170}
171
172static void mem_remap(void)
173{
174 u32 start = (DDR_ROW + DDR_COL + (DDR_DW32 ? 4 : 2) / 2) - 12;
175 u32 num = DDR_BANK8 ? 3 : 2;
176
177 if (DDR_CS0EN && DDR_CS1EN)
178 num++;
179
180 for (; num > 0; num--)
181 remap_swap(0 + num - 1, start + num - 1);
182}
183
184/* Fetch DRAM config from board file */
185__weak const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
186{
187 return NULL;
188}
189
190void sdram_init(void)
191{
192 const struct jz4780_ddr_config *ddr_config = jz4780_get_ddr_config();
193 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
194 void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
195 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
196 u32 mem_clk, tmp, i;
197 u32 mem_base0, mem_base1;
198 u32 mem_mask0, mem_mask1;
199 u32 mem_size0, mem_size1;
200
201 if (!ddr_config)
202 hang();
203
204 /* Reset DLL in DDR PHY */
205 writel(0x3, cpm_regs + 0xd0);
206 mdelay(400);
207 writel(0x1, cpm_regs + 0xd0);
208 mdelay(400);
209
210 /* Enter reset */
211 writel(0xf << 20, ddr_ctl_regs + DDRC_CTRL);
212
213 mem_clk = get_mem_clk();
214
215 tmp = 1000000000 / mem_clk;
216 if (1000000000 % mem_clk)
217 tmp++;
218 tmp = DDR_tREFI / tmp;
219 tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1;
220 if (tmp > 0xff)
221 tmp = 0xff;
222 if (tmp < 1)
223 tmp = 1;
224
225 writel(0x0, ddr_ctl_regs + DDRC_CTRL);
226
227 writel(0x150000, ddr_phy_regs + DDRP_DTAR);
228 ddr_phy_init(ddr_config);
229
230 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
231 writel(0x0, ddr_ctl_regs + DDRC_CTRL);
232
233 ddr_cfg_init();
234
235 for (i = 0; i < 6; i++)
236 writel(ddr_config->timing[i], ddr_ctl_regs + DDRC_TIMING(i));
237
238 mem_size0 = sdram_size(0);
239 mem_size1 = sdram_size(1);
240
241 if (!mem_size1 && mem_size0 > 0x20000000) {
242 mem_base0 = 0x0;
243 mem_mask0 = ~(((mem_size0 * 2) >> 24) - 1) & DDRC_MMAP_MASK_MASK;
244 } else {
245 mem_base0 = (DDR_MEM_PHY_BASE >> 24) & 0xff;
246 mem_mask0 = ~((mem_size0 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
247 }
248
249 if (mem_size1) {
250 mem_mask1 = ~((mem_size1 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
251 mem_base1 = ((DDR_MEM_PHY_BASE + mem_size0) >> 24) & 0xff;
252 } else {
253 mem_mask1 = 0;
254 mem_base1 = 0xff;
255 }
256
257 writel(mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0,
258 ddr_ctl_regs + DDRC_MMAP0);
259 writel(mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1,
260 ddr_ctl_regs + DDRC_MMAP1);
261 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
262 writel((DDR_CLK_DIV << 1) | DDRC_REFCNT_REF_EN |
263 (tmp << DDRC_REFCNT_CON_BIT),
264 ddr_ctl_regs + DDRC_REFCNT);
265 writel((1 << 15) | (4 << 12) | (1 << 11) | (1 << 8) | (0 << 6) |
266 (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1),
267 ddr_ctl_regs + DDRC_CTRL);
268 mem_remap();
269 clrbits_le32(ddr_ctl_regs + DDRC_ST, 0x40);
270}
diff --git a/arch/mips/mach-jz47xx/jz4780/timer.c b/arch/mips/mach-jz47xx/jz4780/timer.c
new file mode 100644
index 0000000000..a689b9d71a
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/timer.c
@@ -0,0 +1,239 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * JZ4780 timer
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#include <config.h>
10#include <common.h>
11#include <div64.h>
12#include <asm/io.h>
13#include <asm/mipsregs.h>
14#include <mach/jz4780.h>
15
16#define TCU_TSR 0x1C /* Timer Stop Register */
17#define TCU_TSSR 0x2C /* Timer Stop Set Register */
18#define TCU_TSCR 0x3C /* Timer Stop Clear Register */
19#define TCU_TER 0x10 /* Timer Counter Enable Register */
20#define TCU_TESR 0x14 /* Timer Counter Enable Set Register */
21#define TCU_TECR 0x18 /* Timer Counter Enable Clear Register */
22#define TCU_TFR 0x20 /* Timer Flag Register */
23#define TCU_TFSR 0x24 /* Timer Flag Set Register */
24#define TCU_TFCR 0x28 /* Timer Flag Clear Register */
25#define TCU_TMR 0x30 /* Timer Mask Register */
26#define TCU_TMSR 0x34 /* Timer Mask Set Register */
27#define TCU_TMCR 0x38 /* Timer Mask Clear Register */
28/* n = 0,1,2,3,4,5 */
29#define TCU_TDFR(n) (0x40 + (n) * 0x10) /* Timer Data Full Reg */
30#define TCU_TDHR(n) (0x44 + (n) * 0x10) /* Timer Data Half Reg */
31#define TCU_TCNT(n) (0x48 + (n) * 0x10) /* Timer Counter Reg */
32#define TCU_TCSR(n) (0x4C + (n) * 0x10) /* Timer Control Reg */
33
34#define TCU_OSTCNTL 0xe4
35#define TCU_OSTCNTH 0xe8
36#define TCU_OSTCSR 0xec
37#define TCU_OSTCNTHBUF 0xfc
38
39/* Register definitions */
40#define TCU_TCSR_PWM_SD BIT(9)
41#define TCU_TCSR_PWM_INITL_HIGH BIT(8)
42#define TCU_TCSR_PWM_EN BIT(7)
43#define TCU_TCSR_PRESCALE_BIT 3
44#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
45#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
46#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
47#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
48#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
49#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
50#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
51#define TCU_TCSR_EXT_EN BIT(2)
52#define TCU_TCSR_RTC_EN BIT(1)
53#define TCU_TCSR_PCK_EN BIT(0)
54
55#define TCU_TER_TCEN5 BIT(5)
56#define TCU_TER_TCEN4 BIT(4)
57#define TCU_TER_TCEN3 BIT(3)
58#define TCU_TER_TCEN2 BIT(2)
59#define TCU_TER_TCEN1 BIT(1)
60#define TCU_TER_TCEN0 BIT(0)
61
62#define TCU_TESR_TCST5 BIT(5)
63#define TCU_TESR_TCST4 BIT(4)
64#define TCU_TESR_TCST3 BIT(3)
65#define TCU_TESR_TCST2 BIT(2)
66#define TCU_TESR_TCST1 BIT(1)
67#define TCU_TESR_TCST0 BIT(0)
68
69#define TCU_TECR_TCCL5 BIT(5)
70#define TCU_TECR_TCCL4 BIT(4)
71#define TCU_TECR_TCCL3 BIT(3)
72#define TCU_TECR_TCCL2 BIT(2)
73#define TCU_TECR_TCCL1 BIT(1)
74#define TCU_TECR_TCCL0 BIT(0)
75
76#define TCU_TFR_HFLAG5 BIT(21)
77#define TCU_TFR_HFLAG4 BIT(20)
78#define TCU_TFR_HFLAG3 BIT(19)
79#define TCU_TFR_HFLAG2 BIT(18)
80#define TCU_TFR_HFLAG1 BIT(17)
81#define TCU_TFR_HFLAG0 BIT(16)
82#define TCU_TFR_FFLAG5 BIT(5)
83#define TCU_TFR_FFLAG4 BIT(4)
84#define TCU_TFR_FFLAG3 BIT(3)
85#define TCU_TFR_FFLAG2 BIT(2)
86#define TCU_TFR_FFLAG1 BIT(1)
87#define TCU_TFR_FFLAG0 BIT(0)
88
89#define TCU_TFSR_HFLAG5 BIT(21)
90#define TCU_TFSR_HFLAG4 BIT(20)
91#define TCU_TFSR_HFLAG3 BIT(19)
92#define TCU_TFSR_HFLAG2 BIT(18)
93#define TCU_TFSR_HFLAG1 BIT(17)
94#define TCU_TFSR_HFLAG0 BIT(16)
95#define TCU_TFSR_FFLAG5 BIT(5)
96#define TCU_TFSR_FFLAG4 BIT(4)
97#define TCU_TFSR_FFLAG3 BIT(3)
98#define TCU_TFSR_FFLAG2 BIT(2)
99#define TCU_TFSR_FFLAG1 BIT(1)
100#define TCU_TFSR_FFLAG0 BIT(0)
101
102#define TCU_TFCR_HFLAG5 BIT(21)
103#define TCU_TFCR_HFLAG4 BIT(20)
104#define TCU_TFCR_HFLAG3 BIT(19)
105#define TCU_TFCR_HFLAG2 BIT(18)
106#define TCU_TFCR_HFLAG1 BIT(17)
107#define TCU_TFCR_HFLAG0 BIT(16)
108#define TCU_TFCR_FFLAG5 BIT(5)
109#define TCU_TFCR_FFLAG4 BIT(4)
110#define TCU_TFCR_FFLAG3 BIT(3)
111#define TCU_TFCR_FFLAG2 BIT(2)
112#define TCU_TFCR_FFLAG1 BIT(1)
113#define TCU_TFCR_FFLAG0 BIT(0)
114
115#define TCU_TMR_HMASK5 BIT(21)
116#define TCU_TMR_HMASK4 BIT(20)
117#define TCU_TMR_HMASK3 BIT(19)
118#define TCU_TMR_HMASK2 BIT(18)
119#define TCU_TMR_HMASK1 BIT(17)
120#define TCU_TMR_HMASK0 BIT(16)
121#define TCU_TMR_FMASK5 BIT(5)
122#define TCU_TMR_FMASK4 BIT(4)
123#define TCU_TMR_FMASK3 BIT(3)
124#define TCU_TMR_FMASK2 BIT(2)
125#define TCU_TMR_FMASK1 BIT(1)
126#define TCU_TMR_FMASK0 BIT(0)
127
128#define TCU_TMSR_HMST5 BIT(21)
129#define TCU_TMSR_HMST4 BIT(20)
130#define TCU_TMSR_HMST3 BIT(19)
131#define TCU_TMSR_HMST2 BIT(18)
132#define TCU_TMSR_HMST1 BIT(17)
133#define TCU_TMSR_HMST0 BIT(16)
134#define TCU_TMSR_FMST5 BIT(5)
135#define TCU_TMSR_FMST4 BIT(4)
136#define TCU_TMSR_FMST3 BIT(3)
137#define TCU_TMSR_FMST2 BIT(2)
138#define TCU_TMSR_FMST1 BIT(1)
139#define TCU_TMSR_FMST0 BIT(0)
140
141#define TCU_TMCR_HMCL5 BIT(21)
142#define TCU_TMCR_HMCL4 BIT(20)
143#define TCU_TMCR_HMCL3 BIT(19)
144#define TCU_TMCR_HMCL2 BIT(18)
145#define TCU_TMCR_HMCL1 BIT(17)
146#define TCU_TMCR_HMCL0 BIT(16)
147#define TCU_TMCR_FMCL5 BIT(5)
148#define TCU_TMCR_FMCL4 BIT(4)
149#define TCU_TMCR_FMCL3 BIT(3)
150#define TCU_TMCR_FMCL2 BIT(2)
151#define TCU_TMCR_FMCL1 BIT(1)
152#define TCU_TMCR_FMCL0 BIT(0)
153
154#define TCU_TSR_WDTS BIT(16)
155#define TCU_TSR_STOP5 BIT(5)
156#define TCU_TSR_STOP4 BIT(4)
157#define TCU_TSR_STOP3 BIT(3)
158#define TCU_TSR_STOP2 BIT(2)
159#define TCU_TSR_STOP1 BIT(1)
160#define TCU_TSR_STOP0 BIT(0)
161
162#define TCU_TSSR_WDTSS BIT(16)
163#define TCU_TSSR_STPS5 BIT(5)
164#define TCU_TSSR_STPS4 BIT(4)
165#define TCU_TSSR_STPS3 BIT(3)
166#define TCU_TSSR_STPS2 BIT(2)
167#define TCU_TSSR_STPS1 BIT(1)
168#define TCU_TSSR_STPS0 BIT(0)
169
170#define TCU_TSSR_WDTSC BIT(16)
171#define TCU_TSSR_STPC5 BIT(5)
172#define TCU_TSSR_STPC4 BIT(4)
173#define TCU_TSSR_STPC3 BIT(3)
174#define TCU_TSSR_STPC2 BIT(2)
175#define TCU_TSSR_STPC1 BIT(1)
176#define TCU_TSSR_STPC0 BIT(0)
177
178#define TER_OSTEN BIT(15)
179
180#define OSTCSR_CNT_MD BIT(15)
181#define OSTCSR_SD BIT(9)
182#define OSTCSR_PRESCALE_16 (0x2 << 3)
183#define OSTCSR_EXT_EN BIT(2)
184
185int timer_init(void)
186{
187 void __iomem *regs = (void __iomem *)TCU_BASE;
188
189 writel(OSTCSR_SD, regs + TCU_OSTCSR);
190 reset_timer();
191 writel(OSTCSR_CNT_MD | OSTCSR_EXT_EN | OSTCSR_PRESCALE_16,
192 regs + TCU_OSTCSR);
193 writew(TER_OSTEN, regs + TCU_TESR);
194 return 0;
195}
196
197void reset_timer(void)
198{
199 void __iomem *regs = (void __iomem *)TCU_BASE;
200
201 writel(0, regs + TCU_OSTCNTH);
202 writel(0, regs + TCU_OSTCNTL);
203}
204
205static u64 get_timer64(void)
206{
207 void __iomem *regs = (void __iomem *)TCU_BASE;
208 u32 low = readl(regs + TCU_OSTCNTL);
209 u32 high = readl(regs + TCU_OSTCNTHBUF);
210
211 return ((u64)high << 32) | low;
212}
213
214ulong get_timer(ulong base)
215{
216 return lldiv(get_timer64(), 3000) - base;
217}
218
219void __udelay(unsigned long usec)
220{
221 /* OST count increments at 3MHz */
222 u64 end = get_timer64() + ((u64)usec * 3);
223
224 while (get_timer64() < end)
225 ;
226}
227
228unsigned long long get_ticks(void)
229{
230 return get_timer64();
231}
232
233void jz4780_tcu_wdt_start(void)
234{
235 void __iomem *tcu_regs = (void __iomem *)TCU_BASE;
236
237 /* Enable WDT clock */
238 writel(TCU_TSSR_WDTSC, tcu_regs + TCU_TSCR);
239}
diff --git a/arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds b/arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
new file mode 100644
index 0000000000..347cabc450
--- /dev/null
+++ b/arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
@@ -0,0 +1,50 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2
3MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
4 LENGTH = CONFIG_SPL_MAX_SIZE }
5MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
6 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
7
8OUTPUT_ARCH(mips)
9ENTRY(_start)
10SECTIONS
11{
12 .text :
13 {
14 __image_copy_start = .;
15 arch/mips/mach-jz47xx/start.o (.text*)
16 *(.text*)
17 } >.sram
18
19 . = ALIGN(4);
20 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
21
22 . = ALIGN(4);
23 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
24
25 . = ALIGN(4);
26 __image_copy_end = .;
27
28 .bss : {
29 . = ALIGN(4);
30 __bss_start = .;
31 *(.sbss.*)
32 *(.bss.*)
33 *(COMMON)
34 . = ALIGN(4);
35 __bss_end = .;
36 } >.sdram
37
38 /DISCARD/ : {
39 *(.dynbss)
40 *(.dynstr)
41 *(.dynamic)
42 *(.interp)
43 *(.hash)
44 *(.gnu.*)
45 *(.plt)
46 *(.got.plt)
47 *(.rel.plt)
48 *(.rel.dyn)
49 }
50}
diff --git a/arch/mips/mach-jz47xx/start.S b/arch/mips/mach-jz47xx/start.S
new file mode 100644
index 0000000000..760d021549
--- /dev/null
+++ b/arch/mips/mach-jz47xx/start.S
@@ -0,0 +1,98 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Startup Code for MIPS32 XBURST CPU-core
4 *
5 * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
6 */
7
8#include <config.h>
9#include <asm/regdef.h>
10#include <asm/mipsregs.h>
11#include <asm/addrspace.h>
12#include <asm/cacheops.h>
13#include <asm/cache.h>
14#include <mach/jz4780.h>
15
16 .set noreorder
17
18 .globl _start
19 .text
20_start:
21#ifdef CONFIG_SPL_BUILD
22
23 /* magic value ("MSPL") */
24 .word 0x4d53504c
25
26 /* Invalidate BTB */
27 mfc0 t0, CP0_CONFIG, 7
28 nop
29 ori t0, 2
30 mtc0 t0, CP0_CONFIG, 7
31 nop
32
33 /*
34 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
35 */
36 li t0, 0x0040FC04
37 mtc0 t0, CP0_STATUS
38
39 /* CAUSE register */
40 /* IV=1, use the specical interrupt vector (0x200) */
41 li t1, 0x00800000
42 mtc0 t1, CP0_CAUSE
43
44#ifdef CONFIG_SOC_JZ4780
45 /* enable bridge radical mode */
46 la t0, CPM_BASE
47 lw t1, 0x24(t0)
48 ori t1, t1, 0x22
49 sw t1, 0x24(t0)
50#endif
51
52 /* Set up stack */
53 li sp, CONFIG_SPL_STACK
54
55 b board_init_f
56 nop
57
58#ifdef CONFIG_SOC_JZ4780
59
60 .globl enable_caches
61 .ent enable_caches
62enable_caches:
63 mtc0 zero, CP0_TAGLO
64 mtc0 zero, CP0_TAGHI
65
66 li t0, KSEG0
67 addu t1, t0, CONFIG_SYS_DCACHE_SIZE
681:
69 cache INDEX_STORE_TAG_D, 0(t0)
70 bne t0, t1, 1b
71 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
72
73 li t0, KSEG0
74 addu t1, t0, CONFIG_SYS_ICACHE_SIZE
752:
76 cache INDEX_STORE_TAG_I, 0(t0)
77 bne t0, t1, 2b
78 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
79
80 /* Invalidate BTB */
81 mfc0 t0, CP0_CONFIG, 7
82 nop
83 ori t0, 2
84 mtc0 t0, CP0_CONFIG, 7
85 nop
86
87 /* Enable caches */
88 li t0, CONF_CM_CACHABLE_NONCOHERENT
89 mtc0 t0, CP0_CONFIG
90 nop
91
92 jr ra
93 nop
94
95 .end enable_caches
96
97#endif /* CONFIG_SOC_JZ4780 */
98#endif /* !CONFIG_SPL_BUILD */
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
new file mode 100644
index 0000000000..0e35b77c9d
--- /dev/null
+++ b/arch/mips/mach-mscc/Kconfig
@@ -0,0 +1,86 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3menu "MSCC VCore-III platforms"
4 depends on ARCH_MSCC
5
6config SOC_VCOREIII
7 select MIPS_TUNE_24KC
8 select ROM_EXCEPTION_VECTORS
9 select SUPPORTS_BIG_ENDIAN
10 select SUPPORTS_CPU_MIPS32_R1
11 select SUPPORTS_CPU_MIPS32_R2
12 select SUPPORTS_LITTLE_ENDIAN
13 bool
14
15config SYS_SOC
16 default "mscc"
17
18config SOC_OCELOT
19 bool
20 select SOC_VCOREIII
21 help
22 This supports MSCC Ocelot family of SOCs.
23
24config SOC_LUTON
25 bool
26 select SOC_VCOREIII
27 help
28 This supports MSCC Luton family of SOCs.
29
30config SYS_CONFIG_NAME
31 default "vcoreiii"
32
33choice
34 prompt "Board select"
35
36config TARGET_OCELOT_PCB120
37 bool "MSCC PCB120 Reference Board (aka VSC5635EV)"
38 select SOC_OCELOT
39 help
40 When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
41 ocelot_pcb120
42
43config TARGET_OCELOT_PCB123
44 bool "MSCC PCB123 Reference Board (aka VSC7514EV))"
45 select SOC_OCELOT
46 help
47 When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
48 ocelot_pcb123
49
50config TARGET_LUTON_PCB091
51 bool "MSCC PCB091 Reference Board"
52 select SOC_LUTON
53 select MSCC_BITBANG_SPI_GPIO
54 help
55 When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
56 luton_pcb091
57endchoice
58
59choice
60 prompt "DDR type"
61
62config DDRTYPE_H5TQ4G63MFR
63 bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
64
65config DDRTYPE_MT41K256M16
66 bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)"
67
68config DDRTYPE_H5TQ1G63BFA
69 bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
70
71config DDRTYPE_MT41J128M16HA
72 bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
73
74config DDRTYPE_MT41K128M16JT
75 bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)"
76
77config DDRTYPE_MT47H128M8HQ
78 bool "Micron MT47H128M8-3 (1Gbit, DDR-533@CL4 @ 4.80ns 16Mbisx8x8)"
79
80endchoice
81
82source "board/mscc/ocelot/Kconfig"
83
84source "board/mscc/luton/Kconfig"
85
86endmenu
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
new file mode 100644
index 0000000000..6c60f26ca4
--- /dev/null
+++ b/arch/mips/mach-mscc/Makefile
@@ -0,0 +1,6 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3CFLAGS_cpu.o += -finline-limit=64000
4
5obj-y += cpu.o dram.o reset.o lowlevel_init.o
6obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
new file mode 100644
index 0000000000..5be8ff69d5
--- /dev/null
+++ b/arch/mips/mach-mscc/cpu.c
@@ -0,0 +1,102 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
7
8#include <asm/io.h>
9#include <asm/types.h>
10
11#include <mach/tlb.h>
12#include <mach/ddr.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
17#define MSCC_RAM_TLB_SIZE SZ_64M
18#define MSCC_ATTRIB2 MMU_REGIO_INVAL
19#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
20#define MSCC_RAM_TLB_SIZE SZ_64M
21#define MSCC_ATTRIB2 MMU_REGIO_RW
22#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
23#define MSCC_RAM_TLB_SIZE SZ_256M
24#define MSCC_ATTRIB2 MMU_REGIO_INVAL
25#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
26#define MSCC_RAM_TLB_SIZE SZ_256M
27#define MSCC_ATTRIB2 MMU_REGIO_RW
28#else
29#define MSCC_RAM_TLB_SIZE SZ_512M
30#define MSCC_ATTRIB2 MMU_REGIO_RW
31#endif
32
33/* NOTE: lowlevel_init() function does not have access to the
34 * stack. Thus, all called functions must be inlined, and (any) local
35 * variables must be kept in registers.
36 */
37void vcoreiii_tlb_init(void)
38{
39 register int tlbix = 0;
40
41 /*
42 * Unlike most of the MIPS based SoCs, the IO register address
43 * are not in KSEG0. The mainline linux kernel built in legacy
44 * mode needs to access some of the registers very early in
45 * the boot and make the assumption that the bootloader has
46 * already configured them, so we have to match this
47 * expectation.
48 */
49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
50 MMU_REGIO_RW);
51#ifdef CONFIG_SOC_LUTON
52 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
53 MMU_REGIO_RW);
54#endif
55
56#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
57 /*
58 * If U-Boot is located in NOR then we want to be able to use
59 * the data cache in order to boot in a decent duration
60 */
61 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C,
62 MMU_REGIO_RO_C);
63 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C,
64 MMU_REGIO_RO_C);
65
66 /*
67 * Using cache for RAM also helps to improve boot time. Thanks
68 * to this the time to relocate U-Boot in RAM went from 2.092
69 * secs to 0.104 secs.
70 */
71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW,
72 MSCC_ATTRIB2);
73
74 /* Enable caches by clearing the bit ERL, which is set on reset */
75 write_c0_status(read_c0_status() & ~BIT(2));
76#endif /* CONFIG_SYS_TEXT_BASE */
77}
78
79int mach_cpu_init(void)
80{
81 /* Speed up NOR flash access */
82#ifdef CONFIG_SOC_LUTON
83 writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
84 ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG);
85
86 writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
87 ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
88 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
89#else
90 writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
91 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
92 /*
93 * Legacy and mainline linux kernel expect that the
94 * interruption map was set as it was done by redboot.
95 */
96 writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0));
97 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1));
98 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2));
99 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3));
100#endif
101 return 0;
102}
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
new file mode 100644
index 0000000000..309007c14e
--- /dev/null
+++ b/arch/mips/mach-mscc/dram.c
@@ -0,0 +1,73 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
7
8#include <asm/io.h>
9#include <asm/types.h>
10
11#include <mach/tlb.h>
12#include <mach/ddr.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16static inline int vcoreiii_train_bytelane(void)
17{
18 int ret;
19
20 ret = hal_vcoreiii_train_bytelane(0);
21
22#ifdef CONFIG_SOC_OCELOT
23 if (ret)
24 return ret;
25 ret = hal_vcoreiii_train_bytelane(1);
26#endif
27
28 return ret;
29}
30
31int vcoreiii_ddr_init(void)
32{
33 int res;
34
35 if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
36 & ICPU_MEMCTRL_STAT_INIT_DONE)) {
37 hal_vcoreiii_init_memctl();
38 hal_vcoreiii_wait_memctl();
39 if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
40 hal_vcoreiii_ddr_failed();
41 }
42#if (CONFIG_SYS_TEXT_BASE != 0x20000000)
43 res = dram_check();
44 if (res == 0)
45 hal_vcoreiii_ddr_verified();
46 else
47 hal_vcoreiii_ddr_failed();
48
49 /* Clear boot-mode and read-back to activate/verify */
50 clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
51 ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
52 readl(BASE_CFG + ICPU_GENERAL_CTRL);
53#else
54 res = 0;
55#endif
56 return res;
57}
58
59int print_cpuinfo(void)
60{
61 printf("MSCC VCore-III MIPS 24Kec\n");
62
63 return 0;
64}
65
66int dram_init(void)
67{
68 while (vcoreiii_ddr_init())
69 ;
70
71 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
72 return 0;
73}
diff --git a/arch/mips/mach-mscc/include/ioremap.h b/arch/mips/mach-mscc/include/ioremap.h
new file mode 100644
index 0000000000..9024364a57
--- /dev/null
+++ b/arch/mips/mach-mscc/include/ioremap.h
@@ -0,0 +1,49 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __ASM_MACH_MSCC_IOREMAP_H
7#define __ASM_MACH_MSCC_IOREMAP_H
8
9#include <linux/types.h>
10#include <mach/common.h>
11
12/*
13 * Allow physical addresses to be fixed up to help peripherals located
14 * outside the low 32-bit range -- generic pass-through version.
15 */
16static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
17 phys_addr_t size)
18{
19 return phys_addr;
20}
21
22static inline int is_vcoreiii_internal_registers(phys_addr_t offset)
23{
24 if ((offset >= MSCC_IO_ORIGIN1_OFFSET &&
25 offset < (MSCC_IO_ORIGIN1_OFFSET + MSCC_IO_ORIGIN1_SIZE)) ||
26 (offset >= MSCC_IO_ORIGIN2_OFFSET &&
27 offset < (MSCC_IO_ORIGIN2_OFFSET + MSCC_IO_ORIGIN2_SIZE)))
28 return 1;
29
30 return 0;
31}
32
33static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
34 unsigned long flags)
35{
36 if (is_vcoreiii_internal_registers(offset))
37 return (void __iomem *)offset;
38
39 return NULL;
40}
41
42static inline int plat_iounmap(const volatile void __iomem *addr)
43{
44 return is_vcoreiii_internal_registers((unsigned long)addr);
45}
46
47#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
48
49#endif /* __ASM_MACH_MSCC_IOREMAP_H */
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
new file mode 100644
index 0000000000..931ecd7985
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -0,0 +1,28 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __ASM_MACH_COMMON_H
7#define __ASM_MACH_COMMON_H
8
9#if defined(CONFIG_SOC_OCELOT)
10#include <mach/ocelot/ocelot.h>
11#include <mach/ocelot/ocelot_devcpu_gcb.h>
12#include <mach/ocelot/ocelot_icpu_cfg.h>
13#elif defined(CONFIG_SOC_LUTON)
14#include <mach/luton/luton.h>
15#include <mach/luton/luton_devcpu_gcb.h>
16#include <mach/luton/luton_icpu_cfg.h>
17#else
18#error Unsupported platform
19#endif
20
21#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
22#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
23#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
24#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
25
26#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
27
28#endif /* __ASM_MACH_COMMON_H */
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
new file mode 100644
index 0000000000..f445e63a35
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -0,0 +1,814 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __ASM_MACH_DDR_H
7#define __ASM_MACH_DDR_H
8
9#include <asm/cacheops.h>
10#include <asm/io.h>
11#include <asm/reboot.h>
12#include <mach/common.h>
13
14#define MIPS_VCOREIII_MEMORY_DDR3
15#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE
16
17#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */
18
19/* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */
20#define VC3_MPAR_bank_addr_cnt 3
21#define VC3_MPAR_row_addr_cnt 13
22#define VC3_MPAR_col_addr_cnt 10
23#define VC3_MPAR_tREFI 2437
24#define VC3_MPAR_tRAS_min 12
25#define VC3_MPAR_CL 6
26#define VC3_MPAR_tWTR 4
27#define VC3_MPAR_tRC 16
28#define VC3_MPR_tFAW 16
29#define VC3_MPAR_tRP 5
30#define VC3_MPAR_tRRD 4
31#define VC3_MPAR_tRCD 5
32#define VC3_MPAR_tMRD 4
33#define VC3_MPAR_tRFC 35
34#define VC3_MPAR_CWL 5
35#define VC3_MPAR_tXPR 38
36#define VC3_MPAR_tMOD 12
37#define VC3_MPAR_tDLLK 512
38#define VC3_MPAR_tWR 5
39
40#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) /* Validation board */
41
42/* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */
43#define VC3_MPAR_bank_addr_cnt 3
44#define VC3_MPAR_row_addr_cnt 14
45#define VC3_MPAR_col_addr_cnt 10
46#define VC3_MPAR_tREFI 2437
47#define VC3_MPAR_tRAS_min 12
48#define VC3_MPAR_CL 5
49#define VC3_MPAR_tWTR 4
50#define VC3_MPAR_tRC 16
51#define VC3_MPAR_tFAW 16
52#define VC3_MPAR_tRP 5
53#define VC3_MPAR_tRRD 4
54#define VC3_MPAR_tRCD 5
55#define VC3_MPAR_tMRD 4
56#define VC3_MPAR_tRFC 50
57#define VC3_MPAR_CWL 5
58#define VC3_MPAR_tXPR 54
59#define VC3_MPAR_tMOD 12
60#define VC3_MPAR_tDLLK 512
61#define VC3_MPAR_tWR 5
62
63#elif defined(CONFIG_DDRTYPE_MT41K256M16) /* JR2 Validation board */
64
65/* Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16) @ 3.20ns */
66#define VC3_MPAR_bank_addr_cnt 3
67#define VC3_MPAR_row_addr_cnt 15
68#define VC3_MPAR_col_addr_cnt 10
69#define VC3_MPAR_tREFI 2437
70#define VC3_MPAR_tRAS_min 12
71#define VC3_MPAR_CL 5
72#define VC3_MPAR_tWTR 4
73#define VC3_MPAR_tRC 16
74#define VC3_MPAR_tFAW 16
75#define VC3_MPAR_tRP 5
76#define VC3_MPAR_tRRD 4
77#define VC3_MPAR_tRCD 5
78#define VC3_MPAR_tMRD 4
79#define VC3_MPAR_tRFC 82
80#define VC3_MPAR_CWL 5
81#define VC3_MPAR_tXPR 85
82#define VC3_MPAR_tMOD 12
83#define VC3_MPAR_tDLLK 512
84#define VC3_MPAR_tWR 5
85
86#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) /* JR2 Reference board */
87
88/* Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16) - 2kb pages @ 3.20ns */
89#define VC3_MPAR_bank_addr_cnt 3
90#define VC3_MPAR_row_addr_cnt 15
91#define VC3_MPAR_col_addr_cnt 10
92#define VC3_MPAR_tREFI 2437
93#define VC3_MPAR_tRAS_min 12
94#define VC3_MPAR_CL 6
95#define VC3_MPAR_tWTR 4
96#define VC3_MPAR_tRC 17
97#define VC3_MPAR_tFAW 16
98#define VC3_MPAR_tRP 5
99#define VC3_MPAR_tRRD 4
100#define VC3_MPAR_tRCD 5
101#define VC3_MPAR_tMRD 4
102#define VC3_MPAR_tRFC 82
103#define VC3_MPAR_CWL 5
104#define VC3_MPAR_tXPR 85
105#define VC3_MPAR_tMOD 12
106#define VC3_MPAR_tDLLK 512
107#define VC3_MPAR_tWR 5
108
109#elif defined(CONFIG_DDRTYPE_MT41K128M16JT)
110
111/* Micron Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16) @ 3.20ns */
112#define VC3_MPAR_bank_addr_cnt 3
113#define VC3_MPAR_row_addr_cnt 14
114#define VC3_MPAR_col_addr_cnt 10
115#define VC3_MPAR_tREFI 2437
116#define VC3_MPAR_tRAS_min 12
117#define VC3_MPAR_CL 6
118#define VC3_MPAR_tWTR 4
119#define VC3_MPAR_tRC 16
120#define VC3_MPAR_tFAW 16
121#define VC3_MPAR_tRP 5
122#define VC3_MPAR_tRRD 4
123#define VC3_MPAR_tRCD 5
124#define VC3_MPAR_tMRD 4
125#define VC3_MPAR_tRFC 82
126#define VC3_MPAR_CWL 5
127#define VC3_MPAR_tXPR 85
128#define VC3_MPAR_tMOD 12
129#define VC3_MPAR_tDLLK 512
130#define VC3_MPAR_tWR 5
131
132#elif defined(CONFIG_DDRTYPE_MT47H128M8HQ) /* Luton10/26 Refboards */
133
134/* Micron 1Gb MT47H128M8-3 16Meg x 8 x 8 banks, DDR-533@CL4 @ 4.80ns */
135#define VC3_MPAR_bank_addr_cnt 3
136#define VC3_MPAR_row_addr_cnt 14
137#define VC3_MPAR_col_addr_cnt 10
138#define VC3_MPAR_tREFI 1625
139#define VC3_MPAR_tRAS_min 9
140#define VC3_MPAR_CL 4
141#define VC3_MPAR_tWTR 2
142#define VC3_MPAR_tRC 12
143#define VC3_MPAR_tFAW 8
144#define VC3_MPAR_tRP 4
145#define VC3_MPAR_tRRD 2
146#define VC3_MPAR_tRCD 4
147
148#define VC3_MPAR_tRPA 4
149#define VC3_MPAR_tRP 4
150
151#define VC3_MPAR_tMRD 2
152#define VC3_MPAR_tRFC 27
153
154#define VC3_MPAR__400_ns_dly 84
155
156#define VC3_MPAR_tWR 4
157#undef MIPS_VCOREIII_MEMORY_DDR3
158#else
159
160#error Unknown DDR system configuration - please add!
161
162#endif
163
164#ifdef CONFIG_SOC_OCELOT
165#define MIPS_VCOREIII_MEMORY_16BIT 1
166#endif
167
168#define MIPS_VCOREIII_MEMORY_SSTL_ODT 7
169#define MIPS_VCOREIII_MEMORY_SSTL_DRIVE 7
170#define VCOREIII_DDR_DQS_MODE_CALIBRATE
171
172#ifdef MIPS_VCOREIII_MEMORY_16BIT
173#define VC3_MPAR_16BIT 1
174#else
175#define VC3_MPAR_16BIT 0
176#endif
177
178#ifdef MIPS_VCOREIII_MEMORY_DDR3
179#define VC3_MPAR_DDR3_MODE 1 /* DDR3 */
180#define VC3_MPAR_BURST_LENGTH 8 /* Always 8 (1) for DDR3 */
181#ifdef MIPS_VCOREIII_MEMORY_16BIT
182#define VC3_MPAR_BURST_SIZE 1 /* Always 1 for DDR3/16bit */
183#else
184#define VC3_MPAR_BURST_SIZE 0
185#endif
186#else
187#define VC3_MPAR_DDR3_MODE 0 /* DDR2 */
188#ifdef MIPS_VCOREIII_MEMORY_16BIT
189#define VC3_MPAR_BURST_LENGTH 4 /* in DDR2 16-bit mode, use burstlen 4 */
190#else
191#define VC3_MPAR_BURST_LENGTH 8 /* For 8-bit IF we must run burst-8 */
192#endif
193#define VC3_MPAR_BURST_SIZE 0 /* Always 0 for DDR2 */
194#endif
195
196#define VC3_MPAR_RL VC3_MPAR_CL
197#if !defined(MIPS_VCOREIII_MEMORY_DDR3)
198#define VC3_MPAR_WL (VC3_MPAR_RL - 1)
199#define VC3_MPAR_MD VC3_MPAR_tMRD
200#define VC3_MPAR_ID VC3_MPAR__400_ns_dly
201#define VC3_MPAR_SD VC3_MPAR_tXSRD
202#define VC3_MPAR_OW (VC3_MPAR_WL - 2)
203#define VC3_MPAR_OR (VC3_MPAR_WL - 3)
204#define VC3_MPAR_RP (VC3_MPAR_bank_addr_cnt < 3 ? VC3_MPAR_tRP : VC3_MPAR_tRPA)
205#define VC3_MPAR_FAW (VC3_MPAR_bank_addr_cnt < 3 ? 1 : VC3_MPAR_tFAW)
206#define VC3_MPAR_BL (VC3_MPAR_BURST_LENGTH == 4 ? 2 : 4)
207#define MSCC_MEMPARM_MR0 \
208 (VC3_MPAR_BURST_LENGTH == 8 ? 3 : 2) | (VC3_MPAR_CL << 4) | \
209 ((VC3_MPAR_tWR - 1) << 9)
210/* DLL-on, Full-OD, AL=0, RTT=off, nDQS-on, RDQS-off, out-en */
211#define MSCC_MEMPARM_MR1 0x382
212#define MSCC_MEMPARM_MR2 0
213#define MSCC_MEMPARM_MR3 0
214#else
215#define VC3_MPAR_WL VC3_MPAR_CWL
216#define VC3_MPAR_MD VC3_MPAR_tMOD
217#define VC3_MPAR_ID VC3_MPAR_tXPR
218#define VC3_MPAR_SD VC3_MPAR_tDLLK
219#define VC3_MPAR_OW 2
220#define VC3_MPAR_OR 2
221#define VC3_MPAR_RP VC3_MPAR_tRP
222#define VC3_MPAR_FAW VC3_MPAR_tFAW
223#define VC3_MPAR_BL 4
224#define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9)
225/* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */
226#define MSCC_MEMPARM_MR1 0x0040
227#define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3)
228#define MSCC_MEMPARM_MR3 0
229#endif /* MIPS_VCOREIII_MEMORY_DDR3 */
230
231#define MSCC_MEMPARM_MEMCFG \
232 ((MIPS_VCOREIII_DDR_SIZE > SZ_512M) ? \
233 ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS : 0) | \
234 (VC3_MPAR_16BIT ? ICPU_MEMCTRL_CFG_DDR_WIDTH : 0) | \
235 (VC3_MPAR_DDR3_MODE ? ICPU_MEMCTRL_CFG_DDR_MODE : 0) | \
236 (VC3_MPAR_BURST_SIZE ? ICPU_MEMCTRL_CFG_BURST_SIZE : 0) | \
237 (VC3_MPAR_BURST_LENGTH == 8 ? ICPU_MEMCTRL_CFG_BURST_LEN : 0) | \
238 (VC3_MPAR_bank_addr_cnt == 3 ? ICPU_MEMCTRL_CFG_BANK_CNT : 0) | \
239 ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \
240 ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
241
242#ifdef CONFIG_SOC_OCELOT
243#define MSCC_MEMPARM_PERIOD \
244 ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
245 ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
246
247#define MSCC_MEMPARM_TIMING0 \
248 ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL + VC3_MPAR_BL + 1 - \
249 VC3_MPAR_WL) | \
250 ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(VC3_MPAR_BL - 1) | \
251 ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(VC3_MPAR_BL) | \
252 ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \
253 ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_WL + \
254 VC3_MPAR_BL + \
255 VC3_MPAR_tWR - 1) | \
256 ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BL - 1) | \
257 ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_WL - 1) | \
258 ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_RL - 3)
259
260#define MSCC_MEMPARM_TIMING1 \
261 ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
262 ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_FAW - 1) | \
263 ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_RP - 1) | \
264 ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
265 ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \
266 ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_WL + \
267 VC3_MPAR_BL + \
268 VC3_MPAR_tWTR - 1)
269
270#define MSCC_MEMPARM_TIMING2 \
271 ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_RP - 1) | \
272 ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_MD - 1) | \
273 ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \
274 ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID - 1)
275
276#define MSCC_MEMPARM_TIMING3 \
277 ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_WL + \
278 VC3_MPAR_tWTR - 1) |\
279 ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(VC3_MPAR_OR - 1) | \
280 ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_OW - 1) | \
281 ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_RL - 3)
282
283#else
284#define MSCC_MEMPARM_PERIOD \
285 ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(1) | \
286 ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
287
288#define MSCC_MEMPARM_TIMING0 \
289 ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \
290 ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_CL + \
291 (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
292 VC3_MPAR_tWR) | \
293 ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BURST_LENGTH == 8 ? 3 : 1) | \
294 ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_CL - 3) | \
295 ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_CL - 3)
296
297#define MSCC_MEMPARM_TIMING1 \
298 ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
299 ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_tFAW - 1) | \
300 ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_tRP - 1) | \
301 ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
302 ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \
303 ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL + \
304 (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
305 VC3_MPAR_tWTR)
306#define MSCC_MEMPARM_TIMING2 \
307 ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_tRPA - 1) | \
308 ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_tMRD - 1) | \
309 ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \
310 ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(VC3_MPAR__400_ns_dly)
311
312#define MSCC_MEMPARM_TIMING3 \
313 ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_CL - 1) | \
314 ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_CL - 1) | \
315 ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_CL - 1)
316
317#endif
318
319enum {
320 DDR_TRAIN_OK,
321 DDR_TRAIN_CONTINUE,
322 DDR_TRAIN_ERROR,
323};
324
325/*
326 * We actually have very few 'pause' possibilities apart from
327 * these assembly nops (at this very early stage).
328 */
329#define PAUSE() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop")
330
331/* NB: Assumes inlining as no stack is available! */
332static inline void set_dly(u32 bytelane, u32 dly)
333{
334 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
335
336 r &= ~ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M;
337 r |= ICPU_MEMCTRL_DQS_DLY_DQS_DLY(dly);
338 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
339}
340
341static inline bool incr_dly(u32 bytelane)
342{
343 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
344
345 if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
346 writel(r + 1, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
347 return true;
348 }
349
350 return false;
351}
352
353static inline bool adjust_dly(int adjust)
354{
355 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0));
356
357 if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
358 writel(r + adjust, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0));
359 return true;
360 }
361
362 return false;
363}
364
365/* NB: Assumes inlining as no stack is available! */
366static inline void center_dly(u32 bytelane, u32 start)
367{
368 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)) - start;
369
370 writel(start + (r >> 1), BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
371}
372
373static inline void memphy_soft_reset(void)
374{
375 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST);
376 PAUSE();
377 clrbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST);
378 PAUSE();
379}
380
381#ifdef CONFIG_SOC_OCELOT
382static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
383
384static inline void sleep_100ns(u32 val)
385{
386 /* Set the timer tick generator to 100 ns */
387 writel(VCOREIII_TIMER_DIVIDER - 1, BASE_CFG + ICPU_TIMER_TICK_DIV);
388
389 /* Set the timer value */
390 writel(val, BASE_CFG + ICPU_TIMER_VALUE(0));
391
392 /* Enable timer 0 for one-shot */
393 writel(ICPU_TIMER_CTRL_ONE_SHOT_ENA | ICPU_TIMER_CTRL_TIMER_ENA,
394 BASE_CFG + ICPU_TIMER_CTRL(0));
395
396 /* Wait for timer 0 to reach 0 */
397 while (readl(BASE_CFG + ICPU_TIMER_VALUE(0)) != 0)
398 ;
399}
400
401static inline void hal_vcoreiii_ddr_reset_assert(void)
402{
403 /* DDR has reset pin on GPIO 19 toggle Low-High to release */
404 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
405 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
406 sleep_100ns(10000);
407}
408
409static inline void hal_vcoreiii_ddr_reset_release(void)
410{
411 /* DDR has reset pin on GPIO 19 toggle Low-High to release */
412 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
413 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
414 sleep_100ns(10000);
415}
416
417/*
418 * DDR memory sanity checking failed, tally and do hard reset
419 *
420 * NB: Assumes inlining as no stack is available!
421 */
422static inline void hal_vcoreiii_ddr_failed(void)
423{
424 register u32 reset;
425
426 writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
427
428 clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
429
430 /* We have to execute the reset function from cache. Indeed,
431 * the reboot workaround in _machine_restart() will change the
432 * SPI NOR into SW bitbang.
433 *
434 * This will render the CPU unable to execute directly from
435 * the NOR, which is why the reset instructions are prefetched
436 * into the I-cache.
437 *
438 * When failing the DDR initialization we are executing from
439 * NOR.
440 *
441 * The last instruction in _machine_restart() will reset the
442 * MIPS CPU (and the cache), and the CPU will start executing
443 * from the reset vector.
444 */
445 reset = KSEG0ADDR(_machine_restart);
446 icache_lock((void *)reset, 128);
447 asm volatile ("jr %0"::"r" (reset));
448
449 panic("DDR init failed\n");
450}
451
452/*
453 * DDR memory sanity checking done, possibly enable ECC.
454 *
455 * NB: Assumes inlining as no stack is available!
456 */
457static inline void hal_vcoreiii_ddr_verified(void)
458{
459#ifdef MIPS_VCOREIII_MEMORY_ECC
460 /* Finally, enable ECC */
461 register u32 val = readl(BASE_CFG + ICPU_MEMCTRL_CFG);
462
463 val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA;
464 val &= ~ICPU_MEMCTRL_CFG_BURST_SIZE;
465
466 writel(val, BASE_CFG + ICPU_MEMCTRL_CFG);
467#endif
468
469 /* Reset Status register - sticky bits */
470 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), BASE_CFG + ICPU_MEMCTRL_STAT);
471}
472
473/* NB: Assumes inlining as no stack is available! */
474static inline int look_for(u32 bytelane)
475{
476 register u32 i;
477
478 /* Reset FIFO in case any previous access failed */
479 for (i = 0; i < sizeof(training_data); i++) {
480 register u32 byte;
481
482 memphy_soft_reset();
483 /* Reset sticky bits */
484 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT),
485 BASE_CFG + ICPU_MEMCTRL_STAT);
486 /* Read data */
487 byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane +
488 (i * 4));
489
490 /*
491 * Prevent the compiler reordering the instruction so
492 * the read of RAM happens after the check of the
493 * errors.
494 */
495 rmb();
496 if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
497 (ICPU_MEMCTRL_STAT_RDATA_MASKED |
498 ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
499 /* Noise on the line */
500 goto read_error;
501 }
502 /* If mismatch, increment DQS - if possible */
503 if (byte != training_data[i]) {
504 read_error:
505 if (!incr_dly(bytelane))
506 return DDR_TRAIN_ERROR;
507 return DDR_TRAIN_CONTINUE;
508 }
509 }
510 return DDR_TRAIN_OK;
511}
512
513/* NB: Assumes inlining as no stack is available! */
514static inline int look_past(u32 bytelane)
515{
516 register u32 i;
517
518 /* Reset FIFO in case any previous access failed */
519 for (i = 0; i < sizeof(training_data); i++) {
520 register u32 byte;
521
522 memphy_soft_reset();
523 /* Ack sticky bits */
524 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT),
525 BASE_CFG + ICPU_MEMCTRL_STAT);
526 byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane +
527 (i * 4));
528 /*
529 * Prevent the compiler reordering the instruction so
530 * the read of RAM happens after the check of the
531 * errors.
532 */
533 rmb();
534 if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
535 (ICPU_MEMCTRL_STAT_RDATA_MASKED |
536 ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
537 /* Noise on the line */
538 goto read_error;
539 }
540 /* Bail out when we see first mismatch */
541 if (byte != training_data[i]) {
542 read_error:
543 return DDR_TRAIN_OK;
544 }
545 }
546 /* All data compares OK, increase DQS and retry */
547 if (!incr_dly(bytelane))
548 return DDR_TRAIN_ERROR;
549
550 return DDR_TRAIN_CONTINUE;
551}
552
553static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
554{
555 register int res;
556 register u32 dqs_s;
557
558 set_dly(bytelane, 0); /* Start training at DQS=0 */
559 while ((res = look_for(bytelane)) == DDR_TRAIN_CONTINUE)
560 ;
561 if (res != DDR_TRAIN_OK)
562 return res;
563
564 dqs_s = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
565 while ((res = look_past(bytelane)) == DDR_TRAIN_CONTINUE)
566 ;
567 if (res != DDR_TRAIN_OK)
568 return res;
569 /* Reset FIFO - for good measure */
570 memphy_soft_reset();
571 /* Adjust to center [dqs_s;cur] */
572 center_dly(bytelane, dqs_s);
573 return DDR_TRAIN_OK;
574}
575
576/* This algorithm is converted from the TCL training algorithm used
577 * during silicon simulation.
578 * NB: Assumes inlining as no stack is available!
579 */
580static inline int hal_vcoreiii_init_dqs(void)
581{
582#define MAX_DQS 32
583 register u32 i, j;
584
585 for (i = 0; i < MAX_DQS; i++) {
586 set_dly(0, i); /* Byte-lane 0 */
587 for (j = 0; j < MAX_DQS; j++) {
588 __maybe_unused register u32 byte;
589
590 set_dly(1, j); /* Byte-lane 1 */
591 /* Reset FIFO in case any previous access failed */
592 memphy_soft_reset();
593 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT),
594 BASE_CFG + ICPU_MEMCTRL_STAT);
595 byte = __raw_readb((void __iomem *)MSCC_DDR_TO);
596 byte = __raw_readb((void __iomem *)(MSCC_DDR_TO + 1));
597 if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
598 (ICPU_MEMCTRL_STAT_RDATA_MASKED |
599 ICPU_MEMCTRL_STAT_RDATA_DUMMY)))
600 return 0;
601 }
602 }
603 return -1;
604}
605
606static inline int dram_check(void)
607{
608 register u32 i;
609
610 for (i = 0; i < 8; i++) {
611 __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4)));
612 if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i)
613 return 1;
614 }
615 return 0;
616}
617#else /* Luton */
618
619static inline void sleep_100ns(u32 val)
620{
621}
622
623static inline void hal_vcoreiii_ddr_reset_assert(void)
624{
625 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_RST);
626 setbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE);
627}
628
629static inline void hal_vcoreiii_ddr_reset_release(void)
630{
631}
632
633static inline void hal_vcoreiii_ddr_failed(void)
634{
635 register u32 memphy_cfg = readl(BASE_CFG + ICPU_MEMPHY_CFG);
636
637 /* Do a fifo reset and start over */
638 writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST,
639 BASE_CFG + ICPU_MEMPHY_CFG);
640 writel(memphy_cfg & ~ICPU_MEMPHY_CFG_PHY_FIFO_RST,
641 BASE_CFG + ICPU_MEMPHY_CFG);
642 writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST,
643 BASE_CFG + ICPU_MEMPHY_CFG);
644}
645
646static inline void hal_vcoreiii_ddr_verified(void)
647{
648}
649
650static inline int look_for(u32 data)
651{
652 register u32 byte = __raw_readb((void __iomem *)MSCC_DDR_TO);
653
654 if (data != byte) {
655 if (!incr_dly(0))
656 return DDR_TRAIN_ERROR;
657 return DDR_TRAIN_CONTINUE;
658 }
659
660 return DDR_TRAIN_OK;
661}
662
663/* This algorithm is converted from the TCL training algorithm used
664 * during silicon simulation.
665 * NB: Assumes inlining as no stack is available!
666 */
667static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
668{
669 register int res;
670
671 set_dly(bytelane, 0); /* Start training at DQS=0 */
672 while ((res = look_for(0xff)) == DDR_TRAIN_CONTINUE)
673 ;
674 if (res != DDR_TRAIN_OK)
675 return res;
676
677 set_dly(bytelane, 0); /* Start training at DQS=0 */
678 while ((res = look_for(0x00)) == DDR_TRAIN_CONTINUE)
679
680 ;
681
682 if (res != DDR_TRAIN_OK)
683 return res;
684
685 adjust_dly(-3);
686
687 return DDR_TRAIN_OK;
688}
689
690static inline int hal_vcoreiii_init_dqs(void)
691{
692 return 0;
693}
694
695static inline int dram_check(void)
696{
697 register u32 i;
698
699 for (i = 0; i < 8; i++) {
700 __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4)));
701
702 if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i)
703 return 1;
704 }
705
706 return 0;
707}
708#endif
709
710/*
711 * NB: Called *early* to init memory controller - assumes inlining as
712 * no stack is available!
713 */
714static inline void hal_vcoreiii_init_memctl(void)
715{
716 /* Ensure DDR is in reset */
717 hal_vcoreiii_ddr_reset_assert();
718
719 /* Wait maybe not needed, but ... */
720 PAUSE();
721
722 /* Drop sys ctl memory controller forced reset */
723 clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE);
724
725 PAUSE();
726
727 /* Drop Reset, enable SSTL */
728 writel(ICPU_MEMPHY_CFG_PHY_SSTL_ENA, BASE_CFG + ICPU_MEMPHY_CFG);
729 PAUSE();
730
731 /* Start the automatic SSTL output and ODT drive-strength calibration */
732 writel(ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(MIPS_VCOREIII_MEMORY_SSTL_ODT) |
733 /* drive strength */
734 ICPU_MEMPHY_ZCAL_ZCAL_PROG(MIPS_VCOREIII_MEMORY_SSTL_DRIVE) |
735 /* Start calibration process */
736 ICPU_MEMPHY_ZCAL_ZCAL_ENA, BASE_CFG + ICPU_MEMPHY_ZCAL);
737
738 /* Wait for ZCAL to clear */
739 while (readl(BASE_CFG + ICPU_MEMPHY_ZCAL) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
740 ;
741#ifdef CONFIG_SOC_OCELOT
742 /* Check no ZCAL_ERR */
743 if (readl(BASE_CFG + ICPU_MEMPHY_ZCAL_STAT)
744 & ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
745 hal_vcoreiii_ddr_failed();
746#endif
747 /* Drive CL, CK, ODT */
748 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_ODT_OE |
749 ICPU_MEMPHY_CFG_PHY_CK_OE | ICPU_MEMPHY_CFG_PHY_CL_OE);
750
751 /* Initialize memory controller */
752 writel(MSCC_MEMPARM_MEMCFG, BASE_CFG + ICPU_MEMCTRL_CFG);
753 writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD);
754
755#ifdef CONFIG_SOC_OCELOT
756 writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0);
757#else /* Luton */
758 clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1));
759 setbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, MSCC_MEMPARM_TIMING0);
760#endif
761
762 writel(MSCC_MEMPARM_TIMING1, BASE_CFG + ICPU_MEMCTRL_TIMING1);
763 writel(MSCC_MEMPARM_TIMING2, BASE_CFG + ICPU_MEMCTRL_TIMING2);
764 writel(MSCC_MEMPARM_TIMING3, BASE_CFG + ICPU_MEMCTRL_TIMING3);
765 writel(MSCC_MEMPARM_MR0, BASE_CFG + ICPU_MEMCTRL_MR0_VAL);
766 writel(MSCC_MEMPARM_MR1, BASE_CFG + ICPU_MEMCTRL_MR1_VAL);
767 writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL);
768 writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL);
769
770#ifdef CONFIG_SOC_OCELOT
771 /* Termination setup - enable ODT */
772 writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
773 /* Assert ODT0 for any write */
774 ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
775 BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
776
777 /* Release Reset from DDR */
778 hal_vcoreiii_ddr_reset_release();
779
780 writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7));
781#else /* Luton */
782 /* Termination setup - disable ODT */
783 writel(0, BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
784
785#endif
786}
787
788static inline void hal_vcoreiii_wait_memctl(void)
789{
790 /* Now, rip it! */
791 writel(ICPU_MEMCTRL_CTRL_INITIALIZE, BASE_CFG + ICPU_MEMCTRL_CTRL);
792
793 while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
794 & ICPU_MEMCTRL_STAT_INIT_DONE))
795 ;
796
797 /* Settle...? */
798 sleep_100ns(10000);
799#ifdef CONFIG_SOC_OCELOT
800 /* Establish data contents in DDR RAM for training */
801
802 __raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
803 __raw_writel(0x22221111, ((void __iomem *)MSCC_DDR_TO + 0x4));
804 __raw_writel(0x44443333, ((void __iomem *)MSCC_DDR_TO + 0x8));
805 __raw_writel(0x66665555, ((void __iomem *)MSCC_DDR_TO + 0xC));
806 __raw_writel(0x88887777, ((void __iomem *)MSCC_DDR_TO + 0x10));
807 __raw_writel(0xaaaa9999, ((void __iomem *)MSCC_DDR_TO + 0x14));
808 __raw_writel(0xccccbbbb, ((void __iomem *)MSCC_DDR_TO + 0x18));
809 __raw_writel(0xeeeedddd, ((void __iomem *)MSCC_DDR_TO + 0x1C));
810#else
811 __raw_writel(0xff, ((void __iomem *)MSCC_DDR_TO));
812#endif
813}
814#endif /* __ASM_MACH_DDR_H */
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton.h b/arch/mips/mach-mscc/include/mach/luton/luton.h
new file mode 100644
index 0000000000..19f02ede66
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/luton/luton.h
@@ -0,0 +1,24 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2018 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_H_
9#define _MSCC_OCELOT_H_
10
11#include <linux/bitops.h>
12#include <dm.h>
13
14/*
15 * Target offset base(s)
16 */
17#define MSCC_IO_ORIGIN1_OFFSET 0x60000000
18#define MSCC_IO_ORIGIN1_SIZE 0x01000000
19#define MSCC_IO_ORIGIN2_OFFSET 0x70000000
20#define MSCC_IO_ORIGIN2_SIZE 0x00200000
21#define BASE_CFG ((void __iomem *)0x70000000)
22#define BASE_DEVCPU_GCB ((void __iomem *)0x60070000)
23
24#endif
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
new file mode 100644
index 0000000000..8c0b612325
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -0,0 +1,14 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
7#define _MSCC_OCELOT_DEVCPU_GCB_H_
8
9#define PERF_SOFT_RST 0x90
10
11#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
12#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
13
14#endif
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
new file mode 100644
index 0000000000..9233f037bb
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
@@ -0,0 +1,245 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef _MSCC_OCELOT_ICPU_CFG_H_
7#define _MSCC_OCELOT_ICPU_CFG_H_
8
9#define ICPU_GPR(x) (0x4 * (x))
10#define ICPU_GPR_RSZ 0x4
11
12#define ICPU_RESET 0x20
13
14#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16#define ICPU_RESET_CORE_RST_FORCE BIT(1)
17#define ICPU_RESET_MEM_RST_FORCE BIT(0)
18
19#define ICPU_GENERAL_CTRL 0x24
20
21#define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6)
22#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5)
23#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4)
24#define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3)
25#define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2)
26#define ICPU_GENERAL_CTRL_IF_MASTER_PI_ENA BIT(1)
27
28#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
29
30#define ICPU_PI_MST_CFG 0x2c
31
32#define ICPU_PI_MST_CFG_ATE_MODE_DIS BIT(7)
33#define ICPU_PI_MST_CFG_CLK_POL BIT(6)
34#define ICPU_PI_MST_CFG_TRISTATE_CTRL BIT(5)
35#define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
36#define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
37
38#define ICPU_SPI_MST_CFG 0x50
39
40#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
41#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
42#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
43#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
44#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
46
47#define ICPU_SW_MODE 0x64
48
49#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
50#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
51#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
52#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
53#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
54#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
55#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
56#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
57#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
58#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
59#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
60#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
61
62#define ICPU_INTR_ENA 0x88
63
64#define ICPU_INTR_IRQ0_ENA 0x98
65#define ICPU_INTR_IRQ0_ENA_IRQ0_ENA BIT(0)
66
67#define ICPU_MEMCTRL_CTRL 0x234
68
69#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
70#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
71#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
72#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
73
74#define ICPU_MEMCTRL_CFG 0x238
75
76#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
77#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
78#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
79#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
80#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
81#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
82#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
83#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
84#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
85#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
86#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
87#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
88#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
89#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
90
91#define ICPU_MEMCTRL_STAT 0x23C
92
93#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
94#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
95#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
96#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
97#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
98#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
99
100#define ICPU_MEMCTRL_REF_PERIOD 0x240
101
102#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
103#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
104#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
105#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
106#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
107
108#define ICPU_MEMCTRL_TIMING0 0x248
109
110#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
111#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
112#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
113#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
114#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
115#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
116#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
117#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
118#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
119#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
120#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
121#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
122#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
123#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
124#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
125#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
126#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
127#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
128#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
129#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
130#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
131#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
132#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
133
134#define ICPU_MEMCTRL_TIMING1 0x24c
135
136#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
137#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
138#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
139#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
140#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
141#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
142#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
143#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
144#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
145#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
146#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
147#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
148#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
149#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
150#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
151#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
152#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
153
154#define ICPU_MEMCTRL_TIMING2 0x250
155
156#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
157#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
158#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
159#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
160#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
161#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
162#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
163#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
164#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
165#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(x) ((x) & GENMASK(15, 0))
166#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY_M GENMASK(15, 0)
167
168#define ICPU_MEMCTRL_TIMING3 0x254
169
170#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
171#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
172#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
173#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
174#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
175#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
176#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
177#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
178#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
179#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
180#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
181#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
182#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
183#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
184
185#define ICPU_MEMCTRL_MR0_VAL 0x258
186
187#define ICPU_MEMCTRL_MR1_VAL 0x25c
188
189#define ICPU_MEMCTRL_MR2_VAL 0x260
190
191#define ICPU_MEMCTRL_MR3_VAL 0x264
192
193#define ICPU_MEMCTRL_TERMRES_CTRL 0x268
194
195#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
196#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
197#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
198#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
199#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
200#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
201#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
202#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
203#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
204#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
205
206#define ICPU_MEMCTRL_DQS_DLY(x) (0x270)
207
208#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
209#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
210#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
211#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
212#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
213#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
214#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
215#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
216#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
217
218#define ICPU_MEMPHY_CFG 0x278
219
220#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
221#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
222#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
223#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
224#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
225#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
226#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
227#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
228#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
229#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
230#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
231#define ICPU_MEMPHY_DQ_DLY_TRM 0x180
232#define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4
233
234#define ICPU_MEMPHY_ZCAL 0x294
235
236#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
237#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
238#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
239#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
240#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
241#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
242#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
243#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
244
245#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
new file mode 100644
index 0000000000..2cb2135d37
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
@@ -0,0 +1,24 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2018 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_H_
9#define _MSCC_OCELOT_H_
10
11#include <linux/bitops.h>
12#include <dm.h>
13
14/*
15 * Target offset base(s)
16 */
17#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18#define MSCC_IO_ORIGIN1_SIZE 0x00200000
19#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20#define MSCC_IO_ORIGIN2_SIZE 0x01000000
21#define BASE_CFG ((void __iomem *)0x70000000)
22#define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
23
24#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
new file mode 100644
index 0000000000..f8aa97ba26
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -0,0 +1,21 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
7#define _MSCC_OCELOT_DEVCPU_GCB_H_
8
9#define PERF_SOFT_RST 0x8
10
11#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
12#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
13#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
14
15#define PERF_GPIO_OUT_SET 0x34
16
17#define PERF_GPIO_OUT_CLR 0x38
18
19#define PERF_GPIO_OE 0x44
20
21#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
new file mode 100644
index 0000000000..04cf70bec3
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
@@ -0,0 +1,274 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef _MSCC_OCELOT_ICPU_CFG_H_
7#define _MSCC_OCELOT_ICPU_CFG_H_
8
9#define ICPU_GPR(x) (0x4 * (x))
10#define ICPU_GPR_RSZ 0x4
11
12#define ICPU_RESET 0x20
13
14#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16#define ICPU_RESET_CORE_RST_FORCE BIT(1)
17#define ICPU_RESET_MEM_RST_FORCE BIT(0)
18
19#define ICPU_GENERAL_CTRL 0x24
20
21#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
26#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9)
27#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8)
28#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7)
29#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6)
30#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
31#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
33#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3)
34#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
35#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
36#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
37#define ICPU_SPI_MST_CFG 0x3c
38
39#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
40#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
41#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
42#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
43#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
44#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
46
47#define ICPU_SW_MODE 0x50
48
49#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
50#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
51#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
52#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
53#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
54#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
55#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
56#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
57#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
58#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
59#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
60#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
61
62#define ICPU_INTR_ENA 0x88
63
64#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
65#define ICPU_DST_INTR_MAP_RSZ 0x4
66
67#define ICPU_DST_INTR_IDENT 0xa8
68#define ICPU_DST_INTR_IDENT_RSZ 0x4
69
70#define ICPU_TIMER_TICK_DIV 0xe8
71#define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x))
72
73#define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x))
74#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
75#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
76#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
77#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
78
79#define ICPU_MEMCTRL_CTRL 0x110
80#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
81#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
82#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
83#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
84
85#define ICPU_MEMCTRL_CFG 0x114
86
87#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
88#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
89#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
90#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
91#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
92#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
93#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
94#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
95#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
96#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
97#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
98#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
99#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
100#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
101
102#define ICPU_MEMCTRL_STAT 0x118
103
104#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
105#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
106#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
107#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
108#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
109#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
110
111#define ICPU_MEMCTRL_REF_PERIOD 0x11c
112
113#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
114#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
115#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
116#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
117#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
118
119#define ICPU_MEMCTRL_TIMING0 0x124
120
121#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
122#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
123#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
124#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
125#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
126#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
127#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
128#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
129#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
130#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
131#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
132#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
133#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
134#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
135#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
136#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
137#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
138#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
139#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
140#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
141#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
142#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
143#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
144
145#define ICPU_MEMCTRL_TIMING1 0x128
146
147#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
148#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
149#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
150#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
151#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
152#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
153#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
154#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
155#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
156#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
157#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
158#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
159#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
160#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
161#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
162#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
163#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
164
165#define ICPU_MEMCTRL_TIMING2 0x12c
166
167#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
168#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
169#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
170#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
171#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
172#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
173#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
174#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
175#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
176#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
177#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
178
179#define ICPU_MEMCTRL_TIMING3 0x130
180
181#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
182#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
183#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
184#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
185#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
186#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
187#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
188#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
189#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
190#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
191#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
192#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
193#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
194#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
195
196#define ICPU_MEMCTRL_MR0_VAL 0x138
197
198#define ICPU_MEMCTRL_MR1_VAL 0x13c
199
200#define ICPU_MEMCTRL_MR2_VAL 0x140
201
202#define ICPU_MEMCTRL_MR3_VAL 0x144
203
204#define ICPU_MEMCTRL_TERMRES_CTRL 0x148
205
206#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
207#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
208#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
209#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
210#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
211#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
212#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
213#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
214#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
215#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
216
217#define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x))
218#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4
219
220#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
221#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
222#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
223#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
224#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
225#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
226#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
227#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
228#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
229
230#define ICPU_MEMPHY_CFG 0x160
231
232#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
233#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
234#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
235#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
236#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
237#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
238#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
239#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
240#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
241#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
242#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
243
244#define ICPU_MEMPHY_ZCAL 0x188
245
246#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
247#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
248#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
249#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
250#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
251#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
252#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
253#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
254
255#define ICPU_MEMPHY_ZCAL_STAT 0x18c
256
257#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
258#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
259#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
260#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
261#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
262#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
263#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
264#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
265#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
266#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
267#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
268#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
269#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
270#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
271#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
272#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
273#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
274#endif
diff --git a/arch/mips/mach-mscc/include/mach/tlb.h b/arch/mips/mach-mscc/include/mach/tlb.h
new file mode 100644
index 0000000000..fdb554f551
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/tlb.h
@@ -0,0 +1,55 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __ASM_MACH_TLB_H
7#define __ASM_MACH_TLB_H
8
9#include <asm/mipsregs.h>
10#include <mach/common.h>
11#include <linux/sizes.h>
12
13#define TLB_HI_MASK 0xffffe000
14#define TLB_LO_MASK 0x3fffffff /* Masks off Fill bits */
15#define TLB_LO_SHIFT 6 /* PFN Start bit */
16
17#define PAGEMASK_SHIFT 13
18
19#define MMU_PAGE_CACHED (3 << 3) /* C(5:3) Cache Coherency Attributes */
20#define MMU_PAGE_UNCACHED (2 << 3) /* C(5:3) Cache Coherency Attributes */
21#define MMU_PAGE_DIRTY BIT(2) /* = Writeable */
22#define MMU_PAGE_VALID BIT(1)
23#define MMU_PAGE_GLOBAL BIT(0)
24#define MMU_REGIO_RO_C (MMU_PAGE_CACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
25#define MMU_REGIO_RO (MMU_PAGE_UNCACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
26#define MMU_REGIO_RW (MMU_PAGE_DIRTY | MMU_REGIO_RO)
27#define MMU_REGIO_INVAL (MMU_PAGE_GLOBAL)
28
29#define TLB_COUNT_MASK GENMASK(5, 0)
30#define TLB_COUNT_OFF 25
31
32static inline u32 get_tlb_count(void)
33{
34 register u32 config1;
35
36 config1 = read_c0_config1();
37 config1 >>= TLB_COUNT_OFF;
38 config1 &= TLB_COUNT_MASK;
39
40 return 1 + config1;
41}
42
43static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1,
44 u32 tlb_attrib2)
45{
46 register u32 tlb_mask, tlb_lo0, tlb_lo1;
47
48 tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT;
49 tlb_lo0 = tlb_attrib1 | (offset >> TLB_LO_SHIFT);
50 tlb_lo1 = tlb_attrib2 | ((offset + size) >> TLB_LO_SHIFT);
51
52 write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK,
53 tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK);
54}
55#endif /* __ASM_MACH_TLB_H */
diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S
new file mode 100644
index 0000000000..dfbe06766c
--- /dev/null
+++ b/arch/mips/mach-mscc/lowlevel_init.S
@@ -0,0 +1,30 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <asm/asm.h>
7#include <asm/regdef.h>
8
9 .set noreorder
10 .extern vcoreiii_tlb_init
11#ifdef CONFIG_SOC_LUTON
12 .extern pll_init
13#endif
14
15LEAF(lowlevel_init)
16 /*
17 * As we have no stack yet, we can assume the restricted
18 * luxury of the sX-registers without saving them
19 */
20 move s0,ra
21
22 jal vcoreiii_tlb_init
23 nop
24#ifdef CONFIG_SOC_LUTON
25 jal pll_init
26 nop
27#endif
28 jr s0
29 nop
30 END(lowlevel_init)
diff --git a/arch/mips/mach-mscc/lowlevel_init_luton.S b/arch/mips/mach-mscc/lowlevel_init_luton.S
new file mode 100644
index 0000000000..8a528fa83a
--- /dev/null
+++ b/arch/mips/mach-mscc/lowlevel_init_luton.S
@@ -0,0 +1,62 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <asm/asm.h>
7#include <asm/regdef.h>
8
9#define BASE_MACRO 0x600a0000
10#define REG_OFFSET(t, o) (t + (o*4))
11#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x)
12#define BIT(nr) (1 << (nr))
13
14#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 REG_MACRO(6)
15#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS BIT(0)
16#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 REG_MACRO(2)
17#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 REG_MACRO(0)
18#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV (0x3F << 6)
19#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(x) (x << 6)
20
21 .set noreorder
22LEAF(pll_init)
23 /* Make sure PLL is locked */
24 lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
25 andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
26 bne v1, zero, 1f
27 nop
28
29 /* Black magic from frontend */
30 li v1, 0x00610400
31 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
32
33 li v1, 0x00610c00
34 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
35
36 li v1, 0x00610800
37 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
38
39 li v1, 0x00610000
40 sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
41
42 /* Wait for lock */
432: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
44 andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
45 /* Keep looping if zero (no lock bit yet) */
46 beq v1, zero, 2b
47 nop
48
49 /* Setup PLL CPU clock divider for 416MHz */
501: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
51
52 /* Keep reserved bits */
53 li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV
54 and v0, v0, v1
55
56 /* Set code 6 ~ 416.66 MHz */
57 ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6)
58
59 sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
60 jr ra
61 nop
62 END(pll_init)
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
new file mode 100644
index 0000000000..390bbd086a
--- /dev/null
+++ b/arch/mips/mach-mscc/reset.c
@@ -0,0 +1,30 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
7
8#include <asm/sections.h>
9#include <asm/io.h>
10
11#include <asm/reboot.h>
12
13void _machine_restart(void)
14{
15 register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
16 (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
17
18 /* Make sure VCore is NOT protected from reset */
19 clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
20
21 /* Change to SPI bitbang for SPI reset workaround... */
22 writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
23 ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
24
25 /* Do the global reset */
26 writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
27
28 while (1)
29 ; /* NOP */
30}
diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c
index 87cc973b75..9e0ca716f7 100644
--- a/arch/mips/mach-mt7620/cpu.c
+++ b/arch/mips/mach-mt7620/cpu.c
@@ -89,9 +89,21 @@ void watchdog_reset(void)
89 wdt_reset(watchdog_dev); 89 wdt_reset(watchdog_dev);
90 } 90 }
91} 91}
92#endif
92 93
93int arch_misc_init(void) 94int arch_misc_init(void)
94{ 95{
96 /*
97 * It has been noticed, that sometimes the d-cache is not in a
98 * "clean-state" when U-Boot is running on MT7688. This was
99 * detected when using the ethernet driver (which uses d-cache)
100 * and a TFTP command does not complete. Flushing the complete
101 * d-cache (again?) here seems to fix this issue.
102 */
103 flush_dcache_range(gd->bd->bi_memstart,
104 gd->bd->bi_memstart + gd->ram_size - 1);
105
106#ifdef CONFIG_WATCHDOG
95 /* Init watchdog */ 107 /* Init watchdog */
96 if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { 108 if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
97 debug("Watchdog: Not found by seq!\n"); 109 debug("Watchdog: Not found by seq!\n");
@@ -103,7 +115,7 @@ int arch_misc_init(void)
103 115
104 wdt_start(watchdog_dev, 60000, 0); /* 60 seconds */ 116 wdt_start(watchdog_dev, 60000, 0); /* 60 seconds */
105 printf("Watchdog: Started\n"); 117 printf("Watchdog: Started\n");
118#endif
106 119
107 return 0; 120 return 0;
108} 121}
109#endif
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 732a357a99..c45e4d73a8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,6 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig"
22 22
23# platform-specific options below 23# platform-specific options below
24source "arch/riscv/cpu/ax25/Kconfig" 24source "arch/riscv/cpu/ax25/Kconfig"
25source "arch/riscv/cpu/qemu/Kconfig"
25 26
26# architecture-specific options below 27# architecture-specific options below
27 28
@@ -44,6 +45,40 @@ config ARCH_RV64I
44 45
45endchoice 46endchoice
46 47
48choice
49 prompt "Code Model"
50 default CMODEL_MEDLOW
51
52config CMODEL_MEDLOW
53 bool "medium low code model"
54 help
55 U-Boot and its statically defined symbols must lie within a single 2 GiB
56 address range and must lie between absolute addresses -2 GiB and +2 GiB.
57
58config CMODEL_MEDANY
59 bool "medium any code model"
60 help
61 U-Boot and its statically defined symbols must be within any single 2 GiB
62 address range.
63
64endchoice
65
66choice
67 prompt "Run Mode"
68 default RISCV_MMODE
69
70config RISCV_MMODE
71 bool "Machine"
72 help
73 Choose this option to build U-Boot for RISC-V M-Mode.
74
75config RISCV_SMODE
76 bool "Supervisor"
77 help
78 Choose this option to build U-Boot for RISC-V S-Mode.
79
80endchoice
81
47config RISCV_ISA_C 82config RISCV_ISA_C
48 bool "Emit compressed instructions" 83 bool "Emit compressed instructions"
49 default y 84 default y
@@ -55,15 +90,30 @@ config RISCV_ISA_C
55config RISCV_ISA_A 90config RISCV_ISA_A
56 def_bool y 91 def_bool y
57 92
58config RISCV_SMODE
59 bool "Run in S-Mode"
60 help
61 Enable this option to build U-Boot for RISC-V S-Mode
62
63config 32BIT 93config 32BIT
64 bool 94 bool
65 95
66config 64BIT 96config 64BIT
67 bool 97 bool
68 98
99config SIFIVE_CLINT
100 bool
101 depends on RISCV_MMODE
102 select REGMAP
103 select SYSCON
104 help
105 The SiFive CLINT block holds memory-mapped control and status registers
106 associated with software and timer interrupts.
107
108config RISCV_RDTIME
109 bool
110 default y if RISCV_SMODE
111 help
112 The provides the riscv_get_time() API that is implemented using the
113 standard rdtime instruction. This is the case for S-mode U-Boot, and
114 is useful for processors that support rdtime in M-mode too.
115
116config SYS_MALLOC_F_LEN
117 default 0x1000
118
69endmenu 119endmenu
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 55d7c6550e..0b80eb8d86 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -17,8 +17,15 @@ endif
17ifeq ($(CONFIG_RISCV_ISA_C),y) 17ifeq ($(CONFIG_RISCV_ISA_C),y)
18 ARCH_C = c 18 ARCH_C = c
19endif 19endif
20ifeq ($(CONFIG_CMODEL_MEDLOW),y)
21 CMODEL = medlow
22endif
23ifeq ($(CONFIG_CMODEL_MEDANY),y)
24 CMODEL = medany
25endif
20 26
21ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) 27ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
28 -mcmodel=$(CMODEL)
22 29
23PLATFORM_CPPFLAGS += $(ARCH_FLAGS) 30PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
24CFLAGS_EFI += $(ARCH_FLAGS) 31CFLAGS_EFI += $(ARCH_FLAGS)
diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
index 2cc6757fcf..6bf6f911c6 100644
--- a/arch/riscv/cpu/Makefile
+++ b/arch/riscv/cpu/Makefile
@@ -4,4 +4,4 @@
4 4
5extra-y = start.o 5extra-y = start.o
6 6
7obj-y += cpu.o 7obj-y += cpu.o mtrap.o
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6c7022f0f5..e9dbca2fae 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,7 +1,14 @@
1config RISCV_NDS 1config RISCV_NDS
2 bool "AndeStar V5 ISA support" 2 bool
3 default n
4 help 3 help
5 Say Y here if you plan to run U-Boot on AndeStar v5 4 Run U-Boot on AndeStar V5 platforms and use some specific features
6 platforms and use some specific features which are 5 which are provided by Andes Technology AndeStar V5 families.
7 provided by Andes Technology AndeStar V5 Families. 6
7if RISCV_NDS
8
9config RISCV_NDS_CACHE
10 bool "AndeStar V5 families specific cache support"
11 help
12 Provide Andes Technology AndeStar V5 families specific cache support.
13
14endif
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 6600ac2fac..8d6ae170b8 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -9,7 +9,7 @@
9void icache_enable(void) 9void icache_enable(void)
10{ 10{
11#ifndef CONFIG_SYS_ICACHE_OFF 11#ifndef CONFIG_SYS_ICACHE_OFF
12#ifdef CONFIG_RISCV_NDS 12#ifdef CONFIG_RISCV_NDS_CACHE
13 asm volatile ( 13 asm volatile (
14 "csrr t1, mcache_ctl\n\t" 14 "csrr t1, mcache_ctl\n\t"
15 "ori t0, t1, 0x1\n\t" 15 "ori t0, t1, 0x1\n\t"
@@ -22,7 +22,7 @@ void icache_enable(void)
22void icache_disable(void) 22void icache_disable(void)
23{ 23{
24#ifndef CONFIG_SYS_ICACHE_OFF 24#ifndef CONFIG_SYS_ICACHE_OFF
25#ifdef CONFIG_RISCV_NDS 25#ifdef CONFIG_RISCV_NDS_CACHE
26 asm volatile ( 26 asm volatile (
27 "fence.i\n\t" 27 "fence.i\n\t"
28 "csrr t1, mcache_ctl\n\t" 28 "csrr t1, mcache_ctl\n\t"
@@ -36,7 +36,7 @@ void icache_disable(void)
36void dcache_enable(void) 36void dcache_enable(void)
37{ 37{
38#ifndef CONFIG_SYS_DCACHE_OFF 38#ifndef CONFIG_SYS_DCACHE_OFF
39#ifdef CONFIG_RISCV_NDS 39#ifdef CONFIG_RISCV_NDS_CACHE
40 asm volatile ( 40 asm volatile (
41 "csrr t1, mcache_ctl\n\t" 41 "csrr t1, mcache_ctl\n\t"
42 "ori t0, t1, 0x2\n\t" 42 "ori t0, t1, 0x2\n\t"
@@ -49,7 +49,7 @@ void dcache_enable(void)
49void dcache_disable(void) 49void dcache_disable(void)
50{ 50{
51#ifndef CONFIG_SYS_DCACHE_OFF 51#ifndef CONFIG_SYS_DCACHE_OFF
52#ifdef CONFIG_RISCV_NDS 52#ifdef CONFIG_RISCV_NDS_CACHE
53 asm volatile ( 53 asm volatile (
54 "fence\n\t" 54 "fence\n\t"
55 "csrr t1, mcache_ctl\n\t" 55 "csrr t1, mcache_ctl\n\t"
@@ -64,7 +64,7 @@ int icache_status(void)
64{ 64{
65 int ret = 0; 65 int ret = 0;
66 66
67#ifdef CONFIG_RISCV_NDS 67#ifdef CONFIG_RISCV_NDS_CACHE
68 asm volatile ( 68 asm volatile (
69 "csrr t1, mcache_ctl\n\t" 69 "csrr t1, mcache_ctl\n\t"
70 "andi %0, t1, 0x01\n\t" 70 "andi %0, t1, 0x01\n\t"
@@ -81,7 +81,7 @@ int dcache_status(void)
81{ 81{
82 int ret = 0; 82 int ret = 0;
83 83
84#ifdef CONFIG_RISCV_NDS 84#ifdef CONFIG_RISCV_NDS_CACHE
85 asm volatile ( 85 asm volatile (
86 "csrr t1, mcache_ctl\n\t" 86 "csrr t1, mcache_ctl\n\t"
87 "andi %0, t1, 0x02\n\t" 87 "andi %0, t1, 0x02\n\t"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d9f820c44c..e662140427 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -4,7 +4,12 @@
4 */ 4 */
5 5
6#include <common.h> 6#include <common.h>
7#include <cpu.h>
8#include <dm.h>
9#include <log.h>
7#include <asm/csr.h> 10#include <asm/csr.h>
11#include <asm/encoding.h>
12#include <dm/uclass-internal.h>
8 13
9/* 14/*
10 * prior_stage_fdt_address must be stored in the data section since it is used 15 * prior_stage_fdt_address must be stored in the data section since it is used
@@ -12,44 +17,79 @@
12 */ 17 */
13phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); 18phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
14 19
15enum {
16 ISA_INVALID = 0,
17 ISA_32BIT,
18 ISA_64BIT,
19 ISA_128BIT
20};
21
22static const char * const isa_bits[] = {
23 [ISA_INVALID] = NULL,
24 [ISA_32BIT] = "32",
25 [ISA_64BIT] = "64",
26 [ISA_128BIT] = "128"
27};
28
29static inline bool supports_extension(char ext) 20static inline bool supports_extension(char ext)
30{ 21{
22#ifdef CONFIG_CPU
23 struct udevice *dev;
24 char desc[32];
25
26 uclass_find_first_device(UCLASS_CPU, &dev);
27 if (!dev) {
28 debug("unable to find the RISC-V cpu device\n");
29 return false;
30 }
31 if (!cpu_get_desc(dev, desc, sizeof(desc))) {
32 /* skip the first 4 characters (rv32|rv64) */
33 if (strchr(desc + 4, ext))
34 return true;
35 }
36
37 return false;
38#else /* !CONFIG_CPU */
39#ifdef CONFIG_RISCV_MMODE
31 return csr_read(misa) & (1 << (ext - 'a')); 40 return csr_read(misa) & (1 << (ext - 'a'));
41#else /* !CONFIG_RISCV_MMODE */
42#warning "There is no way to determine the available extensions in S-mode."
43#warning "Please convert your board to use the RISC-V CPU driver."
44 return false;
45#endif /* CONFIG_RISCV_MMODE */
46#endif /* CONFIG_CPU */
47}
48
49static int riscv_cpu_probe(void)
50{
51#ifdef CONFIG_CPU
52 int ret;
53
54 /* probe cpus so that RISC-V timer can be bound */
55 ret = cpu_probe_all();
56 if (ret)
57 return log_msg_ret("RISC-V cpus probe failed\n", ret);
58#endif
59
60 return 0;
32} 61}
33 62
34int print_cpuinfo(void) 63int arch_cpu_init_dm(void)
35{ 64{
36 char name[32]; 65 int ret;
37 char *s = name; 66
38 int bit; 67 ret = riscv_cpu_probe();
68 if (ret)
69 return ret;
39 70
40 s += sprintf(name, "rv"); 71 /* Enable FPU */
41 bit = csr_read(misa) >> (sizeof(long) * 8 - 2); 72 if (supports_extension('d') || supports_extension('f')) {
42 s += sprintf(s, isa_bits[bit]); 73 csr_set(MODE_PREFIX(status), MSTATUS_FS);
74 csr_write(fcsr, 0);
75 }
43 76
44 supports_extension('i') ? *s++ = 'i' : 'r'; 77 if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
45 supports_extension('m') ? *s++ = 'm' : 'i'; 78 /*
46 supports_extension('a') ? *s++ = 'a' : 's'; 79 * Enable perf counters for cycle, time,
47 supports_extension('f') ? *s++ = 'f' : 'c'; 80 * and instret counters only
48 supports_extension('d') ? *s++ = 'd' : '-'; 81 */
49 supports_extension('c') ? *s++ = 'c' : 'v'; 82 csr_write(mcounteren, GENMASK(2, 0));
50 *s++ = '\0';
51 83
52 printf("CPU: %s\n", name); 84 /* Disable paging */
85 if (supports_extension('s'))
86 csr_write(satp, 0);
87 }
53 88
54 return 0; 89 return 0;
55} 90}
91
92int arch_early_init_r(void)
93{
94 return riscv_cpu_probe();
95}
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
new file mode 100644
index 0000000000..407ecfa9c0
--- /dev/null
+++ b/arch/riscv/cpu/mtrap.S
@@ -0,0 +1,103 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * M-mode Trap Handler Code for RISC-V Core
4 *
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
7 *
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
10 *
11 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
12 */
13
14#include <common.h>
15#include <asm/encoding.h>
16
17#ifdef CONFIG_32BIT
18#define LREG lw
19#define SREG sw
20#define REGBYTES 4
21#else
22#define LREG ld
23#define SREG sd
24#define REGBYTES 8
25#endif
26
27 .text
28
29 /* trap entry */
30 .align 2
31 .global trap_entry
32trap_entry:
33 addi sp, sp, -32 * REGBYTES
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
42 SREG x9, 9 * REGBYTES(sp)
43 SREG x10, 10 * REGBYTES(sp)
44 SREG x11, 11 * REGBYTES(sp)
45 SREG x12, 12 * REGBYTES(sp)
46 SREG x13, 13 * REGBYTES(sp)
47 SREG x14, 14 * REGBYTES(sp)
48 SREG x15, 15 * REGBYTES(sp)
49 SREG x16, 16 * REGBYTES(sp)
50 SREG x17, 17 * REGBYTES(sp)
51 SREG x18, 18 * REGBYTES(sp)
52 SREG x19, 19 * REGBYTES(sp)
53 SREG x20, 20 * REGBYTES(sp)
54 SREG x21, 21 * REGBYTES(sp)
55 SREG x22, 22 * REGBYTES(sp)
56 SREG x23, 23 * REGBYTES(sp)
57 SREG x24, 24 * REGBYTES(sp)
58 SREG x25, 25 * REGBYTES(sp)
59 SREG x26, 26 * REGBYTES(sp)
60 SREG x27, 27 * REGBYTES(sp)
61 SREG x28, 28 * REGBYTES(sp)
62 SREG x29, 29 * REGBYTES(sp)
63 SREG x30, 30 * REGBYTES(sp)
64 SREG x31, 31 * REGBYTES(sp)
65 csrr a0, MODE_PREFIX(cause)
66 csrr a1, MODE_PREFIX(epc)
67 mv a2, sp
68 jal handle_trap
69 csrw MODE_PREFIX(epc), a0
70
71 LREG x1, 1 * REGBYTES(sp)
72 LREG x3, 3 * REGBYTES(sp)
73 LREG x4, 4 * REGBYTES(sp)
74 LREG x5, 5 * REGBYTES(sp)
75 LREG x6, 6 * REGBYTES(sp)
76 LREG x7, 7 * REGBYTES(sp)
77 LREG x8, 8 * REGBYTES(sp)
78 LREG x9, 9 * REGBYTES(sp)
79 LREG x10, 10 * REGBYTES(sp)
80 LREG x11, 11 * REGBYTES(sp)
81 LREG x12, 12 * REGBYTES(sp)
82 LREG x13, 13 * REGBYTES(sp)
83 LREG x14, 14 * REGBYTES(sp)
84 LREG x15, 15 * REGBYTES(sp)
85 LREG x16, 16 * REGBYTES(sp)
86 LREG x17, 17 * REGBYTES(sp)
87 LREG x18, 18 * REGBYTES(sp)
88 LREG x19, 19 * REGBYTES(sp)
89 LREG x20, 20 * REGBYTES(sp)
90 LREG x21, 21 * REGBYTES(sp)
91 LREG x22, 22 * REGBYTES(sp)
92 LREG x23, 23 * REGBYTES(sp)
93 LREG x24, 24 * REGBYTES(sp)
94 LREG x25, 25 * REGBYTES(sp)
95 LREG x26, 26 * REGBYTES(sp)
96 LREG x27, 27 * REGBYTES(sp)
97 LREG x28, 28 * REGBYTES(sp)
98 LREG x29, 29 * REGBYTES(sp)
99 LREG x30, 30 * REGBYTES(sp)
100 LREG x31, 31 * REGBYTES(sp)
101 LREG x2, 2 * REGBYTES(sp)
102 addi sp, sp, 32 * REGBYTES
103 MODE_PREFIX(ret)
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig
new file mode 100644
index 0000000000..f48751e6de
--- /dev/null
+++ b/arch/riscv/cpu/qemu/Kconfig
@@ -0,0 +1,12 @@
1# SPDX-License-Identifier: GPL-2.0+
2#
3# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4
5config QEMU_RISCV
6 bool
7 select ARCH_EARLY_INIT_R
8 imply CPU
9 imply CPU_RISCV
10 imply RISCV_TIMER
11 imply SIFIVE_CLINT if RISCV_MMODE
12 imply CMD_CPU
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c
index 25d97d0b41..ad2950ce40 100644
--- a/arch/riscv/cpu/qemu/cpu.c
+++ b/arch/riscv/cpu/qemu/cpu.c
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6#include <common.h> 6#include <common.h>
7#include <dm.h>
7 8
8/* 9/*
9 * cleanup_before_linux() is called just before we call linux 10 * cleanup_before_linux() is called just before we call linux
@@ -19,3 +20,16 @@ int cleanup_before_linux(void)
19 20
20 return 0; 21 return 0;
21} 22}
23
24/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */
25static const struct udevice_id riscv_virtio_soc_ids[] = {
26 { .compatible = "riscv-virtio-soc" },
27 { }
28};
29
30U_BOOT_DRIVER(riscv_virtio_soc) = {
31 .name = "riscv_virtio_soc",
32 .id = UCLASS_SIMPLE_BUS,
33 .of_match = riscv_virtio_soc_ids,
34 .flags = DM_FLAG_PRE_RELOC,
35};
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 64246a4e09..81ea52b170 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -14,6 +14,7 @@
14#include <common.h> 14#include <common.h>
15#include <elf.h> 15#include <elf.h>
16#include <asm/encoding.h> 16#include <asm/encoding.h>
17#include <generated/asm-offsets.h>
17 18
18#ifdef CONFIG_32BIT 19#ifdef CONFIG_32BIT
19#define LREG lw 20#define LREG lw
@@ -70,6 +71,9 @@ call_board_init_f_0:
70 71
71 jal board_init_f_init_reserve 72 jal board_init_f_init_reserve
72 73
74 /* save the boot hart id to global_data */
75 SREG s0, GD_BOOT_HART(gp)
76
73 mv a0, zero /* a0 <-- boot_flags = 0 */ 77 mv a0, zero /* a0 <-- boot_flags = 0 */
74 la t5, board_init_f 78 la t5, board_init_f
75 jr t5 /* jump to board_init_f() */ 79 jr t5 /* jump to board_init_f() */
@@ -198,92 +202,3 @@ call_board_init_r:
198 * jump to it ... 202 * jump to it ...
199 */ 203 */
200 jr t4 /* jump to board_init_r() */ 204 jr t4 /* jump to board_init_r() */
201
202/*
203 * trap entry
204 */
205.align 2
206trap_entry:
207 addi sp, sp, -32*REGBYTES
208 SREG x1, 1*REGBYTES(sp)
209 SREG x2, 2*REGBYTES(sp)
210 SREG x3, 3*REGBYTES(sp)
211 SREG x4, 4*REGBYTES(sp)
212 SREG x5, 5*REGBYTES(sp)
213 SREG x6, 6*REGBYTES(sp)
214 SREG x7, 7*REGBYTES(sp)
215 SREG x8, 8*REGBYTES(sp)
216 SREG x9, 9*REGBYTES(sp)
217 SREG x10, 10*REGBYTES(sp)
218 SREG x11, 11*REGBYTES(sp)
219 SREG x12, 12*REGBYTES(sp)
220 SREG x13, 13*REGBYTES(sp)
221 SREG x14, 14*REGBYTES(sp)
222 SREG x15, 15*REGBYTES(sp)
223 SREG x16, 16*REGBYTES(sp)
224 SREG x17, 17*REGBYTES(sp)
225 SREG x18, 18*REGBYTES(sp)
226 SREG x19, 19*REGBYTES(sp)
227 SREG x20, 20*REGBYTES(sp)
228 SREG x21, 21*REGBYTES(sp)
229 SREG x22, 22*REGBYTES(sp)
230 SREG x23, 23*REGBYTES(sp)
231 SREG x24, 24*REGBYTES(sp)
232 SREG x25, 25*REGBYTES(sp)
233 SREG x26, 26*REGBYTES(sp)
234 SREG x27, 27*REGBYTES(sp)
235 SREG x28, 28*REGBYTES(sp)
236 SREG x29, 29*REGBYTES(sp)
237 SREG x30, 30*REGBYTES(sp)
238 SREG x31, 31*REGBYTES(sp)
239 csrr a0, MODE_PREFIX(cause)
240 csrr a1, MODE_PREFIX(epc)
241 mv a2, sp
242 jal handle_trap
243 csrw MODE_PREFIX(epc), a0
244
245#ifdef CONFIG_RISCV_SMODE
246/*
247 * Remain in S-mode after sret
248 */
249 li t0, SSTATUS_SPP
250#else
251/*
252 * Remain in M-mode after mret
253 */
254 li t0, MSTATUS_MPP
255#endif
256 csrs MODE_PREFIX(status), t0
257 LREG x1, 1*REGBYTES(sp)
258 LREG x2, 2*REGBYTES(sp)
259 LREG x3, 3*REGBYTES(sp)
260 LREG x4, 4*REGBYTES(sp)
261 LREG x5, 5*REGBYTES(sp)
262 LREG x6, 6*REGBYTES(sp)
263 LREG x7, 7*REGBYTES(sp)
264 LREG x8, 8*REGBYTES(sp)
265 LREG x9, 9*REGBYTES(sp)
266 LREG x10, 10*REGBYTES(sp)
267 LREG x11, 11*REGBYTES(sp)
268 LREG x12, 12*REGBYTES(sp)
269 LREG x13, 13*REGBYTES(sp)
270 LREG x14, 14*REGBYTES(sp)
271 LREG x15, 15*REGBYTES(sp)
272 LREG x16, 16*REGBYTES(sp)
273 LREG x17, 17*REGBYTES(sp)
274 LREG x18, 18*REGBYTES(sp)
275 LREG x19, 19*REGBYTES(sp)
276 LREG x20, 20*REGBYTES(sp)
277 LREG x21, 21*REGBYTES(sp)
278 LREG x22, 22*REGBYTES(sp)
279 LREG x23, 23*REGBYTES(sp)
280 LREG x24, 24*REGBYTES(sp)
281 LREG x25, 25*REGBYTES(sp)
282 LREG x26, 26*REGBYTES(sp)
283 LREG x27, 27*REGBYTES(sp)
284 LREG x28, 28*REGBYTES(sp)
285 LREG x29, 29*REGBYTES(sp)
286 LREG x30, 30*REGBYTES(sp)
287 LREG x31, 31*REGBYTES(sp)
288 addi sp, sp, 32*REGBYTES
289 MODE_PREFIX(ret)
diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts
deleted file mode 100644
index e48c298645..0000000000
--- a/arch/riscv/dts/ae350.dts
+++ /dev/null
@@ -1,229 +0,0 @@
1/dts-v1/;
2
3/ {
4 #address-cells = <2>;
5 #size-cells = <2>;
6 compatible = "andestech,ax25";
7 model = "andestech,ax25";
8
9 aliases {
10 uart0 = &serial0;
11 spi0 = &spi;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,38400n8 debug loglevel=7";
16 stdout-path = "uart0:38400n8";
17 };
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22 timebase-frequency = <60000000>;
23 CPU0: cpu@0 {
24 device_type = "cpu";
25 reg = <0>;
26 status = "okay";
27 compatible = "riscv";
28 riscv,isa = "rv64imafdc";
29 mmu-type = "riscv,sv39";
30 clock-frequency = <60000000>;
31 d-cache-size = <0x8000>;
32 d-cache-line-size = <32>;
33 CPU0_intc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
36 compatible = "riscv,cpu-intc";
37 };
38 };
39 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x00000000 0x0 0x40000000>;
44 };
45
46 soc {
47 #address-cells = <2>;
48 #size-cells = <2>;
49 compatible = "andestech,riscv-ae350-soc";
50 ranges;
51
52 plic0: interrupt-controller@e4000000 {
53 compatible = "riscv,plic0";
54 #address-cells = <2>;
55 #interrupt-cells = <2>;
56 interrupt-controller;
57 reg = <0x0 0xe4000000 0x0 0x2000000>;
58 riscv,ndev=<71>;
59 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
60 };
61
62 plic1: interrupt-controller@e6400000 {
63 compatible = "riscv,plic1";
64 #address-cells = <2>;
65 #interrupt-cells = <2>;
66 interrupt-controller;
67 reg = <0x0 0xe6400000 0x0 0x400000>;
68 riscv,ndev=<1>;
69 interrupts-extended = <&CPU0_intc 3>;
70 };
71
72 plmt0@e6000000 {
73 compatible = "riscv,plmt0";
74 interrupts-extended = <&CPU0_intc 7>;
75 reg = <0x0 0xe6000000 0x0 0x100000>;
76 };
77 };
78
79 spiclk: virt_100mhz {
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 clock-frequency = <100000000>;
83 };
84
85 timer0: timer@f0400000 {
86 compatible = "andestech,atcpit100";
87 reg = <0x0 0xf0400000 0x0 0x1000>;
88 clock-frequency = <60000000>;
89 interrupts = <3 4>;
90 interrupt-parent = <&plic0>;
91 };
92
93 serial0: serial@f0300000 {
94 compatible = "andestech,uart16550", "ns16550a";
95 reg = <0x0 0xf0300000 0x0 0x1000>;
96 interrupts = <9 4>;
97 clock-frequency = <19660800>;
98 reg-shift = <2>;
99 reg-offset = <32>;
100 no-loopback-test = <1>;
101 interrupt-parent = <&plic0>;
102 };
103
104 mac0: mac@e0100000 {
105 compatible = "andestech,atmac100";
106 reg = <0x0 0xe0100000 0x0 0x1000>;
107 interrupts = <19 4>;
108 interrupt-parent = <&plic0>;
109 };
110
111 mmc0: mmc@f0e00000 {
112 compatible = "andestech,atfsdc010";
113 max-frequency = <100000000>;
114 clock-freq-min-max = <400000 100000000>;
115 fifo-depth = <0x10>;
116 reg = <0x0 0xf0e00000 0x0 0x1000>;
117 interrupts = <18 4>;
118 cap-sd-highspeed;
119 interrupt-parent = <&plic0>;
120 };
121
122 dma0: dma@f0c00000 {
123 compatible = "andestech,atcdmac300";
124 reg = <0x0 0xf0c00000 0x0 0x1000>;
125 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
126 dma-channels = <8>;
127 interrupt-parent = <&plic0>;
128 };
129
130 lcd0: lcd@e0200000 {
131 compatible = "andestech,atflcdc100";
132 reg = <0x0 0xe0200000 0x0 0x1000>;
133 interrupts = <20 4>;
134 interrupt-parent = <&plic0>;
135 };
136
137 smc0: smc@e0400000 {
138 compatible = "andestech,atfsmc020";
139 reg = <0x0 0xe0400000 0x0 0x1000>;
140 };
141
142 snd0: snd@f0d00000 {
143 compatible = "andestech,atfac97";
144 reg = <0x0 0xf0d00000 0x0 0x1000>;
145 interrupts = <17 4>;
146 interrupt-parent = <&plic0>;
147 };
148
149 virtio_mmio@fe007000 {
150 interrupts = <0x17 0x4>;
151 interrupt-parent = <0x2>;
152 reg = <0x0 0xfe007000 0x0 0x1000>;
153 compatible = "virtio,mmio";
154 };
155
156 virtio_mmio@fe006000 {
157 interrupts = <0x16 0x4>;
158 interrupt-parent = <0x2>;
159 reg = <0x0 0xfe006000 0x0 0x1000>;
160 compatible = "virtio,mmio";
161 };
162
163 virtio_mmio@fe005000 {
164 interrupts = <0x15 0x4>;
165 interrupt-parent = <0x2>;
166 reg = <0x0 0xfe005000 0x0 0x1000>;
167 compatible = "virtio,mmio";
168 };
169
170 virtio_mmio@fe004000 {
171 interrupts = <0x14 0x4>;
172 interrupt-parent = <0x2>;
173 reg = <0x0 0xfe004000 0x0 0x1000>;
174 compatible = "virtio,mmio";
175 };
176
177 virtio_mmio@fe003000 {
178 interrupts = <0x13 0x4>;
179 interrupt-parent = <0x2>;
180 reg = <0x0 0xfe003000 0x0 0x1000>;
181 compatible = "virtio,mmio";
182 };
183
184 virtio_mmio@fe002000 {
185 interrupts = <0x12 0x4>;
186 interrupt-parent = <0x2>;
187 reg = <0x0 0xfe002000 0x0 0x1000>;
188 compatible = "virtio,mmio";
189 };
190
191 virtio_mmio@fe001000 {
192 interrupts = <0x11 0x4>;
193 interrupt-parent = <0x2>;
194 reg = <0x0 0xfe001000 0x0 0x1000>;
195 compatible = "virtio,mmio";
196 };
197
198 virtio_mmio@fe000000 {
199 interrupts = <0x10 0x4>;
200 interrupt-parent = <0x2>;
201 reg = <0x0 0xfe000000 0x0 0x1000>;
202 compatible = "virtio,mmio";
203 };
204
205 nor@0,0 {
206 compatible = "cfi-flash";
207 reg = <0x0 0x88000000 0x0 0x1000>;
208 bank-width = <2>;
209 device-width = <1>;
210 };
211
212 spi: spi@f0b00000 {
213 compatible = "andestech,atcspi200";
214 reg = <0x0 0xf0b00000 0x0 0x1000>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 num-cs = <1>;
218 clocks = <&spiclk>;
219 interrupts = <4 4>;
220 interrupt-parent = <&plic0>;
221 flash@0 {
222 compatible = "spi-flash";
223 spi-max-frequency = <50000000>;
224 reg = <0>;
225 spi-cpol;
226 spi-cpha;
227 };
228 };
229};
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 29624fdbb5..86136f542c 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -61,10 +61,12 @@
61 61
62#ifndef __ASSEMBLY__ 62#ifndef __ASSEMBLY__
63 63
64#define xcsr(csr) #csr
65
64#define csr_swap(csr, val) \ 66#define csr_swap(csr, val) \
65({ \ 67({ \
66 unsigned long __v = (unsigned long)(val); \ 68 unsigned long __v = (unsigned long)(val); \
67 __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ 69 __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
68 : "=r" (__v) : "rK" (__v) \ 70 : "=r" (__v) : "rK" (__v) \
69 : "memory"); \ 71 : "memory"); \
70 __v; \ 72 __v; \
@@ -73,7 +75,7 @@
73#define csr_read(csr) \ 75#define csr_read(csr) \
74({ \ 76({ \
75 register unsigned long __v; \ 77 register unsigned long __v; \
76 __asm__ __volatile__ ("csrr %0, " #csr \ 78 __asm__ __volatile__ ("csrr %0, " xcsr(csr) \
77 : "=r" (__v) : \ 79 : "=r" (__v) : \
78 : "memory"); \ 80 : "memory"); \
79 __v; \ 81 __v; \
@@ -82,7 +84,7 @@
82#define csr_write(csr, val) \ 84#define csr_write(csr, val) \
83({ \ 85({ \
84 unsigned long __v = (unsigned long)(val); \ 86 unsigned long __v = (unsigned long)(val); \
85 __asm__ __volatile__ ("csrw " #csr ", %0" \ 87 __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
86 : : "rK" (__v) \ 88 : : "rK" (__v) \
87 : "memory"); \ 89 : "memory"); \
88}) 90})
@@ -90,7 +92,7 @@
90#define csr_read_set(csr, val) \ 92#define csr_read_set(csr, val) \
91({ \ 93({ \
92 unsigned long __v = (unsigned long)(val); \ 94 unsigned long __v = (unsigned long)(val); \
93 __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ 95 __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
94 : "=r" (__v) : "rK" (__v) \ 96 : "=r" (__v) : "rK" (__v) \
95 : "memory"); \ 97 : "memory"); \
96 __v; \ 98 __v; \
@@ -99,7 +101,7 @@
99#define csr_set(csr, val) \ 101#define csr_set(csr, val) \
100({ \ 102({ \
101 unsigned long __v = (unsigned long)(val); \ 103 unsigned long __v = (unsigned long)(val); \
102 __asm__ __volatile__ ("csrs " #csr ", %0" \ 104 __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \
103 : : "rK" (__v) \ 105 : : "rK" (__v) \
104 : "memory"); \ 106 : "memory"); \
105}) 107})
@@ -107,7 +109,7 @@
107#define csr_read_clear(csr, val) \ 109#define csr_read_clear(csr, val) \
108({ \ 110({ \
109 unsigned long __v = (unsigned long)(val); \ 111 unsigned long __v = (unsigned long)(val); \
110 __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ 112 __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \
111 : "=r" (__v) : "rK" (__v) \ 113 : "=r" (__v) : "rK" (__v) \
112 : "memory"); \ 114 : "memory"); \
113 __v; \ 115 __v; \
@@ -116,7 +118,7 @@
116#define csr_clear(csr, val) \ 118#define csr_clear(csr, val) \
117({ \ 119({ \
118 unsigned long __v = (unsigned long)(val); \ 120 unsigned long __v = (unsigned long)(val); \
119 __asm__ __volatile__ ("csrc " #csr ", %0" \ 121 __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \
120 : : "rK" (__v) \ 122 : : "rK" (__v) \
121 : "memory"); \ 123 : "memory"); \
122}) 124})
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index 97cf906aa6..772668c74e 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -85,6 +85,21 @@
85#define IRQ_COP 12 85#define IRQ_COP 12
86#define IRQ_HOST 13 86#define IRQ_HOST 13
87 87
88#define CAUSE_MISALIGNED_FETCH 0
89#define CAUSE_FETCH_ACCESS 1
90#define CAUSE_ILLEGAL_INSTRUCTION 2
91#define CAUSE_BREAKPOINT 3
92#define CAUSE_MISALIGNED_LOAD 4
93#define CAUSE_LOAD_ACCESS 5
94#define CAUSE_MISALIGNED_STORE 6
95#define CAUSE_STORE_ACCESS 7
96#define CAUSE_USER_ECALL 8
97#define CAUSE_SUPERVISOR_ECALL 9
98#define CAUSE_MACHINE_ECALL 11
99#define CAUSE_FETCH_PAGE_FAULT 12
100#define CAUSE_LOAD_PAGE_FAULT 13
101#define CAUSE_STORE_PAGE_FAULT 15
102
88#define DEFAULT_RSTVEC 0x00001000 103#define DEFAULT_RSTVEC 0x00001000
89#define DEFAULT_NMIVEC 0x00001004 104#define DEFAULT_NMIVEC 0x00001004
90#define DEFAULT_MTVEC 0x00001010 105#define DEFAULT_MTVEC 0x00001010
@@ -152,6 +167,227 @@
152#define RISCV_PGSHIFT 12 167#define RISCV_PGSHIFT 12
153#define RISCV_PGSIZE BIT(RISCV_PGSHIFT) 168#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
154 169
170/* CSR numbers */
171#define CSR_FFLAGS 0x1
172#define CSR_FRM 0x2
173#define CSR_FCSR 0x3
174
175#define CSR_SSTATUS 0x100
176#define CSR_SEDELEG 0x102
177#define CSR_SIDELEG 0x103
178#define CSR_SIE 0x104
179#define CSR_STVEC 0x105
180#define CSR_SCOUNTEREN 0x106
181#define CSR_SSCRATCH 0x140
182#define CSR_SEPC 0x141
183#define CSR_SCAUSE 0x142
184#define CSR_STVAL 0x143
185#define CSR_SIP 0x144
186#define CSR_SATP 0x180
187
188#define CSR_MSTATUS 0x300
189#define CSR_MISA 0x301
190#define CSR_MEDELEG 0x302
191#define CSR_MIDELEG 0x303
192#define CSR_MIE 0x304
193#define CSR_MTVEC 0x305
194#define CSR_MCOUNTEREN 0x306
195#define CSR_MHPMEVENT3 0x323
196#define CSR_MHPMEVENT4 0x324
197#define CSR_MHPMEVENT5 0x325
198#define CSR_MHPMEVENT6 0x326
199#define CSR_MHPMEVENT7 0x327
200#define CSR_MHPMEVENT8 0x328
201#define CSR_MHPMEVENT9 0x329
202#define CSR_MHPMEVENT10 0x32a
203#define CSR_MHPMEVENT11 0x32b
204#define CSR_MHPMEVENT12 0x32c
205#define CSR_MHPMEVENT13 0x32d
206#define CSR_MHPMEVENT14 0x32e
207#define CSR_MHPMEVENT15 0x32f
208#define CSR_MHPMEVENT16 0x330
209#define CSR_MHPMEVENT17 0x331
210#define CSR_MHPMEVENT18 0x332
211#define CSR_MHPMEVENT19 0x333
212#define CSR_MHPMEVENT20 0x334
213#define CSR_MHPMEVENT21 0x335
214#define CSR_MHPMEVENT22 0x336
215#define CSR_MHPMEVENT23 0x337
216#define CSR_MHPMEVENT24 0x338
217#define CSR_MHPMEVENT25 0x339
218#define CSR_MHPMEVENT26 0x33a
219#define CSR_MHPMEVENT27 0x33b
220#define CSR_MHPMEVENT28 0x33c
221#define CSR_MHPMEVENT29 0x33d
222#define CSR_MHPMEVENT30 0x33e
223#define CSR_MHPMEVENT31 0x33f
224#define CSR_MSCRATCH 0x340
225#define CSR_MEPC 0x341
226#define CSR_MCAUSE 0x342
227#define CSR_MTVAL 0x343
228#define CSR_MIP 0x344
229#define CSR_PMPCFG0 0x3a0
230#define CSR_PMPCFG1 0x3a1
231#define CSR_PMPCFG2 0x3a2
232#define CSR_PMPCFG3 0x3a3
233#define CSR_PMPADDR0 0x3b0
234#define CSR_PMPADDR1 0x3b1
235#define CSR_PMPADDR2 0x3b2
236#define CSR_PMPADDR3 0x3b3
237#define CSR_PMPADDR4 0x3b4
238#define CSR_PMPADDR5 0x3b5
239#define CSR_PMPADDR6 0x3b6
240#define CSR_PMPADDR7 0x3b7
241#define CSR_PMPADDR8 0x3b8
242#define CSR_PMPADDR9 0x3b9
243#define CSR_PMPADDR10 0x3ba
244#define CSR_PMPADDR11 0x3bb
245#define CSR_PMPADDR12 0x3bc
246#define CSR_PMPADDR13 0x3bd
247#define CSR_PMPADDR14 0x3be
248#define CSR_PMPADDR15 0x3bf
249
250#define CSR_TSELECT 0x7a0
251#define CSR_TDATA1 0x7a1
252#define CSR_TDATA2 0x7a2
253#define CSR_TDATA3 0x7a3
254#define CSR_DCSR 0x7b0
255#define CSR_DPC 0x7b1
256#define CSR_DSCRATCH 0x7b2
257
258#define CSR_MCYCLE 0xb00
259#define CSR_MINSTRET 0xb02
260#define CSR_MHPMCOUNTER3 0xb03
261#define CSR_MHPMCOUNTER4 0xb04
262#define CSR_MHPMCOUNTER5 0xb05
263#define CSR_MHPMCOUNTER6 0xb06
264#define CSR_MHPMCOUNTER7 0xb07
265#define CSR_MHPMCOUNTER8 0xb08
266#define CSR_MHPMCOUNTER9 0xb09
267#define CSR_MHPMCOUNTER10 0xb0a
268#define CSR_MHPMCOUNTER11 0xb0b
269#define CSR_MHPMCOUNTER12 0xb0c
270#define CSR_MHPMCOUNTER13 0xb0d
271#define CSR_MHPMCOUNTER14 0xb0e
272#define CSR_MHPMCOUNTER15 0xb0f
273#define CSR_MHPMCOUNTER16 0xb10
274#define CSR_MHPMCOUNTER17 0xb11
275#define CSR_MHPMCOUNTER18 0xb12
276#define CSR_MHPMCOUNTER19 0xb13
277#define CSR_MHPMCOUNTER20 0xb14
278#define CSR_MHPMCOUNTER21 0xb15
279#define CSR_MHPMCOUNTER22 0xb16
280#define CSR_MHPMCOUNTER23 0xb17
281#define CSR_MHPMCOUNTER24 0xb18
282#define CSR_MHPMCOUNTER25 0xb19
283#define CSR_MHPMCOUNTER26 0xb1a
284#define CSR_MHPMCOUNTER27 0xb1b
285#define CSR_MHPMCOUNTER28 0xb1c
286#define CSR_MHPMCOUNTER29 0xb1d
287#define CSR_MHPMCOUNTER30 0xb1e
288#define CSR_MHPMCOUNTER31 0xb1f
289#define CSR_MCYCLEH 0xb80
290#define CSR_MINSTRETH 0xb82
291#define CSR_MHPMCOUNTER3H 0xb83
292#define CSR_MHPMCOUNTER4H 0xb84
293#define CSR_MHPMCOUNTER5H 0xb85
294#define CSR_MHPMCOUNTER6H 0xb86
295#define CSR_MHPMCOUNTER7H 0xb87
296#define CSR_MHPMCOUNTER8H 0xb88
297#define CSR_MHPMCOUNTER9H 0xb89
298#define CSR_MHPMCOUNTER10H 0xb8a
299#define CSR_MHPMCOUNTER11H 0xb8b
300#define CSR_MHPMCOUNTER12H 0xb8c
301#define CSR_MHPMCOUNTER13H 0xb8d
302#define CSR_MHPMCOUNTER14H 0xb8e
303#define CSR_MHPMCOUNTER15H 0xb8f
304#define CSR_MHPMCOUNTER16H 0xb90
305#define CSR_MHPMCOUNTER17H 0xb91
306#define CSR_MHPMCOUNTER18H 0xb92
307#define CSR_MHPMCOUNTER19H 0xb93
308#define CSR_MHPMCOUNTER20H 0xb94
309#define CSR_MHPMCOUNTER21H 0xb95
310#define CSR_MHPMCOUNTER22H 0xb96
311#define CSR_MHPMCOUNTER23H 0xb97
312#define CSR_MHPMCOUNTER24H 0xb98
313#define CSR_MHPMCOUNTER25H 0xb99
314#define CSR_MHPMCOUNTER26H 0xb9a
315#define CSR_MHPMCOUNTER27H 0xb9b
316#define CSR_MHPMCOUNTER28H 0xb9c
317#define CSR_MHPMCOUNTER29H 0xb9d
318#define CSR_MHPMCOUNTER30H 0xb9e
319#define CSR_MHPMCOUNTER31H 0xb9f
320
321#define CSR_CYCLE 0xc00
322#define CSR_TIME 0xc01
323#define CSR_INSTRET 0xc02
324#define CSR_HPMCOUNTER3 0xc03
325#define CSR_HPMCOUNTER4 0xc04
326#define CSR_HPMCOUNTER5 0xc05
327#define CSR_HPMCOUNTER6 0xc06
328#define CSR_HPMCOUNTER7 0xc07
329#define CSR_HPMCOUNTER8 0xc08
330#define CSR_HPMCOUNTER9 0xc09
331#define CSR_HPMCOUNTER10 0xc0a
332#define CSR_HPMCOUNTER11 0xc0b
333#define CSR_HPMCOUNTER12 0xc0c
334#define CSR_HPMCOUNTER13 0xc0d
335#define CSR_HPMCOUNTER14 0xc0e
336#define CSR_HPMCOUNTER15 0xc0f
337#define CSR_HPMCOUNTER16 0xc10
338#define CSR_HPMCOUNTER17 0xc11
339#define CSR_HPMCOUNTER18 0xc12
340#define CSR_HPMCOUNTER19 0xc13
341#define CSR_HPMCOUNTER20 0xc14
342#define CSR_HPMCOUNTER21 0xc15
343#define CSR_HPMCOUNTER22 0xc16
344#define CSR_HPMCOUNTER23 0xc17
345#define CSR_HPMCOUNTER24 0xc18
346#define CSR_HPMCOUNTER25 0xc19
347#define CSR_HPMCOUNTER26 0xc1a
348#define CSR_HPMCOUNTER27 0xc1b
349#define CSR_HPMCOUNTER28 0xc1c
350#define CSR_HPMCOUNTER29 0xc1d
351#define CSR_HPMCOUNTER30 0xc1e
352#define CSR_HPMCOUNTER31 0xc1f
353#define CSR_CYCLEH 0xc80
354#define CSR_TIMEH 0xc81
355#define CSR_INSTRETH 0xc82
356#define CSR_HPMCOUNTER3H 0xc83
357#define CSR_HPMCOUNTER4H 0xc84
358#define CSR_HPMCOUNTER5H 0xc85
359#define CSR_HPMCOUNTER6H 0xc86
360#define CSR_HPMCOUNTER7H 0xc87
361#define CSR_HPMCOUNTER8H 0xc88
362#define CSR_HPMCOUNTER9H 0xc89
363#define CSR_HPMCOUNTER10H 0xc8a
364#define CSR_HPMCOUNTER11H 0xc8b
365#define CSR_HPMCOUNTER12H 0xc8c
366#define CSR_HPMCOUNTER13H 0xc8d
367#define CSR_HPMCOUNTER14H 0xc8e
368#define CSR_HPMCOUNTER15H 0xc8f
369#define CSR_HPMCOUNTER16H 0xc90
370#define CSR_HPMCOUNTER17H 0xc91
371#define CSR_HPMCOUNTER18H 0xc92
372#define CSR_HPMCOUNTER19H 0xc93
373#define CSR_HPMCOUNTER20H 0xc94
374#define CSR_HPMCOUNTER21H 0xc95
375#define CSR_HPMCOUNTER22H 0xc96
376#define CSR_HPMCOUNTER23H 0xc97
377#define CSR_HPMCOUNTER24H 0xc98
378#define CSR_HPMCOUNTER25H 0xc99
379#define CSR_HPMCOUNTER26H 0xc9a
380#define CSR_HPMCOUNTER27H 0xc9b
381#define CSR_HPMCOUNTER28H 0xc9c
382#define CSR_HPMCOUNTER29H 0xc9d
383#define CSR_HPMCOUNTER30H 0xc9e
384#define CSR_HPMCOUNTER31H 0xc9f
385
386#define CSR_MVENDORID 0xf11
387#define CSR_MARCHID 0xf12
388#define CSR_MIMPID 0xf13
389#define CSR_MHARTID 0xf14
390
155#endif /* __riscv */ 391#endif /* __riscv */
156 392
157#endif /* RISCV_CSR_ENCODING_H */ 393#endif /* RISCV_CSR_ENCODING_H */
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 4d5d623725..a3a342c6e1 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -12,6 +12,10 @@
12 12
13/* Architecture-specific global data */ 13/* Architecture-specific global data */
14struct arch_global_data { 14struct arch_global_data {
15 long boot_hart; /* boot hart id */
16#ifdef CONFIG_SIFIVE_CLINT
17 void __iomem *clint; /* clint base address */
18#endif
15}; 19};
16 20
17#include <asm-generic/global_data.h> 21#include <asm-generic/global_data.h>
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
new file mode 100644
index 0000000000..d311ee6b45
--- /dev/null
+++ b/arch/riscv/include/asm/syscon.h
@@ -0,0 +1,19 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#ifndef _ASM_SYSCON_H
7#define _ASM_SYSCON_H
8
9/*
10 * System controllers in a RISC-V system
11 *
12 * So far only SiFive's Core Local Interruptor (CLINT) is defined.
13 */
14enum {
15 RISCV_NONE,
16 RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
17};
18
19#endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index b58db89752..edfa61690c 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -9,6 +9,8 @@
9obj-$(CONFIG_CMD_BOOTM) += bootm.o 9obj-$(CONFIG_CMD_BOOTM) += bootm.o
10obj-$(CONFIG_CMD_GO) += boot.o 10obj-$(CONFIG_CMD_GO) += boot.o
11obj-y += cache.o 11obj-y += cache.o
12obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
13obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
12obj-y += interrupts.o 14obj-y += interrupts.o
13obj-y += reset.o 15obj-y += reset.o
14obj-y += setjmp.o 16obj-y += setjmp.o
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
new file mode 100644
index 0000000000..e0b71f5691
--- /dev/null
+++ b/arch/riscv/lib/asm-offsets.c
@@ -0,0 +1,19 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * From arch/x86/lib/asm-offsets.c
6 *
7 * This program is used to generate definitions needed by
8 * assembly language modules.
9 */
10
11#include <common.h>
12#include <linux/kbuild.h>
13
14int main(void)
15{
16 DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
17
18 return 0;
19}
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 124aeefff8..f36b8702ef 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -86,14 +86,14 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
86 86
87 bootstage_mark(BOOTSTAGE_ID_RUN_OS); 87 bootstage_mark(BOOTSTAGE_ID_RUN_OS);
88 88
89 debug("## Transferring control to Linux (at address %08lx) ...\n", 89 debug("## Transferring control to kernel (at address %08lx) ...\n",
90 (ulong)kernel); 90 (ulong)kernel);
91 91
92 announce_and_cleanup(fake); 92 announce_and_cleanup(fake);
93 93
94 if (!fake) { 94 if (!fake) {
95 if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) 95 if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
96 kernel(csr_read(mhartid), images->ft_addr); 96 kernel(gd->arch.boot_hart, images->ft_addr);
97 } 97 }
98} 98}
99 99
@@ -118,3 +118,9 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
118 boot_jump_linux(images, flag); 118 boot_jump_linux(images, flag);
119 return 0; 119 return 0;
120} 120}
121
122int do_bootm_vxworks(int flag, int argc, char * const argv[],
123 bootm_headers_t *images)
124{
125 return do_bootm_linux(flag, argc, argv, images);
126}
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 3aff006977..e185933b01 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -12,7 +12,36 @@
12#include <asm/system.h> 12#include <asm/system.h>
13#include <asm/encoding.h> 13#include <asm/encoding.h>
14 14
15static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs); 15static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
16{
17 static const char * const exception_code[] = {
18 "Instruction address misaligned",
19 "Instruction access fault",
20 "Illegal instruction",
21 "Breakpoint",
22 "Load address misaligned",
23 "Load access fault",
24 "Store/AMO address misaligned",
25 "Store/AMO access fault",
26 "Environment call from U-mode",
27 "Environment call from S-mode",
28 "Reserved",
29 "Environment call from M-mode",
30 "Instruction page fault",
31 "Load page fault",
32 "Reserved",
33 "Store/AMO page fault",
34 };
35
36 if (code < ARRAY_SIZE(exception_code)) {
37 printf("exception code: %ld , %s , epc %lx , ra %lx\n",
38 code, exception_code[code], epc, regs->ra);
39 } else {
40 printf("Reserved\n");
41 }
42
43 hang();
44}
16 45
17int interrupt_init(void) 46int interrupt_init(void)
18{ 47{
@@ -72,34 +101,3 @@ __attribute__((weak)) void external_interrupt(struct pt_regs *regs)
72__attribute__((weak)) void timer_interrupt(struct pt_regs *regs) 101__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
73{ 102{
74} 103}
75
76static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
77{
78 static const char * const exception_code[] = {
79 "Instruction address misaligned",
80 "Instruction access fault",
81 "Illegal instruction",
82 "Breakpoint",
83 "Load address misaligned",
84 "Load access fault",
85 "Store/AMO address misaligned",
86 "Store/AMO access fault",
87 "Environment call from U-mode",
88 "Environment call from S-mode",
89 "Reserved",
90 "Environment call from M-mode",
91 "Instruction page fault",
92 "Load page fault",
93 "Reserved",
94 "Store/AMO page fault",
95 };
96
97 if (code < ARRAY_SIZE(exception_code)) {
98 printf("exception code: %ld , %s , epc %lx , ra %lx\n",
99 code, exception_code[code], epc, regs->ra);
100 } else {
101 printf("Reserved\n");
102 }
103
104 hang();
105}
diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c
new file mode 100644
index 0000000000..e128d7fce6
--- /dev/null
+++ b/arch/riscv/lib/rdtime.c
@@ -0,0 +1,38 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Anup Patel <anup@brainfault.org>
4 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
5 *
6 * The riscv_get_time() API implementation that is using the
7 * standard rdtime instruction.
8 */
9
10#include <common.h>
11
12/* Implement the API required by RISC-V timer driver */
13int riscv_get_time(u64 *time)
14{
15#ifdef CONFIG_64BIT
16 u64 n;
17
18 __asm__ __volatile__ (
19 "rdtime %0"
20 : "=r" (n));
21
22 *time = n;
23#else
24 u32 lo, hi, tmp;
25
26 __asm__ __volatile__ (
27 "1:\n"
28 "rdtimeh %0\n"
29 "rdtime %1\n"
30 "rdtimeh %2\n"
31 "bne %0, %2, 1b"
32 : "=&r" (hi), "=&r" (lo), "=&r" (tmp));
33
34 *time = ((u64)hi << 32) | lo;
35#endif
36
37 return 0;
38}
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
new file mode 100644
index 0000000000..d24e0d585b
--- /dev/null
+++ b/arch/riscv/lib/sifive_clint.c
@@ -0,0 +1,84 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
6 * The CLINT block holds memory-mapped control and status registers
7 * associated with software and timer interrupts.
8 */
9
10#include <common.h>
11#include <dm.h>
12#include <regmap.h>
13#include <syscon.h>
14#include <asm/io.h>
15#include <asm/syscon.h>
16
17/* MSIP registers */
18#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
19/* mtime compare register */
20#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
21/* mtime register */
22#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
23
24DECLARE_GLOBAL_DATA_PTR;
25
26#define CLINT_BASE_GET(void) \
27 do { \
28 long *ret; \
29 \
30 if (!gd->arch.clint) { \
31 ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \
32 if (IS_ERR(ret)) \
33 return PTR_ERR(ret); \
34 gd->arch.clint = ret; \
35 } \
36 } while (0)
37
38int riscv_get_time(u64 *time)
39{
40 CLINT_BASE_GET();
41
42 *time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
43
44 return 0;
45}
46
47int riscv_set_timecmp(int hart, u64 cmp)
48{
49 CLINT_BASE_GET();
50
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
52
53 return 0;
54}
55
56int riscv_send_ipi(int hart)
57{
58 CLINT_BASE_GET();
59
60 writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
61
62 return 0;
63}
64
65int riscv_clear_ipi(int hart)
66{
67 CLINT_BASE_GET();
68
69 writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
70
71 return 0;
72}
73
74static const struct udevice_id sifive_clint_ids[] = {
75 { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
76 { }
77};
78
79U_BOOT_DRIVER(sifive_clint) = {
80 .name = "sifive_clint",
81 .id = UCLASS_SYSCON,
82 .of_match = sifive_clint_ids,
83 .flags = DM_FLAG_PRE_RELOC,
84};
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index bb69ea3489..44cb302f70 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -21,4 +21,8 @@ config ENV_SIZE
21config ENV_OFFSET 21config ENV_OFFSET
22 default 0x140000 if ENV_IS_IN_SPI_FLASH 22 default 0x140000 if ENV_IS_IN_SPI_FLASH
23 23
24config BOARD_SPECIFIC_OPTIONS # dummy
25 def_bool y
26 select RISCV_NDS
27
24endif 28endif
diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ax25-ae350/MAINTAINERS
index d87446ee1c..b0a99e4ac4 100644
--- a/board/AndesTech/ax25-ae350/MAINTAINERS
+++ b/board/AndesTech/ax25-ae350/MAINTAINERS
@@ -3,6 +3,5 @@ M: Rick Chen <rick@andestech.com>
3S: Maintained 3S: Maintained
4F: board/AndesTech/ax25-ae350/ 4F: board/AndesTech/ax25-ae350/
5F: include/configs/ax25-ae350.h 5F: include/configs/ax25-ae350.h
6F: configs/a25-ae350_32_defconfig 6F: configs/ae350_rv32_defconfig
7F: configs/ax25-ae350_64_defconfig 7F: configs/ae350_rv64_defconfig
8F: configs/ax25-ae350_defconfig
diff --git a/board/embest/mx6boards/MAINTAINERS b/board/embest/mx6boards/MAINTAINERS
index 0ffd4668b4..02756c58b3 100644
--- a/board/embest/mx6boards/MAINTAINERS
+++ b/board/embest/mx6boards/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/embest/mx6boards/
5F: include/configs/embestmx6boards.h 5F: include/configs/embestmx6boards.h
6F: configs/marsboard_defconfig 6F: configs/marsboard_defconfig
7F: configs/riotboard_defconfig 7F: configs/riotboard_defconfig
8F: configs/riotboard_spl_defconfig
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index 8930c36fe6..fed92aa88a 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -608,3 +608,51 @@ int checkboard(void)
608 608
609 return 0; 609 return 0;
610} 610}
611
612#ifdef CONFIG_SPL_BUILD
613#include <spl.h>
614
615void board_init_f(ulong dummy)
616{
617 u32 cputype = cpu_type(get_cpu_rev());
618
619 switch (cputype) {
620 case MXC_CPU_MX6SOLO:
621 board_type = BOARD_IS_RIOTBOARD;
622 break;
623 case MXC_CPU_MX6D:
624 board_type = BOARD_IS_MARSBOARD;
625 break;
626 }
627 arch_cpu_init();
628
629 /* setup GP timer */
630 timer_init();
631
632#ifdef CONFIG_SPL_SERIAL_SUPPORT
633 setup_iomux_uart();
634 preloader_console_init();
635#endif
636}
637
638void board_boot_order(u32 *spl_boot_list)
639{
640 spl_boot_list[0] = BOOT_DEVICE_MMC1;
641}
642
643/*
644 * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
645 * to pin 3 (ground).
646 */
647int spl_start_uboot(void)
648{
649 int gpio_key = IMX_GPIO_NR(4, 16);
650
651 gpio_direction_input(gpio_key);
652 if (gpio_get_value(gpio_key) == 0)
653 return 1;
654 else
655 return 0;
656}
657
658#endif
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 56bb5337d4..0d865acf10 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -18,6 +18,7 @@ config SYS_TEXT_BASE
18 18
19config BOARD_SPECIFIC_OPTIONS # dummy 19config BOARD_SPECIFIC_OPTIONS # dummy
20 def_bool y 20 def_bool y
21 select QEMU_RISCV
21 imply SYS_NS16550 22 imply SYS_NS16550
22 imply VIRTIO_MMIO 23 imply VIRTIO_MMIO
23 imply VIRTIO_NET 24 imply VIRTIO_NET
@@ -32,5 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
32 imply CMD_FAT 33 imply CMD_FAT
33 imply BOARD_LATE_INIT 34 imply BOARD_LATE_INIT
34 imply OF_BOARD_SETUP 35 imply OF_BOARD_SETUP
36 imply SIFIVE_SERIAL
35 37
36endif 38endif
diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig
new file mode 100644
index 0000000000..421b081c76
--- /dev/null
+++ b/board/freescale/imx8mq_evk/Kconfig
@@ -0,0 +1,12 @@
1if TARGET_IMX8MQ_EVK
2
3config SYS_BOARD
4 default "imx8mq_evk"
5
6config SYS_VENDOR
7 default "freescale"
8
9config SYS_CONFIG_NAME
10 default "imx8mq_evk"
11
12endif
diff --git a/board/freescale/imx8mq_evk/MAINTAINERS b/board/freescale/imx8mq_evk/MAINTAINERS
new file mode 100644
index 0000000000..a2e320cb10
--- /dev/null
+++ b/board/freescale/imx8mq_evk/MAINTAINERS
@@ -0,0 +1,6 @@
1i.MX8MQ EVK BOARD
2M: Peng Fan <peng.fan@nxp.com>
3S: Maintained
4F: board/freescale/imx8mq_evk/
5F: include/configs/imx8mq_evk.h
6F: configs/imx8mq_evk_defconfig
diff --git a/board/freescale/imx8mq_evk/Makefile b/board/freescale/imx8mq_evk/Makefile
new file mode 100644
index 0000000000..cf046963d2
--- /dev/null
+++ b/board/freescale/imx8mq_evk/Makefile
@@ -0,0 +1,12 @@
1#
2# Copyright 2017 NXP
3#
4# SPDX-License-Identifier: GPL-2.0+
5#
6
7obj-y += imx8mq_evk.o
8
9ifdef CONFIG_SPL_BUILD
10obj-y += spl.o
11obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
12endif
diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README
new file mode 100644
index 0000000000..07dbfb01fe
--- /dev/null
+++ b/board/freescale/imx8mq_evk/README
@@ -0,0 +1,36 @@
1U-Boot for the NXP i.MX8MQ EVK board
2
3Quick Start
4====================
5- Build the ARM Trusted firmware binary
6- Get ddr and hdmi fimware
7- Build U-Boot
8- Boot
9
10Get and Build the ARM Trusted firmware
11====================
12Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
13branch: imx_4.14.62_1.0.0_beta
14$ make PLAT=imx8mq bl31
15
16Get the ddr and hdmi firmware
17====================
18Note: srctree is U-Boot source directory
19$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
20$ chmod +x firmware-imx-7.9.bin
21$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
22$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee)
23
24Build U-Boot
25====================
26$ export ARCH=arm64
27$ export CROSS_COMPILE=aarch64-poky-linux-
28$ make imx8mq_evk_defconfig
29$ make flash.bin
30
31Burn the flash.bin to MicroSD card offset 33KB
32$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
33
34Boot
35====================
36Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
new file mode 100644
index 0000000000..54e0c38431
--- /dev/null
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -0,0 +1,130 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <malloc.h>
8#include <errno.h>
9#include <asm/io.h>
10#include <miiphy.h>
11#include <netdev.h>
12#include <asm/mach-imx/iomux-v3.h>
13#include <asm-generic/gpio.h>
14#include <fsl_esdhc.h>
15#include <mmc.h>
16#include <asm/arch/imx8mq_pins.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/mach-imx/gpio.h>
19#include <asm/mach-imx/mxc_i2c.h>
20#include <asm/arch/clock.h>
21#include <spl.h>
22#include <power/pmic.h>
23#include <power/pfuze100_pmic.h>
24#include "../common/pfuze.h"
25
26DECLARE_GLOBAL_DATA_PTR;
27
28#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
29
30#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
31
32static iomux_v3_cfg_t const wdog_pads[] = {
33 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
34};
35
36static iomux_v3_cfg_t const uart_pads[] = {
37 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
38 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39};
40
41int board_early_init_f(void)
42{
43 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
44
45 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
46 set_wdog_reset(wdog);
47
48 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
49
50 return 0;
51}
52
53int dram_init(void)
54{
55 /* rom_pointer[1] contains the size of TEE occupies */
56 if (rom_pointer[1])
57 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
58 else
59 gd->ram_size = PHYS_SDRAM_SIZE;
60
61 return 0;
62}
63
64#ifdef CONFIG_FEC_MXC
65#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
66static iomux_v3_cfg_t const fec1_rst_pads[] = {
67 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
68};
69
70static void setup_iomux_fec(void)
71{
72 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
73 ARRAY_SIZE(fec1_rst_pads));
74
75 gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
76 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
77 udelay(500);
78 gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
79}
80
81static int setup_fec(void)
82{
83 struct iomuxc_gpr_base_regs *gpr =
84 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
85
86 setup_iomux_fec();
87
88 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
89 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
90 return set_clk_enet(ENET_125MHZ);
91}
92
93int board_phy_config(struct phy_device *phydev)
94{
95 /* enable rgmii rxc skew and phy mode select to RGMII copper */
96 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
98
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
101
102 if (phydev->drv->config)
103 phydev->drv->config(phydev);
104 return 0;
105}
106#endif
107
108int board_init(void)
109{
110#ifdef CONFIG_FEC_MXC
111 setup_fec();
112#endif
113
114 return 0;
115}
116
117int board_mmc_get_env_dev(int devno)
118{
119 return devno;
120}
121
122int board_late_init(void)
123{
124#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
125 env_set("board_name", "EVK");
126 env_set("board_rev", "iMX8MQ");
127#endif
128
129 return 0;
130}
diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c
new file mode 100644
index 0000000000..f7ea799343
--- /dev/null
+++ b/board/freescale/imx8mq_evk/lpddr4_timing.c
@@ -0,0 +1,1320 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <linux/kernel.h>
7#include <common.h>
8#include <asm/arch/ddr.h>
9#include <asm/arch/lpddr4_define.h>
10
11#define WR_POST_EXT_3200 /* recommened to define */
12
13struct dram_cfg_param lpddr4_ddrc_cfg[] = {
14 /* Start to config, default 3200mbps */
15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
23#ifdef WR_POST_EXT_3200
24 { DDRC_INIT4(0), 0x00330008 },
25#else
26 { DDRC_INIT4(0), 0x00310008 },
27#endif
28 { DDRC_INIT6(0), 0x0066004a },
29 { DDRC_INIT7(0), 0x0006004a },
30
31 { DDRC_DRAMTMG0(0), 0x1A201B22 },
32 { DDRC_DRAMTMG1(0), 0x00060633 },
33 { DDRC_DRAMTMG3(0), 0x00C0C000 },
34 { DDRC_DRAMTMG4(0), 0x0F04080F },
35 { DDRC_DRAMTMG5(0), 0x02040C0C },
36 { DDRC_DRAMTMG6(0), 0x01010007 },
37 { DDRC_DRAMTMG7(0), 0x00000401 },
38 { DDRC_DRAMTMG12(0), 0x00020600 },
39 { DDRC_DRAMTMG13(0), 0x0C100002 },
40 { DDRC_DRAMTMG14(0), 0x000000E6 },
41 { DDRC_DRAMTMG17(0), 0x00A00050 },
42
43 { DDRC_ZQCTL0(0), 0x03200018 },
44 { DDRC_ZQCTL1(0), 0x028061A8 },
45 { DDRC_ZQCTL2(0), 0x00000000 },
46
47 { DDRC_DFITMG0(0), 0x0497820A },
48 { DDRC_DFITMG1(0), 0x00080303 },
49 { DDRC_DFIUPD0(0), 0xE0400018 },
50 { DDRC_DFIUPD1(0), 0x00DF00E4 },
51 { DDRC_DFIUPD2(0), 0x80000000 },
52 { DDRC_DFIMISC(0), 0x00000011 },
53 { DDRC_DFITMG2(0), 0x0000170A },
54
55 { DDRC_DBICTL(0), 0x00000001 },
56 { DDRC_DFIPHYMSTR(0), 0x00000001 },
57 { DDRC_RANKCTL(0), 0x00000c99 },
58 { DDRC_DRAMTMG2(0), 0x070E171a },
59
60 /* address mapping */
61 { DDRC_ADDRMAP0(0), 0x00000015 },
62 { DDRC_ADDRMAP3(0), 0x00000000 },
63 { DDRC_ADDRMAP4(0), 0x00001F1F },
64 /* bank interleave */
65 { DDRC_ADDRMAP1(0), 0x00080808 },
66 { DDRC_ADDRMAP5(0), 0x07070707 },
67 { DDRC_ADDRMAP6(0), 0x08080707 },
68
69 /* performance setting */
70 { DDRC_ODTCFG(0), 0x0b060908 },
71 { DDRC_ODTMAP(0), 0x00000000 },
72 { DDRC_SCHED(0), 0x29511505 },
73 { DDRC_SCHED1(0), 0x0000002c },
74 { DDRC_PERFHPR1(0), 0x5900575b },
75 { DDRC_PERFLPR1(0), 0x00000009 },
76 { DDRC_PERFWR1(0), 0x02005574 },
77 { DDRC_DBG0(0), 0x00000016 },
78 { DDRC_DBG1(0), 0x00000000 },
79 { DDRC_DBGCMD(0), 0x00000000 },
80 { DDRC_SWCTL(0), 0x00000001 },
81 { DDRC_POISONCFG(0), 0x00000011 },
82 { DDRC_PCCFG(0), 0x00000111 },
83 { DDRC_PCFGR_0(0), 0x000010f3 },
84 { DDRC_PCFGW_0(0), 0x000072ff },
85 { DDRC_PCTRL_0(0), 0x00000001 },
86 { DDRC_PCFGQOS0_0(0), 0x01110d00 },
87 { DDRC_PCFGQOS1_0(0), 0x00620790 },
88 { DDRC_PCFGWQOS0_0(0), 0x00100001 },
89 { DDRC_PCFGWQOS1_0(0), 0x0000041f },
90
91 /* Frequency 1: 400mbps */
92 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
93 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
94 { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
95 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
96 { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
97 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
98 { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
99 { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
100 { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
101 { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
102 { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
103 { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
104 { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
105 { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
106 { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
107 { DDRC_FREQ1_INIT3(0), 0x00840000 },
108 { DDRC_FREQ1_INIT4(0), 0x00310008 },
109 { DDRC_FREQ1_INIT6(0), 0x0066004a },
110 { DDRC_FREQ1_INIT7(0), 0x0006004a },
111
112 /* Frequency 2: 100mbps */
113 { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
114 { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
115 { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
116 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
117 { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
118 { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
119 { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
120 { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
121 { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
122 { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
123 { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
124 { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
125 { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
126 { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
127 { DDRC_FREQ2_INIT3(0), 0x00840000 },
128 { DDRC_FREQ2_INIT4(0), 0x00310008 },
129 { DDRC_FREQ2_INIT6(0), 0x0066004a },
130 { DDRC_FREQ2_INIT7(0), 0x0006004a },
131};
132
133/* PHY Initialize Configuration */
134struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
135 { 0x20110, 0x02 },
136 { 0x20111, 0x03 },
137 { 0x20112, 0x04 },
138 { 0x20113, 0x05 },
139 { 0x20114, 0x00 },
140 { 0x20115, 0x01 },
141
142 { 0x1005f, 0x1ff },
143 { 0x1015f, 0x1ff },
144 { 0x1105f, 0x1ff },
145 { 0x1115f, 0x1ff },
146 { 0x1205f, 0x1ff },
147 { 0x1215f, 0x1ff },
148 { 0x1305f, 0x1ff },
149 { 0x1315f, 0x1ff },
150
151 { 0x11005f, 0x1ff },
152 { 0x11015f, 0x1ff },
153 { 0x11105f, 0x1ff },
154 { 0x11115f, 0x1ff },
155 { 0x11205f, 0x1ff },
156 { 0x11215f, 0x1ff },
157 { 0x11305f, 0x1ff },
158 { 0x11315f, 0x1ff },
159
160 { 0x21005f, 0x1ff },
161 { 0x21015f, 0x1ff },
162 { 0x21105f, 0x1ff },
163 { 0x21115f, 0x1ff },
164 { 0x21205f, 0x1ff },
165 { 0x21215f, 0x1ff },
166 { 0x21305f, 0x1ff },
167 { 0x21315f, 0x1ff },
168
169 { 0x55, 0x1ff },
170 { 0x1055, 0x1ff },
171 { 0x2055, 0x1ff },
172 { 0x3055, 0x1ff },
173 { 0x4055, 0x1ff },
174 { 0x5055, 0x1ff },
175 { 0x6055, 0x1ff },
176 { 0x7055, 0x1ff },
177 { 0x8055, 0x1ff },
178 { 0x9055, 0x1ff },
179
180 { 0x200c5, 0x19 },
181 { 0x1200c5, 0x7 },
182 { 0x2200c5, 0x7 },
183
184 { 0x2002e, 0x2 },
185 { 0x12002e, 0x2 },
186 { 0x22002e, 0x2 },
187
188 { 0x90204, 0x0 },
189 { 0x190204, 0x0 },
190 { 0x290204, 0x0 },
191
192#ifdef WR_POST_EXT_3200
193 { 0x20024, 0xeb },
194#else
195 { 0x20024, 0xab },
196#endif
197 { 0x2003a, 0x0 },
198 { 0x120024, 0xab },
199 { 0x2003a, 0x0 },
200 { 0x220024, 0xab },
201 { 0x2003a, 0x0 },
202 { 0x20056, 0x3 },
203 { 0x120056, 0xa },
204 { 0x220056, 0xa },
205 { 0x1004d, 0xe00 },
206 { 0x1014d, 0xe00 },
207 { 0x1104d, 0xe00 },
208 { 0x1114d, 0xe00 },
209 { 0x1204d, 0xe00 },
210 { 0x1214d, 0xe00 },
211 { 0x1304d, 0xe00 },
212 { 0x1314d, 0xe00 },
213 { 0x11004d, 0xe00 },
214 { 0x11014d, 0xe00 },
215 { 0x11104d, 0xe00 },
216 { 0x11114d, 0xe00 },
217 { 0x11204d, 0xe00 },
218 { 0x11214d, 0xe00 },
219 { 0x11304d, 0xe00 },
220 { 0x11314d, 0xe00 },
221 { 0x21004d, 0xe00 },
222 { 0x21014d, 0xe00 },
223 { 0x21104d, 0xe00 },
224 { 0x21114d, 0xe00 },
225 { 0x21204d, 0xe00 },
226 { 0x21214d, 0xe00 },
227 { 0x21304d, 0xe00 },
228 { 0x21314d, 0xe00 },
229
230 { 0x10049, 0xfbe },
231 { 0x10149, 0xfbe },
232 { 0x11049, 0xfbe },
233 { 0x11149, 0xfbe },
234 { 0x12049, 0xfbe },
235 { 0x12149, 0xfbe },
236 { 0x13049, 0xfbe },
237 { 0x13149, 0xfbe },
238 { 0x110049, 0xfbe },
239 { 0x110149, 0xfbe },
240 { 0x111049, 0xfbe },
241 { 0x111149, 0xfbe },
242 { 0x112049, 0xfbe },
243 { 0x112149, 0xfbe },
244 { 0x113049, 0xfbe },
245 { 0x113149, 0xfbe },
246 { 0x210049, 0xfbe },
247 { 0x210149, 0xfbe },
248 { 0x211049, 0xfbe },
249 { 0x211149, 0xfbe },
250 { 0x212049, 0xfbe },
251 { 0x212149, 0xfbe },
252 { 0x213049, 0xfbe },
253 { 0x213149, 0xfbe },
254
255 { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
256 { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
257 { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
258 { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
259 { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
260 { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
261 { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
262 { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
263 { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
264 { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
265
266 { 0x20018, 0x3 },
267 { 0x20075, 0x4 },
268 { 0x20050, 0x0 },
269 { 0x20008, 0x320 },
270 { 0x120008, 0x64 },
271 { 0x220008, 0x19 },
272 { 0x20088, 0x9 },
273 { 0x200b2, 0x104 },
274 { 0x10043, 0x5a1 },
275 { 0x10143, 0x5a1 },
276 { 0x11043, 0x5a1 },
277 { 0x11143, 0x5a1 },
278 { 0x12043, 0x5a1 },
279 { 0x12143, 0x5a1 },
280 { 0x13043, 0x5a1 },
281 { 0x13143, 0x5a1 },
282 { 0x1200b2, 0x104 },
283 { 0x110043, 0x5a1 },
284 { 0x110143, 0x5a1 },
285 { 0x111043, 0x5a1 },
286 { 0x111143, 0x5a1 },
287 { 0x112043, 0x5a1 },
288 { 0x112143, 0x5a1 },
289 { 0x113043, 0x5a1 },
290 { 0x113143, 0x5a1 },
291 { 0x2200b2, 0x104 },
292 { 0x210043, 0x5a1 },
293 { 0x210143, 0x5a1 },
294 { 0x211043, 0x5a1 },
295 { 0x211143, 0x5a1 },
296 { 0x212043, 0x5a1 },
297 { 0x212143, 0x5a1 },
298 { 0x213043, 0x5a1 },
299 { 0x213143, 0x5a1 },
300 { 0x200fa, 0x1 },
301 { 0x1200fa, 0x1 },
302 { 0x2200fa, 0x1 },
303 { 0x20019, 0x1 },
304 { 0x120019, 0x1 },
305 { 0x220019, 0x1 },
306 { 0x200f0, 0x660 },
307 { 0x200f1, 0x0 },
308 { 0x200f2, 0x4444 },
309 { 0x200f3, 0x8888 },
310 { 0x200f4, 0x5665 },
311 { 0x200f5, 0x0 },
312 { 0x200f6, 0x0 },
313 { 0x200f7, 0xf000 },
314 { 0x20025, 0x0 },
315 { 0x2002d, 0x0 },
316 { 0x12002d, 0x0 },
317 { 0x22002d, 0x0 },
318
319 { 0x200c7, 0x80 },
320 { 0x1200c7, 0x80 },
321 { 0x2200c7, 0x80 },
322 { 0x200ca, 0x106 },
323 { 0x1200ca, 0x106 },
324 { 0x2200ca, 0x106 },
325};
326
327/* P0 message block paremeter for training firmware */
328struct dram_cfg_param lpddr4_fsp0_cfg[] = {
329 { 0xd0000, 0x0 },
330 { 0x54000, 0x0 },
331 { 0x54001, 0x0 },
332 { 0x54002, 0x0 },
333 { 0x54003, 0xc80 },
334 { 0x54004, 0x2 },
335 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
336 { 0x54006, LPDDR4_PHY_VREF_VALUE },
337 { 0x54007, 0x0 },
338 { 0x54008, 0x131f },
339 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
340 { 0x5400a, 0x0 },
341 { 0x5400b, 0x2 },
342 { 0x5400c, 0x0 },
343 { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
344 { 0x5400e, 0x0 },
345 { 0x5400f, 0x0 },
346 { 0x54010, 0x0 },
347 { 0x54011, 0x0 },
348 { 0x54012, 0x310 },
349 { 0x54013, 0x0 },
350 { 0x54014, 0x0 },
351 { 0x54015, 0x0 },
352 { 0x54016, 0x0 },
353 { 0x54017, 0x0 },
354 { 0x54018, 0x0 },
355
356 { 0x54019, 0x2dd4 },
357#ifdef WR_POST_EXT_3200
358 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
359#else
360 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
361#endif
362 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
363 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
364 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
365 { 0x5401d, 0x0 },
366 { 0x5401e, LPDDR4_MR22_RANK0 },
367 { 0x5401f, 0x2dd4 },
368#ifdef WR_POST_EXT_3200
369 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
370#else
371 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
372#endif
373 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
374 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
375 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
376 { 0x54023, 0x0 },
377 { 0x54024, LPDDR4_MR22_RANK1 },
378
379 { 0x54025, 0x0 },
380 { 0x54026, 0x0 },
381 { 0x54027, 0x0 },
382 { 0x54028, 0x0 },
383 { 0x54029, 0x0 },
384 { 0x5402a, 0x0 },
385 { 0x5402b, 0x1000 },
386 { 0x5402c, 0x3 },
387 { 0x5402d, 0x0 },
388 { 0x5402e, 0x0 },
389 { 0x5402f, 0x0 },
390 { 0x54030, 0x0 },
391 { 0x54031, 0x0 },
392 { 0x54032, 0xd400 },
393 /* MR3/MR2 */
394#ifdef WR_POST_EXT_3200
395 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
396#else
397 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
398#endif
399 /* MR11/MR4 */
400 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
401 /* self:0x284d//MR13/MR12 */
402 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
403 /* MR16/MR14*/
404 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
405 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
406 /* MR1 */
407 { 0x54038, 0xd400 },
408 /* MR3/MR2 */
409#ifdef WR_POST_EXT_3200
410 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
411#else
412 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
413#endif
414 /* MR11/MR4 */
415 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
416 /* self:0x284d//MR13/MR12 */
417 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
418 /* MR16/MR14 */
419 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
420 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
421 /* { 0x5403d, 0x500 } */
422 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
423 { 0x5403e, 0x0 },
424 { 0x5403f, 0x0 },
425 { 0x54040, 0x0 },
426 { 0x54041, 0x0 },
427 { 0x54042, 0x0 },
428 { 0x54043, 0x0 },
429 { 0x54044, 0x0 },
430 { 0xd0000, 0x1 },
431};
432
433/* P1 message block paremeter for training firmware */
434struct dram_cfg_param lpddr4_fsp1_cfg[] = {
435 { 0xd0000, 0x0 },
436 { 0x54000, 0x0 },
437 { 0x54001, 0x0 },
438 { 0x54002, 0x101 },
439 { 0x54003, 0x190 },
440 { 0x54004, 0x2 },
441 /* PHY Ron/Rtt */
442 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
443 { 0x54006, LPDDR4_PHY_VREF_VALUE },
444 { 0x54007, 0x0 },
445 { 0x54008, LPDDR4_TRAIN_SEQ_400 },
446 { 0x54009, LPDDR4_HDT_CTL_400_1D },
447 { 0x5400a, 0x0 },
448 { 0x5400b, 0x2 },
449 { 0x5400c, 0x0 },
450 { 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
451 { 0x5400e, 0x0 },
452 { 0x5400f, 0x0 },
453 { 0x54010, 0x0 },
454 { 0x54011, 0x0 },
455 { 0x54012, 0x310 },
456 { 0x54013, 0x0 },
457 { 0x54014, 0x0 },
458 { 0x54015, 0x0 },
459 { 0x54016, 0x0 },
460 { 0x54017, 0x0 },
461 { 0x54018, 0x0 },
462 { 0x54019, 0x84 },
463 /* MR4/MR3 */
464 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
465 /* MR12/MR11 */
466 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
467 LPDDR4_RTT_DQ)/*0x4d46*/ },
468 /* self:0x4d28//MR14/MR13 */
469 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
470 { 0x5401d, 0x0 },
471 { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
472 { 0x5401f, 0x84 },
473 { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
474 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
475 LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
476 /* self:0x4d28//MR14/MR13 */
477 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
478 { 0x54023, 0x0 },
479 { 0x54024, LPDDR4_MR22_RANK1 },
480 { 0x54025, 0x0 },
481 { 0x54026, 0x0 },
482 { 0x54027, 0x0 },
483 { 0x54028, 0x0 },
484 { 0x54029, 0x0 },
485 { 0x5402a, 0x0 },
486 { 0x5402b, 0x1000 },
487 { 0x5402c, 0x3 },
488 { 0x5402d, 0x0 },
489 { 0x5402e, 0x0 },
490 { 0x5402f, 0x0 },
491 { 0x54030, 0x0 },
492 { 0x54031, 0x0 },
493 { 0x54032, 0x8400 },
494 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
495 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
496 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
497 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
498 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
499 { 0x54038, 0x8400 },
500 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
501 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
502 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
503 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
504 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
505 { 0x5403e, 0x0 },
506 { 0x5403f, 0x0 },
507 { 0x54040, 0x0 },
508 { 0x54041, 0x0 },
509 { 0x54042, 0x0 },
510 { 0x54043, 0x0 },
511 { 0x54044, 0x0 },
512 { 0xd0000, 0x1 },
513};
514
515/* P2 message block paremeter for training firmware */
516struct dram_cfg_param lpddr4_fsp2_cfg[] = {
517 { 0xd0000, 0x0 },
518 { 0x54000, 0x0 },
519 { 0x54001, 0x0 },
520 { 0x54002, 0x102 },
521 { 0x54003, 0x64 },
522 { 0x54004, 0x2 },
523 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
524 { 0x54006, LPDDR4_PHY_VREF_VALUE },
525 { 0x54007, 0x0 },
526 { 0x54008, LPDDR4_TRAIN_SEQ_100 },
527 { 0x54009, LPDDR4_HDT_CTL_100_1D },
528 { 0x5400a, 0x0 },
529 { 0x5400b, 0x2 },
530 { 0x5400c, 0x0 },
531 { 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
532 { 0x5400e, 0x0 },
533 { 0x5400f, 0x0 },
534 { 0x54010, 0x0 },
535 { 0x54011, 0x0 },
536 { 0x54012, 0x310 },
537 { 0x54013, 0x0 },
538 { 0x54014, 0x0 },
539 { 0x54015, 0x0 },
540 { 0x54016, 0x0 },
541 { 0x54017, 0x0 },
542 { 0x54018, 0x0 },
543 { 0x54019, 0x84 },
544 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
545 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
546 LPDDR4_RTT_DQ) },
547 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
548 { 0x5401d, 0x0 },
549 { 0x5401e, LPDDR4_MR22_RANK0 },
550 { 0x5401f, 0x84 },
551 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
552 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
553 LPDDR4_RTT_DQ) },
554 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
555 { 0x54023, 0x0 },
556 { 0x54024, LPDDR4_MR22_RANK1 },
557 { 0x54025, 0x0 },
558 { 0x54026, 0x0 },
559 { 0x54027, 0x0 },
560 { 0x54028, 0x0 },
561 { 0x54029, 0x0 },
562 { 0x5402a, 0x0 },
563 { 0x5402b, 0x1000 },
564 { 0x5402c, 0x3 },
565 { 0x5402d, 0x0 },
566 { 0x5402e, 0x0 },
567 { 0x5402f, 0x0 },
568 { 0x54030, 0x0 },
569 { 0x54031, 0x0 },
570 { 0x54032, 0x8400 },
571 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
572 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
573 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
574 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
575 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
576 { 0x54038, 0x8400 },
577 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
578 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
579 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
580 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
581 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
582 { 0x5403e, 0x0 },
583 { 0x5403f, 0x0 },
584 { 0x54040, 0x0 },
585 { 0x54041, 0x0 },
586 { 0x54042, 0x0 },
587 { 0x54043, 0x0 },
588 { 0x54044, 0x0 },
589 { 0xd0000, 0x1 },
590};
591
592/* P0 2D message block paremeter for training firmware */
593struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
594 { 0xd0000, 0x0 },
595 { 0x54000, 0x0 },
596 { 0x54001, 0x0 },
597 { 0x54002, 0x0 },
598 { 0x54003, 0xc80 },
599 { 0x54004, 0x2 },
600 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
601 { 0x54006, LPDDR4_PHY_VREF_VALUE },
602 { 0x54007, 0x0 },
603 { 0x54008, 0x61 },
604 { 0x54009, LPDDR4_HDT_CTL_2D },
605 { 0x5400a, 0x0 },
606 { 0x5400b, 0x2 },
607 { 0x5400c, 0x0 },
608 { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
609 { 0x5400e, 0x0 },
610 { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
611 { 0x54010, LPDDR4_2D_WEIGHT },
612 { 0x54011, 0x0 },
613 { 0x54012, 0x310 },
614 { 0x54013, 0x0 },
615 { 0x54014, 0x0 },
616 { 0x54015, 0x0 },
617 { 0x54016, 0x0 },
618 { 0x54017, 0x0 },
619 { 0x54018, 0x0 },
620 { 0x54019, 0x2dd4 },
621#ifdef WR_POST_EXT_3200
622 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
623#else
624 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
625#endif
626 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
627 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
628 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
629 { 0x5401d, 0x0 },
630 { 0x5401e, LPDDR4_MR22_RANK0 },
631 { 0x5401f, 0x2dd4 },
632#ifdef WR_POST_EXT_3200
633 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
634#else
635 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
636#endif
637 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
638 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
639 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
640 { 0x54023, 0x0 },
641 { 0x54024, LPDDR4_MR22_RANK1 },
642 { 0x54025, 0x0 },
643 { 0x54026, 0x0 },
644 { 0x54027, 0x0 },
645 { 0x54028, 0x0 },
646 { 0x54029, 0x0 },
647 { 0x5402a, 0x0 },
648 { 0x5402b, 0x1000 },
649 { 0x5402c, 0x3 },
650 { 0x5402d, 0x0 },
651 { 0x5402e, 0x0 },
652 { 0x5402f, 0x0 },
653 { 0x54030, 0x0 },
654 { 0x54031, 0x0 },
655
656 { 0x54032, 0xd400 },
657#ifdef WR_POST_EXT_3200
658 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
659#else
660 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
661#endif
662 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
663 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
664 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
665 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
666 { 0x54038, 0xd400 },
667#ifdef WR_POST_EXT_3200
668 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
669#else
670 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
671#endif
672 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
673 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
674 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
675 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
676 { 0x5403e, 0x0 },
677 { 0x5403f, 0x0 },
678 { 0x54040, 0x0 },
679 { 0x54041, 0x0 },
680 { 0x54042, 0x0 },
681 { 0x54043, 0x0 },
682 { 0x54044, 0x0 },
683 { 0xd0000, 0x1 },
684};
685
686/* DRAM PHY init engine image */
687struct dram_cfg_param lpddr4_phy_pie[] = {
688 { 0xd0000, 0x0 },
689 { 0x90000, 0x10 },
690 { 0x90001, 0x400 },
691 { 0x90002, 0x10e },
692 { 0x90003, 0x0 },
693 { 0x90004, 0x0 },
694 { 0x90005, 0x8 },
695 { 0x90029, 0xb },
696 { 0x9002a, 0x480 },
697 { 0x9002b, 0x109 },
698 { 0x9002c, 0x8 },
699 { 0x9002d, 0x448 },
700 { 0x9002e, 0x139 },
701 { 0x9002f, 0x8 },
702 { 0x90030, 0x478 },
703 { 0x90031, 0x109 },
704 { 0x90032, 0x0 },
705 { 0x90033, 0xe8 },
706 { 0x90034, 0x109 },
707 { 0x90035, 0x2 },
708 { 0x90036, 0x10 },
709 { 0x90037, 0x139 },
710 { 0x90038, 0xf },
711 { 0x90039, 0x7c0 },
712 { 0x9003a, 0x139 },
713 { 0x9003b, 0x44 },
714 { 0x9003c, 0x630 },
715 { 0x9003d, 0x159 },
716 { 0x9003e, 0x14f },
717 { 0x9003f, 0x630 },
718 { 0x90040, 0x159 },
719 { 0x90041, 0x47 },
720 { 0x90042, 0x630 },
721 { 0x90043, 0x149 },
722 { 0x90044, 0x4f },
723 { 0x90045, 0x630 },
724 { 0x90046, 0x179 },
725 { 0x90047, 0x8 },
726 { 0x90048, 0xe0 },
727 { 0x90049, 0x109 },
728 { 0x9004a, 0x0 },
729 { 0x9004b, 0x7c8 },
730 { 0x9004c, 0x109 },
731 { 0x9004d, 0x0 },
732 { 0x9004e, 0x1 },
733 { 0x9004f, 0x8 },
734 { 0x90050, 0x0 },
735 { 0x90051, 0x45a },
736 { 0x90052, 0x9 },
737 { 0x90053, 0x0 },
738 { 0x90054, 0x448 },
739 { 0x90055, 0x109 },
740 { 0x90056, 0x40 },
741 { 0x90057, 0x630 },
742 { 0x90058, 0x179 },
743 { 0x90059, 0x1 },
744 { 0x9005a, 0x618 },
745 { 0x9005b, 0x109 },
746 { 0x9005c, 0x40c0 },
747 { 0x9005d, 0x630 },
748 { 0x9005e, 0x149 },
749 { 0x9005f, 0x8 },
750 { 0x90060, 0x4 },
751 { 0x90061, 0x48 },
752 { 0x90062, 0x4040 },
753 { 0x90063, 0x630 },
754 { 0x90064, 0x149 },
755 { 0x90065, 0x0 },
756 { 0x90066, 0x4 },
757 { 0x90067, 0x48 },
758 { 0x90068, 0x40 },
759 { 0x90069, 0x630 },
760 { 0x9006a, 0x149 },
761 { 0x9006b, 0x10 },
762 { 0x9006c, 0x4 },
763 { 0x9006d, 0x18 },
764 { 0x9006e, 0x0 },
765 { 0x9006f, 0x4 },
766 { 0x90070, 0x78 },
767 { 0x90071, 0x549 },
768 { 0x90072, 0x630 },
769 { 0x90073, 0x159 },
770 { 0x90074, 0xd49 },
771 { 0x90075, 0x630 },
772 { 0x90076, 0x159 },
773 { 0x90077, 0x94a },
774 { 0x90078, 0x630 },
775 { 0x90079, 0x159 },
776 { 0x9007a, 0x441 },
777 { 0x9007b, 0x630 },
778 { 0x9007c, 0x149 },
779 { 0x9007d, 0x42 },
780 { 0x9007e, 0x630 },
781 { 0x9007f, 0x149 },
782 { 0x90080, 0x1 },
783 { 0x90081, 0x630 },
784 { 0x90082, 0x149 },
785 { 0x90083, 0x0 },
786 { 0x90084, 0xe0 },
787 { 0x90085, 0x109 },
788 { 0x90086, 0xa },
789 { 0x90087, 0x10 },
790 { 0x90088, 0x109 },
791 { 0x90089, 0x9 },
792 { 0x9008a, 0x3c0 },
793 { 0x9008b, 0x149 },
794 { 0x9008c, 0x9 },
795 { 0x9008d, 0x3c0 },
796 { 0x9008e, 0x159 },
797 { 0x9008f, 0x18 },
798 { 0x90090, 0x10 },
799 { 0x90091, 0x109 },
800 { 0x90092, 0x0 },
801 { 0x90093, 0x3c0 },
802 { 0x90094, 0x109 },
803 { 0x90095, 0x18 },
804 { 0x90096, 0x4 },
805 { 0x90097, 0x48 },
806 { 0x90098, 0x18 },
807 { 0x90099, 0x4 },
808 { 0x9009a, 0x58 },
809 { 0x9009b, 0xa },
810 { 0x9009c, 0x10 },
811 { 0x9009d, 0x109 },
812 { 0x9009e, 0x2 },
813 { 0x9009f, 0x10 },
814 { 0x900a0, 0x109 },
815 { 0x900a1, 0x5 },
816 { 0x900a2, 0x7c0 },
817 { 0x900a3, 0x109 },
818 { 0x900a4, 0x10 },
819 { 0x900a5, 0x10 },
820 { 0x900a6, 0x109 },
821 { 0x40000, 0x811 },
822 { 0x40020, 0x880 },
823 { 0x40040, 0x0 },
824 { 0x40060, 0x0 },
825 { 0x40001, 0x4008 },
826 { 0x40021, 0x83 },
827 { 0x40041, 0x4f },
828 { 0x40061, 0x0 },
829 { 0x40002, 0x4040 },
830 { 0x40022, 0x83 },
831 { 0x40042, 0x51 },
832 { 0x40062, 0x0 },
833 { 0x40003, 0x811 },
834 { 0x40023, 0x880 },
835 { 0x40043, 0x0 },
836 { 0x40063, 0x0 },
837 { 0x40004, 0x720 },
838 { 0x40024, 0xf },
839 { 0x40044, 0x1740 },
840 { 0x40064, 0x0 },
841 { 0x40005, 0x16 },
842 { 0x40025, 0x83 },
843 { 0x40045, 0x4b },
844 { 0x40065, 0x0 },
845 { 0x40006, 0x716 },
846 { 0x40026, 0xf },
847 { 0x40046, 0x2001 },
848 { 0x40066, 0x0 },
849 { 0x40007, 0x716 },
850 { 0x40027, 0xf },
851 { 0x40047, 0x2800 },
852 { 0x40067, 0x0 },
853 { 0x40008, 0x716 },
854 { 0x40028, 0xf },
855 { 0x40048, 0xf00 },
856 { 0x40068, 0x0 },
857 { 0x40009, 0x720 },
858 { 0x40029, 0xf },
859 { 0x40049, 0x1400 },
860 { 0x40069, 0x0 },
861 { 0x4000a, 0xe08 },
862 { 0x4002a, 0xc15 },
863 { 0x4004a, 0x0 },
864 { 0x4006a, 0x0 },
865 { 0x4000b, 0x623 },
866 { 0x4002b, 0x15 },
867 { 0x4004b, 0x0 },
868 { 0x4006b, 0x0 },
869 { 0x4000c, 0x4028 },
870 { 0x4002c, 0x80 },
871 { 0x4004c, 0x0 },
872 { 0x4006c, 0x0 },
873 { 0x4000d, 0xe08 },
874 { 0x4002d, 0xc1a },
875 { 0x4004d, 0x0 },
876 { 0x4006d, 0x0 },
877 { 0x4000e, 0x623 },
878 { 0x4002e, 0x1a },
879 { 0x4004e, 0x0 },
880 { 0x4006e, 0x0 },
881 { 0x4000f, 0x4040 },
882 { 0x4002f, 0x80 },
883 { 0x4004f, 0x0 },
884 { 0x4006f, 0x0 },
885 { 0x40010, 0x2604 },
886 { 0x40030, 0x15 },
887 { 0x40050, 0x0 },
888 { 0x40070, 0x0 },
889 { 0x40011, 0x708 },
890 { 0x40031, 0x5 },
891 { 0x40051, 0x0 },
892 { 0x40071, 0x2002 },
893 { 0x40012, 0x8 },
894 { 0x40032, 0x80 },
895 { 0x40052, 0x0 },
896 { 0x40072, 0x0 },
897 { 0x40013, 0x2604 },
898 { 0x40033, 0x1a },
899 { 0x40053, 0x0 },
900 { 0x40073, 0x0 },
901 { 0x40014, 0x708 },
902 { 0x40034, 0xa },
903 { 0x40054, 0x0 },
904 { 0x40074, 0x2002 },
905 { 0x40015, 0x4040 },
906 { 0x40035, 0x80 },
907 { 0x40055, 0x0 },
908 { 0x40075, 0x0 },
909 { 0x40016, 0x60a },
910 { 0x40036, 0x15 },
911 { 0x40056, 0x1200 },
912 { 0x40076, 0x0 },
913 { 0x40017, 0x61a },
914 { 0x40037, 0x15 },
915 { 0x40057, 0x1300 },
916 { 0x40077, 0x0 },
917 { 0x40018, 0x60a },
918 { 0x40038, 0x1a },
919 { 0x40058, 0x1200 },
920 { 0x40078, 0x0 },
921 { 0x40019, 0x642 },
922 { 0x40039, 0x1a },
923 { 0x40059, 0x1300 },
924 { 0x40079, 0x0 },
925 { 0x4001a, 0x4808 },
926 { 0x4003a, 0x880 },
927 { 0x4005a, 0x0 },
928 { 0x4007a, 0x0 },
929 { 0x900a7, 0x0 },
930 { 0x900a8, 0x790 },
931 { 0x900a9, 0x11a },
932 { 0x900aa, 0x8 },
933 { 0x900ab, 0x7aa },
934 { 0x900ac, 0x2a },
935 { 0x900ad, 0x10 },
936 { 0x900ae, 0x7b2 },
937 { 0x900af, 0x2a },
938 { 0x900b0, 0x0 },
939 { 0x900b1, 0x7c8 },
940 { 0x900b2, 0x109 },
941 { 0x900b3, 0x10 },
942 { 0x900b4, 0x2a8 },
943 { 0x900b5, 0x129 },
944 { 0x900b6, 0x8 },
945 { 0x900b7, 0x370 },
946 { 0x900b8, 0x129 },
947 { 0x900b9, 0xa },
948 { 0x900ba, 0x3c8 },
949 { 0x900bb, 0x1a9 },
950 { 0x900bc, 0xc },
951 { 0x900bd, 0x408 },
952 { 0x900be, 0x199 },
953 { 0x900bf, 0x14 },
954 { 0x900c0, 0x790 },
955 { 0x900c1, 0x11a },
956 { 0x900c2, 0x8 },
957 { 0x900c3, 0x4 },
958 { 0x900c4, 0x18 },
959 { 0x900c5, 0xe },
960 { 0x900c6, 0x408 },
961 { 0x900c7, 0x199 },
962 { 0x900c8, 0x8 },
963 { 0x900c9, 0x8568 },
964 { 0x900ca, 0x108 },
965 { 0x900cb, 0x18 },
966 { 0x900cc, 0x790 },
967 { 0x900cd, 0x16a },
968 { 0x900ce, 0x8 },
969 { 0x900cf, 0x1d8 },
970 { 0x900d0, 0x169 },
971 { 0x900d1, 0x10 },
972 { 0x900d2, 0x8558 },
973 { 0x900d3, 0x168 },
974 { 0x900d4, 0x70 },
975 { 0x900d5, 0x788 },
976 { 0x900d6, 0x16a },
977 { 0x900d7, 0x1ff8 },
978 { 0x900d8, 0x85a8 },
979 { 0x900d9, 0x1e8 },
980 { 0x900da, 0x50 },
981 { 0x900db, 0x798 },
982 { 0x900dc, 0x16a },
983 { 0x900dd, 0x60 },
984 { 0x900de, 0x7a0 },
985 { 0x900df, 0x16a },
986 { 0x900e0, 0x8 },
987 { 0x900e1, 0x8310 },
988 { 0x900e2, 0x168 },
989 { 0x900e3, 0x8 },
990 { 0x900e4, 0xa310 },
991 { 0x900e5, 0x168 },
992 { 0x900e6, 0xa },
993 { 0x900e7, 0x408 },
994 { 0x900e8, 0x169 },
995 { 0x900e9, 0x6e },
996 { 0x900ea, 0x0 },
997 { 0x900eb, 0x68 },
998 { 0x900ec, 0x0 },
999 { 0x900ed, 0x408 },
1000 { 0x900ee, 0x169 },
1001 { 0x900ef, 0x0 },
1002 { 0x900f0, 0x8310 },
1003 { 0x900f1, 0x168 },
1004 { 0x900f2, 0x0 },
1005 { 0x900f3, 0xa310 },
1006 { 0x900f4, 0x168 },
1007 { 0x900f5, 0x1ff8 },
1008 { 0x900f6, 0x85a8 },
1009 { 0x900f7, 0x1e8 },
1010 { 0x900f8, 0x68 },
1011 { 0x900f9, 0x798 },
1012 { 0x900fa, 0x16a },
1013 { 0x900fb, 0x78 },
1014 { 0x900fc, 0x7a0 },
1015 { 0x900fd, 0x16a },
1016 { 0x900fe, 0x68 },
1017 { 0x900ff, 0x790 },
1018 { 0x90100, 0x16a },
1019 { 0x90101, 0x8 },
1020 { 0x90102, 0x8b10 },
1021 { 0x90103, 0x168 },
1022 { 0x90104, 0x8 },
1023 { 0x90105, 0xab10 },
1024 { 0x90106, 0x168 },
1025 { 0x90107, 0xa },
1026 { 0x90108, 0x408 },
1027 { 0x90109, 0x169 },
1028 { 0x9010a, 0x58 },
1029 { 0x9010b, 0x0 },
1030 { 0x9010c, 0x68 },
1031 { 0x9010d, 0x0 },
1032 { 0x9010e, 0x408 },
1033 { 0x9010f, 0x169 },
1034 { 0x90110, 0x0 },
1035 { 0x90111, 0x8b10 },
1036 { 0x90112, 0x168 },
1037 { 0x90113, 0x0 },
1038 { 0x90114, 0xab10 },
1039 { 0x90115, 0x168 },
1040 { 0x90116, 0x0 },
1041 { 0x90117, 0x1d8 },
1042 { 0x90118, 0x169 },
1043 { 0x90119, 0x80 },
1044 { 0x9011a, 0x790 },
1045 { 0x9011b, 0x16a },
1046 { 0x9011c, 0x18 },
1047 { 0x9011d, 0x7aa },
1048 { 0x9011e, 0x6a },
1049 { 0x9011f, 0xa },
1050 { 0x90120, 0x0 },
1051 { 0x90121, 0x1e9 },
1052 { 0x90122, 0x8 },
1053 { 0x90123, 0x8080 },
1054 { 0x90124, 0x108 },
1055 { 0x90125, 0xf },
1056 { 0x90126, 0x408 },
1057 { 0x90127, 0x169 },
1058 { 0x90128, 0xc },
1059 { 0x90129, 0x0 },
1060 { 0x9012a, 0x68 },
1061 { 0x9012b, 0x9 },
1062 { 0x9012c, 0x0 },
1063 { 0x9012d, 0x1a9 },
1064 { 0x9012e, 0x0 },
1065 { 0x9012f, 0x408 },
1066 { 0x90130, 0x169 },
1067 { 0x90131, 0x0 },
1068 { 0x90132, 0x8080 },
1069 { 0x90133, 0x108 },
1070 { 0x90134, 0x8 },
1071 { 0x90135, 0x7aa },
1072 { 0x90136, 0x6a },
1073 { 0x90137, 0x0 },
1074 { 0x90138, 0x8568 },
1075 { 0x90139, 0x108 },
1076 { 0x9013a, 0xb7 },
1077 { 0x9013b, 0x790 },
1078 { 0x9013c, 0x16a },
1079 { 0x9013d, 0x1f },
1080 { 0x9013e, 0x0 },
1081 { 0x9013f, 0x68 },
1082 { 0x90140, 0x8 },
1083 { 0x90141, 0x8558 },
1084 { 0x90142, 0x168 },
1085 { 0x90143, 0xf },
1086 { 0x90144, 0x408 },
1087 { 0x90145, 0x169 },
1088 { 0x90146, 0xc },
1089 { 0x90147, 0x0 },
1090 { 0x90148, 0x68 },
1091 { 0x90149, 0x0 },
1092 { 0x9014a, 0x408 },
1093 { 0x9014b, 0x169 },
1094 { 0x9014c, 0x0 },
1095 { 0x9014d, 0x8558 },
1096 { 0x9014e, 0x168 },
1097 { 0x9014f, 0x8 },
1098 { 0x90150, 0x3c8 },
1099 { 0x90151, 0x1a9 },
1100 { 0x90152, 0x3 },
1101 { 0x90153, 0x370 },
1102 { 0x90154, 0x129 },
1103 { 0x90155, 0x20 },
1104 { 0x90156, 0x2aa },
1105 { 0x90157, 0x9 },
1106 { 0x90158, 0x0 },
1107 { 0x90159, 0x400 },
1108 { 0x9015a, 0x10e },
1109 { 0x9015b, 0x8 },
1110 { 0x9015c, 0xe8 },
1111 { 0x9015d, 0x109 },
1112 { 0x9015e, 0x0 },
1113 { 0x9015f, 0x8140 },
1114 { 0x90160, 0x10c },
1115 { 0x90161, 0x10 },
1116 { 0x90162, 0x8138 },
1117 { 0x90163, 0x10c },
1118 { 0x90164, 0x8 },
1119 { 0x90165, 0x7c8 },
1120 { 0x90166, 0x101 },
1121 { 0x90167, 0x8 },
1122 { 0x90168, 0x0 },
1123 { 0x90169, 0x8 },
1124 { 0x9016a, 0x8 },
1125 { 0x9016b, 0x448 },
1126 { 0x9016c, 0x109 },
1127 { 0x9016d, 0xf },
1128 { 0x9016e, 0x7c0 },
1129 { 0x9016f, 0x109 },
1130 { 0x90170, 0x0 },
1131 { 0x90171, 0xe8 },
1132 { 0x90172, 0x109 },
1133 { 0x90173, 0x47 },
1134 { 0x90174, 0x630 },
1135 { 0x90175, 0x109 },
1136 { 0x90176, 0x8 },
1137 { 0x90177, 0x618 },
1138 { 0x90178, 0x109 },
1139 { 0x90179, 0x8 },
1140 { 0x9017a, 0xe0 },
1141 { 0x9017b, 0x109 },
1142 { 0x9017c, 0x0 },
1143 { 0x9017d, 0x7c8 },
1144 { 0x9017e, 0x109 },
1145 { 0x9017f, 0x8 },
1146 { 0x90180, 0x8140 },
1147 { 0x90181, 0x10c },
1148 { 0x90182, 0x0 },
1149 { 0x90183, 0x1 },
1150 { 0x90184, 0x8 },
1151 { 0x90185, 0x8 },
1152 { 0x90186, 0x4 },
1153 { 0x90187, 0x8 },
1154 { 0x90188, 0x8 },
1155 { 0x90189, 0x7c8 },
1156 { 0x9018a, 0x101 },
1157 { 0x90006, 0x0 },
1158 { 0x90007, 0x0 },
1159 { 0x90008, 0x8 },
1160 { 0x90009, 0x0 },
1161 { 0x9000a, 0x0 },
1162 { 0x9000b, 0x0 },
1163 { 0xd00e7, 0x400 },
1164 { 0x90017, 0x0 },
1165 { 0x9001f, 0x2a },
1166 { 0x90026, 0x6a },
1167 { 0x400d0, 0x0 },
1168 { 0x400d1, 0x101 },
1169 { 0x400d2, 0x105 },
1170 { 0x400d3, 0x107 },
1171 { 0x400d4, 0x10f },
1172 { 0x400d5, 0x202 },
1173 { 0x400d6, 0x20a },
1174 { 0x400d7, 0x20b },
1175 { 0x2003a, 0x2 },
1176 { 0x2000b, 0x64 },
1177 { 0x2000c, 0xc8 },
1178 { 0x2000d, 0x7d0 },
1179 { 0x2000e, 0x2c },
1180 { 0x12000b, 0xc },
1181 { 0x12000c, 0x19 },
1182 { 0x12000d, 0xfa },
1183 { 0x12000e, 0x10 },
1184 { 0x22000b, 0x3 },
1185 { 0x22000c, 0x6 },
1186 { 0x22000d, 0x3e },
1187 { 0x22000e, 0x10 },
1188 { 0x9000c, 0x0 },
1189 { 0x9000d, 0x173 },
1190 { 0x9000e, 0x60 },
1191 { 0x9000f, 0x6110 },
1192 { 0x90010, 0x2152 },
1193 { 0x90011, 0xdfbd },
1194 { 0x90012, 0x60 },
1195 { 0x90013, 0x6152 },
1196 { 0x20010, 0x5a },
1197 { 0x20011, 0x3 },
1198 { 0x40080, 0xe0 },
1199 { 0x40081, 0x12 },
1200 { 0x40082, 0xe0 },
1201 { 0x40083, 0x12 },
1202 { 0x40084, 0xe0 },
1203 { 0x40085, 0x12 },
1204 { 0x140080, 0xe0 },
1205 { 0x140081, 0x12 },
1206 { 0x140082, 0xe0 },
1207 { 0x140083, 0x12 },
1208 { 0x140084, 0xe0 },
1209 { 0x140085, 0x12 },
1210 { 0x240080, 0xe0 },
1211 { 0x240081, 0x12 },
1212 { 0x240082, 0xe0 },
1213 { 0x240083, 0x12 },
1214 { 0x240084, 0xe0 },
1215 { 0x240085, 0x12 },
1216 { 0x400fd, 0xf },
1217 { 0x10011, 0x1 },
1218 { 0x10012, 0x1 },
1219 { 0x10013, 0x180 },
1220 { 0x10018, 0x1 },
1221 { 0x10002, 0x6209 },
1222 { 0x100b2, 0x1 },
1223 { 0x101b4, 0x1 },
1224 { 0x102b4, 0x1 },
1225 { 0x103b4, 0x1 },
1226 { 0x104b4, 0x1 },
1227 { 0x105b4, 0x1 },
1228 { 0x106b4, 0x1 },
1229 { 0x107b4, 0x1 },
1230 { 0x108b4, 0x1 },
1231 { 0x11011, 0x1 },
1232 { 0x11012, 0x1 },
1233 { 0x11013, 0x180 },
1234 { 0x11018, 0x1 },
1235 { 0x11002, 0x6209 },
1236 { 0x110b2, 0x1 },
1237 { 0x111b4, 0x1 },
1238 { 0x112b4, 0x1 },
1239 { 0x113b4, 0x1 },
1240 { 0x114b4, 0x1 },
1241 { 0x115b4, 0x1 },
1242 { 0x116b4, 0x1 },
1243 { 0x117b4, 0x1 },
1244 { 0x118b4, 0x1 },
1245 { 0x12011, 0x1 },
1246 { 0x12012, 0x1 },
1247 { 0x12013, 0x180 },
1248 { 0x12018, 0x1 },
1249 { 0x12002, 0x6209 },
1250 { 0x120b2, 0x1 },
1251 { 0x121b4, 0x1 },
1252 { 0x122b4, 0x1 },
1253 { 0x123b4, 0x1 },
1254 { 0x124b4, 0x1 },
1255 { 0x125b4, 0x1 },
1256 { 0x126b4, 0x1 },
1257 { 0x127b4, 0x1 },
1258 { 0x128b4, 0x1 },
1259 { 0x13011, 0x1 },
1260 { 0x13012, 0x1 },
1261 { 0x13013, 0x180 },
1262 { 0x13018, 0x1 },
1263 { 0x13002, 0x6209 },
1264 { 0x130b2, 0x1 },
1265 { 0x131b4, 0x1 },
1266 { 0x132b4, 0x1 },
1267 { 0x133b4, 0x1 },
1268 { 0x134b4, 0x1 },
1269 { 0x135b4, 0x1 },
1270 { 0x136b4, 0x1 },
1271 { 0x137b4, 0x1 },
1272 { 0x138b4, 0x1 },
1273 { 0x2003a, 0x2 },
1274 { 0xc0080, 0x2 },
1275 { 0xd0000, 0x1 },
1276};
1277
1278struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1279 {
1280 /* P0 3200mts 1D */
1281 .drate = 3200,
1282 .fw_type = FW_1D_IMAGE,
1283 .fsp_cfg = lpddr4_fsp0_cfg,
1284 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1285 },
1286 {
1287 /* P1 400mts 1D */
1288 .drate = 400,
1289 .fw_type = FW_1D_IMAGE,
1290 .fsp_cfg = lpddr4_fsp1_cfg,
1291 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1292 },
1293 {
1294 /* P1 100mts 1D */
1295 .drate = 100,
1296 .fw_type = FW_1D_IMAGE,
1297 .fsp_cfg = lpddr4_fsp2_cfg,
1298 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
1299 },
1300 {
1301 /* P0 3200mts 2D */
1302 .drate = 3200,
1303 .fw_type = FW_2D_IMAGE,
1304 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1305 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1306 },
1307};
1308
1309/* lpddr4 timing config params on EVK board */
1310struct dram_timing_info dram_timing = {
1311 .ddrc_cfg = lpddr4_ddrc_cfg,
1312 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1313 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1314 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1315 .fsp_msg = lpddr4_dram_fsp_msg,
1316 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1317 .ddrphy_pie = lpddr4_phy_pie,
1318 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1319 .fsp_table = { 3200, 400, 100, },
1320};
diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
new file mode 100644
index 0000000000..ec68edaf69
--- /dev/null
+++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
@@ -0,0 +1,1191 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <linux/kernel.h>
7#include <common.h>
8#include <asm/arch/ddr.h>
9#include <asm/arch/lpddr4_define.h>
10
11#define WR_POST_EXT_3200 /* recommened to define */
12
13static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
14 /* Start to config, default 3200mbps */
15 /* dis_dq=1, indicates no reads or writes are issued to SDRAM */
16 { DDRC_DBG1(0), 0x00000001 },
17 /* selfref_en=1, SDRAM enter self-refresh state */
18 { DDRC_PWRCTL(0), 0x00000001 },
19 { DDRC_MSTR(0), 0xa3080020 },
20 { DDRC_MSTR2(0), 0x00000000 },
21 { DDRC_RFSHTMG(0), 0x006100E0 },
22 { DDRC_INIT0(0), 0xC003061B },
23 { DDRC_INIT1(0), 0x009D0000 },
24 { DDRC_INIT3(0), 0x00D4002D },
25#ifdef WR_POST_EXT_3200 /* recommened to define */
26 { DDRC_INIT4(0), 0x00330008 },
27#else
28 { DDRC_INIT4(0), 0x00310008 },
29#endif
30 { DDRC_INIT6(0), 0x0066004a },
31 { DDRC_INIT7(0), 0x0006004a },
32
33 { DDRC_DRAMTMG0(0), 0x1A201B22 },
34 { DDRC_DRAMTMG1(0), 0x00060633 },
35 { DDRC_DRAMTMG3(0), 0x00C0C000 },
36 { DDRC_DRAMTMG4(0), 0x0F04080F },
37 { DDRC_DRAMTMG5(0), 0x02040C0C },
38 { DDRC_DRAMTMG6(0), 0x01010007 },
39 { DDRC_DRAMTMG7(0), 0x00000401 },
40 { DDRC_DRAMTMG12(0), 0x00020600 },
41 { DDRC_DRAMTMG13(0), 0x0C100002 },
42 { DDRC_DRAMTMG14(0), 0x000000E6 },
43 { DDRC_DRAMTMG17(0), 0x00A00050 },
44
45 { DDRC_ZQCTL0(0), 0x03200018 },
46 { DDRC_ZQCTL1(0), 0x028061A8 },
47 { DDRC_ZQCTL2(0), 0x00000000 },
48
49 { DDRC_DFITMG0(0), 0x0497820A },
50 { DDRC_DFITMG1(0), 0x00080303 },
51 { DDRC_DFIUPD0(0), 0xE0400018 },
52 { DDRC_DFIUPD1(0), 0x00DF00E4 },
53 { DDRC_DFIUPD2(0), 0x80000000 },
54 { DDRC_DFIMISC(0), 0x00000011 },
55 { DDRC_DFITMG2(0), 0x0000170A },
56
57 { DDRC_DBICTL(0), 0x00000001 },
58 { DDRC_DFIPHYMSTR(0), 0x00000001 },
59
60 /* need be refined by ddrphy trained value */
61 { DDRC_RANKCTL(0), 0x00000c99 },
62 { DDRC_DRAMTMG2(0), 0x070E171a },
63
64 /* address mapping */
65 /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
66 { DDRC_ADDRMAP0(0), 0x00000015 },
67 { DDRC_ADDRMAP3(0), 0x00000000 },
68 /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */
69 { DDRC_ADDRMAP4(0), 0x00001F1F },
70 /* bank interleave */
71 /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
72 { DDRC_ADDRMAP1(0), 0x00080808 },
73 /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */
74 { DDRC_ADDRMAP5(0), 0x07070707 },
75 /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */
76 { DDRC_ADDRMAP6(0), 0x08080707 },
77
78 /* 667mts frequency setting */
79 { DDRC_FREQ1_DERATEEN(0), 0x0000000 },
80 { DDRC_FREQ1_DERATEINT(0), 0x0800000 },
81 { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
82 { DDRC_FREQ1_RFSHTMG(0), 0x014001E },
83 { DDRC_FREQ1_INIT3(0), 0x0140009 },
84 { DDRC_FREQ1_INIT4(0), 0x00310008 },
85 { DDRC_FREQ1_INIT6(0), 0x0066004a },
86 { DDRC_FREQ1_INIT7(0), 0x0006004a },
87 { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
88 { DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
89 { DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
90 { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
91 { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 },
92 { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
93 { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 },
94 { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 },
95 { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 },
96 { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
97 { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 },
98 { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
99 { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 },
100 { DDRC_FREQ1_DFITMG0(0), 0x3858202 },
101 { DDRC_FREQ1_DFITMG1(0), 0x0000404 },
102 { DDRC_FREQ1_DFITMG2(0), 0x0000502 },
103
104 /* performance setting */
105 { DDRC_ODTCFG(0), 0x0b060908 },
106 { DDRC_ODTMAP(0), 0x00000000 },
107 { DDRC_SCHED(0), 0x29511505 },
108 { DDRC_SCHED1(0), 0x0000002c },
109 { DDRC_PERFHPR1(0), 0x5900575b },
110 /* 150T starve and 0x90 max tran len */
111 { DDRC_PERFLPR1(0), 0x90000096 },
112 /* 300T starve and 0x10 max tran len */
113 { DDRC_PERFWR1(0), 0x1000012c },
114 { DDRC_DBG0(0), 0x00000016 },
115 { DDRC_DBG1(0), 0x00000000 },
116 { DDRC_DBGCMD(0), 0x00000000 },
117 { DDRC_SWCTL(0), 0x00000001 },
118 { DDRC_POISONCFG(0), 0x00000011 },
119 { DDRC_PCCFG(0), 0x00000111 },
120 { DDRC_PCFGR_0(0), 0x000010f3 },
121 { DDRC_PCFGW_0(0), 0x000072ff },
122 { DDRC_PCTRL_0(0), 0x00000001 },
123 /* disable Read Qos*/
124 { DDRC_PCFGQOS0_0(0), 0x00000e00 },
125 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
126 /* disable Write Qos*/
127 { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
128 { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
129 { DDRC_FREQ1_DERATEEN(0), 0x00000202 },
130 { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 },
131 { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
132 { DDRC_FREQ1_RFSHTMG(0), 0x00610090 },
133};
134
135/* PHY Initialize Configuration */
136static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
137 { 0x20110, 0x02 }, /* MapCAB0toDFI */
138 { 0x20111, 0x03 }, /* MapCAB1toDFI */
139 { 0x20112, 0x04 }, /* MapCAB2toDFI */
140 { 0x20113, 0x05 }, /* MapCAB3toDFI */
141 { 0x20114, 0x00 }, /* MapCAB4toDFI */
142 { 0x20115, 0x01 }, /* MapCAB5toDFI */
143
144 /* Initialize PHY Configuration */
145 { 0x1005f, 0x1ff },
146 { 0x1015f, 0x1ff },
147 { 0x1105f, 0x1ff },
148 { 0x1115f, 0x1ff },
149 { 0x1205f, 0x1ff },
150 { 0x1215f, 0x1ff },
151 { 0x1305f, 0x1ff },
152 { 0x1315f, 0x1ff },
153
154 { 0x11005f, 0x1ff },
155 { 0x11015f, 0x1ff },
156 { 0x11105f, 0x1ff },
157 { 0x11115f, 0x1ff },
158 { 0x11205f, 0x1ff },
159 { 0x11215f, 0x1ff },
160 { 0x11305f, 0x1ff },
161 { 0x11315f, 0x1ff },
162
163 { 0x21005f, 0x1ff },
164 { 0x21015f, 0x1ff },
165 { 0x21105f, 0x1ff },
166 { 0x21115f, 0x1ff },
167 { 0x21205f, 0x1ff },
168 { 0x21215f, 0x1ff },
169 { 0x21305f, 0x1ff },
170 { 0x21315f, 0x1ff },
171
172 { 0x55, 0x1ff },
173 { 0x1055, 0x1ff },
174 { 0x2055, 0x1ff },
175 { 0x3055, 0x1ff },
176 { 0x4055, 0x1ff },
177 { 0x5055, 0x1ff },
178 { 0x6055, 0x1ff },
179 { 0x7055, 0x1ff },
180 { 0x8055, 0x1ff },
181 { 0x9055, 0x1ff },
182 { 0x200c5, 0x19 },
183 { 0x1200c5, 0x7 },
184 { 0x2200c5, 0x7 },
185 { 0x2002e, 0x2 },
186 { 0x12002e, 0x1 },
187 { 0x22002e, 0x2 },
188 { 0x90204, 0x0 },
189 { 0x190204, 0x0 },
190 { 0x290204, 0x0 },
191
192 { 0x20024, 0xe3 },
193 { 0x2003a, 0x2 },
194 { 0x120024, 0xa3 },
195 { 0x2003a, 0x2 },
196 { 0x220024, 0xa3 },
197 { 0x2003a, 0x2 },
198
199 { 0x20056, 0x3 },
200 { 0x120056, 0xa },
201 { 0x220056, 0xa },
202
203 { 0x1004d, 0xe00 },
204 { 0x1014d, 0xe00 },
205 { 0x1104d, 0xe00 },
206 { 0x1114d, 0xe00 },
207 { 0x1204d, 0xe00 },
208 { 0x1214d, 0xe00 },
209 { 0x1304d, 0xe00 },
210 { 0x1314d, 0xe00 },
211 { 0x11004d, 0xe00 },
212 { 0x11014d, 0xe00 },
213 { 0x11104d, 0xe00 },
214 { 0x11114d, 0xe00 },
215 { 0x11204d, 0xe00 },
216 { 0x11214d, 0xe00 },
217 { 0x11304d, 0xe00 },
218 { 0x11314d, 0xe00 },
219 { 0x21004d, 0xe00 },
220 { 0x21014d, 0xe00 },
221 { 0x21104d, 0xe00 },
222 { 0x21114d, 0xe00 },
223 { 0x21204d, 0xe00 },
224 { 0x21214d, 0xe00 },
225 { 0x21304d, 0xe00 },
226 { 0x21314d, 0xe00 },
227
228 { 0x10049, 0xfbe },
229 { 0x10149, 0xfbe },
230 { 0x11049, 0xfbe },
231 { 0x11149, 0xfbe },
232 { 0x12049, 0xfbe },
233 { 0x12149, 0xfbe },
234 { 0x13049, 0xfbe },
235 { 0x13149, 0xfbe },
236
237 { 0x110049, 0xfbe },
238 { 0x110149, 0xfbe },
239 { 0x111049, 0xfbe },
240 { 0x111149, 0xfbe },
241 { 0x112049, 0xfbe },
242 { 0x112149, 0xfbe },
243 { 0x113049, 0xfbe },
244 { 0x113149, 0xfbe },
245
246 { 0x210049, 0xfbe },
247 { 0x210149, 0xfbe },
248 { 0x211049, 0xfbe },
249 { 0x211149, 0xfbe },
250 { 0x212049, 0xfbe },
251 { 0x212149, 0xfbe },
252 { 0x213049, 0xfbe },
253 { 0x213149, 0xfbe },
254
255 { 0x43, 0x63 },
256 { 0x1043, 0x63 },
257 { 0x2043, 0x63 },
258 { 0x3043, 0x63 },
259 { 0x4043, 0x63 },
260 { 0x5043, 0x63 },
261 { 0x6043, 0x63 },
262 { 0x7043, 0x63 },
263 { 0x8043, 0x63 },
264 { 0x9043, 0x63 },
265
266 { 0x20018, 0x3 },
267 { 0x20075, 0x4 },
268 { 0x20050, 0x0 },
269 { 0x20008, 0x320 },
270 { 0x120008, 0xa7 },
271 { 0x220008, 0x19 },
272 { 0x20088, 0x9 },
273 { 0x200b2, 0x104 },
274 { 0x10043, 0x5a1 },
275 { 0x10143, 0x5a1 },
276 { 0x11043, 0x5a1 },
277 { 0x11143, 0x5a1 },
278 { 0x12043, 0x5a1 },
279 { 0x12143, 0x5a1 },
280 { 0x13043, 0x5a1 },
281 { 0x13143, 0x5a1 },
282 { 0x1200b2, 0x104 },
283 { 0x110043, 0x5a1 },
284 { 0x110143, 0x5a1 },
285 { 0x111043, 0x5a1 },
286 { 0x111143, 0x5a1 },
287 { 0x112043, 0x5a1 },
288 { 0x112143, 0x5a1 },
289 { 0x113043, 0x5a1 },
290 { 0x113143, 0x5a1 },
291 { 0x2200b2, 0x104 },
292 { 0x210043, 0x5a1 },
293 { 0x210143, 0x5a1 },
294 { 0x211043, 0x5a1 },
295 { 0x211143, 0x5a1 },
296 { 0x212043, 0x5a1 },
297 { 0x212143, 0x5a1 },
298 { 0x213043, 0x5a1 },
299 { 0x213143, 0x5a1 },
300 { 0x200fa, 0x1 },
301 { 0x1200fa, 0x1 },
302 { 0x2200fa, 0x1 },
303 { 0x20019, 0x1 },
304 { 0x120019, 0x1 },
305 { 0x220019, 0x1 },
306 { 0x200f0, 0x600 },
307 { 0x200f1, 0x0 },
308 { 0x200f2, 0x4444 },
309 { 0x200f3, 0x8888 },
310 { 0x200f4, 0x5655 },
311 { 0x200f5, 0x0 },
312 { 0x200f6, 0x0 },
313 { 0x200f7, 0xf000 },
314 { 0x20025, 0x0 },
315 { 0x2002d, 0x0 },
316 { 0x12002d, 0x0 },
317 { 0x22002d, 0x0 },
318};
319
320/* P0 message block paremeter for training firmware */
321static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
322 { 0xd0000, 0x0 },
323 { 0x54000, 0x0 },
324 { 0x54001, 0x0 },
325 { 0x54002, 0x0 },
326 { 0x54003, 0xc80 },
327 { 0x54004, 0x2 },
328 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
329 { 0x54006, LPDDR4_PHY_VREF_VALUE },
330 { 0x54007, 0x0 },
331 { 0x54008, 0x131f },
332 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
333 { 0x5400a, 0x0 },
334 { 0x5400b, 0x2 },
335 { 0x5400c, 0x0 },
336 { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
337 { 0x5400e, 0x0 },
338 { 0x5400f, 0x0 },
339 { 0x54010, 0x0 },
340 { 0x54011, 0x0 },
341 { 0x54012, 0x310 },
342 { 0x54013, 0x0 },
343 { 0x54014, 0x0 },
344 { 0x54015, 0x0 },
345 { 0x54016, 0x0 },
346 { 0x54017, 0x0 },
347 { 0x54018, 0x0 },
348 { 0x54019, 0x2dd4 },
349 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
350 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
351 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
352 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
353 { 0x5401d, 0x0 },
354 { 0x5401e, LPDDR4_MR22_RANK0 },
355 { 0x5401f, 0x2dd4 },
356 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
357 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
358 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
359 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
360 { 0x54023, 0x0 },
361 { 0x54024, LPDDR4_MR22_RANK1 },
362 { 0x54025, 0x0 },
363 { 0x54026, 0x0 },
364 { 0x54027, 0x0 },
365 { 0x54028, 0x0 },
366 { 0x54029, 0x0 },
367 { 0x5402a, 0x0 },
368 { 0x5402b, 0x1000 },
369 { 0x5402c, 0x3 },
370 { 0x5402d, 0x0 },
371 { 0x5402e, 0x0 },
372 { 0x5402f, 0x0 },
373 { 0x54030, 0x0 },
374 { 0x54031, 0x0 },
375 { 0x54032, 0xd400 },
376 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
377 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
378 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
379 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
380 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
381 { 0x54038, 0xd400 },
382 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
383 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
384 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
385 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
386 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
387 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
388 { 0x5403e, 0x0 },
389 { 0x5403f, 0x0 },
390 { 0x54040, 0x0 },
391 { 0x54041, 0x0 },
392 { 0x54042, 0x0 },
393 { 0x54043, 0x0 },
394 { 0x54044, 0x0 },
395 { 0xd0000, 0x1 },
396};
397
398/* P1 message block paremeter for training firmware */
399static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
400 { 0xd0000, 0x0 },
401 { 0x54000, 0x0 },
402 { 0x54001, 0x0 },
403 { 0x54002, 0x1 },
404 { 0x54003, 0x29c },
405 { 0x54004, 0x2 },
406 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
407 { 0x54006, LPDDR4_PHY_VREF_VALUE },
408 { 0x54007, 0x0 },
409 { 0x54008, 0x121f },
410 { 0x54009, 0xc8 },
411 { 0x5400a, 0x0 },
412 { 0x5400b, 0x2 },
413 { 0x5400c, 0x0 },
414 { 0x5400d, 0x0 },
415 { 0x5400e, 0x0 },
416 { 0x5400f, 0x0 },
417 { 0x54010, 0x0 },
418 { 0x54011, 0x0 },
419 { 0x54012, 0x310 },
420 { 0x54013, 0x0 },
421 { 0x54014, 0x0 },
422 { 0x54015, 0x0 },
423 { 0x54016, 0x0 },
424 { 0x54017, 0x0 },
425 { 0x54018, 0x0 },
426 { 0x54019, 0x914 },
427 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
428 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
429 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
430 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
431 { 0x5401e, 0x6 },
432 { 0x5401f, 0x914 },
433 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
434 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
435 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
436 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
437 { 0x54023, 0x0 },
438 { 0x54024, LPDDR4_MR22_RANK1 },
439 { 0x54025, 0x0 },
440 { 0x54026, 0x0 },
441 { 0x54027, 0x0 },
442 { 0x54028, 0x0 },
443 { 0x54029, 0x0 },
444 { 0x5402a, 0x0 },
445 { 0x5402b, 0x1000 },
446 { 0x5402c, 0x3 },
447 { 0x5402d, 0x0 },
448 { 0x5402e, 0x0 },
449 { 0x5402f, 0x0 },
450 { 0x54030, 0x0 },
451 { 0x54031, 0x0 },
452 { 0x54032, 0x1400 },
453 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
454 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
455 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
456 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
457 { 0x54037, 0x600 },
458 { 0x54038, 0x1400 },
459 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
460 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
461 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
462 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
463 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
464 { 0x5403e, 0x0 },
465 { 0x5403f, 0x0 },
466 { 0x54040, 0x0 },
467 { 0x54041, 0x0 },
468 { 0x54042, 0x0 },
469 { 0x54043, 0x0 },
470 { 0xd0000, 0x1 },
471
472};
473
474/* P0 2D message block paremeter for training firmware */
475static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
476 { 0xd0000, 0x0 },
477 { 0x54000, 0x0 },
478 { 0x54001, 0x0 },
479 { 0x54002, 0x0 },
480 { 0x54003, 0xc80 },
481 { 0x54004, 0x2 },
482 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
483 { 0x54006, LPDDR4_PHY_VREF_VALUE },
484 { 0x54007, 0x0 },
485 { 0x54008, 0x61 },
486 { 0x54009, LPDDR4_HDT_CTL_2D },
487 { 0x5400a, 0x0 },
488 { 0x5400b, 0x2 },
489 { 0x5400c, 0x0 },
490 { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
491 { 0x5400e, 0x0 },
492 { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
493 { 0x54010, LPDDR4_2D_WEIGHT },
494 { 0x54011, 0x0 },
495 { 0x54012, 0x310 },
496 { 0x54013, 0x0 },
497 { 0x54014, 0x0 },
498 { 0x54015, 0x0 },
499 { 0x54016, 0x0 },
500 { 0x54017, 0x0 },
501 { 0x54018, 0x0 },
502 { 0x54024, 0x5 },
503 { 0x54019, 0x2dd4 },
504 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
505 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
506 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
507 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
508 { 0x5401d, 0x0 },
509 { 0x5401e, LPDDR4_MR22_RANK0 },
510 { 0x5401f, 0x2dd4 },
511 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
512 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
513 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
514 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
515 { 0x54023, 0x0 },
516 { 0x54024, LPDDR4_MR22_RANK1 },
517 { 0x54025, 0x0 },
518 { 0x54026, 0x0 },
519 { 0x54027, 0x0 },
520 { 0x54028, 0x0 },
521 { 0x54029, 0x0 },
522 { 0x5402a, 0x0 },
523 { 0x5402b, 0x1000 },
524 { 0x5402c, 0x3 },
525 { 0x5402d, 0x0 },
526 { 0x5402e, 0x0 },
527 { 0x5402f, 0x0 },
528 { 0x54030, 0x0 },
529 { 0x54031, 0x0 },
530 { 0x54032, 0xd400 },
531 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
532 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
533 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
534 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
535 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
536 { 0x54038, 0xd400 },
537 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
538 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
539 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
540 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
541 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
542 { 0x5403e, 0x0 },
543 { 0x5403f, 0x0 },
544 { 0x54040, 0x0 },
545 { 0x54041, 0x0 },
546 { 0x54042, 0x0 },
547 { 0x54043, 0x0 },
548 { 0x54044, 0x0 },
549 { 0xd0000, 0x1 },
550
551};
552
553/* DRAM PHY init engine image */
554static struct dram_cfg_param lpddr4_phy_pie[] = {
555 { 0xd0000, 0x0 },
556 { 0x90000, 0x10 },
557 { 0x90001, 0x400 },
558 { 0x90002, 0x10e },
559 { 0x90003, 0x0 },
560 { 0x90004, 0x0 },
561 { 0x90005, 0x8 },
562 { 0x90029, 0xb },
563 { 0x9002a, 0x480 },
564 { 0x9002b, 0x109 },
565 { 0x9002c, 0x8 },
566 { 0x9002d, 0x448 },
567 { 0x9002e, 0x139 },
568 { 0x9002f, 0x8 },
569 { 0x90030, 0x478 },
570 { 0x90031, 0x109 },
571 { 0x90032, 0x0 },
572 { 0x90033, 0xe8 },
573 { 0x90034, 0x109 },
574 { 0x90035, 0x2 },
575 { 0x90036, 0x10 },
576 { 0x90037, 0x139 },
577 { 0x90038, 0xb },
578 { 0x90039, 0x7c0 },
579 { 0x9003a, 0x139 },
580 { 0x9003b, 0x44 },
581 { 0x9003c, 0x630 },
582 { 0x9003d, 0x159 },
583 { 0x9003e, 0x14f },
584 { 0x9003f, 0x630 },
585 { 0x90040, 0x159 },
586 { 0x90041, 0x47 },
587 { 0x90042, 0x630 },
588 { 0x90043, 0x149 },
589 { 0x90044, 0x4f },
590 { 0x90045, 0x630 },
591 { 0x90046, 0x179 },
592 { 0x90047, 0x8 },
593 { 0x90048, 0xe0 },
594 { 0x90049, 0x109 },
595 { 0x9004a, 0x0 },
596 { 0x9004b, 0x7c8 },
597 { 0x9004c, 0x109 },
598 { 0x9004d, 0x0 },
599 { 0x9004e, 0x1 },
600 { 0x9004f, 0x8 },
601 { 0x90050, 0x0 },
602 { 0x90051, 0x45a },
603 { 0x90052, 0x9 },
604 { 0x90053, 0x0 },
605 { 0x90054, 0x448 },
606 { 0x90055, 0x109 },
607 { 0x90056, 0x40 },
608 { 0x90057, 0x630 },
609 { 0x90058, 0x179 },
610 { 0x90059, 0x1 },
611 { 0x9005a, 0x618 },
612 { 0x9005b, 0x109 },
613 { 0x9005c, 0x40c0 },
614 { 0x9005d, 0x630 },
615 { 0x9005e, 0x149 },
616 { 0x9005f, 0x8 },
617 { 0x90060, 0x4 },
618 { 0x90061, 0x48 },
619 { 0x90062, 0x4040 },
620 { 0x90063, 0x630 },
621 { 0x90064, 0x149 },
622 { 0x90065, 0x0 },
623 { 0x90066, 0x4 },
624 { 0x90067, 0x48 },
625 { 0x90068, 0x40 },
626 { 0x90069, 0x630 },
627 { 0x9006a, 0x149 },
628 { 0x9006b, 0x10 },
629 { 0x9006c, 0x4 },
630 { 0x9006d, 0x18 },
631 { 0x9006e, 0x0 },
632 { 0x9006f, 0x4 },
633 { 0x90070, 0x78 },
634 { 0x90071, 0x549 },
635 { 0x90072, 0x630 },
636 { 0x90073, 0x159 },
637 { 0x90074, 0xd49 },
638 { 0x90075, 0x630 },
639 { 0x90076, 0x159 },
640 { 0x90077, 0x94a },
641 { 0x90078, 0x630 },
642 { 0x90079, 0x159 },
643 { 0x9007a, 0x441 },
644 { 0x9007b, 0x630 },
645 { 0x9007c, 0x149 },
646 { 0x9007d, 0x42 },
647 { 0x9007e, 0x630 },
648 { 0x9007f, 0x149 },
649 { 0x90080, 0x1 },
650 { 0x90081, 0x630 },
651 { 0x90082, 0x149 },
652 { 0x90083, 0x0 },
653 { 0x90084, 0xe0 },
654 { 0x90085, 0x109 },
655 { 0x90086, 0xa },
656 { 0x90087, 0x10 },
657 { 0x90088, 0x109 },
658 { 0x90089, 0x9 },
659 { 0x9008a, 0x3c0 },
660 { 0x9008b, 0x149 },
661 { 0x9008c, 0x9 },
662 { 0x9008d, 0x3c0 },
663 { 0x9008e, 0x159 },
664 { 0x9008f, 0x18 },
665 { 0x90090, 0x10 },
666 { 0x90091, 0x109 },
667 { 0x90092, 0x0 },
668 { 0x90093, 0x3c0 },
669 { 0x90094, 0x109 },
670 { 0x90095, 0x18 },
671 { 0x90096, 0x4 },
672 { 0x90097, 0x48 },
673 { 0x90098, 0x18 },
674 { 0x90099, 0x4 },
675 { 0x9009a, 0x58 },
676 { 0x9009b, 0xa },
677 { 0x9009c, 0x10 },
678 { 0x9009d, 0x109 },
679 { 0x9009e, 0x2 },
680 { 0x9009f, 0x10 },
681 { 0x900a0, 0x109 },
682 { 0x900a1, 0x5 },
683 { 0x900a2, 0x7c0 },
684 { 0x900a3, 0x109 },
685 { 0x900a4, 0xd },
686 { 0x900a5, 0x7c0 },
687 { 0x900a6, 0x109 },
688 { 0x900a7, 0x4 },
689 { 0x900a8, 0x7c0 },
690 { 0x900a9, 0x109 },
691 { 0x40000, 0x811 },
692 { 0x40020, 0x880 },
693 { 0x40040, 0x0 },
694 { 0x40060, 0x0 },
695 { 0x40001, 0x4008 },
696 { 0x40021, 0x83 },
697 { 0x40041, 0x4f },
698 { 0x40061, 0x0 },
699 { 0x40002, 0x4040 },
700 { 0x40022, 0x83 },
701 { 0x40042, 0x51 },
702 { 0x40062, 0x0 },
703 { 0x40003, 0x811 },
704 { 0x40023, 0x880 },
705 { 0x40043, 0x0 },
706 { 0x40063, 0x0 },
707 { 0x40004, 0x720 },
708 { 0x40024, 0xf },
709 { 0x40044, 0x1740 },
710 { 0x40064, 0x0 },
711 { 0x40005, 0x16 },
712 { 0x40025, 0x83 },
713 { 0x40045, 0x4b },
714 { 0x40065, 0x0 },
715 { 0x40006, 0x716 },
716 { 0x40026, 0xf },
717 { 0x40046, 0x2001 },
718 { 0x40066, 0x0 },
719 { 0x40007, 0x716 },
720 { 0x40027, 0xf },
721 { 0x40047, 0x2800 },
722 { 0x40067, 0x0 },
723 { 0x40008, 0x716 },
724 { 0x40028, 0xf },
725 { 0x40048, 0xf00 },
726 { 0x40068, 0x0 },
727 { 0x40009, 0x720 },
728 { 0x40029, 0xf },
729 { 0x40049, 0x1400 },
730 { 0x40069, 0x0 },
731 { 0x4000a, 0xe08 },
732 { 0x4002a, 0xc15 },
733 { 0x4004a, 0x0 },
734 { 0x4006a, 0x0 },
735 { 0x4000b, 0x623 },
736 { 0x4002b, 0x15 },
737 { 0x4004b, 0x0 },
738 { 0x4006b, 0x0 },
739 { 0x4000c, 0x4028 },
740 { 0x4002c, 0x80 },
741 { 0x4004c, 0x0 },
742 { 0x4006c, 0x0 },
743 { 0x4000d, 0xe08 },
744 { 0x4002d, 0xc1a },
745 { 0x4004d, 0x0 },
746 { 0x4006d, 0x0 },
747 { 0x4000e, 0x623 },
748 { 0x4002e, 0x1a },
749 { 0x4004e, 0x0 },
750 { 0x4006e, 0x0 },
751 { 0x4000f, 0x4040 },
752 { 0x4002f, 0x80 },
753 { 0x4004f, 0x0 },
754 { 0x4006f, 0x0 },
755 { 0x40010, 0x2604 },
756 { 0x40030, 0x15 },
757 { 0x40050, 0x0 },
758 { 0x40070, 0x0 },
759 { 0x40011, 0x708 },
760 { 0x40031, 0x5 },
761 { 0x40051, 0x0 },
762 { 0x40071, 0x2002 },
763 { 0x40012, 0x8 },
764 { 0x40032, 0x80 },
765 { 0x40052, 0x0 },
766 { 0x40072, 0x0 },
767 { 0x40013, 0x2604 },
768 { 0x40033, 0x1a },
769 { 0x40053, 0x0 },
770 { 0x40073, 0x0 },
771 { 0x40014, 0x708 },
772 { 0x40034, 0xa },
773 { 0x40054, 0x0 },
774 { 0x40074, 0x2002 },
775 { 0x40015, 0x4040 },
776 { 0x40035, 0x80 },
777 { 0x40055, 0x0 },
778 { 0x40075, 0x0 },
779 { 0x40016, 0x60a },
780 { 0x40036, 0x15 },
781 { 0x40056, 0x1200 },
782 { 0x40076, 0x0 },
783 { 0x40017, 0x61a },
784 { 0x40037, 0x15 },
785 { 0x40057, 0x1300 },
786 { 0x40077, 0x0 },
787 { 0x40018, 0x60a },
788 { 0x40038, 0x1a },
789 { 0x40058, 0x1200 },
790 { 0x40078, 0x0 },
791 { 0x40019, 0x642 },
792 { 0x40039, 0x1a },
793 { 0x40059, 0x1300 },
794 { 0x40079, 0x0 },
795 { 0x4001a, 0x4808 },
796 { 0x4003a, 0x880 },
797 { 0x4005a, 0x0 },
798 { 0x4007a, 0x0 },
799 { 0x900aa, 0x0 },
800 { 0x900ab, 0x790 },
801 { 0x900ac, 0x11a },
802 { 0x900ad, 0x8 },
803 { 0x900ae, 0x7aa },
804 { 0x900af, 0x2a },
805 { 0x900b0, 0x10 },
806 { 0x900b1, 0x7b2 },
807 { 0x900b2, 0x2a },
808 { 0x900b3, 0x0 },
809 { 0x900b4, 0x7c8 },
810 { 0x900b5, 0x109 },
811 { 0x900b6, 0x10 },
812 { 0x900b7, 0x10 },
813 { 0x900b8, 0x109 },
814 { 0x900b9, 0x10 },
815 { 0x900ba, 0x2a8 },
816 { 0x900bb, 0x129 },
817 { 0x900bc, 0x8 },
818 { 0x900bd, 0x370 },
819 { 0x900be, 0x129 },
820 { 0x900bf, 0xa },
821 { 0x900c0, 0x3c8 },
822 { 0x900c1, 0x1a9 },
823 { 0x900c2, 0xc },
824 { 0x900c3, 0x408 },
825 { 0x900c4, 0x199 },
826 { 0x900c5, 0x14 },
827 { 0x900c6, 0x790 },
828 { 0x900c7, 0x11a },
829 { 0x900c8, 0x8 },
830 { 0x900c9, 0x4 },
831 { 0x900ca, 0x18 },
832 { 0x900cb, 0xe },
833 { 0x900cc, 0x408 },
834 { 0x900cd, 0x199 },
835 { 0x900ce, 0x8 },
836 { 0x900cf, 0x8568 },
837 { 0x900d0, 0x108 },
838 { 0x900d1, 0x18 },
839 { 0x900d2, 0x790 },
840 { 0x900d3, 0x16a },
841 { 0x900d4, 0x8 },
842 { 0x900d5, 0x1d8 },
843 { 0x900d6, 0x169 },
844 { 0x900d7, 0x10 },
845 { 0x900d8, 0x8558 },
846 { 0x900d9, 0x168 },
847 { 0x900da, 0x70 },
848 { 0x900db, 0x788 },
849 { 0x900dc, 0x16a },
850 { 0x900dd, 0x1ff8 },
851 { 0x900de, 0x85a8 },
852 { 0x900df, 0x1e8 },
853 { 0x900e0, 0x50 },
854 { 0x900e1, 0x798 },
855 { 0x900e2, 0x16a },
856 { 0x900e3, 0x60 },
857 { 0x900e4, 0x7a0 },
858 { 0x900e5, 0x16a },
859 { 0x900e6, 0x8 },
860 { 0x900e7, 0x8310 },
861 { 0x900e8, 0x168 },
862 { 0x900e9, 0x8 },
863 { 0x900ea, 0xa310 },
864 { 0x900eb, 0x168 },
865 { 0x900ec, 0xa },
866 { 0x900ed, 0x408 },
867 { 0x900ee, 0x169 },
868 { 0x900ef, 0x6e },
869 { 0x900f0, 0x0 },
870 { 0x900f1, 0x68 },
871 { 0x900f2, 0x0 },
872 { 0x900f3, 0x408 },
873 { 0x900f4, 0x169 },
874 { 0x900f5, 0x0 },
875 { 0x900f6, 0x8310 },
876 { 0x900f7, 0x168 },
877 { 0x900f8, 0x0 },
878 { 0x900f9, 0xa310 },
879 { 0x900fa, 0x168 },
880 { 0x900fb, 0x1ff8 },
881 { 0x900fc, 0x85a8 },
882 { 0x900fd, 0x1e8 },
883 { 0x900fe, 0x68 },
884 { 0x900ff, 0x798 },
885 { 0x90100, 0x16a },
886 { 0x90101, 0x78 },
887 { 0x90102, 0x7a0 },
888 { 0x90103, 0x16a },
889 { 0x90104, 0x68 },
890 { 0x90105, 0x790 },
891 { 0x90106, 0x16a },
892 { 0x90107, 0x8 },
893 { 0x90108, 0x8b10 },
894 { 0x90109, 0x168 },
895 { 0x9010a, 0x8 },
896 { 0x9010b, 0xab10 },
897 { 0x9010c, 0x168 },
898 { 0x9010d, 0xa },
899 { 0x9010e, 0x408 },
900 { 0x9010f, 0x169 },
901 { 0x90110, 0x58 },
902 { 0x90111, 0x0 },
903 { 0x90112, 0x68 },
904 { 0x90113, 0x0 },
905 { 0x90114, 0x408 },
906 { 0x90115, 0x169 },
907 { 0x90116, 0x0 },
908 { 0x90117, 0x8b10 },
909 { 0x90118, 0x168 },
910 { 0x90119, 0x0 },
911 { 0x9011a, 0xab10 },
912 { 0x9011b, 0x168 },
913 { 0x9011c, 0x0 },
914 { 0x9011d, 0x1d8 },
915 { 0x9011e, 0x169 },
916 { 0x9011f, 0x80 },
917 { 0x90120, 0x790 },
918 { 0x90121, 0x16a },
919 { 0x90122, 0x18 },
920 { 0x90123, 0x7aa },
921 { 0x90124, 0x6a },
922 { 0x90125, 0xa },
923 { 0x90126, 0x0 },
924 { 0x90127, 0x1e9 },
925 { 0x90128, 0x8 },
926 { 0x90129, 0x8080 },
927 { 0x9012a, 0x108 },
928 { 0x9012b, 0xf },
929 { 0x9012c, 0x408 },
930 { 0x9012d, 0x169 },
931 { 0x9012e, 0xc },
932 { 0x9012f, 0x0 },
933 { 0x90130, 0x68 },
934 { 0x90131, 0x9 },
935 { 0x90132, 0x0 },
936 { 0x90133, 0x1a9 },
937 { 0x90134, 0x0 },
938 { 0x90135, 0x408 },
939 { 0x90136, 0x169 },
940 { 0x90137, 0x0 },
941 { 0x90138, 0x8080 },
942 { 0x90139, 0x108 },
943 { 0x9013a, 0x8 },
944 { 0x9013b, 0x7aa },
945 { 0x9013c, 0x6a },
946 { 0x9013d, 0x0 },
947 { 0x9013e, 0x8568 },
948 { 0x9013f, 0x108 },
949 { 0x90140, 0xb7 },
950 { 0x90141, 0x790 },
951 { 0x90142, 0x16a },
952 { 0x90143, 0x1f },
953 { 0x90144, 0x0 },
954 { 0x90145, 0x68 },
955 { 0x90146, 0x8 },
956 { 0x90147, 0x8558 },
957 { 0x90148, 0x168 },
958 { 0x90149, 0xf },
959 { 0x9014a, 0x408 },
960 { 0x9014b, 0x169 },
961 { 0x9014c, 0xc },
962 { 0x9014d, 0x0 },
963 { 0x9014e, 0x68 },
964 { 0x9014f, 0x0 },
965 { 0x90150, 0x408 },
966 { 0x90151, 0x169 },
967 { 0x90152, 0x0 },
968 { 0x90153, 0x8558 },
969 { 0x90154, 0x168 },
970 { 0x90155, 0x8 },
971 { 0x90156, 0x3c8 },
972 { 0x90157, 0x1a9 },
973 { 0x90158, 0x3 },
974 { 0x90159, 0x370 },
975 { 0x9015a, 0x129 },
976 { 0x9015b, 0x20 },
977 { 0x9015c, 0x2aa },
978 { 0x9015d, 0x9 },
979 { 0x9015e, 0x0 },
980 { 0x9015f, 0x400 },
981 { 0x90160, 0x10e },
982 { 0x90161, 0x8 },
983 { 0x90162, 0xe8 },
984 { 0x90163, 0x109 },
985 { 0x90164, 0x0 },
986 { 0x90165, 0x8140 },
987 { 0x90166, 0x10c },
988 { 0x90167, 0x10 },
989 { 0x90168, 0x8138 },
990 { 0x90169, 0x10c },
991 { 0x9016a, 0x8 },
992 { 0x9016b, 0x7c8 },
993 { 0x9016c, 0x101 },
994 { 0x9016d, 0x8 },
995 { 0x9016e, 0x0 },
996 { 0x9016f, 0x8 },
997 { 0x90170, 0x8 },
998 { 0x90171, 0x448 },
999 { 0x90172, 0x109 },
1000 { 0x90173, 0xf },
1001 { 0x90174, 0x7c0 },
1002 { 0x90175, 0x109 },
1003 { 0x90176, 0x0 },
1004 { 0x90177, 0xe8 },
1005 { 0x90178, 0x109 },
1006 { 0x90179, 0x47 },
1007 { 0x9017a, 0x630 },
1008 { 0x9017b, 0x109 },
1009 { 0x9017c, 0x8 },
1010 { 0x9017d, 0x618 },
1011 { 0x9017e, 0x109 },
1012 { 0x9017f, 0x8 },
1013 { 0x90180, 0xe0 },
1014 { 0x90181, 0x109 },
1015 { 0x90182, 0x0 },
1016 { 0x90183, 0x7c8 },
1017 { 0x90184, 0x109 },
1018 { 0x90185, 0x8 },
1019 { 0x90186, 0x8140 },
1020 { 0x90187, 0x10c },
1021 { 0x90188, 0x0 },
1022 { 0x90189, 0x1 },
1023 { 0x9018a, 0x8 },
1024 { 0x9018b, 0x8 },
1025 { 0x9018c, 0x4 },
1026 { 0x9018d, 0x8 },
1027 { 0x9018e, 0x8 },
1028 { 0x9018f, 0x7c8 },
1029 { 0x90190, 0x101 },
1030 { 0x90006, 0x0 },
1031 { 0x90007, 0x0 },
1032 { 0x90008, 0x8 },
1033 { 0x90009, 0x0 },
1034 { 0x9000a, 0x0 },
1035 { 0x9000b, 0x0 },
1036 { 0xd00e7, 0x400 },
1037 { 0x90017, 0x0 },
1038 { 0x9001f, 0x2b },
1039 { 0x90026, 0x6c },
1040 { 0x400d0, 0x0 },
1041 { 0x400d1, 0x101 },
1042 { 0x400d2, 0x105 },
1043 { 0x400d3, 0x107 },
1044 { 0x400d4, 0x10f },
1045 { 0x400d5, 0x202 },
1046 { 0x400d6, 0x20a },
1047 { 0x400d7, 0x20b },
1048 { 0x2003a, 0x2 },
1049 { 0x2000b, 0x64 },
1050 { 0x2000c, 0xc8 },
1051 { 0x2000d, 0x7d0 },
1052 { 0x2000e, 0x2c },
1053 { 0x12000b, 0x14 },
1054 { 0x12000c, 0x29 },
1055 { 0x12000d, 0x1a1 },
1056 { 0x12000e, 0x10 },
1057 { 0x22000b, 0x3 },
1058 { 0x22000c, 0x6 },
1059 { 0x22000d, 0x3e },
1060 { 0x22000e, 0x10 },
1061 { 0x9000c, 0x0 },
1062 { 0x9000d, 0x173 },
1063 { 0x9000e, 0x60 },
1064 { 0x9000f, 0x6110 },
1065 { 0x90010, 0x2152 },
1066 { 0x90011, 0xdfbd },
1067 { 0x90012, 0x60 },
1068 { 0x90013, 0x6152 },
1069 { 0x20010, 0x5a },
1070 { 0x20011, 0x3 },
1071 { 0x40080, 0xe0 },
1072 { 0x40081, 0x12 },
1073 { 0x40082, 0xe0 },
1074 { 0x40083, 0x12 },
1075 { 0x40084, 0xe0 },
1076 { 0x40085, 0x12 },
1077 { 0x140080, 0xe0 },
1078 { 0x140081, 0x12 },
1079 { 0x140082, 0xe0 },
1080 { 0x140083, 0x12 },
1081 { 0x140084, 0xe0 },
1082 { 0x140085, 0x12 },
1083 { 0x240080, 0xe0 },
1084 { 0x240081, 0x12 },
1085 { 0x240082, 0xe0 },
1086 { 0x240083, 0x12 },
1087 { 0x240084, 0xe0 },
1088 { 0x240085, 0x12 },
1089 { 0x400fd, 0xf },
1090 { 0x10011, 0x1 },
1091 { 0x10012, 0x1 },
1092 { 0x10013, 0x180 },
1093 { 0x10018, 0x1 },
1094 { 0x10002, 0x6209 },
1095 { 0x100b2, 0x1 },
1096 { 0x101b4, 0x1 },
1097 { 0x102b4, 0x1 },
1098 { 0x103b4, 0x1 },
1099 { 0x104b4, 0x1 },
1100 { 0x105b4, 0x1 },
1101 { 0x106b4, 0x1 },
1102 { 0x107b4, 0x1 },
1103 { 0x108b4, 0x1 },
1104 { 0x11011, 0x1 },
1105 { 0x11012, 0x1 },
1106 { 0x11013, 0x180 },
1107 { 0x11018, 0x1 },
1108 { 0x11002, 0x6209 },
1109 { 0x110b2, 0x1 },
1110 { 0x111b4, 0x1 },
1111 { 0x112b4, 0x1 },
1112 { 0x113b4, 0x1 },
1113 { 0x114b4, 0x1 },
1114 { 0x115b4, 0x1 },
1115 { 0x116b4, 0x1 },
1116 { 0x117b4, 0x1 },
1117 { 0x118b4, 0x1 },
1118 { 0x12011, 0x1 },
1119 { 0x12012, 0x1 },
1120 { 0x12013, 0x180 },
1121 { 0x12018, 0x1 },
1122 { 0x12002, 0x6209 },
1123 { 0x120b2, 0x1 },
1124 { 0x121b4, 0x1 },
1125 { 0x122b4, 0x1 },
1126 { 0x123b4, 0x1 },
1127 { 0x124b4, 0x1 },
1128 { 0x125b4, 0x1 },
1129 { 0x126b4, 0x1 },
1130 { 0x127b4, 0x1 },
1131 { 0x128b4, 0x1 },
1132 { 0x13011, 0x1 },
1133 { 0x13012, 0x1 },
1134 { 0x13013, 0x180 },
1135 { 0x13018, 0x1 },
1136 { 0x13002, 0x6209 },
1137 { 0x130b2, 0x1 },
1138 { 0x131b4, 0x1 },
1139 { 0x132b4, 0x1 },
1140 { 0x133b4, 0x1 },
1141 { 0x134b4, 0x1 },
1142 { 0x135b4, 0x1 },
1143 { 0x136b4, 0x1 },
1144 { 0x137b4, 0x1 },
1145 { 0x138b4, 0x1 },
1146 { 0x20089, 0x1 },
1147 { 0x20088, 0x19 },
1148 { 0xc0080, 0x2 },
1149 { 0xd0000, 0x1 },
1150};
1151
1152static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1153 {
1154 /* P0 3200mts 1D */
1155 .drate = 3200,
1156 .fw_type = FW_1D_IMAGE,
1157 .fsp_cfg = lpddr4_fsp0_cfg,
1158 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1159 },
1160 {
1161 /* P1 667mts 1D */
1162 .drate = 667,
1163 .fw_type = FW_1D_IMAGE,
1164 .fsp_cfg = lpddr4_fsp1_cfg,
1165 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1166 },
1167 {
1168 /* P0 3200mts 2D */
1169 .drate = 3200,
1170 .fw_type = FW_2D_IMAGE,
1171 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1172 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1173 },
1174};
1175
1176/* lpddr4 timing config params on EVK board */
1177struct dram_timing_info dram_timing_b0 = {
1178 .ddrc_cfg = lpddr4_ddrc_cfg,
1179 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1180 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1181 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1182 .fsp_msg = lpddr4_dram_fsp_msg,
1183 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1184 .ddrphy_pie = lpddr4_phy_pie,
1185 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1186 /*
1187 * this table must be initialized if DDRPHY bypass mode is
1188 * not used: all fsp drate > 666MTS.
1189 */
1190 .fsp_table = { 3200, 667, },
1191};
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
new file mode 100644
index 0000000000..e6cbc34b0d
--- /dev/null
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -0,0 +1,246 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <errno.h>
11#include <asm/io.h>
12#include <asm/arch/ddr.h>
13#include <asm/arch/imx8mq_pins.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/arch/clock.h>
16#include <asm/mach-imx/iomux-v3.h>
17#include <asm/mach-imx/gpio.h>
18#include <asm/mach-imx/mxc_i2c.h>
19#include <fsl_esdhc.h>
20#include <mmc.h>
21#include <power/pmic.h>
22#include <power/pfuze100_pmic.h>
23#include <spl.h>
24#include "../common/pfuze.h"
25
26DECLARE_GLOBAL_DATA_PTR;
27
28extern struct dram_timing_info dram_timing_b0;
29
30void spl_dram_init(void)
31{
32 /* ddr init */
33 if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
34 ddr_init(&dram_timing);
35 else
36 ddr_init(&dram_timing_b0);
37}
38
39#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
40#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
41struct i2c_pads_info i2c_pad_info1 = {
42 .scl = {
43 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
44 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
45 .gp = IMX_GPIO_NR(5, 14),
46 },
47 .sda = {
48 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
49 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
50 .gp = IMX_GPIO_NR(5, 15),
51 },
52};
53
54#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
55#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
56#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
57
58int board_mmc_getcd(struct mmc *mmc)
59{
60 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
61 int ret = 0;
62
63 switch (cfg->esdhc_base) {
64 case USDHC1_BASE_ADDR:
65 ret = 1;
66 break;
67 case USDHC2_BASE_ADDR:
68 ret = !gpio_get_value(USDHC2_CD_GPIO);
69 return ret;
70 }
71
72 return 1;
73}
74
75#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
76 PAD_CTL_FSEL2)
77#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
78
79static iomux_v3_cfg_t const usdhc1_pads[] = {
80 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
91};
92
93static iomux_v3_cfg_t const usdhc2_pads[] = {
94 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
95 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
96 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
97 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
98 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
99 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
100 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
101 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
102};
103
104static struct fsl_esdhc_cfg usdhc_cfg[2] = {
105 {USDHC1_BASE_ADDR, 0, 8},
106 {USDHC2_BASE_ADDR, 0, 4},
107};
108
109int board_mmc_init(bd_t *bis)
110{
111 int i, ret;
112 /*
113 * According to the board_mmc_init() the following map is done:
114 * (U-Boot device node) (Physical Port)
115 * mmc0 USDHC1
116 * mmc1 USDHC2
117 */
118 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
119 switch (i) {
120 case 0:
121 init_clk_usdhc(0);
122 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
123 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
124 ARRAY_SIZE(usdhc1_pads));
125 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
126 gpio_direction_output(USDHC1_PWR_GPIO, 0);
127 udelay(500);
128 gpio_direction_output(USDHC1_PWR_GPIO, 1);
129 break;
130 case 1:
131 init_clk_usdhc(1);
132 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
133 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
134 ARRAY_SIZE(usdhc2_pads));
135 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
136 gpio_direction_output(USDHC2_PWR_GPIO, 0);
137 udelay(500);
138 gpio_direction_output(USDHC2_PWR_GPIO, 1);
139 break;
140 default:
141 printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
142 return -EINVAL;
143 }
144
145 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
146 if (ret)
147 return ret;
148 }
149
150 return 0;
151}
152
153#ifdef CONFIG_POWER
154#define I2C_PMIC 0
155int power_init_board(void)
156{
157 struct pmic *p;
158 int ret;
159 unsigned int reg;
160
161 ret = power_pfuze100_init(I2C_PMIC);
162 if (ret)
163 return -ENODEV;
164
165 p = pmic_get("PFUZE100");
166 ret = pmic_probe(p);
167 if (ret)
168 return -ENODEV;
169
170 pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
171 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
172
173 pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
174 if ((reg & 0x3f) != 0x18) {
175 reg &= ~0x3f;
176 reg |= 0x18;
177 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
178 }
179
180 ret = pfuze_mode_init(p, APS_PFM);
181 if (ret < 0)
182 return ret;
183
184 /* set SW3A standby mode to off */
185 pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
186 reg &= ~0xf;
187 reg |= APS_OFF;
188 pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
189
190 return 0;
191}
192#endif
193
194void spl_board_init(void)
195{
196 puts("Normal Boot\n");
197}
198
199#ifdef CONFIG_SPL_LOAD_FIT
200int board_fit_config_name_match(const char *name)
201{
202 /* Just empty function now - can't decide what to choose */
203 debug("%s: %s\n", __func__, name);
204
205 return 0;
206}
207#endif
208
209void board_init_f(ulong dummy)
210{
211 int ret;
212
213 /* Clear global data */
214 memset((void *)gd, 0, sizeof(gd_t));
215
216 arch_cpu_init();
217
218 init_uart_clk(0);
219
220 board_early_init_f();
221
222 timer_init();
223
224 preloader_console_init();
225
226 /* Clear the BSS. */
227 memset(__bss_start, 0, __bss_end - __bss_start);
228
229 ret = spl_init();
230 if (ret) {
231 debug("spl_init() failed: %d\n", ret);
232 hang();
233 }
234
235 enable_tzc380();
236
237 /* Adjust pmic voltage to 1.0V for 800M */
238 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
239
240 power_init_board();
241
242 /* DDR initialization */
243 spl_dram_init();
244
245 board_init_r(NULL, 0);
246}
diff --git a/board/freescale/imx8qxp_mek/imximage.cfg b/board/freescale/imx8qxp_mek/imximage.cfg
index 9d39f25bf6..bbffb1a88f 100644
--- a/board/freescale/imx8qxp_mek/imximage.cfg
+++ b/board/freescale/imx8qxp_mek/imximage.cfg
@@ -7,7 +7,6 @@
7 */ 7 */
8 8
9#define __ASSEMBLY__ 9#define __ASSEMBLY__
10#include <config.h>
11 10
12/* Boot from SD, sector size 0x400 */ 11/* Boot from SD, sector size 0x400 */
13BOOT_FROM SD 0x400 12BOOT_FROM SD 0x400
diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
index 993b055930..05938560ab 100644
--- a/board/ge/bx50v3/Kconfig
+++ b/board/ge/bx50v3/Kconfig
@@ -15,4 +15,6 @@ config SYS_SOC
15config SYS_CONFIG_NAME 15config SYS_CONFIG_NAME
16 default "ge_bx50v3" 16 default "ge_bx50v3"
17 17
18source "board/ge/common/Kconfig"
19
18endif 20endif
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 245852510f..079d302fbe 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -33,20 +33,9 @@
33#include "../../../drivers/net/e1000.h" 33#include "../../../drivers/net/e1000.h"
34DECLARE_GLOBAL_DATA_PTR; 34DECLARE_GLOBAL_DATA_PTR;
35 35
36struct vpd_cache;
37
38static int confidx = 3; /* Default to b850v3. */ 36static int confidx = 3; /* Default to b850v3. */
39static struct vpd_cache vpd; 37static struct vpd_cache vpd;
40 38
41#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
42# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
43# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
44#endif
45
46#ifndef CONFIG_SYS_I2C_EEPROM_BUS
47#define CONFIG_SYS_I2C_EEPROM_BUS 4
48#endif
49
50#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 39#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
52 PAD_CTL_HYS) 41 PAD_CTL_HYS)
@@ -569,6 +558,7 @@ int overwrite_console(void)
569#define VPD_MAC_ADDRESS_LENGTH 6 558#define VPD_MAC_ADDRESS_LENGTH 6
570 559
571struct vpd_cache { 560struct vpd_cache {
561 bool is_read;
572 u8 product_id; 562 u8 product_id;
573 u8 has; 563 u8 has;
574 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH]; 564 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
@@ -578,11 +568,9 @@ struct vpd_cache {
578/* 568/*
579 * Extracts MAC and product information from the VPD. 569 * Extracts MAC and product information from the VPD.
580 */ 570 */
581static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, 571static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
582 size_t size, u8 const *data) 572 size_t size, u8 const *data)
583{ 573{
584 struct vpd_cache *vpd = (struct vpd_cache *)userdata;
585
586 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID && 574 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
587 size >= 1) { 575 size >= 1) {
588 vpd->product_id = data[0]; 576 vpd->product_id = data[0];
@@ -606,6 +594,11 @@ static void process_vpd(struct vpd_cache *vpd)
606 int fec_index = -1; 594 int fec_index = -1;
607 int i210_index = -1; 595 int i210_index = -1;
608 596
597 if (!vpd->is_read) {
598 printf("VPD wasn't read");
599 return;
600 }
601
609 switch (vpd->product_id) { 602 switch (vpd->product_id) {
610 case VPD_PRODUCT_B450: 603 case VPD_PRODUCT_B450:
611 env_set("confidx", "1"); 604 env_set("confidx", "1");
@@ -631,35 +624,6 @@ static void process_vpd(struct vpd_cache *vpd)
631 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2); 624 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
632} 625}
633 626
634static int read_vpd(uint eeprom_bus)
635{
636 int res;
637 int size = 1024;
638 uint8_t *data;
639 unsigned int current_i2c_bus = i2c_get_bus_num();
640
641 res = i2c_set_bus_num(eeprom_bus);
642 if (res < 0)
643 return res;
644
645 data = (uint8_t *)malloc(size);
646 if (!data)
647 return -ENOMEM;
648
649 res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
650 CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
651
652 if (res == 0) {
653 memset(&vpd, 0, sizeof(vpd));
654 vpd_reader(size, data, &vpd, vpd_callback);
655 }
656
657 free(data);
658
659 i2c_set_bus_num(current_i2c_bus);
660 return res;
661}
662
663int board_eth_init(bd_t *bis) 627int board_eth_init(bd_t *bis)
664{ 628{
665 setup_iomux_enet(); 629 setup_iomux_enet();
@@ -718,9 +682,10 @@ int board_init(void)
718 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 682 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
719 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); 683 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
720 684
721 read_vpd(CONFIG_SYS_I2C_EEPROM_BUS); 685 if (!read_vpd(&vpd, vpd_callback)) {
722 686 vpd.is_read = true;
723 set_confidx(&vpd); 687 set_confidx(&vpd);
688 }
724 689
725 gpio_direction_output(SUS_S3_OUT, 1); 690 gpio_direction_output(SUS_S3_OUT, 1);
726 gpio_direction_output(WIFI_EN, 1); 691 gpio_direction_output(WIFI_EN, 1);
diff --git a/board/ge/common/Kconfig b/board/ge/common/Kconfig
new file mode 100644
index 0000000000..637b264954
--- /dev/null
+++ b/board/ge/common/Kconfig
@@ -0,0 +1,14 @@
1config SYS_VPD_EEPROM_I2C_ADDR
2 hex "I2C address of the EEPROM device used for VPD"
3 help
4 VPD = Vital Product Data
5
6config SYS_VPD_EEPROM_I2C_BUS
7 int "I2C bus of the EEPROM device used for VPD."
8
9config SYS_VPD_EEPROM_SIZE
10 int "Size in bytes of the EEPROM device used for VPD"
11
12config SYS_VPD_EEPROM_I2C_ADDR_LEN
13 int "Number of bytes to use for VPD EEPROM address"
14 default 1
diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c
index c471583be8..12410d9b71 100644
--- a/board/ge/common/vpd_reader.c
+++ b/board/ge/common/vpd_reader.c
@@ -5,6 +5,7 @@
5 5
6#include "vpd_reader.h" 6#include "vpd_reader.h"
7 7
8#include <i2c.h>
8#include <linux/bch.h> 9#include <linux/bch.h>
9#include <stdlib.h> 10#include <stdlib.h>
10 11
@@ -105,9 +106,9 @@ static const size_t HEADER_BLOCK_ECC_LEN = 4;
105 106
106static const u8 ECC_BLOCK_ID = 0xFF; 107static const u8 ECC_BLOCK_ID = 0xFF;
107 108
108int vpd_reader(size_t size, u8 *data, void *userdata, 109static int vpd_reader(size_t size, u8 *data, struct vpd_cache *userdata,
109 int (*fn)(void *userdata, u8 id, u8 version, u8 type, 110 int (*fn)(struct vpd_cache *, u8 id, u8 version, u8 type,
110 size_t size, u8 const *data)) 111 size_t size, u8 const *data))
111{ 112{
112 if (size < HEADER_BLOCK_LEN || !data || !fn) 113 if (size < HEADER_BLOCK_LEN || !data || !fn)
113 return -EINVAL; 114 return -EINVAL;
@@ -194,3 +195,33 @@ int vpd_reader(size_t size, u8 *data, void *userdata,
194 return ret; 195 return ret;
195 } 196 }
196} 197}
198
199int read_vpd(struct vpd_cache *cache,
200 int (*process_block)(struct vpd_cache *, u8 id, u8 version,
201 u8 type, size_t size, u8 const *data))
202{
203 static const size_t size = CONFIG_SYS_VPD_EEPROM_SIZE;
204
205 int res;
206 u8 *data;
207 unsigned int current_i2c_bus = i2c_get_bus_num();
208
209 res = i2c_set_bus_num(CONFIG_SYS_VPD_EEPROM_I2C_BUS);
210 if (res < 0)
211 return res;
212
213 data = malloc(size);
214 if (!data)
215 return -ENOMEM;
216
217 res = i2c_read(CONFIG_SYS_VPD_EEPROM_I2C_ADDR, 0,
218 CONFIG_SYS_VPD_EEPROM_I2C_ADDR_LEN,
219 data, size);
220 if (res == 0)
221 res = vpd_reader(size, data, cache, process_block);
222
223 free(data);
224
225 i2c_set_bus_num(current_i2c_bus);
226 return res;
227}
diff --git a/board/ge/common/vpd_reader.h b/board/ge/common/vpd_reader.h
index e60acf3d07..3045b7e21e 100644
--- a/board/ge/common/vpd_reader.h
+++ b/board/ge/common/vpd_reader.h
@@ -5,12 +5,18 @@
5 5
6#include "common.h" 6#include "common.h"
7 7
8struct vpd_cache;
9
8/* 10/*
9 * Read VPD from given data, verify content, and call callback 11 * Read VPD from given data, verify content, call callback for each vital
10 * for each vital product data block. 12 * product data block.
13 *
14 * cache: structure used by process block to store VPD information
15 * process_block: callback called for each VPD data block
11 * 16 *
12 * Returns Non-zero on error. Negative numbers encode errno. 17 * Returns Non-zero on error. Negative numbers encode errno.
13 */ 18 */
14int vpd_reader(size_t size, u8 *data, void *userdata, 19int read_vpd(struct vpd_cache *cache,
15 int (*fn)(void *userdata, u8 id, u8 version, u8 type, 20 int (*process_block)(struct vpd_cache *,
16 size_t size, u8 const *data)); 21 u8 id, u8 version, u8 type,
22 size_t size, u8 const *data));
diff --git a/board/ge/mx53ppd/Kconfig b/board/ge/mx53ppd/Kconfig
index 6dc3818cb7..bebb2fab01 100644
--- a/board/ge/mx53ppd/Kconfig
+++ b/board/ge/mx53ppd/Kconfig
@@ -13,4 +13,6 @@ config SYS_SOC
13config SYS_CONFIG_NAME 13config SYS_CONFIG_NAME
14 default "mx53ppd" 14 default "mx53ppd"
15 15
16source "board/ge/common/Kconfig"
17
16endif 18endif
diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
index cf278e8f47..23bfe55541 100644
--- a/board/ge/mx53ppd/mx53ppd.c
+++ b/board/ge/mx53ppd/mx53ppd.c
@@ -40,13 +40,6 @@
40 40
41DECLARE_GLOBAL_DATA_PTR; 41DECLARE_GLOBAL_DATA_PTR;
42 42
43/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
44#define VPD_EEPROM_BUS 2
45
46/* Address of 24C08 EEPROM. */
47#define VPD_EEPROM_ADDR 0x50
48#define VPD_EEPROM_ADDR_LEN 1
49
50static u32 mx53_dram_size[2]; 43static u32 mx53_dram_size[2];
51 44
52phys_size_t get_effective_memsize(void) 45phys_size_t get_effective_memsize(void)
@@ -297,10 +290,10 @@ struct vpd_cache {
297/* 290/*
298 * Extracts MAC and product information from the VPD. 291 * Extracts MAC and product information from the VPD.
299 */ 292 */
300static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size, 293static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version,
301 u8 const *data) 294 u8 type, size_t size, u8 const *data)
302{ 295{
303 struct vpd_cache *vpd = (struct vpd_cache *)userdata; 296 struct vpd_cache *vpd = userdata;
304 297
305 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID && 298 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
306 size >= 1) { 299 size >= 1) {
@@ -328,35 +321,6 @@ static void process_vpd(struct vpd_cache *vpd)
328 eth_env_set_enetaddr("ethaddr", vpd->mac1); 321 eth_env_set_enetaddr("ethaddr", vpd->mac1);
329} 322}
330 323
331static int read_vpd(uint eeprom_bus)
332{
333 struct vpd_cache vpd;
334 int res;
335 int size = 1024;
336 u8 *data;
337 unsigned int current_i2c_bus = i2c_get_bus_num();
338
339 res = i2c_set_bus_num(eeprom_bus);
340 if (res < 0)
341 return res;
342
343 data = malloc(size);
344 if (!data)
345 return -ENOMEM;
346
347 res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size);
348 if (res == 0) {
349 memset(&vpd, 0, sizeof(vpd));
350 vpd_reader(size, data, &vpd, vpd_callback);
351 process_vpd(&vpd);
352 }
353
354 free(data);
355
356 i2c_set_bus_num(current_i2c_bus);
357 return res;
358}
359
360int board_init(void) 324int board_init(void)
361{ 325{
362 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 326 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -389,8 +353,14 @@ int misc_init_r(void)
389int board_late_init(void) 353int board_late_init(void)
390{ 354{
391 int res; 355 int res;
356 struct vpd_cache vpd;
392 357
393 read_vpd(VPD_EEPROM_BUS); 358 memset(&vpd, 0, sizeof(vpd));
359 res = read_vpd(&vpd, vpd_callback);
360 if (!res)
361 process_vpd(&vpd);
362 else
363 printf("Can't read VPD");
394 364
395 res = clock_1GHz(); 365 res = clock_1GHz();
396 if (res != 0) 366 if (res != 0)
diff --git a/board/imgtec/ci20/Kconfig b/board/imgtec/ci20/Kconfig
new file mode 100644
index 0000000000..82bf65d64f
--- /dev/null
+++ b/board/imgtec/ci20/Kconfig
@@ -0,0 +1,15 @@
1if TARGET_JZ4780_CI20
2
3config SYS_BOARD
4 default "ci20"
5
6config SYS_VENDOR
7 default "imgtec"
8
9config SYS_CONFIG_NAME
10 default "ci20"
11
12config SYS_TEXT_BASE
13 default 0x80000000
14
15endif
diff --git a/board/imgtec/ci20/MAINTAINERS b/board/imgtec/ci20/MAINTAINERS
new file mode 100644
index 0000000000..dca6bf3537
--- /dev/null
+++ b/board/imgtec/ci20/MAINTAINERS
@@ -0,0 +1,6 @@
1Creator CI20 BOARD
2M: Ezequiel Garcia <ezequiel@collabora.com>
3S: Maintained
4F: board/imgtec/ci20/
5F: include/configs/ci20.h
6F: configs/ci20_mmc_defconfig
diff --git a/board/imgtec/ci20/Makefile b/board/imgtec/ci20/Makefile
new file mode 100644
index 0000000000..7843b46791
--- /dev/null
+++ b/board/imgtec/ci20/Makefile
@@ -0,0 +1,3 @@
1# SPDX-License-Identifier: GPL-2.0+
2
3obj-y := ci20.o
diff --git a/board/imgtec/ci20/README b/board/imgtec/ci20/README
new file mode 100644
index 0000000000..07d89d7e2b
--- /dev/null
+++ b/board/imgtec/ci20/README
@@ -0,0 +1,10 @@
1CI20 U-Boot
2
3Installation to an SD card:
4 Repartition your card with an MBR such that the first partition starts at an
5 offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image
6 to the card like so:
7
8 dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1
9 dd if=u-boot-dtb.img of=/dev/sdX obs=1K seek=14
10 sync
diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c
new file mode 100644
index 0000000000..9811ef559f
--- /dev/null
+++ b/board/imgtec/ci20/ci20.c
@@ -0,0 +1,362 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * CI20 setup code
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#include <common.h>
10#include <environment.h>
11#include <net.h>
12#include <netdev.h>
13#include <asm/io.h>
14#include <asm/gpio.h>
15#include <mach/jz4780.h>
16#include <mach/jz4780_dram.h>
17#include <mach/jz4780_gpio.h>
18
19struct ci20_otp {
20 u32 serial_number;
21 u32 date;
22 u8 manufacturer[2];
23 u8 mac[6];
24} __packed;
25
26static void ci20_mux_mmc(void)
27{
28 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
29
30 /* setup MSC1 pins */
31 writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
32 writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
33 writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
34 writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
35 writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
36 jz4780_clk_ungate_mmc();
37}
38
39#ifndef CONFIG_SPL_BUILD
40
41static void ci20_mux_eth(void)
42{
43 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
44
45#ifdef CONFIG_NAND
46 /* setup pins (some already setup for NAND) */
47 writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
48 writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
49 writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
50 writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
51 writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
52#else
53 /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
54 writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
55 writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
56 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
57 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
58 writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
59 writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
60 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
61 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
62 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
63 writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
64#endif
65}
66
67static void ci20_mux_jtag(void)
68{
69#ifdef CONFIG_JTAG
70 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
71
72 /* enable JTAG */
73 writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
74 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
75 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
76 writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
77#endif
78}
79
80static void ci20_mux_nand(void)
81{
82 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
83
84 /* setup pins */
85 writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
86 writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
87 writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
88 writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
89 writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
90 writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
91 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
92 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
93 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
94 writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
95
96 /* FRB0_N */
97 jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
98 writel(20, gpio_regs + GPIO_PXPENS(0));
99
100 /* disable write protect */
101 jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
102}
103
104static void ci20_mux_uart(void)
105{
106 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
107
108 /* UART0 */
109 writel(0x9, gpio_regs + GPIO_PXINTC(5));
110 writel(0x9, gpio_regs + GPIO_PXMASKC(5));
111 writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
112 writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
113 writel(0x9, gpio_regs + GPIO_PXPENC(5));
114 jz4780_clk_ungate_uart(0);
115
116 /* UART 1 and 2 */
117 jz4780_clk_ungate_uart(1);
118 jz4780_clk_ungate_uart(2);
119
120#ifndef CONFIG_JTAG
121 /* UART3 */
122 writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
123 writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
124 writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
125 writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
126 writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
127 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
128 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
129 writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
130 writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
131 jz4780_clk_ungate_uart(3);
132#endif
133
134 /* UART4 */
135 writel(0x100400, gpio_regs + GPIO_PXINTC(2));
136 writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
137 writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
138 writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
139 writel(0x100400, gpio_regs + GPIO_PXPENC(2));
140 jz4780_clk_ungate_uart(4);
141}
142
143int board_early_init_f(void)
144{
145 ci20_mux_jtag();
146 ci20_mux_uart();
147
148 ci20_mux_eth();
149 ci20_mux_mmc();
150 ci20_mux_nand();
151
152 /* SYS_POWER_IND high (LED blue, VBUS off) */
153 jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
154
155 /* LEDs off */
156 jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
157 jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
158 jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
159 jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
160
161 return 0;
162}
163
164int misc_init_r(void)
165{
166 const u32 efuse_clk = jz4780_clk_get_efuse_clk();
167 struct ci20_otp otp;
168 char manufacturer[3];
169
170 /* Read the board OTP data */
171 jz4780_efuse_init(efuse_clk);
172 jz4780_efuse_read(0x18, 16, (u8 *)&otp);
173
174 /* Set MAC address */
175 if (!is_valid_ethaddr(otp.mac)) {
176 /* no MAC assigned, generate one from the unique chip ID */
177 jz4780_efuse_read(0x8, 4, &otp.mac[0]);
178 jz4780_efuse_read(0x12, 2, &otp.mac[4]);
179 otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
180 }
181 eth_env_set_enetaddr("ethaddr", otp.mac);
182
183 /* Put other board information into the environment */
184 env_set_ulong("serial#", otp.serial_number);
185 env_set_ulong("board_date", otp.date);
186 manufacturer[0] = otp.manufacturer[0];
187 manufacturer[1] = otp.manufacturer[1];
188 manufacturer[2] = 0;
189 env_set("board_mfr", manufacturer);
190
191 return 0;
192}
193
194#ifdef CONFIG_DRIVER_DM9000
195int board_eth_init(bd_t *bis)
196{
197 /* Enable clock */
198 jz4780_clk_ungate_ethernet();
199
200 /* Enable power (PB25) */
201 jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
202
203 /* Reset (PF12) */
204 mdelay(10);
205 jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
206 mdelay(10);
207 jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
208 mdelay(10);
209
210 return dm9000_initialize(bis);
211}
212#endif /* CONFIG_DRIVER_DM9000 */
213#endif
214
215static u8 ci20_revision(void)
216{
217 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
218 int val;
219
220 jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
221 jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
222
223 /* Enable pullups */
224 writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
225
226 /* Read PC18/19 for version */
227 val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
228 ((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
229
230 if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */
231 return 1;
232 if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */
233 return 2;
234
235 return 0;
236}
237
238int dram_init(void)
239{
240 gd->ram_size = sdram_size(0) + sdram_size(1);
241 return 0;
242}
243
244/* U-Boot common routines */
245int checkboard(void)
246{
247 printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
248 return 0;
249}
250
251#ifdef CONFIG_SPL_BUILD
252
253#if defined(CONFIG_SPL_MMC_SUPPORT)
254int board_mmc_init(bd_t *bd)
255{
256 ci20_mux_mmc();
257 return jz_mmc_init((void __iomem *)MSC0_BASE);
258}
259#endif
260
261static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
262 .timing = {
263 (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
264 (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
265
266 (4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
267 (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
268
269 (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
270 (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
271 (21 << DDRC_TIMING3_TRC_BIT),
272
273 (31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
274 (4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
275 (8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
276
277 (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
278 (4 << DDRC_TIMING5_TWDLAT_BIT),
279
280 (25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
281 (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
282 },
283
284 /* PHY */
285 /* Mode Register 0 */
286 .mr0 = 0x420,
287#ifdef SDRAM_DISABLE_DLL
288 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
289#else
290 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
291#endif
292
293 .ptr0 = 0x002000d4,
294 .ptr1 = 0x02230d40,
295 .ptr2 = 0x04013880,
296
297 .dtpr0 = 0x2a8f6690,
298 .dtpr1 = 0x00400860,
299 .dtpr2 = 0x10042a00,
300
301 .pullup = 0x0b,
302 .pulldn = 0x0b,
303};
304
305static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
306 .timing = {
307 (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
308 (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
309
310 (4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
311 (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
312
313 (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
314 (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
315 (22 << DDRC_TIMING3_TRC_BIT),
316
317 (42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
318 (4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
319 (3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
320
321 (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
322 (4 << DDRC_TIMING5_TWDLAT_BIT),
323
324 (25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
325 (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
326 },
327
328 /* PHY */
329 /* Mode Register 0 */
330 .mr0 = 0x420,
331#ifdef SDRAM_DISABLE_DLL
332 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
333#else
334 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
335#endif
336
337 .ptr0 = 0x002000d4,
338 .ptr1 = 0x02d30d40,
339 .ptr2 = 0x04013880,
340
341 .dtpr0 = 0x2c906690,
342 .dtpr1 = 0x005608a0,
343 .dtpr2 = 0x10042a00,
344
345 .pullup = 0x0e,
346 .pulldn = 0x0e,
347};
348
349#if (CONFIG_SYS_MHZ != 1200)
350#error No DDR configuration for CPU speed
351#endif
352
353const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
354{
355 const int board_revision = ci20_revision();
356
357 if (board_revision == 2)
358 return &K4B2G0846Q_48_config;
359 else /* Fall back to H5TQ2G83CFR RAM */
360 return &H5TQ2G83CFR_48_config;
361}
362#endif
diff --git a/board/isee/igep003x/MAINTAINERS b/board/isee/igep003x/MAINTAINERS
index a74938a7d2..ba92e64e2a 100644
--- a/board/isee/igep003x/MAINTAINERS
+++ b/board/isee/igep003x/MAINTAINERS
@@ -1,5 +1,5 @@
1IGEP003X BOARD 1IGEP003X BOARD
2M: Enric Balletbo i Serra <eballetbo@gmail.com> 2M: Javier Martínez Canillas <javier@dowhile0.org>
3S: Maintained 3S: Maintained
4F: board/isee/igep003x/ 4F: board/isee/igep003x/
5F: include/configs/am335x_igep003x.h 5F: include/configs/am335x_igep003x.h
diff --git a/board/mscc/luton/Kconfig b/board/mscc/luton/Kconfig
new file mode 100644
index 0000000000..e1199808d5
--- /dev/null
+++ b/board/mscc/luton/Kconfig
@@ -0,0 +1,14 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3if SOC_LUTON
4
5config SYS_VENDOR
6 default "mscc"
7
8config SYS_BOARD
9 default "luton"
10
11config SYS_CONFIG_NAME
12 default "luton"
13
14endif
diff --git a/board/mscc/luton/Makefile b/board/mscc/luton/Makefile
new file mode 100644
index 0000000000..b27f7c7739
--- /dev/null
+++ b/board/mscc/luton/Makefile
@@ -0,0 +1,3 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3obj-$(CONFIG_SOC_LUTON) := luton.o
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
new file mode 100644
index 0000000000..41fc6d56a7
--- /dev/null
+++ b/board/mscc/luton/luton.c
@@ -0,0 +1,28 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
7#include <asm/io.h>
8
9#define MSCC_GPIO_ALT0 0x88
10#define MSCC_GPIO_ALT1 0x8C
11
12DECLARE_GLOBAL_DATA_PTR;
13
14void board_debug_uart_init(void)
15{
16 /* too early for the pinctrl driver, so configure the UART pins here */
17 setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
18}
19
20int board_early_init_r(void)
21{
22 /* Prepare SPI controller to be used in master mode */
23 writel(0, BASE_CFG + ICPU_SW_MODE);
24
25 /* Address of boot parameters */
26 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
27 return 0;
28}
diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig
new file mode 100644
index 0000000000..9ddc0880b1
--- /dev/null
+++ b/board/mscc/ocelot/Kconfig
@@ -0,0 +1,14 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3config SYS_VENDOR
4 default "mscc"
5
6if SOC_OCELOT
7
8config SYS_BOARD
9 default "ocelot"
10
11config SYS_CONFIG_NAME
12 default "ocelot"
13
14endif
diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile
new file mode 100644
index 0000000000..9f28c81268
--- /dev/null
+++ b/board/mscc/ocelot/Makefile
@@ -0,0 +1,4 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3obj-$(CONFIG_SOC_OCELOT) := ocelot.o
4
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
new file mode 100644
index 0000000000..d521a61957
--- /dev/null
+++ b/board/mscc/ocelot/ocelot.c
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/addrspace.h>
9#include <asm/types.h>
10#include <environment.h>
11#include <spi.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
15#define MSCC_GPIO_ALT0 0x54
16#define MSCC_GPIO_ALT1 0x58
17
18void external_cs_manage(struct udevice *dev, bool enable)
19{
20 u32 cs = spi_chip_select(dev);
21 /* IF_SI0_OWNER, select the owner of the SI interface
22 * Encoding: 0: SI Slave
23 * 1: SI Boot Master
24 * 2: SI Master Controller
25 */
26 if (!enable) {
27 writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
28 ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
29 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
30 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
31 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
32 } else {
33 writel(0, BASE_CFG + ICPU_SW_MODE);
34 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
35 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
36 ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
37 }
38}
39
40void board_debug_uart_init(void)
41{
42 /* too early for the pinctrl driver, so configure the UART pins here */
43 setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
44 clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
45}
46
47int board_early_init_r(void)
48{
49 /* Prepare SPI controller to be used in master mode */
50 writel(0, BASE_CFG + ICPU_SW_MODE);
51 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
52 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
53 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
54
55 /* Address of boot parameters */
56 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
57 return 0;
58}
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 917f5b18f6..f022f365e9 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -637,6 +637,13 @@ void sunxi_board_init(void)
637 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 637 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
638#endif 638#endif
639#endif 639#endif
640 printf("DRAM:");
641 gd->ram_size = sunxi_dram_init();
642 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
643 if (!gd->ram_size)
644 hang();
645
646 sunxi_spl_store_dram_size(gd->ram_size);
640 647
641 /* 648 /*
642 * Only clock up the CPU to full speed if we are reasonably 649 * Only clock up the CPU to full speed if we are reasonably
@@ -645,16 +652,7 @@ void sunxi_board_init(void)
645 if (!power_failed) 652 if (!power_failed)
646 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 653 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
647 else 654 else
648 printf("Error setting up the power controller.\n" 655 printf("Failed to set core voltage! Can't set CPU frequency\n");
649 "CPU frequency not set.\n");
650
651 printf("DRAM:");
652 gd->ram_size = sunxi_dram_init();
653 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
654 if (!gd->ram_size)
655 hang();
656
657 sunxi_spl_store_dram_size(gd->ram_size);
658} 656}
659#endif 657#endif
660 658
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 4db1757469..19cf748c5d 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -42,14 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
42#define USB_CDET_GPIO 102 42#define USB_CDET_GPIO 102
43 43
44static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { 44static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
45 /* levelling */
46 { DDRMC_CR97_WRLVL_EN, 97 },
47 { DDRMC_CR98_WRLVL_DL_0(0), 98 },
48 { DDRMC_CR99_WRLVL_DL_1(0), 99 },
49 { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
50 { DDRMC_CR105_RDLVL_DL_0(0), 105 },
51 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
52 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
53 /* AXI */ 45 /* AXI */
54 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, 46 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
55 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, 47 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
@@ -88,7 +80,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
88 DDRMC_CR154_PAD_ZQ_MODE(1) | 80 DDRMC_CR154_PAD_ZQ_MODE(1) |
89 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 81 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
90 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, 82 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
91 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, 83 { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
92 { DDRMC_CR158_TWR(6), 158 }, 84 { DDRMC_CR158_TWR(6), 158 },
93 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | 85 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
94 DDRMC_CR161_TODTH_WR(2), 161 }, 86 DDRMC_CR161_TODTH_WR(2), 161 },
diff --git a/cmd/cbfs.c b/cmd/cbfs.c
index ece790e56e..c118a952ac 100644
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -112,12 +112,21 @@ static int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc,
112 printf(" %8d", file_cbfs_size(file)); 112 printf(" %8d", file_cbfs_size(file));
113 113
114 switch (type) { 114 switch (type) {
115 case CBFS_TYPE_BOOTBLOCK:
116 type_name = "bootblock";
117 break;
118 case CBFS_TYPE_CBFSHEADER:
119 type_name = "cbfs header";
120 break;
115 case CBFS_TYPE_STAGE: 121 case CBFS_TYPE_STAGE:
116 type_name = "stage"; 122 type_name = "stage";
117 break; 123 break;
118 case CBFS_TYPE_PAYLOAD: 124 case CBFS_TYPE_PAYLOAD:
119 type_name = "payload"; 125 type_name = "payload";
120 break; 126 break;
127 case CBFS_TYPE_FIT:
128 type_name = "fit";
129 break;
121 case CBFS_TYPE_OPTIONROM: 130 case CBFS_TYPE_OPTIONROM:
122 type_name = "option rom"; 131 type_name = "option rom";
123 break; 132 break;
@@ -136,10 +145,31 @@ static int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc,
136 case CBFS_TYPE_MICROCODE: 145 case CBFS_TYPE_MICROCODE:
137 type_name = "microcode"; 146 type_name = "microcode";
138 break; 147 break;
139 case CBFS_COMPONENT_CMOS_DEFAULT: 148 case CBFS_TYPE_FSP:
149 type_name = "fsp";
150 break;
151 case CBFS_TYPE_MRC:
152 type_name = "mrc";
153 break;
154 case CBFS_TYPE_MMA:
155 type_name = "mma";
156 break;
157 case CBFS_TYPE_EFI:
158 type_name = "efi";
159 break;
160 case CBFS_TYPE_STRUCT:
161 type_name = "struct";
162 break;
163 case CBFS_TYPE_CMOS_DEFAULT:
140 type_name = "cmos default"; 164 type_name = "cmos default";
141 break; 165 break;
142 case CBFS_COMPONENT_CMOS_LAYOUT: 166 case CBFS_TYPE_SPD:
167 type_name = "spd";
168 break;
169 case CBFS_TYPE_MRC_CACHE:
170 type_name = "mrc cache";
171 break;
172 case CBFS_TYPE_CMOS_LAYOUT:
143 type_name = "cmos layout"; 173 type_name = "cmos layout";
144 break; 174 break;
145 case -1: 175 case -1:
diff --git a/common/bootm_os.c b/common/bootm_os.c
index f302135868..855c471c28 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -260,7 +260,7 @@ static int do_bootm_plan9(int flag, int argc, char * const argv[],
260#if defined(CONFIG_BOOTM_VXWORKS) && \ 260#if defined(CONFIG_BOOTM_VXWORKS) && \
261 (defined(CONFIG_PPC) || defined(CONFIG_ARM)) 261 (defined(CONFIG_PPC) || defined(CONFIG_ARM))
262 262
263void do_bootvx_fdt(bootm_headers_t *images) 263static void do_bootvx_fdt(bootm_headers_t *images)
264{ 264{
265#if defined(CONFIG_OF_LIBFDT) 265#if defined(CONFIG_OF_LIBFDT)
266 int ret; 266 int ret;
@@ -317,8 +317,8 @@ void do_bootvx_fdt(bootm_headers_t *images)
317 puts("## vxWorks terminated\n"); 317 puts("## vxWorks terminated\n");
318} 318}
319 319
320static int do_bootm_vxworks(int flag, int argc, char * const argv[], 320int do_bootm_vxworks(int flag, int argc, char * const argv[],
321 bootm_headers_t *images) 321 bootm_headers_t *images)
322{ 322{
323 if (flag != BOOTM_STATE_OS_GO) 323 if (flag != BOOTM_STATE_OS_GO)
324 return 0; 324 return 0;
@@ -482,7 +482,7 @@ static boot_os_fn *boot_os[] = {
482 [IH_OS_PLAN9] = do_bootm_plan9, 482 [IH_OS_PLAN9] = do_bootm_plan9,
483#endif 483#endif
484#if defined(CONFIG_BOOTM_VXWORKS) && \ 484#if defined(CONFIG_BOOTM_VXWORKS) && \
485 (defined(CONFIG_PPC) || defined(CONFIG_ARM)) 485 (defined(CONFIG_PPC) || defined(CONFIG_ARM) || defined(CONFIG_RISCV))
486 [IH_OS_VXWORKS] = do_bootm_vxworks, 486 [IH_OS_VXWORKS] = do_bootm_vxworks,
487#endif 487#endif
488#if defined(CONFIG_CMD_ELF) 488#if defined(CONFIG_CMD_ELF)
diff --git a/common/image.c b/common/image.c
index 0659133fcc..4d4248f234 100644
--- a/common/image.c
+++ b/common/image.c
@@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = {
140 { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, 140 { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",},
141 { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, 141 { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",},
142 { IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",}, 142 { IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",},
143 { IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot Image",},
143 { IH_TYPE_INVALID, "invalid", "Invalid Image", }, 144 { IH_TYPE_INVALID, "invalid", "Invalid Image", },
144 { IH_TYPE_MULTI, "multi", "Multi-File Image", }, 145 { IH_TYPE_MULTI, "multi", "Multi-File Image", },
145 { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",}, 146 { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",},
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 953841ebe7..37ecbc6b1c 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -286,6 +286,7 @@ config SPL_FIT_IMAGE_TINY
286 bool "Remove functionality from SPL FIT loading to reduce size" 286 bool "Remove functionality from SPL FIT loading to reduce size"
287 depends on SPL_FIT 287 depends on SPL_FIT
288 default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 288 default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
289 default y if ARCH_IMX8M
289 help 290 help
290 Enable this to reduce the size of the FIT image loading code 291 Enable this to reduce the size of the FIT image loading code
291 in SPL, if space for the SPL binary is very tight. 292 in SPL, if space for the SPL binary is very tight.
@@ -775,13 +776,13 @@ config SPL_USB_SUPPORT
775 config options. This enables loading from USB using a configured 776 config options. This enables loading from USB using a configured
776 device. 777 device.
777 778
778config SPL_USB_GADGET_SUPPORT 779config SPL_USB_GADGET
779 bool "Suppport USB Gadget drivers" 780 bool "Suppport USB Gadget drivers"
780 help 781 help
781 Enable USB Gadget API which allows to enable USB device functions 782 Enable USB Gadget API which allows to enable USB device functions
782 in SPL. 783 in SPL.
783 784
784if SPL_USB_GADGET_SUPPORT 785if SPL_USB_GADGET
785 786
786config SPL_USB_ETHER 787config SPL_USB_ETHER
787 bool "Support USB Ethernet drivers" 788 bool "Support USB Ethernet drivers"
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index faf4ddbd1f..db436268cb 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -15,6 +15,15 @@
15#define CONFIG_SYS_BOOTM_LEN (64 << 20) 15#define CONFIG_SYS_BOOTM_LEN (64 << 20)
16#endif 16#endif
17 17
18__weak void board_spl_fit_post_load(ulong load_addr, size_t length)
19{
20}
21
22__weak ulong board_spl_fit_size_align(ulong size)
23{
24 return size;
25}
26
18/** 27/**
19 * spl_fit_get_image_name(): By using the matching configuration subnode, 28 * spl_fit_get_image_name(): By using the matching configuration subnode,
20 * retrieve the name of an image, specified by a property name and an index 29 * retrieve the name of an image, specified by a property name and an index
@@ -350,6 +359,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
350 */ 359 */
351 size = fdt_totalsize(fit); 360 size = fdt_totalsize(fit);
352 size = (size + 3) & ~3; 361 size = (size + 3) & ~3;
362 size = board_spl_fit_size_align(size);
353 base_offset = (size + 3) & ~3; 363 base_offset = (size + 3) & ~3;
354 364
355 /* 365 /*
@@ -373,8 +383,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
373 fit = spl_get_load_buffer(-hsize, hsize); 383 fit = spl_get_load_buffer(-hsize, hsize);
374 sectors = get_aligned_image_size(info, size, 0); 384 sectors = get_aligned_image_size(info, size, 0);
375 count = info->read(info, sector, sectors, fit); 385 count = info->read(info, sector, sectors, fit);
376 debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n", 386 debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
377 sector, sectors, fit, count); 387 sector, sectors, fit, count, size);
388
378 if (count == 0) 389 if (count == 0)
379 return -EIO; 390 return -EIO;
380 391
@@ -510,5 +521,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
510 if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0) 521 if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0)
511 spl_image->entry_point = spl_image->load_addr; 522 spl_image->entry_point = spl_image->load_addr;
512 523
524 spl_image->flags |= SPL_FIT_FOUND;
525
526#ifdef CONFIG_SECURE_BOOT
527 board_spl_fit_post_load((ulong)fit, size);
528#endif
529
513 return 0; 530 return 0;
514} 531}
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index dee8d028ee..3e9f57446c 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -26,9 +26,9 @@ CONFIG_ETH_DESIGNWARE=y
26CONFIG_RGMII=y 26CONFIG_RGMII=y
27CONFIG_MII=y 27CONFIG_MII=y
28CONFIG_SUN7I_GMAC=y 28CONFIG_SUN7I_GMAC=y
29CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
30CONFIG_AXP_ALDO3_VOLT=2800 29CONFIG_AXP_ALDO3_VOLT=2800
31CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y 30CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
31CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
32CONFIG_AXP_ALDO4_VOLT=2800 32CONFIG_AXP_ALDO4_VOLT=2800
33CONFIG_SCSI=y 33CONFIG_SCSI=y
34CONFIG_USB_EHCI_HCD=y 34CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 0c04ae6491..e7ca33576a 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -25,9 +25,9 @@ CONFIG_ETH_DESIGNWARE=y
25CONFIG_RGMII=y 25CONFIG_RGMII=y
26CONFIG_MII=y 26CONFIG_MII=y
27CONFIG_SUN7I_GMAC=y 27CONFIG_SUN7I_GMAC=y
28CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
29CONFIG_AXP_ALDO3_VOLT=2800 28CONFIG_AXP_ALDO3_VOLT=2800
30CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y 29CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
30CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
31CONFIG_AXP_ALDO4_VOLT=2800 31CONFIG_AXP_ALDO4_VOLT=2800
32CONFIG_SCSI=y 32CONFIG_SCSI=y
33CONFIG_USB_EHCI_HCD=y 33CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index 33c6073648..3fa68babe7 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -64,19 +64,18 @@ CONFIG_CMD_DHCP=y
64CONFIG_CMD_MII=y 64CONFIG_CMD_MII=y
65CONFIG_CMD_PING=y 65CONFIG_CMD_PING=y
66# CONFIG_CMD_MISC is not set 66# CONFIG_CMD_MISC is not set
67CONFIG_OF_CONTROL=y
68CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
67CONFIG_ENV_IS_IN_FLASH=y 69CONFIG_ENV_IS_IN_FLASH=y
70CONFIG_DM=y
68# CONFIG_MMC is not set 71# CONFIG_MMC is not set
69CONFIG_MTD_NOR_FLASH=y 72CONFIG_MTD_NOR_FLASH=y
70CONFIG_FLASH_CFI_DRIVER=y 73CONFIG_FLASH_CFI_DRIVER=y
71CONFIG_SYS_FLASH_CFI=y 74CONFIG_SYS_FLASH_CFI=y
72CONFIG_MPC8XX_FEC=y 75CONFIG_MPC8XX_FEC=y
73# CONFIG_PCI is not set 76# CONFIG_PCI is not set
74CONFIG_SHA256=y 77CONFIG_DM_SERIAL=y
75CONFIG_LZMA=y
76CONFIG_OF_LIBFDT=y
77CONFIG_DM=y
78CONFIG_OF_CONTROL=y
79CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
80CONFIG_WDT=y 78CONFIG_WDT=y
81CONFIG_WDT_MPC8xx=y 79CONFIG_WDT_MPC8xx=y
82CONFIG_DM_SERIAL=y 80CONFIG_SHA256=y
81CONFIG_LZMA=y
diff --git a/configs/a25-ae350_32_defconfig b/configs/ae350_rv32_defconfig
index 5837b48903..5837b48903 100644
--- a/configs/a25-ae350_32_defconfig
+++ b/configs/ae350_rv32_defconfig
diff --git a/configs/ax25-ae350_64_defconfig b/configs/ae350_rv64_defconfig
index b250d3fc7e..b250d3fc7e 100644
--- a/configs/ax25-ae350_64_defconfig
+++ b/configs/ae350_rv64_defconfig
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 05d41aea87..d2c8825a18 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -61,7 +61,6 @@ CONFIG_DM_USB=y
61CONFIG_USB_MUSB_HOST=y 61CONFIG_USB_MUSB_HOST=y
62CONFIG_USB_MUSB_GADGET=y 62CONFIG_USB_MUSB_GADGET=y
63CONFIG_USB_MUSB_DSPS=y 63CONFIG_USB_MUSB_DSPS=y
64CONFIG_USB_STORAGE=y
65CONFIG_USB_GADGET=y 64CONFIG_USB_GADGET=y
66CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 65CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
67CONFIG_USB_GADGET_VENDOR_NUM=0x0403 66CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 90ccf9adfe..439d0cba05 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -32,15 +32,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
32CONFIG_MMC_OMAP_HS=y 32CONFIG_MMC_OMAP_HS=y
33CONFIG_SPI_FLASH=y 33CONFIG_SPI_FLASH=y
34CONFIG_SPI_FLASH_WINBOND=y 34CONFIG_SPI_FLASH_WINBOND=y
35CONFIG_DRIVER_TI_CPSW=y
36CONFIG_MII=y 35CONFIG_MII=y
36CONFIG_DRIVER_TI_CPSW=y
37CONFIG_SPI=y 37CONFIG_SPI=y
38CONFIG_OMAP3_SPI=y 38CONFIG_OMAP3_SPI=y
39CONFIG_USB=y 39CONFIG_USB=y
40CONFIG_USB_MUSB_HOST=y 40CONFIG_USB_MUSB_HOST=y
41CONFIG_USB_MUSB_GADGET=y 41CONFIG_USB_MUSB_GADGET=y
42CONFIG_USB_MUSB_DSPS=y 42CONFIG_USB_MUSB_DSPS=y
43CONFIG_USB_STORAGE=y
44CONFIG_USB_GADGET=y 43CONFIG_USB_GADGET=y
45CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 44CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
46CONFIG_USB_GADGET_VENDOR_NUM=0x0451 45CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index be04424375..f455b01e1e 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -16,7 +16,7 @@ CONFIG_SPL_MUSB_NEW_SUPPORT=y
16CONFIG_SPL_NET_SUPPORT=y 16CONFIG_SPL_NET_SUPPORT=y
17CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL" 17CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL"
18CONFIG_SPL_OS_BOOT=y 18CONFIG_SPL_OS_BOOT=y
19CONFIG_SPL_USB_GADGET_SUPPORT=y 19CONFIG_SPL_USB_GADGET=y
20CONFIG_SPL_USB_ETHER=y 20CONFIG_SPL_USB_ETHER=y
21CONFIG_AUTOBOOT_KEYED=y 21CONFIG_AUTOBOOT_KEYED=y
22CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" 22CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
@@ -41,23 +41,21 @@ CONFIG_MMC_OMAP_HS=y
41CONFIG_SPI_FLASH=y 41CONFIG_SPI_FLASH=y
42CONFIG_SPI_FLASH_WINBOND=y 42CONFIG_SPI_FLASH_WINBOND=y
43CONFIG_DM_ETH=y 43CONFIG_DM_ETH=y
44CONFIG_DRIVER_TI_CPSW=y
45CONFIG_PHY_GIGE=y 44CONFIG_PHY_GIGE=y
46CONFIG_MII=y 45CONFIG_MII=y
46CONFIG_DRIVER_TI_CPSW=y
47CONFIG_SPI=y 47CONFIG_SPI=y
48CONFIG_OMAP3_SPI=y 48CONFIG_OMAP3_SPI=y
49CONFIG_TIMER=y 49CONFIG_TIMER=y
50CONFIG_OMAP_TIMER=y 50CONFIG_OMAP_TIMER=y
51CONFIG_USB=y 51CONFIG_USB=y
52CONFIG_DM_USB=y 52CONFIG_DM_USB=y
53CONFIG_SPL_DM_USB=y
54CONFIG_DM_USB_GADGET=y 53CONFIG_DM_USB_GADGET=y
55CONFIG_SPL_DM_USB_GADGET=y 54CONFIG_SPL_DM_USB_GADGET=y
56CONFIG_USB_MUSB_HOST=y 55CONFIG_USB_MUSB_HOST=y
57CONFIG_USB_MUSB_GADGET=y 56CONFIG_USB_MUSB_GADGET=y
58CONFIG_USB_MUSB_TI=y 57CONFIG_USB_MUSB_TI=y
59CONFIG_USB_MUSB_DSPS=y 58CONFIG_USB_MUSB_DSPS=y
60CONFIG_USB_STORAGE=y
61CONFIG_USB_GADGET=y 59CONFIG_USB_GADGET=y
62CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 60CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
63CONFIG_USB_GADGET_VENDOR_NUM=0x0451 61CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 6cc170ad40..0931c1e97f 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -54,7 +54,6 @@ CONFIG_USB_MUSB_HOST=y
54CONFIG_USB_MUSB_GADGET=y 54CONFIG_USB_MUSB_GADGET=y
55CONFIG_USB_MUSB_TI=y 55CONFIG_USB_MUSB_TI=y
56CONFIG_USB_MUSB_DSPS=y 56CONFIG_USB_MUSB_DSPS=y
57CONFIG_USB_STORAGE=y
58CONFIG_USB_GADGET=y 57CONFIG_USB_GADGET=y
59CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 58CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
60CONFIG_USB_GADGET_VENDOR_NUM=0x0451 59CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 54dc7dff78..e08234e9f8 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -35,15 +35,14 @@ CONFIG_SYS_FLASH_CFI=y
35CONFIG_NAND=y 35CONFIG_NAND=y
36CONFIG_SPI_FLASH=y 36CONFIG_SPI_FLASH=y
37CONFIG_SPI_FLASH_WINBOND=y 37CONFIG_SPI_FLASH_WINBOND=y
38CONFIG_DRIVER_TI_CPSW=y
39CONFIG_MII=y 38CONFIG_MII=y
39CONFIG_DRIVER_TI_CPSW=y
40CONFIG_SPI=y 40CONFIG_SPI=y
41CONFIG_OMAP3_SPI=y 41CONFIG_OMAP3_SPI=y
42CONFIG_USB=y 42CONFIG_USB=y
43CONFIG_USB_MUSB_HOST=y 43CONFIG_USB_MUSB_HOST=y
44CONFIG_USB_MUSB_GADGET=y 44CONFIG_USB_MUSB_GADGET=y
45CONFIG_USB_MUSB_DSPS=y 45CONFIG_USB_MUSB_DSPS=y
46CONFIG_USB_STORAGE=y
47CONFIG_USB_GADGET=y 46CONFIG_USB_GADGET=y
48CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 47CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
49CONFIG_USB_GADGET_VENDOR_NUM=0x0451 48CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 5d7ccf0c5a..040384f3c7 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -31,15 +31,14 @@ CONFIG_SYS_FLASH_PROTECTION=y
31CONFIG_SYS_FLASH_CFI=y 31CONFIG_SYS_FLASH_CFI=y
32CONFIG_SPI_FLASH=y 32CONFIG_SPI_FLASH=y
33CONFIG_SPI_FLASH_WINBOND=y 33CONFIG_SPI_FLASH_WINBOND=y
34CONFIG_DRIVER_TI_CPSW=y
35CONFIG_MII=y 34CONFIG_MII=y
35CONFIG_DRIVER_TI_CPSW=y
36CONFIG_SPI=y 36CONFIG_SPI=y
37CONFIG_OMAP3_SPI=y 37CONFIG_OMAP3_SPI=y
38CONFIG_USB=y 38CONFIG_USB=y
39CONFIG_USB_MUSB_HOST=y 39CONFIG_USB_MUSB_HOST=y
40CONFIG_USB_MUSB_GADGET=y 40CONFIG_USB_MUSB_GADGET=y
41CONFIG_USB_MUSB_DSPS=y 41CONFIG_USB_MUSB_DSPS=y
42CONFIG_USB_STORAGE=y
43CONFIG_USB_GADGET=y 42CONFIG_USB_GADGET=y
44CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 43CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
45CONFIG_USB_GADGET_VENDOR_NUM=0x0451 44CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 10a935f0c0..1f430ad416 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -30,15 +30,14 @@ CONFIG_MMC_OMAP_HS=y
30CONFIG_MTD_DEVICE=y 30CONFIG_MTD_DEVICE=y
31CONFIG_SPI_FLASH=y 31CONFIG_SPI_FLASH=y
32CONFIG_SPI_FLASH_WINBOND=y 32CONFIG_SPI_FLASH_WINBOND=y
33CONFIG_DRIVER_TI_CPSW=y
34CONFIG_MII=y 33CONFIG_MII=y
34CONFIG_DRIVER_TI_CPSW=y
35CONFIG_SPI=y 35CONFIG_SPI=y
36CONFIG_OMAP3_SPI=y 36CONFIG_OMAP3_SPI=y
37CONFIG_USB=y 37CONFIG_USB=y
38CONFIG_USB_MUSB_HOST=y 38CONFIG_USB_MUSB_HOST=y
39CONFIG_USB_MUSB_GADGET=y 39CONFIG_USB_MUSB_GADGET=y
40CONFIG_USB_MUSB_DSPS=y 40CONFIG_USB_MUSB_DSPS=y
41CONFIG_USB_STORAGE=y
42CONFIG_USB_GADGET=y 41CONFIG_USB_GADGET=y
43CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 42CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
44CONFIG_USB_GADGET_VENDOR_NUM=0x0451 43CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index ec72538ddc..bda1785e7e 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -16,7 +16,7 @@ CONFIG_SPL_MUSB_NEW_SUPPORT=y
16CONFIG_SPL_NET_SUPPORT=y 16CONFIG_SPL_NET_SUPPORT=y
17CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" 17CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
18CONFIG_SPL_OS_BOOT=y 18CONFIG_SPL_OS_BOOT=y
19CONFIG_SPL_USB_GADGET_SUPPORT=y 19CONFIG_SPL_USB_GADGET=y
20CONFIG_SPL_USB_ETHER=y 20CONFIG_SPL_USB_ETHER=y
21# CONFIG_SPL_YMODEM_SUPPORT is not set 21# CONFIG_SPL_YMODEM_SUPPORT is not set
22CONFIG_CMD_SPL=y 22CONFIG_CMD_SPL=y
@@ -38,15 +38,14 @@ CONFIG_MMC_OMAP_HS=y
38CONFIG_NAND=y 38CONFIG_NAND=y
39CONFIG_SPI_FLASH=y 39CONFIG_SPI_FLASH=y
40CONFIG_SPI_FLASH_WINBOND=y 40CONFIG_SPI_FLASH_WINBOND=y
41CONFIG_DRIVER_TI_CPSW=y
42CONFIG_MII=y 41CONFIG_MII=y
42CONFIG_DRIVER_TI_CPSW=y
43CONFIG_SPI=y 43CONFIG_SPI=y
44CONFIG_OMAP3_SPI=y 44CONFIG_OMAP3_SPI=y
45CONFIG_USB=y 45CONFIG_USB=y
46CONFIG_USB_MUSB_HOST=y 46CONFIG_USB_MUSB_HOST=y
47CONFIG_USB_MUSB_GADGET=y 47CONFIG_USB_MUSB_GADGET=y
48CONFIG_USB_MUSB_DSPS=y 48CONFIG_USB_MUSB_DSPS=y
49CONFIG_USB_STORAGE=y
50CONFIG_USB_GADGET=y 49CONFIG_USB_GADGET=y
51CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 50CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
52CONFIG_USB_GADGET_VENDOR_NUM=0x0451 51CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index 16affb8a05..186c65f0bf 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -44,8 +44,8 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
44CONFIG_MMC_OMAP_HS=y 44CONFIG_MMC_OMAP_HS=y
45CONFIG_NAND=y 45CONFIG_NAND=y
46CONFIG_MTD_UBI_FASTMAP=y 46CONFIG_MTD_UBI_FASTMAP=y
47CONFIG_DRIVER_TI_CPSW=y
48CONFIG_MII=y 47CONFIG_MII=y
48CONFIG_DRIVER_TI_CPSW=y
49CONFIG_SPI=y 49CONFIG_SPI=y
50CONFIG_OMAP3_SPI=y 50CONFIG_OMAP3_SPI=y
51CONFIG_FAT_WRITE=y 51CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index b69cee01e4..e93c411766 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -16,9 +16,9 @@ CONFIG_BOOTDELAY=1
16# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set 16# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
17CONFIG_SPL_I2C_SUPPORT=y 17CONFIG_SPL_I2C_SUPPORT=y
18# CONFIG_SPL_NAND_SUPPORT is not set 18# CONFIG_SPL_NAND_SUPPORT is not set
19CONFIG_SPL_POWER_SUPPORT=y
19CONFIG_SPL_WATCHDOG_SUPPORT=y 20CONFIG_SPL_WATCHDOG_SUPPORT=y
20CONFIG_SPL_YMODEM_SUPPORT=y 21CONFIG_SPL_YMODEM_SUPPORT=y
21CONFIG_SPL_POWER_SUPPORT=y
22CONFIG_AUTOBOOT_KEYED=y 22CONFIG_AUTOBOOT_KEYED=y
23CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" 23CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
24CONFIG_AUTOBOOT_STOP_STR=" " 24CONFIG_AUTOBOOT_STOP_STR=" "
@@ -32,17 +32,13 @@ CONFIG_CMD_PMIC=y
32CONFIG_CMD_REGULATOR=y 32CONFIG_CMD_REGULATOR=y
33CONFIG_OF_CONTROL=y 33CONFIG_OF_CONTROL=y
34CONFIG_SPL_OF_CONTROL=y 34CONFIG_SPL_OF_CONTROL=y
35CONFIG_OF_SEPARATE=y
36CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001" 35CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
37# CONFIG_NET is not set 36# CONFIG_NET is not set
38CONFIG_SPL_DM=y 37CONFIG_SPL_DM=y
39CONFIG_SPL_DM_SEQ_ALIAS=y 38CONFIG_SPL_DM_SEQ_ALIAS=y
40CONFIG_DM_GPIO=y 39CONFIG_DM_GPIO=y
41CONFIG_DM_I2C=y 40CONFIG_DM_I2C=y
42CONFIG_BLK=y
43CONFIG_SPL_BLK=y
44CONFIG_DM_MMC=y 41CONFIG_DM_MMC=y
45CONFIG_SPL_DM_MMC=y
46CONFIG_MMC_OMAP_HS=y 42CONFIG_MMC_OMAP_HS=y
47CONFIG_MMC_SDHCI=y 43CONFIG_MMC_SDHCI=y
48CONFIG_PINCTRL=y 44CONFIG_PINCTRL=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 25e1a4f943..0eaf9c5ab0 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -37,8 +37,8 @@ CONFIG_ENV_IS_IN_MMC=y
37CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 37CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
38CONFIG_MMC_OMAP_HS=y 38CONFIG_MMC_OMAP_HS=y
39CONFIG_PHY_ADDR_ENABLE=y 39CONFIG_PHY_ADDR_ENABLE=y
40CONFIG_DRIVER_TI_CPSW=y
41CONFIG_MII=y 40CONFIG_MII=y
41CONFIG_DRIVER_TI_CPSW=y
42CONFIG_SPI=y 42CONFIG_SPI=y
43CONFIG_OMAP3_SPI=y 43CONFIG_OMAP3_SPI=y
44CONFIG_FAT_WRITE=y 44CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 9ebfe5e7f5..06339a9572 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -38,8 +38,8 @@ CONFIG_ENV_IS_IN_MMC=y
38CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 38CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
39CONFIG_MMC_OMAP_HS=y 39CONFIG_MMC_OMAP_HS=y
40CONFIG_PHY_ADDR_ENABLE=y 40CONFIG_PHY_ADDR_ENABLE=y
41CONFIG_DRIVER_TI_CPSW=y
42CONFIG_MII=y 41CONFIG_MII=y
42CONFIG_DRIVER_TI_CPSW=y
43CONFIG_SPI=y 43CONFIG_SPI=y
44CONFIG_OMAP3_SPI=y 44CONFIG_OMAP3_SPI=y
45CONFIG_FAT_WRITE=y 45CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 064b3c355c..25582f3dfc 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -39,8 +39,8 @@ CONFIG_ENV_IS_IN_MMC=y
39CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 39CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
40CONFIG_MMC_OMAP_HS=y 40CONFIG_MMC_OMAP_HS=y
41CONFIG_PHY_ADDR_ENABLE=y 41CONFIG_PHY_ADDR_ENABLE=y
42CONFIG_DRIVER_TI_CPSW=y
43CONFIG_MII=y 42CONFIG_MII=y
43CONFIG_DRIVER_TI_CPSW=y
44CONFIG_SPI=y 44CONFIG_SPI=y
45CONFIG_OMAP3_SPI=y 45CONFIG_OMAP3_SPI=y
46CONFIG_FAT_WRITE=y 46CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
index dce8334732..5a08c9bcc3 100644
--- a/configs/am335x_shc_prompt_defconfig
+++ b/configs/am335x_shc_prompt_defconfig
@@ -36,8 +36,8 @@ CONFIG_ENV_IS_IN_MMC=y
36CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 36CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
37CONFIG_MMC_OMAP_HS=y 37CONFIG_MMC_OMAP_HS=y
38CONFIG_PHY_ADDR_ENABLE=y 38CONFIG_PHY_ADDR_ENABLE=y
39CONFIG_DRIVER_TI_CPSW=y
40CONFIG_MII=y 39CONFIG_MII=y
40CONFIG_DRIVER_TI_CPSW=y
41CONFIG_SPI=y 41CONFIG_SPI=y
42CONFIG_OMAP3_SPI=y 42CONFIG_OMAP3_SPI=y
43CONFIG_FAT_WRITE=y 43CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index e4e6adef19..7b74e850fc 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -38,8 +38,8 @@ CONFIG_ENV_IS_IN_MMC=y
38CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 38CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
39CONFIG_MMC_OMAP_HS=y 39CONFIG_MMC_OMAP_HS=y
40CONFIG_PHY_ADDR_ENABLE=y 40CONFIG_PHY_ADDR_ENABLE=y
41CONFIG_DRIVER_TI_CPSW=y
42CONFIG_MII=y 41CONFIG_MII=y
42CONFIG_DRIVER_TI_CPSW=y
43CONFIG_SPI=y 43CONFIG_SPI=y
44CONFIG_OMAP3_SPI=y 44CONFIG_OMAP3_SPI=y
45CONFIG_FAT_WRITE=y 45CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
index e4e6adef19..7b74e850fc 100644
--- a/configs/am335x_shc_sdboot_prompt_defconfig
+++ b/configs/am335x_shc_sdboot_prompt_defconfig
@@ -38,8 +38,8 @@ CONFIG_ENV_IS_IN_MMC=y
38CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 38CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
39CONFIG_MMC_OMAP_HS=y 39CONFIG_MMC_OMAP_HS=y
40CONFIG_PHY_ADDR_ENABLE=y 40CONFIG_PHY_ADDR_ENABLE=y
41CONFIG_DRIVER_TI_CPSW=y
42CONFIG_MII=y 41CONFIG_MII=y
42CONFIG_DRIVER_TI_CPSW=y
43CONFIG_SPI=y 43CONFIG_SPI=y
44CONFIG_OMAP3_SPI=y 44CONFIG_OMAP3_SPI=y
45CONFIG_FAT_WRITE=y 45CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index a45fd3d1c5..822f73d114 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -41,8 +41,8 @@ CONFIG_ENV_IS_IN_MMC=y
41CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 41CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
42CONFIG_BOOTCOUNT_LIMIT=y 42CONFIG_BOOTCOUNT_LIMIT=y
43CONFIG_MMC_OMAP_HS=y 43CONFIG_MMC_OMAP_HS=y
44CONFIG_DRIVER_TI_CPSW=y
45CONFIG_MII=y 44CONFIG_MII=y
45CONFIG_DRIVER_TI_CPSW=y
46CONFIG_SPI=y 46CONFIG_SPI=y
47CONFIG_OMAP3_SPI=y 47CONFIG_OMAP3_SPI=y
48CONFIG_FAT_WRITE=y 48CONFIG_FAT_WRITE=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 14805575ab..0fe3f7ef09 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -20,7 +20,6 @@ CONFIG_SYS_PROMPT="AM3517_EVM # "
20CONFIG_CMD_SPL=y 20CONFIG_CMD_SPL=y
21CONFIG_CMD_SPL_NAND_OFS=0xaa0000 21CONFIG_CMD_SPL_NAND_OFS=0xaa0000
22CONFIG_CMD_SPL_WRITE_SIZE=0x20000 22CONFIG_CMD_SPL_WRITE_SIZE=0x20000
23# CONFIG_CMD_EEPROM is not set
24# CONFIG_CMD_FLASH is not set 23# CONFIG_CMD_FLASH is not set
25# CONFIG_CMD_GPT is not set 24# CONFIG_CMD_GPT is not set
26CONFIG_CMD_NAND=y 25CONFIG_CMD_NAND=y
@@ -54,4 +53,3 @@ CONFIG_USB=y
54CONFIG_USB_MUSB_HOST=y 53CONFIG_USB_MUSB_HOST=y
55CONFIG_USB_MUSB_AM35X=y 54CONFIG_USB_MUSB_AM35X=y
56CONFIG_BCH=y 55CONFIG_BCH=y
57# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 9bbda434ee..e3464145eb 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -16,7 +16,7 @@ CONFIG_SPL_MTD_SUPPORT=y
16CONFIG_SPL_NET_SUPPORT=y 16CONFIG_SPL_NET_SUPPORT=y
17CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" 17CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
18CONFIG_SPL_OS_BOOT=y 18CONFIG_SPL_OS_BOOT=y
19CONFIG_SPL_USB_GADGET_SUPPORT=y 19CONFIG_SPL_USB_GADGET=y
20CONFIG_SPL_USB_ETHER=y 20CONFIG_SPL_USB_ETHER=y
21CONFIG_CMD_SPL=y 21CONFIG_CMD_SPL=y
22CONFIG_CMD_SPL_NAND_OFS=0x00100000 22CONFIG_CMD_SPL_NAND_OFS=0x00100000
@@ -47,9 +47,9 @@ CONFIG_MMC_OMAP_HS=y
47CONFIG_NAND=y 47CONFIG_NAND=y
48CONFIG_SPI_FLASH=y 48CONFIG_SPI_FLASH=y
49CONFIG_SPI_FLASH_MACRONIX=y 49CONFIG_SPI_FLASH_MACRONIX=y
50CONFIG_DRIVER_TI_CPSW=y
51CONFIG_PHY_GIGE=y 50CONFIG_PHY_GIGE=y
52CONFIG_MII=y 51CONFIG_MII=y
52CONFIG_DRIVER_TI_CPSW=y
53CONFIG_PHY=y 53CONFIG_PHY=y
54CONFIG_SPL_PHY=y 54CONFIG_SPL_PHY=y
55CONFIG_OMAP_USB2_PHY=y 55CONFIG_OMAP_USB2_PHY=y
@@ -60,7 +60,6 @@ CONFIG_TIMER=y
60CONFIG_OMAP_TIMER=y 60CONFIG_OMAP_TIMER=y
61CONFIG_USB=y 61CONFIG_USB=y
62CONFIG_DM_USB=y 62CONFIG_DM_USB=y
63CONFIG_SPL_DM_USB=y
64CONFIG_DM_USB_GADGET=y 63CONFIG_DM_USB_GADGET=y
65CONFIG_SPL_DM_USB_GADGET=y 64CONFIG_SPL_DM_USB_GADGET=y
66CONFIG_USB_XHCI_HCD=y 65CONFIG_USB_XHCI_HCD=y
@@ -71,7 +70,6 @@ CONFIG_USB_DWC3_OMAP=y
71CONFIG_USB_DWC3_GENERIC=y 70CONFIG_USB_DWC3_GENERIC=y
72CONFIG_USB_DWC3_PHY_OMAP=y 71CONFIG_USB_DWC3_PHY_OMAP=y
73CONFIG_OMAP_USB_PHY=y 72CONFIG_OMAP_USB_PHY=y
74CONFIG_USB_STORAGE=y
75CONFIG_USB_GADGET=y 73CONFIG_USB_GADGET=y
76CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 74CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
77CONFIG_USB_GADGET_VENDOR_NUM=0x0403 75CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index ea46236bc4..c1b32be190 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -43,8 +43,8 @@ CONFIG_MMC_OMAP_HS=y
43CONFIG_NAND=y 43CONFIG_NAND=y
44CONFIG_SPI_FLASH=y 44CONFIG_SPI_FLASH=y
45CONFIG_SPI_FLASH_MACRONIX=y 45CONFIG_SPI_FLASH_MACRONIX=y
46CONFIG_DRIVER_TI_CPSW=y
47CONFIG_MII=y 46CONFIG_MII=y
47CONFIG_DRIVER_TI_CPSW=y
48CONFIG_SYS_NS16550=y 48CONFIG_SYS_NS16550=y
49CONFIG_SPI=y 49CONFIG_SPI=y
50CONFIG_TI_QSPI=y 50CONFIG_TI_QSPI=y
@@ -56,7 +56,6 @@ CONFIG_USB_DWC3_GADGET=y
56CONFIG_USB_DWC3_OMAP=y 56CONFIG_USB_DWC3_OMAP=y
57CONFIG_USB_DWC3_PHY_OMAP=y 57CONFIG_USB_DWC3_PHY_OMAP=y
58CONFIG_OMAP_USB_PHY=y 58CONFIG_OMAP_USB_PHY=y
59CONFIG_USB_STORAGE=y
60CONFIG_USB_GADGET=y 59CONFIG_USB_GADGET=y
61CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 60CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
62CONFIG_USB_GADGET_VENDOR_NUM=0x0403 61CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index c38fdc1921..0d7bd72157 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -12,7 +12,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
12CONFIG_VERSION_VARIABLE=y 12CONFIG_VERSION_VARIABLE=y
13CONFIG_BOARD_EARLY_INIT_F=y 13CONFIG_BOARD_EARLY_INIT_F=y
14CONFIG_CMD_ASKENV=y 14CONFIG_CMD_ASKENV=y
15CONFIG_CMD_EEPROM=y
16CONFIG_CMD_DFU=y 15CONFIG_CMD_DFU=y
17# CONFIG_CMD_FLASH is not set 16# CONFIG_CMD_FLASH is not set
18CONFIG_CMD_GPIO=y 17CONFIG_CMD_GPIO=y
@@ -41,8 +40,8 @@ CONFIG_DM_MMC=y
41CONFIG_MMC_OMAP_HS=y 40CONFIG_MMC_OMAP_HS=y
42CONFIG_SPI_FLASH=y 41CONFIG_SPI_FLASH=y
43CONFIG_SPI_FLASH_MACRONIX=y 42CONFIG_SPI_FLASH_MACRONIX=y
44CONFIG_DRIVER_TI_CPSW=y
45CONFIG_MII=y 43CONFIG_MII=y
44CONFIG_DRIVER_TI_CPSW=y
46CONFIG_SYS_NS16550=y 45CONFIG_SYS_NS16550=y
47CONFIG_SPI=y 46CONFIG_SPI=y
48CONFIG_TI_QSPI=y 47CONFIG_TI_QSPI=y
@@ -54,7 +53,6 @@ CONFIG_USB_DWC3_GADGET=y
54CONFIG_USB_DWC3_OMAP=y 53CONFIG_USB_DWC3_OMAP=y
55CONFIG_USB_DWC3_PHY_OMAP=y 54CONFIG_USB_DWC3_PHY_OMAP=y
56CONFIG_OMAP_USB_PHY=y 55CONFIG_OMAP_USB_PHY=y
57CONFIG_USB_STORAGE=y
58CONFIG_USB_GADGET=y 56CONFIG_USB_GADGET=y
59CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 57CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
60CONFIG_USB_GADGET_VENDOR_NUM=0x0403 58CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index 2d54d1aaf0..7d56db43fd 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -38,9 +38,9 @@ CONFIG_MMC_OMAP_HS=y
38CONFIG_NAND=y 38CONFIG_NAND=y
39CONFIG_SPI_FLASH=y 39CONFIG_SPI_FLASH=y
40CONFIG_SPI_FLASH_MACRONIX=y 40CONFIG_SPI_FLASH_MACRONIX=y
41CONFIG_DRIVER_TI_CPSW=y
42CONFIG_PHY_GIGE=y 41CONFIG_PHY_GIGE=y
43CONFIG_MII=y 42CONFIG_MII=y
43CONFIG_DRIVER_TI_CPSW=y
44CONFIG_DM_SERIAL=y 44CONFIG_DM_SERIAL=y
45CONFIG_SPI=y 45CONFIG_SPI=y
46CONFIG_TI_QSPI=y 46CONFIG_TI_QSPI=y
@@ -54,7 +54,6 @@ CONFIG_USB_DWC3_GADGET=y
54CONFIG_USB_DWC3_OMAP=y 54CONFIG_USB_DWC3_OMAP=y
55CONFIG_USB_DWC3_PHY_OMAP=y 55CONFIG_USB_DWC3_PHY_OMAP=y
56CONFIG_OMAP_USB_PHY=y 56CONFIG_OMAP_USB_PHY=y
57CONFIG_USB_STORAGE=y
58CONFIG_USB_GADGET=y 57CONFIG_USB_GADGET=y
59CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 58CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
60CONFIG_USB_GADGET_VENDOR_NUM=0x0403 59CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 2713833544..5131f190a7 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -19,7 +19,6 @@ CONFIG_CMD_SPL=y
19CONFIG_CMD_SPL_NAND_OFS=0x00100000 19CONFIG_CMD_SPL_NAND_OFS=0x00100000
20CONFIG_CMD_SPL_WRITE_SIZE=0x40000 20CONFIG_CMD_SPL_WRITE_SIZE=0x40000
21CONFIG_CMD_ASKENV=y 21CONFIG_CMD_ASKENV=y
22CONFIG_CMD_EEPROM=y
23CONFIG_CMD_DFU=y 22CONFIG_CMD_DFU=y
24# CONFIG_CMD_FLASH is not set 23# CONFIG_CMD_FLASH is not set
25CONFIG_CMD_GPIO=y 24CONFIG_CMD_GPIO=y
@@ -51,9 +50,9 @@ CONFIG_MMC_OMAP_HS=y
51CONFIG_NAND=y 50CONFIG_NAND=y
52CONFIG_SPI_FLASH=y 51CONFIG_SPI_FLASH=y
53CONFIG_SPI_FLASH_MACRONIX=y 52CONFIG_SPI_FLASH_MACRONIX=y
54CONFIG_DRIVER_TI_CPSW=y
55CONFIG_PHY_GIGE=y 53CONFIG_PHY_GIGE=y
56CONFIG_MII=y 54CONFIG_MII=y
55CONFIG_DRIVER_TI_CPSW=y
57CONFIG_DM_SERIAL=y 56CONFIG_DM_SERIAL=y
58CONFIG_SPI=y 57CONFIG_SPI=y
59CONFIG_TI_QSPI=y 58CONFIG_TI_QSPI=y
@@ -67,7 +66,6 @@ CONFIG_USB_DWC3_GADGET=y
67CONFIG_USB_DWC3_OMAP=y 66CONFIG_USB_DWC3_OMAP=y
68CONFIG_USB_DWC3_PHY_OMAP=y 67CONFIG_USB_DWC3_PHY_OMAP=y
69CONFIG_OMAP_USB_PHY=y 68CONFIG_OMAP_USB_PHY=y
70CONFIG_USB_STORAGE=y
71CONFIG_USB_GADGET=y 69CONFIG_USB_GADGET=y
72CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 70CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
73CONFIG_USB_GADGET_VENDOR_NUM=0x0403 71CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index aaf8d10fec..99e4ccb592 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -25,7 +25,7 @@ CONFIG_SPL_NET_SUPPORT=y
25CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" 25CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
26CONFIG_SPL_USB_HOST_SUPPORT=y 26CONFIG_SPL_USB_HOST_SUPPORT=y
27CONFIG_SPL_USB_SUPPORT=y 27CONFIG_SPL_USB_SUPPORT=y
28CONFIG_SPL_USB_GADGET_SUPPORT=y 28CONFIG_SPL_USB_GADGET=y
29CONFIG_SPL_USB_ETHER=y 29CONFIG_SPL_USB_ETHER=y
30# CONFIG_CMD_FLASH is not set 30# CONFIG_CMD_FLASH is not set
31CONFIG_CMD_NAND=y 31CONFIG_CMD_NAND=y
@@ -48,9 +48,9 @@ CONFIG_MMC_OMAP_HS=y
48CONFIG_NAND=y 48CONFIG_NAND=y
49CONFIG_SPI_FLASH=y 49CONFIG_SPI_FLASH=y
50CONFIG_SPI_FLASH_MACRONIX=y 50CONFIG_SPI_FLASH_MACRONIX=y
51CONFIG_DRIVER_TI_CPSW=y
52CONFIG_PHY_GIGE=y 51CONFIG_PHY_GIGE=y
53CONFIG_MII=y 52CONFIG_MII=y
53CONFIG_DRIVER_TI_CPSW=y
54CONFIG_DM_SERIAL=y 54CONFIG_DM_SERIAL=y
55CONFIG_SPI=y 55CONFIG_SPI=y
56CONFIG_TI_QSPI=y 56CONFIG_TI_QSPI=y
@@ -64,7 +64,6 @@ CONFIG_USB_DWC3_GADGET=y
64CONFIG_USB_DWC3_OMAP=y 64CONFIG_USB_DWC3_OMAP=y
65CONFIG_USB_DWC3_PHY_OMAP=y 65CONFIG_USB_DWC3_PHY_OMAP=y
66CONFIG_OMAP_USB_PHY=y 66CONFIG_OMAP_USB_PHY=y
67CONFIG_USB_STORAGE=y
68CONFIG_USB_GADGET=y 67CONFIG_USB_GADGET=y
69CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 68CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
70CONFIG_USB_GADGET_VENDOR_NUM=0x0403 69CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index aa8283033e..91293daee7 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -61,8 +61,8 @@ CONFIG_SPI_FLASH_SPANSION=y
61CONFIG_PHY_MICREL=y 61CONFIG_PHY_MICREL=y
62CONFIG_PHY_MICREL_KSZ90X1=y 62CONFIG_PHY_MICREL_KSZ90X1=y
63CONFIG_DM_ETH=y 63CONFIG_DM_ETH=y
64CONFIG_DRIVER_TI_CPSW=y
65CONFIG_MII=y 64CONFIG_MII=y
65CONFIG_DRIVER_TI_CPSW=y
66CONFIG_PHY=y 66CONFIG_PHY=y
67CONFIG_PIPE3_PHY=y 67CONFIG_PIPE3_PHY=y
68CONFIG_OMAP_USB2_PHY=y 68CONFIG_OMAP_USB2_PHY=y
@@ -76,7 +76,6 @@ CONFIG_DM_SPI=y
76CONFIG_TI_QSPI=y 76CONFIG_TI_QSPI=y
77CONFIG_USB=y 77CONFIG_USB=y
78CONFIG_DM_USB=y 78CONFIG_DM_USB=y
79CONFIG_SPL_DM_USB=y
80CONFIG_DM_USB_GADGET=y 79CONFIG_DM_USB_GADGET=y
81CONFIG_SPL_DM_USB_GADGET=y 80CONFIG_SPL_DM_USB_GADGET=y
82CONFIG_USB_XHCI_HCD=y 81CONFIG_USB_XHCI_HCD=y
@@ -84,7 +83,6 @@ CONFIG_USB_XHCI_DWC3=y
84CONFIG_USB_DWC3=y 83CONFIG_USB_DWC3=y
85CONFIG_USB_DWC3_GADGET=y 84CONFIG_USB_DWC3_GADGET=y
86CONFIG_USB_DWC3_GENERIC=y 85CONFIG_USB_DWC3_GENERIC=y
87CONFIG_USB_STORAGE=y
88CONFIG_USB_GADGET=y 86CONFIG_USB_GADGET=y
89CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 87CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
90CONFIG_USB_GADGET_VENDOR_NUM=0x0451 88CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 09f3774b6d..6924b0bd06 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -64,8 +64,8 @@ CONFIG_SPI_FLASH_SPANSION=y
64CONFIG_PHY_MICREL=y 64CONFIG_PHY_MICREL=y
65CONFIG_PHY_MICREL_KSZ90X1=y 65CONFIG_PHY_MICREL_KSZ90X1=y
66CONFIG_DM_ETH=y 66CONFIG_DM_ETH=y
67CONFIG_DRIVER_TI_CPSW=y
68CONFIG_MII=y 67CONFIG_MII=y
68CONFIG_DRIVER_TI_CPSW=y
69CONFIG_PHY=y 69CONFIG_PHY=y
70CONFIG_PIPE3_PHY=y 70CONFIG_PIPE3_PHY=y
71CONFIG_OMAP_USB2_PHY=y 71CONFIG_OMAP_USB2_PHY=y
@@ -79,7 +79,6 @@ CONFIG_DM_SPI=y
79CONFIG_TI_QSPI=y 79CONFIG_TI_QSPI=y
80CONFIG_USB=y 80CONFIG_USB=y
81CONFIG_DM_USB=y 81CONFIG_DM_USB=y
82CONFIG_SPL_DM_USB=y
83CONFIG_DM_USB_GADGET=y 82CONFIG_DM_USB_GADGET=y
84CONFIG_SPL_DM_USB_GADGET=y 83CONFIG_SPL_DM_USB_GADGET=y
85CONFIG_USB_XHCI_HCD=y 84CONFIG_USB_XHCI_HCD=y
@@ -87,7 +86,6 @@ CONFIG_USB_XHCI_DWC3=y
87CONFIG_USB_DWC3=y 86CONFIG_USB_DWC3=y
88CONFIG_USB_DWC3_GADGET=y 87CONFIG_USB_DWC3_GADGET=y
89CONFIG_USB_DWC3_GENERIC=y 88CONFIG_USB_DWC3_GENERIC=y
90CONFIG_USB_STORAGE=y
91CONFIG_USB_GADGET=y 89CONFIG_USB_GADGET=y
92CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 90CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
93CONFIG_USB_GADGET_VENDOR_NUM=0x0451 91CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 83721b403b..e0d257564f 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -46,7 +46,6 @@ CONFIG_SYS_NS16550=y
46CONFIG_USB=y 46CONFIG_USB=y
47CONFIG_DM_USB=y 47CONFIG_DM_USB=y
48CONFIG_USB_EHCI_HCD=y 48CONFIG_USB_EHCI_HCD=y
49CONFIG_USB_STORAGE=y
50CONFIG_USB_GADGET=y 49CONFIG_USB_GADGET=y
51CONFIG_USB_GADGET_MANUFACTURER="Toradex" 50CONFIG_USB_GADGET_MANUFACTURER="Toradex"
52CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 51CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 133fc1a4db..e02d9bc7de 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -23,7 +23,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
23CONFIG_SPL_DMA_SUPPORT=y 23CONFIG_SPL_DMA_SUPPORT=y
24CONFIG_SPL_I2C_SUPPORT=y 24CONFIG_SPL_I2C_SUPPORT=y
25CONFIG_SPL_USB_HOST_SUPPORT=y 25CONFIG_SPL_USB_HOST_SUPPORT=y
26CONFIG_SPL_USB_GADGET_SUPPORT=y 26CONFIG_SPL_USB_GADGET=y
27CONFIG_SPL_USB_SDP_SUPPORT=y 27CONFIG_SPL_USB_SDP_SUPPORT=y
28CONFIG_HUSH_PARSER=y 28CONFIG_HUSH_PARSER=y
29CONFIG_SYS_PROMPT="Apalis iMX6 # " 29CONFIG_SYS_PROMPT="Apalis iMX6 # "
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 0e6547b72c..490b93f0de 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -38,7 +38,6 @@ CONFIG_SYS_NS16550=y
38CONFIG_USB=y 38CONFIG_USB=y
39CONFIG_DM_USB=y 39CONFIG_DM_USB=y
40CONFIG_USB_EHCI_HCD=y 40CONFIG_USB_EHCI_HCD=y
41CONFIG_USB_STORAGE=y
42CONFIG_USB_GADGET=y 41CONFIG_USB_GADGET=y
43CONFIG_USB_GADGET_MANUFACTURER="Toradex" 42CONFIG_USB_GADGET_MANUFACTURER="Toradex"
44CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 43CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 2b6af4b221..24422645cb 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -40,6 +40,5 @@ CONFIG_DM_USB=y
40CONFIG_USB_XHCI_HCD=y 40CONFIG_USB_XHCI_HCD=y
41CONFIG_USB_XHCI_DWC3=y 41CONFIG_USB_XHCI_DWC3=y
42CONFIG_USB_EHCI_HCD=y 42CONFIG_USB_EHCI_HCD=y
43CONFIG_USB_STORAGE=y
44CONFIG_USB_HOST_ETHER=y 43CONFIG_USB_HOST_ETHER=y
45CONFIG_USB_ETHER_ASIX88179=y 44CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig
index 9ca884e405..5b5af16df5 100644
--- a/configs/avnet_ultra96_rev1_defconfig
+++ b/configs/avnet_ultra96_rev1_defconfig
@@ -83,7 +83,6 @@ CONFIG_USB_DWC3_GADGET=y
83CONFIG_USB_DWC3_GENERIC=y 83CONFIG_USB_DWC3_GENERIC=y
84CONFIG_USB_ULPI_VIEWPORT=y 84CONFIG_USB_ULPI_VIEWPORT=y
85CONFIG_USB_ULPI=y 85CONFIG_USB_ULPI=y
86CONFIG_USB_STORAGE=y
87CONFIG_USB_GADGET=y 86CONFIG_USB_GADGET=y
88CONFIG_USB_GADGET_DOWNLOAD=y 87CONFIG_USB_GADGET_DOWNLOAD=y
89CONFIG_USB_ETHER=y 88CONFIG_USB_ETHER=y
diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580_ram_defconfig
index 4e10175a50..56e0a56028 100644
--- a/configs/bcm968580_ram_defconfig
+++ b/configs/bcm968580_ram_defconfig
@@ -23,7 +23,6 @@ CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref"
23# CONFIG_NET is not set 23# CONFIG_NET is not set
24CONFIG_BLK=y 24CONFIG_BLK=y
25CONFIG_CLK=y 25CONFIG_CLK=y
26CONFIG_FIRMWARE=y
27# CONFIG_MMC is not set 26# CONFIG_MMC is not set
28CONFIG_SPECIFY_CONSOLE_INDEX=y 27CONFIG_SPECIFY_CONSOLE_INDEX=y
29# CONFIG_SPL_SERIAL_PRESENT is not set 28# CONFIG_SPL_SERIAL_PRESENT is not set
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 28cb04c38b..77d1ad51d8 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -42,7 +42,6 @@ CONFIG_TEGRA20_SLINK=y
42CONFIG_USB=y 42CONFIG_USB=y
43CONFIG_DM_USB=y 43CONFIG_DM_USB=y
44CONFIG_USB_EHCI_HCD=y 44CONFIG_USB_EHCI_HCD=y
45CONFIG_USB_STORAGE=y
46CONFIG_USB_GADGET=y 45CONFIG_USB_GADGET=y
47CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 46CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
48CONFIG_USB_GADGET_VENDOR_NUM=0x0955 47CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 89c777872a..3a25639ab8 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -49,15 +49,14 @@ CONFIG_FASTBOOT_BUF_ADDR=0x82000000
49CONFIG_MMC_OMAP_HS=y 49CONFIG_MMC_OMAP_HS=y
50CONFIG_SPI_FLASH=y 50CONFIG_SPI_FLASH=y
51CONFIG_SPI_FLASH_WINBOND=y 51CONFIG_SPI_FLASH_WINBOND=y
52CONFIG_DRIVER_TI_CPSW=y
53CONFIG_MII=y 52CONFIG_MII=y
53CONFIG_DRIVER_TI_CPSW=y
54CONFIG_SPI=y 54CONFIG_SPI=y
55CONFIG_OMAP3_SPI=y 55CONFIG_OMAP3_SPI=y
56CONFIG_USB=y 56CONFIG_USB=y
57CONFIG_USB_MUSB_HOST=y 57CONFIG_USB_MUSB_HOST=y
58CONFIG_USB_MUSB_GADGET=y 58CONFIG_USB_MUSB_GADGET=y
59CONFIG_USB_MUSB_DSPS=y 59CONFIG_USB_MUSB_DSPS=y
60CONFIG_USB_STORAGE=y
61CONFIG_USB_GADGET=y 60CONFIG_USB_GADGET=y
62CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 61CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
63CONFIG_USB_GADGET_VENDOR_NUM=0x0451 62CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index e3dc88b005..fd29396100 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -49,15 +49,14 @@ CONFIG_FASTBOOT_BUF_ADDR=0x82000000
49CONFIG_MMC_OMAP_HS=y 49CONFIG_MMC_OMAP_HS=y
50CONFIG_SPI_FLASH=y 50CONFIG_SPI_FLASH=y
51CONFIG_SPI_FLASH_WINBOND=y 51CONFIG_SPI_FLASH_WINBOND=y
52CONFIG_DRIVER_TI_CPSW=y
53CONFIG_MII=y 52CONFIG_MII=y
53CONFIG_DRIVER_TI_CPSW=y
54CONFIG_SPI=y 54CONFIG_SPI=y
55CONFIG_OMAP3_SPI=y 55CONFIG_OMAP3_SPI=y
56CONFIG_USB=y 56CONFIG_USB=y
57CONFIG_USB_MUSB_HOST=y 57CONFIG_USB_MUSB_HOST=y
58CONFIG_USB_MUSB_GADGET=y 58CONFIG_USB_MUSB_GADGET=y
59CONFIG_USB_MUSB_DSPS=y 59CONFIG_USB_MUSB_DSPS=y
60CONFIG_USB_STORAGE=y
61CONFIG_USB_GADGET=y 60CONFIG_USB_GADGET=y
62CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 61CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
63CONFIG_USB_GADGET_VENDOR_NUM=0x0451 62CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 3296a74a0a..083b5f7e5f 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -76,9 +76,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
76CONFIG_MISC=y 76CONFIG_MISC=y
77CONFIG_DM_MMC=y 77CONFIG_DM_MMC=y
78CONFIG_MMC_OMAP_HS=y 78CONFIG_MMC_OMAP_HS=y
79CONFIG_PHY_NATSEMI=y
80CONFIG_DM_ETH=y 79CONFIG_DM_ETH=y
81CONFIG_DRIVER_TI_CPSW=y
82# CONFIG_NETDEVICES is not set 80# CONFIG_NETDEVICES is not set
83CONFIG_DM_SERIAL=y 81CONFIG_DM_SERIAL=y
84CONFIG_USB=y 82CONFIG_USB=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index e03eb37dfe..1cfd5fc709 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -80,9 +80,7 @@ CONFIG_MISC=y
80CONFIG_NAND=y 80CONFIG_NAND=y
81CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y 81CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
82CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 82CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
83CONFIG_PHY_NATSEMI=y
84CONFIG_DM_ETH=y 83CONFIG_DM_ETH=y
85CONFIG_DRIVER_TI_CPSW=y
86# CONFIG_NETDEVICES is not set 84# CONFIG_NETDEVICES is not set
87CONFIG_DM_SERIAL=y 85CONFIG_DM_SERIAL=y
88CONFIG_USB=y 86CONFIG_USB=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 2fa5dacd7a..37373967df 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -87,9 +87,7 @@ CONFIG_SPI_FLASH=y
87CONFIG_SPI_FLASH_STMICRO=y 87CONFIG_SPI_FLASH_STMICRO=y
88CONFIG_SPI_FLASH_WINBOND=y 88CONFIG_SPI_FLASH_WINBOND=y
89# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 89# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
90CONFIG_PHY_NATSEMI=y
91CONFIG_DM_ETH=y 90CONFIG_DM_ETH=y
92CONFIG_DRIVER_TI_CPSW=y
93# CONFIG_NETDEVICES is not set 91# CONFIG_NETDEVICES is not set
94CONFIG_DM_SERIAL=y 92CONFIG_DM_SERIAL=y
95CONFIG_SPI=y 93CONFIG_SPI=y
diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig
index 4b00a177f5..74a9121996 100644
--- a/configs/bubblegum_96_defconfig
+++ b/configs/bubblegum_96_defconfig
@@ -1,5 +1,4 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_ARM_SMCCC=y
3CONFIG_ARCH_OWL=y 2CONFIG_ARCH_OWL=y
4CONFIG_SYS_TEXT_BASE=0x11000000 3CONFIG_SYS_TEXT_BASE=0x11000000
5CONFIG_TARGET_BUBBLEGUM_96=y 4CONFIG_TARGET_BUBBLEGUM_96=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index c046ef5d8b..be55728e6f 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -36,6 +36,5 @@ CONFIG_TEGRA20_SLINK=y
36CONFIG_USB=y 36CONFIG_USB=y
37CONFIG_DM_USB=y 37CONFIG_DM_USB=y
38CONFIG_USB_EHCI_HCD=y 38CONFIG_USB_EHCI_HCD=y
39CONFIG_USB_STORAGE=y
40CONFIG_USB_HOST_ETHER=y 39CONFIG_USB_HOST_ETHER=y
41CONFIG_USB_ETHER_ASIX=y 40CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index c782fef89e..74b17ef938 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -45,7 +45,6 @@ CONFIG_TEGRA114_SPI=y
45CONFIG_USB=y 45CONFIG_USB=y
46CONFIG_DM_USB=y 46CONFIG_DM_USB=y
47CONFIG_USB_EHCI_HCD=y 47CONFIG_USB_EHCI_HCD=y
48CONFIG_USB_STORAGE=y
49CONFIG_USB_GADGET=y 48CONFIG_USB_GADGET=y
50CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 49CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
51CONFIG_USB_GADGET_VENDOR_NUM=0x0955 50CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 3de0223469..02eb324811 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -48,8 +48,7 @@ CONFIG_OMAP_TIMER=y
48CONFIG_USB=y 48CONFIG_USB=y
49CONFIG_DM_USB=y 49CONFIG_DM_USB=y
50CONFIG_USB_MUSB_HOST=y 50CONFIG_USB_MUSB_HOST=y
51CONFIG_USB_MUSB_DSPS=y
52CONFIG_USB_MUSB_TI=y 51CONFIG_USB_MUSB_TI=y
53CONFIG_USB_STORAGE=y 52CONFIG_USB_MUSB_DSPS=y
54CONFIG_FAT_WRITE=y 53CONFIG_FAT_WRITE=y
55CONFIG_LZO=y 54CONFIG_LZO=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 79ab6acaec..1c20dcd882 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -79,7 +79,6 @@ CONFIG_ROCKCHIP_SPI=y
79CONFIG_SYSRESET=y 79CONFIG_SYSRESET=y
80CONFIG_USB=y 80CONFIG_USB=y
81CONFIG_ROCKCHIP_USB2_PHY=y 81CONFIG_ROCKCHIP_USB2_PHY=y
82CONFIG_USB_STORAGE=y
83CONFIG_USB_GADGET=y 82CONFIG_USB_GADGET=y
84CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 83CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
85CONFIG_USB_GADGET_VENDOR_NUM=0x2207 84CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index d892d65bf0..94a1af01be 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -80,7 +80,6 @@ CONFIG_ROCKCHIP_SPI=y
80CONFIG_SYSRESET=y 80CONFIG_SYSRESET=y
81CONFIG_USB=y 81CONFIG_USB=y
82CONFIG_ROCKCHIP_USB2_PHY=y 82CONFIG_ROCKCHIP_USB2_PHY=y
83CONFIG_USB_STORAGE=y
84CONFIG_USB_GADGET=y 83CONFIG_USB_GADGET=y
85CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 84CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
86CONFIG_USB_GADGET_VENDOR_NUM=0x2207 85CONFIG_USB_GADGET_VENDOR_NUM=0x2207
@@ -88,10 +87,12 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
88CONFIG_USB_GADGET_DWC2_OTG=y 87CONFIG_USB_GADGET_DWC2_OTG=y
89CONFIG_USB_FUNCTION_MASS_STORAGE=y 88CONFIG_USB_FUNCTION_MASS_STORAGE=y
90CONFIG_DM_VIDEO=y 89CONFIG_DM_VIDEO=y
90CONFIG_CONSOLE_TRUETYPE=y
91CONFIG_DISPLAY=y 91CONFIG_DISPLAY=y
92CONFIG_VIDEO_ROCKCHIP=y 92CONFIG_VIDEO_ROCKCHIP=y
93CONFIG_DISPLAY_ROCKCHIP_EDP=y 93CONFIG_DISPLAY_ROCKCHIP_EDP=y
94CONFIG_DISPLAY_ROCKCHIP_HDMI=y 94CONFIG_DISPLAY_ROCKCHIP_HDMI=y
95# CONFIG_USE_PRIVATE_LIBGCC is not set
95CONFIG_USE_TINY_PRINTF=y 96CONFIG_USE_TINY_PRINTF=y
96CONFIG_CMD_DHRYSTONE=y 97CONFIG_CMD_DHRYSTONE=y
97CONFIG_ERRNO_STR=y 98CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index b042874073..cb7f52f040 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -79,7 +79,6 @@ CONFIG_ROCKCHIP_SPI=y
79CONFIG_SYSRESET=y 79CONFIG_SYSRESET=y
80CONFIG_USB=y 80CONFIG_USB=y
81CONFIG_ROCKCHIP_USB2_PHY=y 81CONFIG_ROCKCHIP_USB2_PHY=y
82CONFIG_USB_STORAGE=y
83CONFIG_USB_GADGET=y 82CONFIG_USB_GADGET=y
84CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 83CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
85CONFIG_USB_GADGET_VENDOR_NUM=0x2207 84CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
new file mode 100644
index 0000000000..c1b1c3f7e9
--- /dev/null
+++ b/configs/ci20_mmc_defconfig
@@ -0,0 +1,48 @@
1CONFIG_MIPS=y
2CONFIG_SPL_LDSCRIPT="arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds"
3CONFIG_SYS_TEXT_BASE=0x80010000
4CONFIG_SPL_GPIO_SUPPORT=y
5CONFIG_SPL_LIBGENERIC_SUPPORT=y
6CONFIG_SYS_MALLOC_F_LEN=0x2000
7CONFIG_SPL_MMC_SUPPORT=y
8CONFIG_SPL=y
9CONFIG_ARCH_JZ47XX=y
10CONFIG_NR_DRAM_BANKS=1
11CONFIG_FIT=y
12CONFIG_USE_BOOTARGS=y
13CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
14CONFIG_USE_BOOTCOMMAND=y
15CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x88000000 /boot/uImage; bootm 0x88000000"
16CONFIG_MISC_INIT_R=y
17CONFIG_DISPLAY_CPUINFO=y
18CONFIG_BOARD_EARLY_INIT_F=y
19# CONFIG_SPL_BANNER_PRINT is not set
20# CONFIG_TPL_BANNER_PRINT is not set
21CONFIG_HUSH_PARSER=y
22CONFIG_CMD_DM=y
23# CONFIG_CMD_FLASH is not set
24CONFIG_CMD_MMC=y
25CONFIG_CMD_DHCP=y
26CONFIG_CMD_EXT4=y
27CONFIG_CMD_FAT=y
28# CONFIG_SPL_DOS_PARTITION is not set
29CONFIG_DEFAULT_DEVICE_TREE="ci20"
30CONFIG_ENV_IS_IN_MMC=y
31# CONFIG_DM_WARN is not set
32# CONFIG_DM_DEVICE_REMOVE is not set
33CONFIG_JZ4780_EFUSE=y
34CONFIG_MMC=y
35CONFIG_MMC_BROKEN_CD=y
36CONFIG_DM_MMC=y
37# CONFIG_MMC_HW_PARTITIONING is not set
38CONFIG_MMC_IO_VOLTAGE=y
39CONFIG_MMC_UHS_SUPPORT=y
40CONFIG_MMC_HS400_SUPPORT=y
41# CONFIG_MMC_VERBOSE is not set
42CONFIG_SPL_MMC_TINY=y
43CONFIG_JZ47XX_MMC=y
44CONFIG_DM_SERIAL=y
45CONFIG_SYS_NS16550=y
46CONFIG_USE_TINY_PRINTF=y
47CONFIG_SPL_TINY_MEMSET=y
48CONFIG_LZO=y
diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig
index c5337f909e..fec5e60832 100644
--- a/configs/cl-som-am57x_defconfig
+++ b/configs/cl-som-am57x_defconfig
@@ -46,8 +46,8 @@ CONFIG_SPI_FLASH_SPANSION=y
46CONFIG_SPI_FLASH_STMICRO=y 46CONFIG_SPI_FLASH_STMICRO=y
47CONFIG_SPI_FLASH_SST=y 47CONFIG_SPI_FLASH_SST=y
48CONFIG_SPI_FLASH_WINBOND=y 48CONFIG_SPI_FLASH_WINBOND=y
49CONFIG_DRIVER_TI_CPSW=y
50CONFIG_MII=y 49CONFIG_MII=y
50CONFIG_DRIVER_TI_CPSW=y
51CONFIG_CONS_INDEX=3 51CONFIG_CONS_INDEX=3
52CONFIG_SYS_NS16550=y 52CONFIG_SYS_NS16550=y
53CONFIG_SPI=y 53CONFIG_SPI=y
@@ -56,7 +56,6 @@ CONFIG_USB=y
56CONFIG_USB_XHCI_HCD=y 56CONFIG_USB_XHCI_HCD=y
57CONFIG_USB_XHCI_DWC3=y 57CONFIG_USB_XHCI_DWC3=y
58CONFIG_OMAP_USB_PHY=y 58CONFIG_OMAP_USB_PHY=y
59CONFIG_USB_STORAGE=y
60CONFIG_USB_HOST_ETHER=y 59CONFIG_USB_HOST_ETHER=y
61CONFIG_USB_ETHER_ASIX=y 60CONFIG_USB_ETHER_ASIX=y
62CONFIG_USB_ETHER_MCS7830=y 61CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 0eed5264f2..ea7ad5c596 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -43,8 +43,11 @@ CONFIG_CMD_EXT4=y
43CONFIG_CMD_EXT4_WRITE=y 43CONFIG_CMD_EXT4_WRITE=y
44CONFIG_CMD_FAT=y 44CONFIG_CMD_FAT=y
45CONFIG_CMD_FS_GENERIC=y 45CONFIG_CMD_FS_GENERIC=y
46CONFIG_OF_CONTROL=y
47CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
46# CONFIG_ENV_IS_IN_MMC is not set 48# CONFIG_ENV_IS_IN_MMC is not set
47CONFIG_ENV_IS_IN_SPI_FLASH=y 49CONFIG_ENV_IS_IN_SPI_FLASH=y
50CONFIG_DM_MMC=y
48CONFIG_FSL_ESDHC=y 51CONFIG_FSL_ESDHC=y
49CONFIG_SPI_FLASH=y 52CONFIG_SPI_FLASH=y
50CONFIG_SPI_FLASH_ATMEL=y 53CONFIG_SPI_FLASH_ATMEL=y
@@ -56,12 +59,13 @@ CONFIG_SPI_FLASH_STMICRO=y
56CONFIG_SPI_FLASH_SST=y 59CONFIG_SPI_FLASH_SST=y
57CONFIG_SPI_FLASH_WINBOND=y 60CONFIG_SPI_FLASH_WINBOND=y
58CONFIG_MII=y 61CONFIG_MII=y
62CONFIG_DM_REGULATOR=y
59CONFIG_SPI=y 63CONFIG_SPI=y
60CONFIG_MXC_SPI=y 64CONFIG_MXC_SPI=y
61CONFIG_USB=y 65CONFIG_USB=y
66CONFIG_DM_USB=y
62CONFIG_USB_EHCI_HCD=y 67CONFIG_USB_EHCI_HCD=y
63CONFIG_MXC_USB_OTG_HACTIVE=y 68CONFIG_MXC_USB_OTG_HACTIVE=y
64CONFIG_USB_STORAGE=y 69CONFIG_USB_STORAGE=y
65CONFIG_USB_GADGET=y 70CONFIG_USB_GADGET=y
66CONFIG_CI_UDC=y 71CONFIG_CI_UDC=y
67CONFIG_OF_LIBFDT=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 2e59686291..e1c5a1fa13 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -63,4 +63,3 @@ CONFIG_KIRKWOOD_SPI=y
63CONFIG_USB=y 63CONFIG_USB=y
64CONFIG_DM_USB=y 64CONFIG_DM_USB=y
65CONFIG_USB_XHCI_HCD=y 65CONFIG_USB_XHCI_HCD=y
66CONFIG_USB_STORAGE=y
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index 8f766c176b..42cdbfab61 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
5CONFIG_TARGET_MVEBU_ARMADA_8K=y 5CONFIG_TARGET_MVEBU_ARMADA_8K=y
6CONFIG_DEBUG_UART_BASE=0xf0512000 6CONFIG_DEBUG_UART_BASE=0xf0512000
7CONFIG_DEBUG_UART_CLOCK=200000000 7CONFIG_DEBUG_UART_CLOCK=200000000
8CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k"
9CONFIG_SMBIOS_PRODUCT_NAME="" 8CONFIG_SMBIOS_PRODUCT_NAME=""
10CONFIG_DEBUG_UART=y 9CONFIG_DEBUG_UART=y
11CONFIG_AHCI=y 10CONFIG_AHCI=y
@@ -34,6 +33,7 @@ CONFIG_CMD_MVEBU_BUBT=y
34CONFIG_CMD_REGULATOR=y 33CONFIG_CMD_REGULATOR=y
35CONFIG_CMD_EXT4_WRITE=y 34CONFIG_CMD_EXT4_WRITE=y
36CONFIG_MAC_PARTITION=y 35CONFIG_MAC_PARTITION=y
36CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k"
37CONFIG_ENV_IS_IN_SPI_FLASH=y 37CONFIG_ENV_IS_IN_SPI_FLASH=y
38CONFIG_AHCI_MVEBU=y 38CONFIG_AHCI_MVEBU=y
39CONFIG_DM_GPIO=y 39CONFIG_DM_GPIO=y
@@ -66,7 +66,6 @@ CONFIG_USB=y
66CONFIG_DM_USB=y 66CONFIG_DM_USB=y
67CONFIG_USB_XHCI_HCD=y 67CONFIG_USB_XHCI_HCD=y
68CONFIG_USB_EHCI_HCD=y 68CONFIG_USB_EHCI_HCD=y
69CONFIG_USB_STORAGE=y
70CONFIG_USB_HOST_ETHER=y 69CONFIG_USB_HOST_ETHER=y
71CONFIG_USB_ETHER_ASIX=y 70CONFIG_USB_ETHER_ASIX=y
72CONFIG_USB_ETHER_MCS7830=y 71CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 4ec74b27cd..d6726f6d97 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -72,7 +72,6 @@ CONFIG_SPI=y
72CONFIG_MXC_SPI=y 72CONFIG_MXC_SPI=y
73CONFIG_USB=y 73CONFIG_USB=y
74CONFIG_DM_USB=y 74CONFIG_DM_USB=y
75CONFIG_USB_STORAGE=y
76CONFIG_USB_KEYBOARD=y 75CONFIG_USB_KEYBOARD=y
77CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y 76CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
78CONFIG_VIDEO=y 77CONFIG_VIDEO=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 134b093e54..b948b89daa 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -45,7 +45,7 @@ CONFIG_LED_STATUS_BOOT_ENABLE=y
45CONFIG_LED_STATUS_BOOT=0 45CONFIG_LED_STATUS_BOOT=0
46CONFIG_MMC_OMAP_HS=y 46CONFIG_MMC_OMAP_HS=y
47CONFIG_NAND=y 47CONFIG_NAND=y
48CONFIG_DRIVER_TI_CPSW=y
49CONFIG_MII=y 48CONFIG_MII=y
49CONFIG_DRIVER_TI_CPSW=y
50CONFIG_FAT_WRITE=y 50CONFIG_FAT_WRITE=y
51CONFIG_OF_LIBFDT=y 51CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 0901fea638..c204a29081 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -54,6 +54,7 @@ CONFIG_USB=y
54CONFIG_USB_MUSB_HOST=y 54CONFIG_USB_MUSB_HOST=y
55CONFIG_USB_MUSB_AM35X=y 55CONFIG_USB_MUSB_AM35X=y
56CONFIG_USB_STORAGE=y 56CONFIG_USB_STORAGE=y
57CONFIG_USB_GADGET=y
57CONFIG_VIDEO_OMAP3=y 58CONFIG_VIDEO_OMAP3=y
58CONFIG_LCD=y 59CONFIG_LCD=y
59CONFIG_OF_LIBFDT=y 60CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index f1fe2d058d..a27c502489 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -56,6 +56,7 @@ CONFIG_USB_MUSB_UDC=y
56CONFIG_USB_OMAP3=y 56CONFIG_USB_OMAP3=y
57CONFIG_TWL4030_USB=y 57CONFIG_TWL4030_USB=y
58CONFIG_USB_STORAGE=y 58CONFIG_USB_STORAGE=y
59CONFIG_USB_GADGET=y
59CONFIG_VIDEO_OMAP3=y 60CONFIG_VIDEO_OMAP3=y
60CONFIG_LCD=y 61CONFIG_LCD=y
61CONFIG_OF_LIBFDT=y 62CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index eb4a8f5a33..a2530b704d 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -58,8 +58,8 @@ CONFIG_SPI_FLASH_SPANSION=y
58CONFIG_SPI_FLASH_STMICRO=y 58CONFIG_SPI_FLASH_STMICRO=y
59CONFIG_SPI_FLASH_SST=y 59CONFIG_SPI_FLASH_SST=y
60CONFIG_SPI_FLASH_WINBOND=y 60CONFIG_SPI_FLASH_WINBOND=y
61CONFIG_DRIVER_TI_CPSW=y
62CONFIG_MII=y 61CONFIG_MII=y
62CONFIG_DRIVER_TI_CPSW=y
63CONFIG_DM_SERIAL=y 63CONFIG_DM_SERIAL=y
64CONFIG_SPI=y 64CONFIG_SPI=y
65CONFIG_OMAP3_SPI=y 65CONFIG_OMAP3_SPI=y
@@ -67,6 +67,5 @@ CONFIG_USB=y
67CONFIG_USB_XHCI_HCD=y 67CONFIG_USB_XHCI_HCD=y
68CONFIG_USB_XHCI_DWC3=y 68CONFIG_USB_XHCI_DWC3=y
69CONFIG_OMAP_USB_PHY=y 69CONFIG_OMAP_USB_PHY=y
70CONFIG_USB_STORAGE=y
71CONFIG_FAT_WRITE=y 70CONFIG_FAT_WRITE=y
72CONFIG_OF_LIBFDT=y 71CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index 955a6a57a9..05ac37cc25 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -39,7 +39,6 @@ CONFIG_SPI=y
39CONFIG_OMAP3_SPI=y 39CONFIG_OMAP3_SPI=y
40CONFIG_USB=y 40CONFIG_USB=y
41CONFIG_USB_EHCI_HCD=y 41CONFIG_USB_EHCI_HCD=y
42CONFIG_USB_STORAGE=y
43CONFIG_USB_HOST_ETHER=y 42CONFIG_USB_HOST_ETHER=y
44CONFIG_USB_ETHER_ASIX=y 43CONFIG_USB_ETHER_ASIX=y
45CONFIG_USB_ETHER_MCS7830=y 44CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index c26b3b9eb4..90eb309379 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -66,7 +66,6 @@ CONFIG_DM_REGULATOR=y
66CONFIG_DM_SERIAL=y 66CONFIG_DM_SERIAL=y
67CONFIG_MXC_UART=y 67CONFIG_MXC_UART=y
68CONFIG_USB=y 68CONFIG_USB=y
69CONFIG_USB_STORAGE=y
70CONFIG_USB_GADGET=y 69CONFIG_USB_GADGET=y
71CONFIG_USB_GADGET_MANUFACTURER="Toradex" 70CONFIG_USB_GADGET_MANUFACTURER="Toradex"
72CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 71CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index d86c0872b4..68f0746657 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -23,7 +23,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
23CONFIG_SPL_DMA_SUPPORT=y 23CONFIG_SPL_DMA_SUPPORT=y
24CONFIG_SPL_I2C_SUPPORT=y 24CONFIG_SPL_I2C_SUPPORT=y
25CONFIG_SPL_USB_HOST_SUPPORT=y 25CONFIG_SPL_USB_HOST_SUPPORT=y
26CONFIG_SPL_USB_GADGET_SUPPORT=y 26CONFIG_SPL_USB_GADGET=y
27CONFIG_SPL_USB_SDP_SUPPORT=y 27CONFIG_SPL_USB_SDP_SUPPORT=y
28CONFIG_HUSH_PARSER=y 28CONFIG_HUSH_PARSER=y
29CONFIG_SYS_PROMPT="Colibri iMX6 # " 29CONFIG_SYS_PROMPT="Colibri iMX6 # "
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 43528ef383..b1cfd65572 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -49,7 +49,6 @@ CONFIG_DM_USB=y
49CONFIG_USB_EHCI_HCD=y 49CONFIG_USB_EHCI_HCD=y
50CONFIG_USB_ULPI_VIEWPORT=y 50CONFIG_USB_ULPI_VIEWPORT=y
51CONFIG_USB_ULPI=y 51CONFIG_USB_ULPI=y
52CONFIG_USB_STORAGE=y
53CONFIG_USB_GADGET=y 52CONFIG_USB_GADGET=y
54CONFIG_USB_GADGET_MANUFACTURER="Toradex" 53CONFIG_USB_GADGET_MANUFACTURER="Toradex"
55CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 54CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index c8b82a9b58..fcbb30d82c 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -32,7 +32,6 @@ CONFIG_SYS_NS16550=y
32CONFIG_USB=y 32CONFIG_USB=y
33CONFIG_DM_USB=y 33CONFIG_DM_USB=y
34CONFIG_USB_EHCI_HCD=y 34CONFIG_USB_EHCI_HCD=y
35CONFIG_USB_STORAGE=y
36CONFIG_USB_GADGET=y 35CONFIG_USB_GADGET=y
37CONFIG_USB_GADGET_MANUFACTURER="Toradex" 36CONFIG_USB_GADGET_MANUFACTURER="Toradex"
38CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 37CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index fb0578868d..4192501257 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -23,11 +23,14 @@ CONFIG_CMD_MEMTEST=y
23CONFIG_CMD_DFU=y 23CONFIG_CMD_DFU=y
24CONFIG_CMD_FUSE=y 24CONFIG_CMD_FUSE=y
25CONFIG_CMD_GPIO=y 25CONFIG_CMD_GPIO=y
26# CONFIG_CMD_LOADB is not set
27# CONFIG_CMD_LOADS is not set
26CONFIG_CMD_MMC=y 28CONFIG_CMD_MMC=y
27CONFIG_CMD_USB=y 29CONFIG_CMD_USB=y
28CONFIG_CMD_USB_MASS_STORAGE=y 30CONFIG_CMD_USB_MASS_STORAGE=y
29# CONFIG_CMD_SETEXPR is not set 31# CONFIG_CMD_SETEXPR is not set
30CONFIG_CMD_DHCP=y 32CONFIG_CMD_DHCP=y
33# CONFIG_CMD_NFS is not set
31CONFIG_CMD_MII=y 34CONFIG_CMD_MII=y
32CONFIG_CMD_PING=y 35CONFIG_CMD_PING=y
33CONFIG_CMD_BMP=y 36CONFIG_CMD_BMP=y
diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig
index d9ef52e68d..1b8e4e43c4 100644
--- a/configs/comtrend_ar5315u_ram_defconfig
+++ b/configs/comtrend_ar5315u_ram_defconfig
@@ -28,11 +28,14 @@ CONFIG_CMD_MEMINFO=y
28CONFIG_CMD_SF=y 28CONFIG_CMD_SF=y
29CONFIG_CMD_SPI=y 29CONFIG_CMD_SPI=y
30CONFIG_CMD_USB=y 30CONFIG_CMD_USB=y
31CONFIG_CMD_MII=y
32CONFIG_CMD_PING=y
31# CONFIG_CMD_MISC is not set 33# CONFIG_CMD_MISC is not set
32CONFIG_OF_EMBED=y 34CONFIG_OF_EMBED=y
33CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u" 35CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u"
34# CONFIG_NET is not set 36CONFIG_NET_RANDOM_ETHADDR=y
35# CONFIG_DM_DEVICE_REMOVE is not set 37# CONFIG_DM_DEVICE_REMOVE is not set
38CONFIG_BCM6348_IUDMA=y
36CONFIG_DM_GPIO=y 39CONFIG_DM_GPIO=y
37CONFIG_LED=y 40CONFIG_LED=y
38CONFIG_LED_BCM6328=y 41CONFIG_LED_BCM6328=y
@@ -41,6 +44,8 @@ CONFIG_DM_SPI_FLASH=y
41CONFIG_SPI_FLASH=y 44CONFIG_SPI_FLASH=y
42CONFIG_SPI_FLASH_WINBOND=y 45CONFIG_SPI_FLASH_WINBOND=y
43CONFIG_SPI_FLASH_MTD=y 46CONFIG_SPI_FLASH_MTD=y
47CONFIG_DM_ETH=y
48CONFIG_BCM6368_ETH=y
44CONFIG_PHY=y 49CONFIG_PHY=y
45CONFIG_BCM6318_USBH_PHY=y 50CONFIG_BCM6318_USBH_PHY=y
46CONFIG_BCM6328_POWER_DOMAIN=y 51CONFIG_BCM6328_POWER_DOMAIN=y
diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig
index f129870ca0..5ba401a441 100644
--- a/configs/comtrend_ar5387un_ram_defconfig
+++ b/configs/comtrend_ar5387un_ram_defconfig
@@ -28,11 +28,14 @@ CONFIG_CMD_MEMINFO=y
28CONFIG_CMD_SF=y 28CONFIG_CMD_SF=y
29CONFIG_CMD_SPI=y 29CONFIG_CMD_SPI=y
30CONFIG_CMD_USB=y 30CONFIG_CMD_USB=y
31CONFIG_CMD_MII=y
32CONFIG_CMD_PING=y
31# CONFIG_CMD_MISC is not set 33# CONFIG_CMD_MISC is not set
32CONFIG_OF_EMBED=y 34CONFIG_OF_EMBED=y
33CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" 35CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
34# CONFIG_NET is not set 36CONFIG_NET_RANDOM_ETHADDR=y
35# CONFIG_DM_DEVICE_REMOVE is not set 37# CONFIG_DM_DEVICE_REMOVE is not set
38CONFIG_BCM6348_IUDMA=y
36CONFIG_DM_GPIO=y 39CONFIG_DM_GPIO=y
37CONFIG_LED=y 40CONFIG_LED=y
38CONFIG_LED_BCM6328=y 41CONFIG_LED_BCM6328=y
@@ -41,6 +44,8 @@ CONFIG_DM_SPI_FLASH=y
41CONFIG_SPI_FLASH=y 44CONFIG_SPI_FLASH=y
42CONFIG_SPI_FLASH_MACRONIX=y 45CONFIG_SPI_FLASH_MACRONIX=y
43CONFIG_SPI_FLASH_MTD=y 46CONFIG_SPI_FLASH_MTD=y
47CONFIG_DM_ETH=y
48CONFIG_BCM6368_ETH=y
44CONFIG_PHY=y 49CONFIG_PHY=y
45CONFIG_BCM6368_USBH_PHY=y 50CONFIG_BCM6368_USBH_PHY=y
46CONFIG_POWER_DOMAIN=y 51CONFIG_POWER_DOMAIN=y
diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig
index 82f2070713..6297e78fd9 100644
--- a/configs/comtrend_ct5361_ram_defconfig
+++ b/configs/comtrend_ct5361_ram_defconfig
@@ -25,11 +25,14 @@ CONFIG_CMD_LICENSE=y
25CONFIG_CMD_MEMINFO=y 25CONFIG_CMD_MEMINFO=y
26# CONFIG_CMD_LOADS is not set 26# CONFIG_CMD_LOADS is not set
27CONFIG_CMD_USB=y 27CONFIG_CMD_USB=y
28CONFIG_CMD_MII=y
29CONFIG_CMD_PING=y
28# CONFIG_CMD_MISC is not set 30# CONFIG_CMD_MISC is not set
29CONFIG_OF_EMBED=y 31CONFIG_OF_EMBED=y
30CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361" 32CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
31# CONFIG_NET is not set 33CONFIG_NET_RANDOM_ETHADDR=y
32# CONFIG_DM_DEVICE_REMOVE is not set 34# CONFIG_DM_DEVICE_REMOVE is not set
35CONFIG_BCM6348_IUDMA=y
33CONFIG_DM_GPIO=y 36CONFIG_DM_GPIO=y
34CONFIG_BCM6345_GPIO=y 37CONFIG_BCM6345_GPIO=y
35CONFIG_LED=y 38CONFIG_LED=y
@@ -40,6 +43,9 @@ CONFIG_FLASH_CFI_DRIVER=y
40CONFIG_CFI_FLASH=y 43CONFIG_CFI_FLASH=y
41CONFIG_SYS_FLASH_PROTECTION=y 44CONFIG_SYS_FLASH_PROTECTION=y
42CONFIG_SYS_FLASH_CFI=y 45CONFIG_SYS_FLASH_CFI=y
46CONFIG_PHY_FIXED=y
47CONFIG_DM_ETH=y
48CONFIG_BCM6348_ETH=y
43CONFIG_PHY=y 49CONFIG_PHY=y
44CONFIG_BCM6348_USBH_PHY=y 50CONFIG_BCM6348_USBH_PHY=y
45CONFIG_DM_RESET=y 51CONFIG_DM_RESET=y
diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig
index 1689eecec1..47f53998e1 100644
--- a/configs/comtrend_vr3032u_ram_defconfig
+++ b/configs/comtrend_vr3032u_ram_defconfig
@@ -26,15 +26,20 @@ CONFIG_CMD_MEMINFO=y
26# CONFIG_CMD_FLASH is not set 26# CONFIG_CMD_FLASH is not set
27# CONFIG_CMD_LOADS is not set 27# CONFIG_CMD_LOADS is not set
28CONFIG_CMD_USB=y 28CONFIG_CMD_USB=y
29CONFIG_CMD_MII=y
30CONFIG_CMD_PING=y
29# CONFIG_CMD_MISC is not set 31# CONFIG_CMD_MISC is not set
30CONFIG_OF_EMBED=y 32CONFIG_OF_EMBED=y
31CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" 33CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
32# CONFIG_NET is not set 34CONFIG_NET_RANDOM_ETHADDR=y
33# CONFIG_DM_DEVICE_REMOVE is not set 35# CONFIG_DM_DEVICE_REMOVE is not set
36CONFIG_BCM6348_IUDMA=y
34CONFIG_DM_GPIO=y 37CONFIG_DM_GPIO=y
35CONFIG_LED=y 38CONFIG_LED=y
36CONFIG_LED_BCM6328=y 39CONFIG_LED_BCM6328=y
37CONFIG_LED_BLINK=y 40CONFIG_LED_BLINK=y
41CONFIG_DM_ETH=y
42CONFIG_BCM6368_ETH=y
38CONFIG_PHY=y 43CONFIG_PHY=y
39CONFIG_BCM6368_USBH_PHY=y 44CONFIG_BCM6368_USBH_PHY=y
40CONFIG_POWER_DOMAIN=y 45CONFIG_POWER_DOMAIN=y
diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig
index 987e4c3fbc..fd5107bb7d 100644
--- a/configs/comtrend_wap5813n_ram_defconfig
+++ b/configs/comtrend_wap5813n_ram_defconfig
@@ -25,11 +25,14 @@ CONFIG_CMD_LICENSE=y
25CONFIG_CMD_MEMINFO=y 25CONFIG_CMD_MEMINFO=y
26# CONFIG_CMD_LOADS is not set 26# CONFIG_CMD_LOADS is not set
27CONFIG_CMD_USB=y 27CONFIG_CMD_USB=y
28CONFIG_CMD_MII=y
29CONFIG_CMD_PING=y
28# CONFIG_CMD_MISC is not set 30# CONFIG_CMD_MISC is not set
29CONFIG_OF_EMBED=y 31CONFIG_OF_EMBED=y
30CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n" 32CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n"
31# CONFIG_NET is not set 33CONFIG_NET_RANDOM_ETHADDR=y
32# CONFIG_DM_DEVICE_REMOVE is not set 34# CONFIG_DM_DEVICE_REMOVE is not set
35CONFIG_BCM6348_IUDMA=y
33CONFIG_DM_GPIO=y 36CONFIG_DM_GPIO=y
34CONFIG_BCM6345_GPIO=y 37CONFIG_BCM6345_GPIO=y
35CONFIG_LED=y 38CONFIG_LED=y
@@ -40,6 +43,9 @@ CONFIG_FLASH_CFI_DRIVER=y
40CONFIG_CFI_FLASH=y 43CONFIG_CFI_FLASH=y
41CONFIG_SYS_FLASH_PROTECTION=y 44CONFIG_SYS_FLASH_PROTECTION=y
42CONFIG_SYS_FLASH_CFI=y 45CONFIG_SYS_FLASH_CFI=y
46CONFIG_DM_ETH=y
47CONFIG_PHY_GIGE=y
48CONFIG_BCM6368_ETH=y
43CONFIG_PHY=y 49CONFIG_PHY=y
44CONFIG_BCM6368_USBH_PHY=y 50CONFIG_BCM6368_USBH_PHY=y
45CONFIG_DM_RESET=y 51CONFIG_DM_RESET=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 1bb7b9a03e..5100ee7b0e 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_SPI_LOAD=y
23CONFIG_HUSH_PARSER=y 23CONFIG_HUSH_PARSER=y
24CONFIG_SYS_PROMPT="U-Boot > " 24CONFIG_SYS_PROMPT="U-Boot > "
25CONFIG_CRC32_VERIFY=y 25CONFIG_CRC32_VERIFY=y
26# CONFIG_CMD_EEPROM is not set
27CONFIG_CMD_DM=y 26CONFIG_CMD_DM=y
28# CONFIG_CMD_FLASH is not set 27# CONFIG_CMD_FLASH is not set
29# CONFIG_CMD_GPT is not set 28# CONFIG_CMD_GPT is not set
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index b4564f2101..be818dff55 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="U-Boot > "
19# CONFIG_CMD_BOOTZ is not set 19# CONFIG_CMD_BOOTZ is not set
20CONFIG_CMD_IMLS=y 20CONFIG_CMD_IMLS=y
21CONFIG_CRC32_VERIFY=y 21CONFIG_CRC32_VERIFY=y
22# CONFIG_CMD_EEPROM is not set
23CONFIG_CMD_DM=y 22CONFIG_CMD_DM=y
24# CONFIG_CMD_GPIO is not set 23# CONFIG_CMD_GPIO is not set
25# CONFIG_CMD_GPT is not set 24# CONFIG_CMD_GPT is not set
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 5c498749d6..1cdde484dd 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -22,7 +22,6 @@ CONFIG_SPL_SPI_LOAD=y
22CONFIG_HUSH_PARSER=y 22CONFIG_HUSH_PARSER=y
23CONFIG_SYS_PROMPT="U-Boot > " 23CONFIG_SYS_PROMPT="U-Boot > "
24CONFIG_CRC32_VERIFY=y 24CONFIG_CRC32_VERIFY=y
25# CONFIG_CMD_EEPROM is not set
26CONFIG_CMD_DM=y 25CONFIG_CMD_DM=y
27# CONFIG_CMD_FLASH is not set 26# CONFIG_CMD_FLASH is not set
28# CONFIG_CMD_GPT is not set 27# CONFIG_CMD_GPT is not set
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 9c08aadc0d..c2ee3d890e 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -36,7 +36,6 @@ CONFIG_TEGRA114_SPI=y
36CONFIG_USB=y 36CONFIG_USB=y
37CONFIG_DM_USB=y 37CONFIG_DM_USB=y
38CONFIG_USB_EHCI_HCD=y 38CONFIG_USB_EHCI_HCD=y
39CONFIG_USB_STORAGE=y
40CONFIG_USB_GADGET=y 39CONFIG_USB_GADGET=y
41CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 40CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
42CONFIG_USB_GADGET_VENDOR_NUM=0x0955 41CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index dd58198a54..9068a58406 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -43,6 +43,9 @@ CONFIG_EFI_PARTITION=y
43CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc" 43CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
44CONFIG_ENV_IS_IN_SPI_FLASH=y 44CONFIG_ENV_IS_IN_SPI_FLASH=y
45CONFIG_SPL_OF_TRANSLATE=y 45CONFIG_SPL_OF_TRANSLATE=y
46CONFIG_BLK=y
47# CONFIG_SPL_BLK is not set
48# CONFIG_BLOCK_CACHE is not set
46CONFIG_DM_I2C=y 49CONFIG_DM_I2C=y
47CONFIG_SYS_I2C_MVTWSI=y 50CONFIG_SYS_I2C_MVTWSI=y
48# CONFIG_MMC is not set 51# CONFIG_MMC is not set
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 92b23778ef..4a65f7f2a5 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -52,7 +52,6 @@ CONFIG_MII=y
52CONFIG_SPI=y 52CONFIG_SPI=y
53CONFIG_MXC_SPI=y 53CONFIG_MXC_SPI=y
54CONFIG_USB=y 54CONFIG_USB=y
55CONFIG_USB_STORAGE=y
56CONFIG_USB_GADGET=y 55CONFIG_USB_GADGET=y
57CONFIG_USB_GADGET_MANUFACTURER="dh" 56CONFIG_USB_GADGET_MANUFACTURER="dh"
58CONFIG_USB_GADGET_VENDOR_NUM=0x0525 57CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 6ef85e246c..4c73a3a246 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -25,7 +25,7 @@ CONFIG_SPL_I2C_SUPPORT=y
25CONFIG_SPL_OS_BOOT=y 25CONFIG_SPL_OS_BOOT=y
26CONFIG_SPL_SPI_LOAD=y 26CONFIG_SPL_SPI_LOAD=y
27CONFIG_SPL_USB_HOST_SUPPORT=y 27CONFIG_SPL_USB_HOST_SUPPORT=y
28CONFIG_SPL_USB_GADGET_SUPPORT=y 28CONFIG_SPL_USB_GADGET=y
29CONFIG_SPL_USB_SDP_SUPPORT=y 29CONFIG_SPL_USB_SDP_SUPPORT=y
30CONFIG_SPL_WATCHDOG_SUPPORT=y 30CONFIG_SPL_WATCHDOG_SUPPORT=y
31CONFIG_HUSH_PARSER=y 31CONFIG_HUSH_PARSER=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 2b6606f9e2..fe253a6552 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -70,9 +70,9 @@ CONFIG_SPI_FLASH=y
70CONFIG_SPI_FLASH_BAR=y 70CONFIG_SPI_FLASH_BAR=y
71CONFIG_SPI_FLASH_SPANSION=y 71CONFIG_SPI_FLASH_SPANSION=y
72CONFIG_DM_ETH=y 72CONFIG_DM_ETH=y
73CONFIG_DRIVER_TI_CPSW=y
74CONFIG_PHY_GIGE=y 73CONFIG_PHY_GIGE=y
75CONFIG_MII=y 74CONFIG_MII=y
75CONFIG_DRIVER_TI_CPSW=y
76CONFIG_SPL_PHY=y 76CONFIG_SPL_PHY=y
77CONFIG_PIPE3_PHY=y 77CONFIG_PIPE3_PHY=y
78CONFIG_OMAP_USB2_PHY=y 78CONFIG_OMAP_USB2_PHY=y
@@ -91,7 +91,6 @@ CONFIG_TIMER=y
91CONFIG_OMAP_TIMER=y 91CONFIG_OMAP_TIMER=y
92CONFIG_USB=y 92CONFIG_USB=y
93CONFIG_DM_USB=y 93CONFIG_DM_USB=y
94CONFIG_SPL_DM_USB=y
95CONFIG_DM_USB_GADGET=y 94CONFIG_DM_USB_GADGET=y
96CONFIG_SPL_DM_USB_GADGET=y 95CONFIG_SPL_DM_USB_GADGET=y
97CONFIG_USB_XHCI_HCD=y 96CONFIG_USB_XHCI_HCD=y
@@ -99,7 +98,6 @@ CONFIG_USB_XHCI_DWC3=y
99CONFIG_USB_DWC3=y 98CONFIG_USB_DWC3=y
100CONFIG_USB_DWC3_GADGET=y 99CONFIG_USB_DWC3_GADGET=y
101CONFIG_USB_DWC3_GENERIC=y 100CONFIG_USB_DWC3_GENERIC=y
102CONFIG_USB_STORAGE=y
103CONFIG_USB_GADGET=y 101CONFIG_USB_GADGET=y
104CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 102CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
105CONFIG_USB_GADGET_VENDOR_NUM=0x0451 103CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 725acb5279..735be5506a 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -68,9 +68,9 @@ CONFIG_SPI_FLASH=y
68CONFIG_SPI_FLASH_BAR=y 68CONFIG_SPI_FLASH_BAR=y
69CONFIG_SPI_FLASH_SPANSION=y 69CONFIG_SPI_FLASH_SPANSION=y
70CONFIG_DM_ETH=y 70CONFIG_DM_ETH=y
71CONFIG_DRIVER_TI_CPSW=y
72CONFIG_PHY_GIGE=y 71CONFIG_PHY_GIGE=y
73CONFIG_MII=y 72CONFIG_MII=y
73CONFIG_DRIVER_TI_CPSW=y
74CONFIG_SPL_PHY=y 74CONFIG_SPL_PHY=y
75CONFIG_PIPE3_PHY=y 75CONFIG_PIPE3_PHY=y
76CONFIG_OMAP_USB2_PHY=y 76CONFIG_OMAP_USB2_PHY=y
@@ -89,7 +89,6 @@ CONFIG_TIMER=y
89CONFIG_OMAP_TIMER=y 89CONFIG_OMAP_TIMER=y
90CONFIG_USB=y 90CONFIG_USB=y
91CONFIG_DM_USB=y 91CONFIG_DM_USB=y
92CONFIG_SPL_DM_USB=y
93CONFIG_DM_USB_GADGET=y 92CONFIG_DM_USB_GADGET=y
94CONFIG_SPL_DM_USB_GADGET=y 93CONFIG_SPL_DM_USB_GADGET=y
95CONFIG_USB_XHCI_HCD=y 94CONFIG_USB_XHCI_HCD=y
@@ -97,7 +96,6 @@ CONFIG_USB_XHCI_DWC3=y
97CONFIG_USB_DWC3=y 96CONFIG_USB_DWC3=y
98CONFIG_USB_DWC3_GADGET=y 97CONFIG_USB_DWC3_GADGET=y
99CONFIG_USB_DWC3_GENERIC=y 98CONFIG_USB_DWC3_GENERIC=y
100CONFIG_USB_STORAGE=y
101CONFIG_USB_GADGET=y 99CONFIG_USB_GADGET=y
102CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 100CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
103CONFIG_USB_GADGET_VENDOR_NUM=0x0451 101CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 634721192d..7eac0f282e 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -47,7 +47,6 @@ CONFIG_USB_EHCI_HCD=y
47CONFIG_USB_EHCI_MSM=y 47CONFIG_USB_EHCI_MSM=y
48CONFIG_USB_ULPI_VIEWPORT=y 48CONFIG_USB_ULPI_VIEWPORT=y
49CONFIG_USB_ULPI=y 49CONFIG_USB_ULPI=y
50CONFIG_USB_STORAGE=y
51CONFIG_USB_GADGET=y 50CONFIG_USB_GADGET=y
52CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 51CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
53CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d 52CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d
diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
index 97d828f441..b2b59e122b 100644
--- a/configs/dragonboard820c_defconfig
+++ b/configs/dragonboard820c_defconfig
@@ -1,5 +1,4 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_ARM_SMCCC=y
3CONFIG_ARCH_SNAPDRAGON=y 2CONFIG_ARCH_SNAPDRAGON=y
4CONFIG_SYS_TEXT_BASE=0x80080000 3CONFIG_SYS_TEXT_BASE=0x80080000
5CONFIG_TARGET_DRAGONBOARD820C=y 4CONFIG_TARGET_DRAGONBOARD820C=y
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index 3c1fee4a90..782a9dc291 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -36,6 +36,6 @@ CONFIG_USB=y
36CONFIG_USB_EHCI_HCD=y 36CONFIG_USB_EHCI_HCD=y
37CONFIG_USB_MUSB_UDC=y 37CONFIG_USB_MUSB_UDC=y
38CONFIG_USB_OMAP3=y 38CONFIG_USB_OMAP3=y
39CONFIG_USB_STORAGE=y 39CONFIG_USB_GADGET=y
40CONFIG_FAT_WRITE=y 40CONFIG_FAT_WRITE=y
41CONFIG_OF_LIBFDT=y 41CONFIG_OF_LIBFDT=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index 89035a051d..afa08a0289 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -31,7 +31,6 @@ CONFIG_TEGRA114_SPI=y
31CONFIG_USB=y 31CONFIG_USB=y
32CONFIG_DM_USB=y 32CONFIG_DM_USB=y
33CONFIG_USB_EHCI_HCD=y 33CONFIG_USB_EHCI_HCD=y
34CONFIG_USB_STORAGE=y
35CONFIG_USB_GADGET=y 34CONFIG_USB_GADGET=y
36CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 35CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
37CONFIG_USB_GADGET_VENDOR_NUM=0x0955 36CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index eb9f9a089f..234dbac4e8 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -18,7 +18,6 @@ CONFIG_CMD_DFU=y
18CONFIG_CMD_GPT=y 18CONFIG_CMD_GPT=y
19CONFIG_CMD_MMC=y 19CONFIG_CMD_MMC=y
20CONFIG_CMD_PART=y 20CONFIG_CMD_PART=y
21# CONFIG_CMD_PCI is not set
22# CONFIG_CMD_NFS is not set 21# CONFIG_CMD_NFS is not set
23CONFIG_CMD_TIMER=y 22CONFIG_CMD_TIMER=y
24CONFIG_CMD_HASH=y 23CONFIG_CMD_HASH=y
diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig
index 40fbd6bd0e..e0bc5776a9 100644
--- a/configs/elgin-rv1108_defconfig
+++ b/configs/elgin-rv1108_defconfig
@@ -49,7 +49,6 @@ CONFIG_USB_EHCI_GENERIC=y
49CONFIG_USB_OHCI_HCD=y 49CONFIG_USB_OHCI_HCD=y
50CONFIG_USB_OHCI_GENERIC=y 50CONFIG_USB_OHCI_GENERIC=y
51CONFIG_USB_DWC2=y 51CONFIG_USB_DWC2=y
52CONFIG_USB_STORAGE=y
53CONFIG_USB_GADGET=y 52CONFIG_USB_GADGET=y
54CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 53CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
55CONFIG_USB_GADGET_VENDOR_NUM=0x2207 54CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 32581f5ada..7fb52d2732 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -12,11 +12,18 @@ CONFIG_PRE_CON_BUF_ADDR=0x1e720000
12# CONFIG_DISPLAY_CPUINFO is not set 12# CONFIG_DISPLAY_CPUINFO is not set
13# CONFIG_AUTO_COMPLETE is not set 13# CONFIG_AUTO_COMPLETE is not set
14CONFIG_CMD_I2C=y 14CONFIG_CMD_I2C=y
15CONFIG_CMD_DHCP=y
16CONFIG_CMD_MII=y
17CONFIG_CMD_PING=y
15CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb" 18CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
16CONFIG_REGMAP=y 19CONFIG_REGMAP=y
17CONFIG_CLK=y 20CONFIG_CLK=y
18CONFIG_DM_I2C=y 21CONFIG_DM_I2C=y
19CONFIG_SYS_I2C_ASPEED=y 22CONFIG_SYS_I2C_ASPEED=y
23CONFIG_PHY_REALTEK=y
24CONFIG_DM_ETH=y
25CONFIG_FTGMAC100=y
26CONFIG_PHY=y
20CONFIG_PINCTRL=y 27CONFIG_PINCTRL=y
21CONFIG_RAM=y 28CONFIG_RAM=y
22CONFIG_DM_RESET=y 29CONFIG_DM_RESET=y
@@ -25,11 +32,3 @@ CONFIG_SYS_NS16550=y
25CONFIG_SYSRESET=y 32CONFIG_SYSRESET=y
26CONFIG_TIMER=y 33CONFIG_TIMER=y
27CONFIG_WDT=y 34CONFIG_WDT=y
28CONFIG_NETDEVICES=y
29CONFIG_PHY=y
30CONFIG_DM_ETH=y
31CONFIG_FTGMAC100=y
32CONFIG_PHY_REALTEK=y
33CONFIG_CMD_PING=y
34CONFIG_CMD_DHCP=y
35CONFIG_CMD_MII=y
diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index 044e60735a..00bf907ff1 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -44,7 +44,6 @@ CONFIG_USB_EHCI_GENERIC=y
44CONFIG_USB_OHCI_HCD=y 44CONFIG_USB_OHCI_HCD=y
45CONFIG_USB_OHCI_GENERIC=y 45CONFIG_USB_OHCI_GENERIC=y
46CONFIG_USB_DWC2=y 46CONFIG_USB_DWC2=y
47CONFIG_USB_STORAGE=y
48CONFIG_USB_GADGET=y 47CONFIG_USB_GADGET=y
49CONFIG_USB_GADGET_DWC2_OTG=y 48CONFIG_USB_GADGET_DWC2_OTG=y
50CONFIG_USE_TINY_PRINTF=y 49CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 1485844aa6..980f7f7b3d 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -71,7 +71,6 @@ CONFIG_SYSRESET=y
71CONFIG_USB=y 71CONFIG_USB=y
72CONFIG_USB_DWC2=y 72CONFIG_USB_DWC2=y
73CONFIG_ROCKCHIP_USB2_PHY=y 73CONFIG_ROCKCHIP_USB2_PHY=y
74CONFIG_USB_STORAGE=y
75CONFIG_USB_GADGET=y 74CONFIG_USB_GADGET=y
76CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 75CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
77CONFIG_USB_GADGET_VENDOR_NUM=0x2207 76CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index f0221633fa..10a5f09b31 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -49,7 +49,6 @@ CONFIG_BAUDRATE=1500000
49CONFIG_DEBUG_UART_SHIFT=2 49CONFIG_DEBUG_UART_SHIFT=2
50CONFIG_SYSRESET=y 50CONFIG_SYSRESET=y
51CONFIG_USB=y 51CONFIG_USB=y
52CONFIG_USB_DWC3=y
53CONFIG_USB_XHCI_HCD=y 52CONFIG_USB_XHCI_HCD=y
54CONFIG_USB_XHCI_DWC3=y 53CONFIG_USB_XHCI_DWC3=y
55CONFIG_USB_EHCI_HCD=y 54CONFIG_USB_EHCI_HCD=y
@@ -57,7 +56,7 @@ CONFIG_USB_EHCI_GENERIC=y
57CONFIG_USB_OHCI_HCD=y 56CONFIG_USB_OHCI_HCD=y
58CONFIG_USB_OHCI_GENERIC=y 57CONFIG_USB_OHCI_GENERIC=y
59CONFIG_USB_DWC2=y 58CONFIG_USB_DWC2=y
60CONFIG_USB_STORAGE=y 59CONFIG_USB_DWC3=y
61CONFIG_USB_GADGET=y 60CONFIG_USB_GADGET=y
62CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 61CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
63CONFIG_USB_GADGET_VENDOR_NUM=0x2207 62CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index f173c10a6b..3ec6b20814 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -67,7 +67,6 @@ CONFIG_USB_XHCI_HCD=y
67CONFIG_USB_XHCI_DWC3=y 67CONFIG_USB_XHCI_DWC3=y
68CONFIG_USB_EHCI_HCD=y 68CONFIG_USB_EHCI_HCD=y
69CONFIG_USB_EHCI_GENERIC=y 69CONFIG_USB_EHCI_GENERIC=y
70CONFIG_USB_STORAGE=y
71CONFIG_USB_HOST_ETHER=y 70CONFIG_USB_HOST_ETHER=y
72CONFIG_USB_ETHER_ASIX=y 71CONFIG_USB_ETHER_ASIX=y
73CONFIG_USB_ETHER_ASIX88179=y 72CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index 2ef041f2c5..0ca6930e43 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -49,7 +49,6 @@ CONFIG_USB_EHCI_GENERIC=y
49CONFIG_USB_OHCI_HCD=y 49CONFIG_USB_OHCI_HCD=y
50CONFIG_USB_OHCI_GENERIC=y 50CONFIG_USB_OHCI_GENERIC=y
51CONFIG_USB_DWC2=y 51CONFIG_USB_DWC2=y
52CONFIG_USB_STORAGE=y
53CONFIG_USB_GADGET=y 52CONFIG_USB_GADGET=y
54CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 53CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
55CONFIG_USB_GADGET_VENDOR_NUM=0x2207 54CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 8860edfd2f..2795ad82b0 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -70,7 +70,6 @@ CONFIG_SYSRESET=y
70CONFIG_USB=y 70CONFIG_USB=y
71CONFIG_USB_DWC2=y 71CONFIG_USB_DWC2=y
72CONFIG_ROCKCHIP_USB2_PHY=y 72CONFIG_ROCKCHIP_USB2_PHY=y
73CONFIG_USB_STORAGE=y
74CONFIG_USB_GADGET=y 73CONFIG_USB_GADGET=y
75CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 74CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
76CONFIG_USB_GADGET_VENDOR_NUM=0x2207 75CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index e890bc2523..a05f832d3c 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -5,12 +5,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
5CONFIG_SPL_LIBGENERIC_SUPPORT=y 5CONFIG_SPL_LIBGENERIC_SUPPORT=y
6CONFIG_SYS_MALLOC_F_LEN=0x4000 6CONFIG_SYS_MALLOC_F_LEN=0x4000
7CONFIG_ROCKCHIP_RK3399=y 7CONFIG_ROCKCHIP_RK3399=y
8CONFIG_TARGET_ROCK960_RK3399=y
9CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 8CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
9CONFIG_TARGET_ROCK960_RK3399=y
10CONFIG_DEBUG_UART_BASE=0xFF1A0000 10CONFIG_DEBUG_UART_BASE=0xFF1A0000
11CONFIG_DEBUG_UART_CLOCK=24000000 11CONFIG_DEBUG_UART_CLOCK=24000000
12CONFIG_SPL_STACK_R_ADDR=0x80000 12CONFIG_SPL_STACK_R_ADDR=0x80000
13CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
14CONFIG_DEBUG_UART=y 13CONFIG_DEBUG_UART=y
15CONFIG_FIT=y 14CONFIG_FIT=y
16CONFIG_SPL_LOAD_FIT=y 15CONFIG_SPL_LOAD_FIT=y
@@ -29,6 +28,7 @@ CONFIG_CMD_USB=y
29# CONFIG_CMD_SETEXPR is not set 28# CONFIG_CMD_SETEXPR is not set
30CONFIG_CMD_TIME=y 29CONFIG_CMD_TIME=y
31CONFIG_SPL_OF_CONTROL=y 30CONFIG_SPL_OF_CONTROL=y
31CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
32CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" 32CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
33CONFIG_ENV_IS_IN_MMC=y 33CONFIG_ENV_IS_IN_MMC=y
34CONFIG_NET_RANDOM_ETHADDR=y 34CONFIG_NET_RANDOM_ETHADDR=y
@@ -66,6 +66,5 @@ CONFIG_SYSRESET=y
66CONFIG_USB=y 66CONFIG_USB=y
67CONFIG_USB_EHCI_HCD=y 67CONFIG_USB_EHCI_HCD=y
68CONFIG_USB_EHCI_GENERIC=y 68CONFIG_USB_EHCI_GENERIC=y
69CONFIG_USB_STORAGE=y
70CONFIG_USE_TINY_PRINTF=y 69CONFIG_USE_TINY_PRINTF=y
71CONFIG_ERRNO_STR=y 70CONFIG_ERRNO_STR=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index b0db15ddc9..f5a8b614f6 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -74,7 +74,6 @@ CONFIG_SYSRESET=y
74CONFIG_USB=y 74CONFIG_USB=y
75CONFIG_USB_DWC2=y 75CONFIG_USB_DWC2=y
76CONFIG_ROCKCHIP_USB2_PHY=y 76CONFIG_ROCKCHIP_USB2_PHY=y
77CONFIG_USB_STORAGE=y
78CONFIG_USB_KEYBOARD=y 77CONFIG_USB_KEYBOARD=y
79CONFIG_USB_GADGET=y 78CONFIG_USB_GADGET=y
80CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 79CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 7ac4064a8b..e77bc4463d 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -66,7 +66,6 @@ CONFIG_USB_XHCI_HCD=y
66CONFIG_USB_XHCI_DWC3=y 66CONFIG_USB_XHCI_DWC3=y
67CONFIG_USB_EHCI_HCD=y 67CONFIG_USB_EHCI_HCD=y
68CONFIG_USB_EHCI_GENERIC=y 68CONFIG_USB_EHCI_GENERIC=y
69CONFIG_USB_STORAGE=y
70CONFIG_USB_HOST_ETHER=y 69CONFIG_USB_HOST_ETHER=y
71CONFIG_USB_ETHER_ASIX=y 70CONFIG_USB_ETHER_ASIX=y
72CONFIG_USB_ETHER_ASIX88179=y 71CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig
index 05e7cf9f88..ae8bf2981f 100644
--- a/configs/gardena-smart-gateway-mt7688-ram_defconfig
+++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_MTDPARTS=y
36CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0" 36CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0"
37CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)" 37CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)"
38CONFIG_CMD_UBI=y 38CONFIG_CMD_UBI=y
39CONFIG_OF_EMBED=y
40CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" 39CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
41CONFIG_ENV_IS_IN_SPI_FLASH=y 40CONFIG_ENV_IS_IN_SPI_FLASH=y
42CONFIG_NET_RANDOM_ETHADDR=y 41CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig
index a08d1dbc9c..b7024e3dec 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -39,7 +39,6 @@ CONFIG_CMD_MTDPARTS=y
39CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0" 39CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0"
40CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)" 40CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)"
41CONFIG_CMD_UBI=y 41CONFIG_CMD_UBI=y
42CONFIG_OF_EMBED=y
43CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" 42CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
44CONFIG_ENV_IS_IN_SPI_FLASH=y 43CONFIG_ENV_IS_IN_SPI_FLASH=y
45CONFIG_NET_RANDOM_ETHADDR=y 44CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index c907779636..84947aaae2 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -1,6 +1,9 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_ARCH_MX6=y 2CONFIG_ARCH_MX6=y
3CONFIG_SYS_TEXT_BASE=0x17800000 3CONFIG_SYS_TEXT_BASE=0x17800000
4CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50
5CONFIG_SYS_VPD_EEPROM_I2C_BUS=4
6CONFIG_SYS_VPD_EEPROM_SIZE=1024
4CONFIG_TARGET_GE_BX50V3=y 7CONFIG_TARGET_GE_BX50V3=y
5CONFIG_NR_DRAM_BANKS=1 8CONFIG_NR_DRAM_BANKS=1
6# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set 9# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 8e99fe7ccb..f0987fc064 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -43,7 +43,6 @@ CONFIG_DM_USB=y
43CONFIG_USB_EHCI_HCD=y 43CONFIG_USB_EHCI_HCD=y
44CONFIG_USB_ULPI_VIEWPORT=y 44CONFIG_USB_ULPI_VIEWPORT=y
45CONFIG_USB_ULPI=y 45CONFIG_USB_ULPI=y
46CONFIG_USB_STORAGE=y
47CONFIG_USB_HOST_ETHER=y 46CONFIG_USB_HOST_ETHER=y
48CONFIG_USB_ETHER_ASIX=y 47CONFIG_USB_ETHER_ASIX=y
49CONFIG_USB_ETHER_MCS7830=y 48CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index 3bb4622fbe..514b40c356 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -7,7 +7,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
7CONFIG_TARGET_HELIOS4=y 7CONFIG_TARGET_HELIOS4=y
8CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y 8CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
9CONFIG_SPL_SERIAL_SUPPORT=y 9CONFIG_SPL_SERIAL_SUPPORT=y
10CONFIG_SPL_SYS_MALLOC_SIMPLE=y
11CONFIG_SPL=y 10CONFIG_SPL=y
12CONFIG_DEBUG_UART_BASE=0xd0012000 11CONFIG_DEBUG_UART_BASE=0xd0012000
13CONFIG_DEBUG_UART_CLOCK=250000000 12CONFIG_DEBUG_UART_CLOCK=250000000
@@ -19,6 +18,7 @@ CONFIG_BOOTDELAY=3
19CONFIG_SYS_CONSOLE_INFO_QUIET=y 18CONFIG_SYS_CONSOLE_INFO_QUIET=y
20# CONFIG_DISPLAY_BOARDINFO is not set 19# CONFIG_DISPLAY_BOARDINFO is not set
21CONFIG_DISPLAY_BOARDINFO_LATE=y 20CONFIG_DISPLAY_BOARDINFO_LATE=y
21CONFIG_SPL_SYS_MALLOC_SIMPLE=y
22CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 22CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
23# CONFIG_CMD_FLASH is not set 23# CONFIG_CMD_FLASH is not set
24CONFIG_CMD_GPIO=y 24CONFIG_CMD_GPIO=y
@@ -38,12 +38,11 @@ CONFIG_NET_RANDOM_ETHADDR=y
38CONFIG_SPL_OF_TRANSLATE=y 38CONFIG_SPL_OF_TRANSLATE=y
39CONFIG_SCSI_AHCI=y 39CONFIG_SCSI_AHCI=y
40CONFIG_DM_GPIO=y 40CONFIG_DM_GPIO=y
41CONFIG_MVEBU_GPIO=y
42CONFIG_DM_PCA953X=y 41CONFIG_DM_PCA953X=y
43CONFIG_DM_I2C=y 42CONFIG_DM_I2C=y
44CONFIG_SYS_I2C_MVTWSI=y
45CONFIG_I2C_SET_DEFAULT_BUS_NUM=y 43CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
46CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 44CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
45CONFIG_SYS_I2C_MVTWSI=y
47CONFIG_MMC_SDHCI=y 46CONFIG_MMC_SDHCI=y
48CONFIG_MMC_SDHCI_SDMA=y 47CONFIG_MMC_SDHCI_SDMA=y
49CONFIG_MMC_SDHCI_MV=y 48CONFIG_MMC_SDHCI_MV=y
@@ -60,4 +59,3 @@ CONFIG_KIRKWOOD_SPI=y
60CONFIG_USB=y 59CONFIG_USB=y
61CONFIG_DM_USB=y 60CONFIG_DM_USB=y
62CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_STORAGE=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 8dc5a2823e..3bc5ceb5d8 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -23,7 +23,6 @@ CONFIG_MMC_DW_K3=y
23CONFIG_CONS_INDEX=4 23CONFIG_CONS_INDEX=4
24CONFIG_USB=y 24CONFIG_USB=y
25CONFIG_USB_DWC2=y 25CONFIG_USB_DWC2=y
26CONFIG_USB_STORAGE=y
27CONFIG_USB_HOST_ETHER=y 26CONFIG_USB_HOST_ETHER=y
28CONFIG_USB_ETHER_ASIX=y 27CONFIG_USB_ETHER_ASIX=y
29CONFIG_USB_ETHER_SMSC95XX=y 28CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig
index 6bb14ba736..d4e6144319 100644
--- a/configs/huawei_hg556a_ram_defconfig
+++ b/configs/huawei_hg556a_ram_defconfig
@@ -25,11 +25,14 @@ CONFIG_CMD_LICENSE=y
25CONFIG_CMD_MEMINFO=y 25CONFIG_CMD_MEMINFO=y
26# CONFIG_CMD_LOADS is not set 26# CONFIG_CMD_LOADS is not set
27CONFIG_CMD_USB=y 27CONFIG_CMD_USB=y
28CONFIG_CMD_MII=y
29CONFIG_CMD_PING=y
28# CONFIG_CMD_MISC is not set 30# CONFIG_CMD_MISC is not set
29CONFIG_OF_EMBED=y 31CONFIG_OF_EMBED=y
30CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" 32CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
31# CONFIG_NET is not set 33CONFIG_NET_RANDOM_ETHADDR=y
32# CONFIG_DM_DEVICE_REMOVE is not set 34# CONFIG_DM_DEVICE_REMOVE is not set
35CONFIG_BCM6348_IUDMA=y
33CONFIG_DM_GPIO=y 36CONFIG_DM_GPIO=y
34CONFIG_BCM6345_GPIO=y 37CONFIG_BCM6345_GPIO=y
35CONFIG_LED=y 38CONFIG_LED=y
@@ -40,6 +43,9 @@ CONFIG_FLASH_CFI_DRIVER=y
40CONFIG_CFI_FLASH=y 43CONFIG_CFI_FLASH=y
41CONFIG_SYS_FLASH_PROTECTION=y 44CONFIG_SYS_FLASH_PROTECTION=y
42CONFIG_SYS_FLASH_CFI=y 45CONFIG_SYS_FLASH_CFI=y
46CONFIG_PHY_FIXED=y
47CONFIG_DM_ETH=y
48CONFIG_BCM6348_ETH=y
43CONFIG_PHY=y 49CONFIG_PHY=y
44CONFIG_BCM6358_USBH_PHY=y 50CONFIG_BCM6358_USBH_PHY=y
45CONFIG_DM_RESET=y 51CONFIG_DM_RESET=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index 383648789c..20d2cf5820 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -45,6 +45,7 @@ CONFIG_USB=y
45CONFIG_USB_MUSB_UDC=y 45CONFIG_USB_MUSB_UDC=y
46CONFIG_USB_OMAP3=y 46CONFIG_USB_OMAP3=y
47CONFIG_TWL4030_USB=y 47CONFIG_TWL4030_USB=y
48CONFIG_USB_GADGET=y
48CONFIG_FAT_WRITE=y 49CONFIG_FAT_WRITE=y
49CONFIG_UBIFS_SILENCE_MSG=y 50CONFIG_UBIFS_SILENCE_MSG=y
50CONFIG_BCH=y 51CONFIG_BCH=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index f2989e34e1..330350c32a 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -46,6 +46,7 @@ CONFIG_USB=y
46CONFIG_USB_MUSB_UDC=y 46CONFIG_USB_MUSB_UDC=y
47CONFIG_USB_OMAP3=y 47CONFIG_USB_OMAP3=y
48CONFIG_TWL4030_USB=y 48CONFIG_TWL4030_USB=y
49CONFIG_USB_GADGET=y
49CONFIG_FAT_WRITE=y 50CONFIG_FAT_WRITE=y
50CONFIG_UBIFS_SILENCE_MSG=y 51CONFIG_UBIFS_SILENCE_MSG=y
51CONFIG_BCH=y 52CONFIG_BCH=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 036069a437..46312a0ece 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -24,7 +24,7 @@ CONFIG_SPL_I2C_SUPPORT=y
24CONFIG_SPL_NAND_SUPPORT=y 24CONFIG_SPL_NAND_SUPPORT=y
25CONFIG_SPL_OS_BOOT=y 25CONFIG_SPL_OS_BOOT=y
26CONFIG_SPL_USB_HOST_SUPPORT=y 26CONFIG_SPL_USB_HOST_SUPPORT=y
27CONFIG_SPL_USB_GADGET_SUPPORT=y 27CONFIG_SPL_USB_GADGET=y
28CONFIG_SPL_USB_SDP_SUPPORT=y 28CONFIG_SPL_USB_SDP_SUPPORT=y
29CONFIG_SPL_WATCHDOG_SUPPORT=y 29CONFIG_SPL_WATCHDOG_SUPPORT=y
30CONFIG_SYS_PROMPT="i.MX6 Logic # " 30CONFIG_SYS_PROMPT="i.MX6 Logic # "
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
new file mode 100644
index 0000000000..f82ef3881f
--- /dev/null
+++ b/configs/imx8mq_evk_defconfig
@@ -0,0 +1,37 @@
1CONFIG_ARM=y
2CONFIG_ARCH_IMX8M=y
3CONFIG_SYS_TEXT_BASE=0x40200000
4CONFIG_SYS_MALLOC_F_LEN=0x2000
5CONFIG_TARGET_IMX8MQ_EVK=y
6CONFIG_SPL_SERIAL_SUPPORT=y
7CONFIG_SPL=y
8CONFIG_FIT=y
9CONFIG_FIT_EXTERNAL_OFFSET=0x3000
10CONFIG_SPL_LOAD_FIT=y
11CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
12CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
13CONFIG_SPL_BOARD_INIT=y
14CONFIG_HUSH_PARSER=y
15CONFIG_DOS_PARTITION=y
16CONFIG_CMD_EXT2=y
17CONFIG_CMD_EXT4=y
18CONFIG_CMD_EXT4_WRITE=y
19CONFIG_CMD_FAT=y
20CONFIG_CMD_GPIO=y
21CONFIG_CMD_I2C=y
22CONFIG_CMD_CACHE=y
23CONFIG_CMD_REGULATOR=y
24CONFIG_OF_CONTROL=y
25CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
26CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
27CONFIG_DM_GPIO=y
28CONFIG_DM_I2C=y
29CONFIG_SYS_I2C_MXC=y
30CONFIG_DM_MMC=y
31CONFIG_DM_ETH=y
32CONFIG_PINCTRL=y
33CONFIG_DM_REGULATOR=y
34CONFIG_DM_REGULATOR_FIXED=y
35CONFIG_DM_REGULATOR_GPIO=y
36CONFIG_DM_THERMAL=y
37CONFIG_FS_FAT=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 76f3376e3c..c39c424e7b 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -46,7 +46,6 @@ CONFIG_TEGRA114_SPI=y
46CONFIG_USB=y 46CONFIG_USB=y
47CONFIG_DM_USB=y 47CONFIG_DM_USB=y
48CONFIG_USB_EHCI_HCD=y 48CONFIG_USB_EHCI_HCD=y
49CONFIG_USB_STORAGE=y
50CONFIG_USB_GADGET=y 49CONFIG_USB_GADGET=y
51CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 50CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
52CONFIG_USB_GADGET_VENDOR_NUM=0x0955 51CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 03a1ceb268..a108f88dfd 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -48,6 +48,7 @@ CONFIG_PHYLIB=y
48CONFIG_PHY_MARVELL=y 48CONFIG_PHY_MARVELL=y
49CONFIG_DM_ETH=y 49CONFIG_DM_ETH=y
50CONFIG_MII=y 50CONFIG_MII=y
51CONFIG_DRIVER_TI_KEYSTONE_NET=y
51CONFIG_PHY=y 52CONFIG_PHY=y
52CONFIG_NOP_PHY=y 53CONFIG_NOP_PHY=y
53CONFIG_KEYSTONE_USB_PHY=y 54CONFIG_KEYSTONE_USB_PHY=y
@@ -62,5 +63,3 @@ CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_DWC3=y 64CONFIG_USB_DWC3=y
64CONFIG_USB_DWC3_GENERIC=y 65CONFIG_USB_DWC3_GENERIC=y
65CONFIG_USB_STORAGE=y
66CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index bb7b31417e..67f6fb1da5 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -41,6 +41,7 @@ CONFIG_PHYLIB=y
41CONFIG_PHY_MARVELL=y 41CONFIG_PHY_MARVELL=y
42CONFIG_DM_ETH=y 42CONFIG_DM_ETH=y
43CONFIG_MII=y 43CONFIG_MII=y
44CONFIG_DRIVER_TI_KEYSTONE_NET=y
44CONFIG_PHY=y 45CONFIG_PHY=y
45CONFIG_NOP_PHY=y 46CONFIG_NOP_PHY=y
46CONFIG_KEYSTONE_USB_PHY=y 47CONFIG_KEYSTONE_USB_PHY=y
@@ -55,5 +56,3 @@ CONFIG_USB_XHCI_HCD=y
55CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
56CONFIG_USB_DWC3=y 57CONFIG_USB_DWC3=y
57CONFIG_USB_DWC3_GENERIC=y 58CONFIG_USB_DWC3_GENERIC=y
58CONFIG_USB_STORAGE=y
59CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 8a07039696..ab9e695b02 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -52,6 +52,7 @@ CONFIG_PHY_MARVELL=y
52CONFIG_PHY_MICREL=y 52CONFIG_PHY_MICREL=y
53CONFIG_DM_ETH=y 53CONFIG_DM_ETH=y
54CONFIG_MII=y 54CONFIG_MII=y
55CONFIG_DRIVER_TI_KEYSTONE_NET=y
55CONFIG_PHY=y 56CONFIG_PHY=y
56CONFIG_NOP_PHY=y 57CONFIG_NOP_PHY=y
57CONFIG_REMOTEPROC_TI_POWER=y 58CONFIG_REMOTEPROC_TI_POWER=y
@@ -68,8 +69,6 @@ CONFIG_USB_XHCI_DWC3=y
68CONFIG_USB_DWC3=y 69CONFIG_USB_DWC3=y
69CONFIG_USB_DWC3_GADGET=y 70CONFIG_USB_DWC3_GADGET=y
70CONFIG_USB_DWC3_GENERIC=y 71CONFIG_USB_DWC3_GENERIC=y
71CONFIG_USB_STORAGE=y
72CONFIG_DRIVER_TI_KEYSTONE_NET=y
73CONFIG_USB_GADGET=y 72CONFIG_USB_GADGET=y
74CONFIG_USB_GADGET_DOWNLOAD=y 73CONFIG_USB_GADGET_DOWNLOAD=y
75CONFIG_USB_FUNCTION_SDP=y 74CONFIG_USB_FUNCTION_SDP=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 5f91f11d36..a6757cc0b4 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -45,6 +45,7 @@ CONFIG_PHY_MARVELL=y
45CONFIG_PHY_MICREL=y 45CONFIG_PHY_MICREL=y
46CONFIG_DM_ETH=y 46CONFIG_DM_ETH=y
47CONFIG_MII=y 47CONFIG_MII=y
48CONFIG_DRIVER_TI_KEYSTONE_NET=y
48CONFIG_PHY=y 49CONFIG_PHY=y
49CONFIG_NOP_PHY=y 50CONFIG_NOP_PHY=y
50CONFIG_REMOTEPROC_TI_POWER=y 51CONFIG_REMOTEPROC_TI_POWER=y
@@ -61,8 +62,6 @@ CONFIG_USB_XHCI_DWC3=y
61CONFIG_USB_DWC3=y 62CONFIG_USB_DWC3=y
62CONFIG_USB_DWC3_GADGET=y 63CONFIG_USB_DWC3_GADGET=y
63CONFIG_USB_DWC3_GENERIC=y 64CONFIG_USB_DWC3_GENERIC=y
64CONFIG_USB_STORAGE=y
65CONFIG_DRIVER_TI_KEYSTONE_NET=y
66CONFIG_USB_GADGET=y 65CONFIG_USB_GADGET=y
67CONFIG_USB_GADGET_DOWNLOAD=y 66CONFIG_USB_GADGET_DOWNLOAD=y
68CONFIG_USB_FUNCTION_SDP=y 67CONFIG_USB_FUNCTION_SDP=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 700fafd5a3..ce139d11d6 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -48,6 +48,7 @@ CONFIG_PHYLIB=y
48CONFIG_PHY_MARVELL=y 48CONFIG_PHY_MARVELL=y
49CONFIG_DM_ETH=y 49CONFIG_DM_ETH=y
50CONFIG_MII=y 50CONFIG_MII=y
51CONFIG_DRIVER_TI_KEYSTONE_NET=y
51CONFIG_PHY=y 52CONFIG_PHY=y
52CONFIG_NOP_PHY=y 53CONFIG_NOP_PHY=y
53CONFIG_KEYSTONE_USB_PHY=y 54CONFIG_KEYSTONE_USB_PHY=y
@@ -62,5 +63,3 @@ CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_DWC3=y 64CONFIG_USB_DWC3=y
64CONFIG_USB_DWC3_GENERIC=y 65CONFIG_USB_DWC3_GENERIC=y
65CONFIG_USB_STORAGE=y
66CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index a6caccce7b..db61557f11 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -41,6 +41,7 @@ CONFIG_PHYLIB=y
41CONFIG_PHY_MARVELL=y 41CONFIG_PHY_MARVELL=y
42CONFIG_DM_ETH=y 42CONFIG_DM_ETH=y
43CONFIG_MII=y 43CONFIG_MII=y
44CONFIG_DRIVER_TI_KEYSTONE_NET=y
44CONFIG_PHY=y 45CONFIG_PHY=y
45CONFIG_NOP_PHY=y 46CONFIG_NOP_PHY=y
46CONFIG_KEYSTONE_USB_PHY=y 47CONFIG_KEYSTONE_USB_PHY=y
@@ -55,5 +56,3 @@ CONFIG_USB_XHCI_HCD=y
55CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
56CONFIG_USB_DWC3=y 57CONFIG_USB_DWC3=y
57CONFIG_USB_DWC3_GENERIC=y 58CONFIG_USB_DWC3_GENERIC=y
58CONFIG_USB_STORAGE=y
59CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index cb638082da..368171d134 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -48,6 +48,7 @@ CONFIG_PHYLIB=y
48CONFIG_PHY_MARVELL=y 48CONFIG_PHY_MARVELL=y
49CONFIG_DM_ETH=y 49CONFIG_DM_ETH=y
50CONFIG_MII=y 50CONFIG_MII=y
51CONFIG_DRIVER_TI_KEYSTONE_NET=y
51CONFIG_PHY=y 52CONFIG_PHY=y
52CONFIG_NOP_PHY=y 53CONFIG_NOP_PHY=y
53CONFIG_KEYSTONE_USB_PHY=y 54CONFIG_KEYSTONE_USB_PHY=y
@@ -62,5 +63,3 @@ CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_DWC3=y 64CONFIG_USB_DWC3=y
64CONFIG_USB_DWC3_GENERIC=y 65CONFIG_USB_DWC3_GENERIC=y
65CONFIG_USB_STORAGE=y
66CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 4ce7801e4e..7bb672f50c 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -40,6 +40,7 @@ CONFIG_PHYLIB=y
40CONFIG_PHY_MARVELL=y 40CONFIG_PHY_MARVELL=y
41CONFIG_DM_ETH=y 41CONFIG_DM_ETH=y
42CONFIG_MII=y 42CONFIG_MII=y
43CONFIG_DRIVER_TI_KEYSTONE_NET=y
43CONFIG_PHY=y 44CONFIG_PHY=y
44CONFIG_NOP_PHY=y 45CONFIG_NOP_PHY=y
45CONFIG_KEYSTONE_USB_PHY=y 46CONFIG_KEYSTONE_USB_PHY=y
@@ -55,4 +56,3 @@ CONFIG_USB_XHCI_DWC3=y
55CONFIG_USB_DWC3=y 56CONFIG_USB_DWC3=y
56CONFIG_USB_DWC3_GENERIC=y 57CONFIG_USB_DWC3_GENERIC=y
57CONFIG_USB_STORAGE=y 58CONFIG_USB_STORAGE=y
58CONFIG_DRIVER_TI_KEYSTONE_NET=y
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 6fe861c0e5..75514d2ca5 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -43,5 +43,4 @@ CONFIG_USB_XHCI_HCD=y
43CONFIG_USB_XHCI_DWC3=y 43CONFIG_USB_XHCI_DWC3=y
44CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y 44CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
45CONFIG_USB_DWC3=y 45CONFIG_USB_DWC3=y
46CONFIG_USB_STORAGE=y
47CONFIG_OF_LIBFDT_OVERLAY=y 46CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 6e855dd6eb..cf87802653 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -48,5 +48,4 @@ CONFIG_USB_XHCI_HCD=y
48CONFIG_USB_XHCI_DWC3=y 48CONFIG_USB_XHCI_DWC3=y
49CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y 49CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
50CONFIG_USB_DWC3=y 50CONFIG_USB_DWC3=y
51CONFIG_USB_STORAGE=y
52CONFIG_OF_LIBFDT_OVERLAY=y 51CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index 5ebbe1dc7c..f0fb52deda 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -39,6 +39,5 @@ CONFIG_FEC_MXC=y
39CONFIG_MII=y 39CONFIG_MII=y
40CONFIG_IMX_THERMAL=y 40CONFIG_IMX_THERMAL=y
41CONFIG_USB=y 41CONFIG_USB=y
42CONFIG_USB_STORAGE=y
43CONFIG_IMX_WATCHDOG=y 42CONFIG_IMX_WATCHDOG=y
44CONFIG_OF_LIBFDT=y 43CONFIG_OF_LIBFDT=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 765003095c..a577605822 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -47,7 +47,6 @@ CONFIG_DM_REGULATOR_FIXED=y
47CONFIG_SYSRESET=y 47CONFIG_SYSRESET=y
48CONFIG_USB=y 48CONFIG_USB=y
49CONFIG_USB_DWC2=y 49CONFIG_USB_DWC2=y
50CONFIG_USB_STORAGE=y
51CONFIG_USB_GADGET=y 50CONFIG_USB_GADGET=y
52CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 51CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
53CONFIG_USB_GADGET_VENDOR_NUM=0x2207 52CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index c2f985fcfb..c21b9ad9ca 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -48,5 +48,4 @@ CONFIG_USB_XHCI_HCD=y
48CONFIG_USB_XHCI_DWC3=y 48CONFIG_USB_XHCI_DWC3=y
49CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y 49CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
50CONFIG_USB_DWC3=y 50CONFIG_USB_DWC3=y
51CONFIG_USB_STORAGE=y
52CONFIG_OF_LIBFDT_OVERLAY=y 51CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig
index 2d20e9edd9..2d3ab7e35c 100644
--- a/configs/linkit-smart-7688-ram_defconfig
+++ b/configs/linkit-smart-7688-ram_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_DHCP=y
26CONFIG_CMD_MII=y 26CONFIG_CMD_MII=y
27CONFIG_CMD_PING=y 27CONFIG_CMD_PING=y
28CONFIG_CMD_TIME=y 28CONFIG_CMD_TIME=y
29CONFIG_OF_EMBED=y
30CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" 29CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
31CONFIG_ENV_IS_IN_SPI_FLASH=y 30CONFIG_ENV_IS_IN_SPI_FLASH=y
32CONFIG_NET_RANDOM_ETHADDR=y 31CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig
index 5add29fb33..ad34aaf640 100644
--- a/configs/linkit-smart-7688_defconfig
+++ b/configs/linkit-smart-7688_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_DHCP=y
30CONFIG_CMD_MII=y 30CONFIG_CMD_MII=y
31CONFIG_CMD_PING=y 31CONFIG_CMD_PING=y
32CONFIG_CMD_TIME=y 32CONFIG_CMD_TIME=y
33CONFIG_OF_EMBED=y
34CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" 33CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
35CONFIG_ENV_IS_IN_SPI_FLASH=y 34CONFIG_ENV_IS_IN_SPI_FLASH=y
36CONFIG_NET_RANDOM_ETHADDR=y 35CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 42d2e2e7b3..ea64172f3d 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -47,4 +47,3 @@ CONFIG_USB=y
47CONFIG_DM_USB=y 47CONFIG_DM_USB=y
48CONFIG_USB_XHCI_HCD=y 48CONFIG_USB_XHCI_HCD=y
49CONFIG_USB_XHCI_DWC3=y 49CONFIG_USB_XHCI_DWC3=y
50CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index 3987eb4d91..3d15745411 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -47,4 +47,3 @@ CONFIG_USB=y
47CONFIG_DM_USB=y 47CONFIG_DM_USB=y
48CONFIG_USB_XHCI_HCD=y 48CONFIG_USB_XHCI_HCD=y
49CONFIG_USB_XHCI_DWC3=y 49CONFIG_USB_XHCI_DWC3=y
50CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index a63b900a2e..7317f5fc04 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -47,4 +47,3 @@ CONFIG_USB=y
47CONFIG_DM_USB=y 47CONFIG_DM_USB=y
48CONFIG_USB_XHCI_HCD=y 48CONFIG_USB_XHCI_HCD=y
49CONFIG_USB_XHCI_DWC3=y 49CONFIG_USB_XHCI_DWC3=y
50CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index 703f9cb99e..051d62645e 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -47,4 +47,3 @@ CONFIG_USB=y
47CONFIG_DM_USB=y 47CONFIG_DM_USB=y
48CONFIG_USB_XHCI_HCD=y 48CONFIG_USB_XHCI_HCD=y
49CONFIG_USB_XHCI_DWC3=y 49CONFIG_USB_XHCI_DWC3=y
50CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index d457d9420b..c273dc937e 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -47,6 +47,5 @@ CONFIG_USB=y
47CONFIG_DM_USB=y 47CONFIG_DM_USB=y
48CONFIG_USB_XHCI_HCD=y 48CONFIG_USB_XHCI_HCD=y
49CONFIG_USB_XHCI_DWC3=y 49CONFIG_USB_XHCI_DWC3=y
50CONFIG_USB_STORAGE=y
51CONFIG_RSA=y 50CONFIG_RSA=y
52CONFIG_RSA_SOFTWARE_EXP=y 51CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index 7fe9556d04..85523ba2d3 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -48,4 +48,3 @@ CONFIG_USB=y
48CONFIG_DM_USB=y 48CONFIG_DM_USB=y
49CONFIG_USB_XHCI_HCD=y 49CONFIG_USB_XHCI_HCD=y
50CONFIG_USB_XHCI_DWC3=y 50CONFIG_USB_XHCI_DWC3=y
51CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 0c6f474066..d9020c5281 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -1,10 +1,10 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_TARGET_LS1012AFRWY=y 2CONFIG_TARGET_LS1012AFRWY=y
3CONFIG_SYS_TEXT_BASE=0x82000000 3CONFIG_SYS_TEXT_BASE=0x82000000
4CONFIG_SECURE_BOOT=y
4CONFIG_TFABOOT=y 5CONFIG_TFABOOT=y
5CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y 6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
6CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y 7CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
7CONFIG_SECURE_BOOT=y
8CONFIG_DISTRO_DEFAULTS=y 8CONFIG_DISTRO_DEFAULTS=y
9CONFIG_NR_DRAM_BANKS=2 9CONFIG_NR_DRAM_BANKS=2
10# CONFIG_SYS_MALLOC_F is not set 10# CONFIG_SYS_MALLOC_F is not set
@@ -16,7 +16,6 @@ CONFIG_USE_BOOTARGS=y
16CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" 16CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
17# CONFIG_DISPLAY_BOARDINFO is not set 17# CONFIG_DISPLAY_BOARDINFO is not set
18CONFIG_DISPLAY_BOARDINFO_LATE=y 18CONFIG_DISPLAY_BOARDINFO_LATE=y
19CONFIG_ENV_IS_NOWHERE=y
20CONFIG_CMD_GREPENV=y 19CONFIG_CMD_GREPENV=y
21CONFIG_CMD_GPT=y 20CONFIG_CMD_GPT=y
22CONFIG_CMD_I2C=y 21CONFIG_CMD_I2C=y
@@ -48,6 +47,5 @@ CONFIG_USB=y
48CONFIG_DM_USB=y 47CONFIG_DM_USB=y
49CONFIG_USB_XHCI_HCD=y 48CONFIG_USB_XHCI_HCD=y
50CONFIG_USB_XHCI_DWC3=y 49CONFIG_USB_XHCI_DWC3=y
51CONFIG_USB_STORAGE=y
52CONFIG_RSA=y 50CONFIG_RSA=y
53CONFIG_RSA_SOFTWARE_EXP=y 51CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index 2d6002c6e5..08b3692f97 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -48,4 +48,3 @@ CONFIG_USB=y
48CONFIG_DM_USB=y 48CONFIG_DM_USB=y
49CONFIG_USB_XHCI_HCD=y 49CONFIG_USB_XHCI_HCD=y
50CONFIG_USB_XHCI_DWC3=y 50CONFIG_USB_XHCI_DWC3=y
51CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 57b5d93870..3a1121c72d 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -60,4 +60,3 @@ CONFIG_USB=y
60CONFIG_DM_USB=y 60CONFIG_DM_USB=y
61CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 62CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index b4423cb2ed..7d0d69017b 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -1,17 +1,17 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_TARGET_LS1012AQDS=y 2CONFIG_TARGET_LS1012AQDS=y
3CONFIG_SECURE_BOOT=y
4CONFIG_SYS_TEXT_BASE=0x82000000 3CONFIG_SYS_TEXT_BASE=0x82000000
5CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y 4CONFIG_SECURE_BOOT=y
6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
7CONFIG_QSPI_AHB_INIT=y 5CONFIG_QSPI_AHB_INIT=y
6CONFIG_TFABOOT=y
7CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
8CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
8CONFIG_DISTRO_DEFAULTS=y 9CONFIG_DISTRO_DEFAULTS=y
9CONFIG_NR_DRAM_BANKS=2 10CONFIG_NR_DRAM_BANKS=2
10# CONFIG_SYS_MALLOC_F is not set 11# CONFIG_SYS_MALLOC_F is not set
11CONFIG_FIT_VERBOSE=y 12CONFIG_FIT_VERBOSE=y
12CONFIG_OF_BOARD_SETUP=y 13CONFIG_OF_BOARD_SETUP=y
13CONFIG_OF_STDOUT_VIA_ALIAS=y 14CONFIG_OF_STDOUT_VIA_ALIAS=y
14CONFIG_TFABOOT=y
15CONFIG_BOOTDELAY=10 15CONFIG_BOOTDELAY=10
16CONFIG_USE_BOOTARGS=y 16CONFIG_USE_BOOTARGS=y
17CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" 17CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
@@ -33,11 +33,9 @@ CONFIG_CMD_CACHE=y
33CONFIG_CMD_DATE=y 33CONFIG_CMD_DATE=y
34CONFIG_OF_CONTROL=y 34CONFIG_OF_CONTROL=y
35CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" 35CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
36CONFIG_ENV_IS_NOWHERE=y
37CONFIG_NET_RANDOM_ETHADDR=y 36CONFIG_NET_RANDOM_ETHADDR=y
38CONFIG_DM=y 37CONFIG_DM=y
39CONFIG_SCSI_AHCI=y 38CONFIG_SCSI_AHCI=y
40CONFIG_SATA_CEVA=y
41CONFIG_DM_MMC=y 39CONFIG_DM_MMC=y
42CONFIG_FSL_ESDHC=y 40CONFIG_FSL_ESDHC=y
43CONFIG_DM_SPI_FLASH=y 41CONFIG_DM_SPI_FLASH=y
@@ -60,6 +58,5 @@ CONFIG_USB=y
60CONFIG_DM_USB=y 58CONFIG_DM_USB=y
61CONFIG_USB_XHCI_HCD=y 59CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 60CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_STORAGE=y
64CONFIG_RSA=y 61CONFIG_RSA=y
65CONFIG_RSA_SOFTWARE_EXP=y 62CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 78a447922f..30f23430ac 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -60,4 +60,3 @@ CONFIG_USB=y
60CONFIG_DM_USB=y 60CONFIG_DM_USB=y
61CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 62CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 3e5ed6362a..f3c1b569c2 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -53,6 +53,5 @@ CONFIG_USB=y
53CONFIG_DM_USB=y 53CONFIG_DM_USB=y
54CONFIG_USB_XHCI_HCD=y 54CONFIG_USB_XHCI_HCD=y
55CONFIG_USB_XHCI_DWC3=y 55CONFIG_USB_XHCI_DWC3=y
56CONFIG_USB_STORAGE=y
57CONFIG_RSA=y 56CONFIG_RSA=y
58CONFIG_RSA_SOFTWARE_EXP=y 57CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 2d0cfca9f9..8ca4c8d735 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -54,4 +54,3 @@ CONFIG_USB=y
54CONFIG_DM_USB=y 54CONFIG_DM_USB=y
55CONFIG_USB_XHCI_HCD=y 55CONFIG_USB_XHCI_HCD=y
56CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
57CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 1cb811f9fa..5e524e74c1 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -1,10 +1,11 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_TARGET_LS1012ARDB=y 2CONFIG_TARGET_LS1012ARDB=y
3CONFIG_SYS_TEXT_BASE=0x82000000 3CONFIG_SYS_TEXT_BASE=0x82000000
4CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
5CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
6CONFIG_SECURE_BOOT=y 4CONFIG_SECURE_BOOT=y
7CONFIG_QSPI_AHB_INIT=y 5CONFIG_QSPI_AHB_INIT=y
6CONFIG_TFABOOT=y
7CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
8CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
8CONFIG_AHCI=y 9CONFIG_AHCI=y
9CONFIG_DISTRO_DEFAULTS=y 10CONFIG_DISTRO_DEFAULTS=y
10CONFIG_NR_DRAM_BANKS=2 11CONFIG_NR_DRAM_BANKS=2
@@ -12,7 +13,6 @@ CONFIG_NR_DRAM_BANKS=2
12CONFIG_FIT_VERBOSE=y 13CONFIG_FIT_VERBOSE=y
13CONFIG_OF_BOARD_SETUP=y 14CONFIG_OF_BOARD_SETUP=y
14CONFIG_OF_STDOUT_VIA_ALIAS=y 15CONFIG_OF_STDOUT_VIA_ALIAS=y
15CONFIG_TFABOOT=y
16CONFIG_BOOTDELAY=10 16CONFIG_BOOTDELAY=10
17CONFIG_USE_BOOTARGS=y 17CONFIG_USE_BOOTARGS=y
18CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" 18CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
@@ -37,7 +37,6 @@ CONFIG_SATA_CEVA=y
37CONFIG_DM_MMC=y 37CONFIG_DM_MMC=y
38CONFIG_FSL_ESDHC=y 38CONFIG_FSL_ESDHC=y
39CONFIG_DM_SPI_FLASH=y 39CONFIG_DM_SPI_FLASH=y
40CONFIG_ENV_IS_NOWHERE=y
41CONFIG_SPI_FLASH=y 40CONFIG_SPI_FLASH=y
42# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 41# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
43CONFIG_E1000=y 42CONFIG_E1000=y
@@ -54,6 +53,5 @@ CONFIG_USB=y
54CONFIG_DM_USB=y 53CONFIG_DM_USB=y
55CONFIG_USB_XHCI_HCD=y 54CONFIG_USB_XHCI_HCD=y
56CONFIG_USB_XHCI_DWC3=y 55CONFIG_USB_XHCI_DWC3=y
57CONFIG_USB_STORAGE=y
58CONFIG_RSA=y 56CONFIG_RSA=y
59CONFIG_RSA_SOFTWARE_EXP=y 57CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index 557bf6c341..aae8df9709 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -54,4 +54,3 @@ CONFIG_USB=y
54CONFIG_DM_USB=y 54CONFIG_DM_USB=y
55CONFIG_USB_XHCI_HCD=y 55CONFIG_USB_XHCI_HCD=y
56CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
57CONFIG_USB_STORAGE=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 97ffa21228..e3cd75563e 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -48,7 +48,6 @@ CONFIG_USB=y
48CONFIG_DM_USB=y 48CONFIG_DM_USB=y
49CONFIG_USB_XHCI_HCD=y 49CONFIG_USB_XHCI_HCD=y
50CONFIG_USB_XHCI_DWC3=y 50CONFIG_USB_XHCI_DWC3=y
51CONFIG_USB_STORAGE=y
52CONFIG_VIDEO_FSL_DCU_FB=y 51CONFIG_VIDEO_FSL_DCU_FB=y
53CONFIG_VIDEO=y 52CONFIG_VIDEO=y
54# CONFIG_VIDEO_SW_CURSOR is not set 53# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 582f52151f..41688263d1 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -53,7 +53,6 @@ CONFIG_USB=y
53CONFIG_DM_USB=y 53CONFIG_DM_USB=y
54CONFIG_USB_XHCI_HCD=y 54CONFIG_USB_XHCI_HCD=y
55CONFIG_USB_XHCI_DWC3=y 55CONFIG_USB_XHCI_DWC3=y
56CONFIG_USB_STORAGE=y
57CONFIG_VIDEO_FSL_DCU_FB=y 56CONFIG_VIDEO_FSL_DCU_FB=y
58CONFIG_VIDEO=y 57CONFIG_VIDEO=y
59# CONFIG_VIDEO_SW_CURSOR is not set 58# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index a567c07062..347c664e60 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -51,7 +51,6 @@ CONFIG_USB=y
51CONFIG_DM_USB=y 51CONFIG_DM_USB=y
52CONFIG_USB_XHCI_HCD=y 52CONFIG_USB_XHCI_HCD=y
53CONFIG_USB_XHCI_DWC3=y 53CONFIG_USB_XHCI_DWC3=y
54CONFIG_USB_STORAGE=y
55CONFIG_VIDEO_FSL_DCU_FB=y 54CONFIG_VIDEO_FSL_DCU_FB=y
56CONFIG_VIDEO=y 55CONFIG_VIDEO=y
57# CONFIG_VIDEO_SW_CURSOR is not set 56# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 1bcf56aa5d..edf74eef48 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -54,7 +54,6 @@ CONFIG_USB=y
54CONFIG_DM_USB=y 54CONFIG_DM_USB=y
55CONFIG_USB_XHCI_HCD=y 55CONFIG_USB_XHCI_HCD=y
56CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
57CONFIG_USB_STORAGE=y
58CONFIG_VIDEO_FSL_DCU_FB=y 57CONFIG_VIDEO_FSL_DCU_FB=y
59CONFIG_VIDEO=y 58CONFIG_VIDEO=y
60# CONFIG_VIDEO_SW_CURSOR is not set 59# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 44e59d2acc..42cf38b347 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -62,7 +62,6 @@ CONFIG_USB=y
62CONFIG_DM_USB=y 62CONFIG_DM_USB=y
63CONFIG_USB_XHCI_HCD=y 63CONFIG_USB_XHCI_HCD=y
64CONFIG_USB_XHCI_DWC3=y 64CONFIG_USB_XHCI_DWC3=y
65CONFIG_USB_STORAGE=y
66CONFIG_VIDEO_FSL_DCU_FB=y 65CONFIG_VIDEO_FSL_DCU_FB=y
67CONFIG_VIDEO=y 66CONFIG_VIDEO=y
68# CONFIG_VIDEO_SW_CURSOR is not set 67# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 4824a83fb4..c69d1dd75a 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -61,7 +61,6 @@ CONFIG_USB=y
61CONFIG_DM_USB=y 61CONFIG_DM_USB=y
62CONFIG_USB_XHCI_HCD=y 62CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
64CONFIG_USB_STORAGE=y
65CONFIG_VIDEO_FSL_DCU_FB=y 64CONFIG_VIDEO_FSL_DCU_FB=y
66CONFIG_VIDEO=y 65CONFIG_VIDEO=y
67# CONFIG_VIDEO_SW_CURSOR is not set 66# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 4b01bc42f0..c59e493490 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -64,7 +64,6 @@ CONFIG_USB=y
64CONFIG_DM_USB=y 64CONFIG_DM_USB=y
65CONFIG_USB_XHCI_HCD=y 65CONFIG_USB_XHCI_HCD=y
66CONFIG_USB_XHCI_DWC3=y 66CONFIG_USB_XHCI_DWC3=y
67CONFIG_USB_STORAGE=y
68CONFIG_VIDEO_FSL_DCU_FB=y 67CONFIG_VIDEO_FSL_DCU_FB=y
69CONFIG_VIDEO=y 68CONFIG_VIDEO=y
70# CONFIG_VIDEO_SW_CURSOR is not set 69# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 7db5d2d43a..8bde83deda 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -53,4 +53,3 @@ CONFIG_USB=y
53CONFIG_DM_USB=y 53CONFIG_DM_USB=y
54CONFIG_USB_XHCI_HCD=y 54CONFIG_USB_XHCI_HCD=y
55CONFIG_USB_XHCI_DWC3=y 55CONFIG_USB_XHCI_DWC3=y
56CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 65f61f43d1..79448129bd 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -52,4 +52,3 @@ CONFIG_USB=y
52CONFIG_DM_USB=y 52CONFIG_DM_USB=y
53CONFIG_USB_XHCI_HCD=y 53CONFIG_USB_XHCI_HCD=y
54CONFIG_USB_XHCI_DWC3=y 54CONFIG_USB_XHCI_DWC3=y
55CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 06b266aa7d..ada225c3b6 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -65,4 +65,3 @@ CONFIG_USB=y
65CONFIG_DM_USB=y 65CONFIG_DM_USB=y
66CONFIG_USB_XHCI_HCD=y 66CONFIG_USB_XHCI_HCD=y
67CONFIG_USB_XHCI_DWC3=y 67CONFIG_USB_XHCI_DWC3=y
68CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 318152a391..e86d4196b5 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -51,4 +51,3 @@ CONFIG_USB=y
51CONFIG_DM_USB=y 51CONFIG_DM_USB=y
52CONFIG_USB_XHCI_HCD=y 52CONFIG_USB_XHCI_HCD=y
53CONFIG_USB_XHCI_DWC3=y 53CONFIG_USB_XHCI_DWC3=y
54CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index c2024cf7c8..d948981080 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -46,4 +46,3 @@ CONFIG_USB=y
46CONFIG_DM_USB=y 46CONFIG_DM_USB=y
47CONFIG_USB_XHCI_HCD=y 47CONFIG_USB_XHCI_HCD=y
48CONFIG_USB_XHCI_DWC3=y 48CONFIG_USB_XHCI_DWC3=y
49CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index d547fefcda..afa91e8b3a 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -65,4 +65,3 @@ CONFIG_USB=y
65CONFIG_DM_USB=y 65CONFIG_DM_USB=y
66CONFIG_USB_XHCI_HCD=y 66CONFIG_USB_XHCI_HCD=y
67CONFIG_USB_XHCI_DWC3=y 67CONFIG_USB_XHCI_DWC3=y
68CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 850b1dc142..310cb2319a 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -59,4 +59,3 @@ CONFIG_USB=y
59CONFIG_DM_USB=y 59CONFIG_DM_USB=y
60CONFIG_USB_XHCI_HCD=y 60CONFIG_USB_XHCI_HCD=y
61CONFIG_USB_XHCI_DWC3=y 61CONFIG_USB_XHCI_DWC3=y
62CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index c375e1b09c..ce6f1ef86f 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -1,15 +1,15 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_TARGET_LS1043AQDS=y 2CONFIG_TARGET_LS1043AQDS=y
3CONFIG_SYS_TEXT_BASE=0x82000000 3CONFIG_SYS_TEXT_BASE=0x82000000
4CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
5CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
6CONFIG_SECURE_BOOT=y 4CONFIG_SECURE_BOOT=y
5CONFIG_TFABOOT=y
6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
7CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
7CONFIG_DISTRO_DEFAULTS=y 8CONFIG_DISTRO_DEFAULTS=y
8CONFIG_NR_DRAM_BANKS=2 9CONFIG_NR_DRAM_BANKS=2
9CONFIG_FIT_VERBOSE=y 10CONFIG_FIT_VERBOSE=y
10CONFIG_OF_BOARD_SETUP=y 11CONFIG_OF_BOARD_SETUP=y
11CONFIG_BOOTDELAY=10 12CONFIG_BOOTDELAY=10
12CONFIG_TFABOOT=y
13CONFIG_USE_BOOTARGS=y 13CONFIG_USE_BOOTARGS=y
14CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" 14CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
15# CONFIG_USE_BOOTCOMMAND is not set 15# CONFIG_USE_BOOTCOMMAND is not set
@@ -30,10 +30,7 @@ CONFIG_MP=y
30CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" 30CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
31CONFIG_OF_CONTROL=y 31CONFIG_OF_CONTROL=y
32CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" 32CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
33CONFIG_ENV_IS_NOWHERE=y
34CONFIG_DM=y 33CONFIG_DM=y
35CONFIG_SATA_CEVA=y
36CONFIG_FSL_CAAM=y
37CONFIG_DM_MMC=y 34CONFIG_DM_MMC=y
38CONFIG_FSL_ESDHC=y 35CONFIG_FSL_ESDHC=y
39CONFIG_MTD_NOR_FLASH=y 36CONFIG_MTD_NOR_FLASH=y
@@ -55,7 +52,6 @@ CONFIG_USB=y
55CONFIG_DM_USB=y 52CONFIG_DM_USB=y
56CONFIG_USB_XHCI_HCD=y 53CONFIG_USB_XHCI_HCD=y
57CONFIG_USB_XHCI_DWC3=y 54CONFIG_USB_XHCI_DWC3=y
58CONFIG_USB_STORAGE=y
59CONFIG_RSA=y 55CONFIG_RSA=y
60CONFIG_SPL_RSA=y 56CONFIG_SPL_RSA=y
61CONFIG_RSA_SOFTWARE_EXP=y 57CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 6fa0418044..ee30589e1d 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -33,7 +33,6 @@ CONFIG_ENV_IS_IN_FLASH=y
33CONFIG_ENV_IS_IN_NAND=y 33CONFIG_ENV_IS_IN_NAND=y
34CONFIG_ENV_IS_IN_SPI_FLASH=y 34CONFIG_ENV_IS_IN_SPI_FLASH=y
35CONFIG_DM=y 35CONFIG_DM=y
36CONFIG_SATA_CEVA=y
37CONFIG_FSL_CAAM=y 36CONFIG_FSL_CAAM=y
38CONFIG_DM_MMC=y 37CONFIG_DM_MMC=y
39CONFIG_FSL_ESDHC=y 38CONFIG_FSL_ESDHC=y
@@ -56,4 +55,3 @@ CONFIG_USB=y
56CONFIG_DM_USB=y 55CONFIG_DM_USB=y
57CONFIG_USB_XHCI_HCD=y 56CONFIG_USB_XHCI_HCD=y
58CONFIG_USB_XHCI_DWC3=y 57CONFIG_USB_XHCI_DWC3=y
59CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 41df0b9fbf..0a51540674 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -45,7 +45,6 @@ CONFIG_USB=y
45CONFIG_DM_USB=y 45CONFIG_DM_USB=y
46CONFIG_USB_XHCI_HCD=y 46CONFIG_USB_XHCI_HCD=y
47CONFIG_USB_XHCI_DWC3=y 47CONFIG_USB_XHCI_DWC3=y
48CONFIG_USB_STORAGE=y
49CONFIG_RSA=y 48CONFIG_RSA=y
50CONFIG_SPL_RSA=y 49CONFIG_SPL_RSA=y
51CONFIG_RSA_SOFTWARE_EXP=y 50CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 7541fad3db..1462a44369 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -46,4 +46,3 @@ CONFIG_USB=y
46CONFIG_DM_USB=y 46CONFIG_DM_USB=y
47CONFIG_USB_XHCI_HCD=y 47CONFIG_USB_XHCI_HCD=y
48CONFIG_USB_XHCI_DWC3=y 48CONFIG_USB_XHCI_DWC3=y
49CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 2879f45d56..8a45f7c8d0 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -63,6 +63,5 @@ CONFIG_USB=y
63CONFIG_DM_USB=y 63CONFIG_DM_USB=y
64CONFIG_USB_XHCI_HCD=y 64CONFIG_USB_XHCI_HCD=y
65CONFIG_USB_XHCI_DWC3=y 65CONFIG_USB_XHCI_DWC3=y
66CONFIG_USB_STORAGE=y
67CONFIG_RSA=y 66CONFIG_RSA=y
68CONFIG_SPL_RSA=y 67CONFIG_SPL_RSA=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 5a23e3cfff..509f2f1e3c 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -63,4 +63,3 @@ CONFIG_USB=y
63CONFIG_DM_USB=y 63CONFIG_DM_USB=y
64CONFIG_USB_XHCI_HCD=y 64CONFIG_USB_XHCI_HCD=y
65CONFIG_USB_XHCI_DWC3=y 65CONFIG_USB_XHCI_DWC3=y
66CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 3c19694456..33ce8acd08 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -61,6 +61,5 @@ CONFIG_USB=y
61CONFIG_DM_USB=y 61CONFIG_DM_USB=y
62CONFIG_USB_XHCI_HCD=y 62CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
64CONFIG_USB_STORAGE=y
65CONFIG_RSA=y 64CONFIG_RSA=y
66CONFIG_SPL_RSA=y 65CONFIG_SPL_RSA=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 144e48b885..91dac81e8b 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -61,4 +61,3 @@ CONFIG_USB=y
61CONFIG_DM_USB=y 61CONFIG_DM_USB=y
62CONFIG_USB_XHCI_HCD=y 62CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
64CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 0ad9db7736..0af2594205 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -1,15 +1,15 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_TARGET_LS1043ARDB=y 2CONFIG_TARGET_LS1043ARDB=y
3CONFIG_SYS_TEXT_BASE=0x82000000 3CONFIG_SYS_TEXT_BASE=0x82000000
4CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
5CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
6CONFIG_SECURE_BOOT=y 4CONFIG_SECURE_BOOT=y
5CONFIG_TFABOOT=y
6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
7CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
7CONFIG_DISTRO_DEFAULTS=y 8CONFIG_DISTRO_DEFAULTS=y
8CONFIG_NR_DRAM_BANKS=2 9CONFIG_NR_DRAM_BANKS=2
9CONFIG_FIT_VERBOSE=y 10CONFIG_FIT_VERBOSE=y
10CONFIG_OF_BOARD_SETUP=y 11CONFIG_OF_BOARD_SETUP=y
11CONFIG_BOOTDELAY=10 12CONFIG_BOOTDELAY=10
12CONFIG_TFABOOT=y
13CONFIG_USE_BOOTARGS=y 13CONFIG_USE_BOOTARGS=y
14CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" 14CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
15CONFIG_MISC_INIT_R=y 15CONFIG_MISC_INIT_R=y
@@ -28,7 +28,6 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
28CONFIG_DM=y 28CONFIG_DM=y
29CONFIG_DM_MMC=y 29CONFIG_DM_MMC=y
30CONFIG_FSL_ESDHC=y 30CONFIG_FSL_ESDHC=y
31CONFIG_FSL_CAAM=y
32CONFIG_MTD_NOR_FLASH=y 31CONFIG_MTD_NOR_FLASH=y
33CONFIG_FLASH_CFI_DRIVER=y 32CONFIG_FLASH_CFI_DRIVER=y
34CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y 33CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
@@ -37,7 +36,6 @@ CONFIG_SPI_FLASH=y
37CONFIG_PHYLIB=y 36CONFIG_PHYLIB=y
38CONFIG_PHY_GIGE=y 37CONFIG_PHY_GIGE=y
39CONFIG_E1000=y 38CONFIG_E1000=y
40CONFIG_ENV_IS_NOWHERE=y
41CONFIG_PCI=y 39CONFIG_PCI=y
42CONFIG_DM_PCI=y 40CONFIG_DM_PCI=y
43CONFIG_DM_PCI_COMPAT=y 41CONFIG_DM_PCI_COMPAT=y
@@ -49,7 +47,6 @@ CONFIG_USB=y
49CONFIG_DM_USB=y 47CONFIG_DM_USB=y
50CONFIG_USB_XHCI_HCD=y 48CONFIG_USB_XHCI_HCD=y
51CONFIG_USB_XHCI_DWC3=y 49CONFIG_USB_XHCI_DWC3=y
52CONFIG_USB_STORAGE=y
53CONFIG_RSA=y 50CONFIG_RSA=y
54CONFIG_SPL_RSA=y 51CONFIG_SPL_RSA=y
55CONFIG_RSA_SOFTWARE_EXP=y 52CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 662a966ebe..da5beeedc2 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -49,4 +49,3 @@ CONFIG_USB=y
49CONFIG_DM_USB=y 49CONFIG_DM_USB=y
50CONFIG_USB_XHCI_HCD=y 50CONFIG_USB_XHCI_HCD=y
51CONFIG_USB_XHCI_DWC3=y 51CONFIG_USB_XHCI_DWC3=y
52CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index 8f61afa5fd..ae05dd150b 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -51,5 +51,4 @@ CONFIG_USB=y
51CONFIG_DM_USB=y 51CONFIG_DM_USB=y
52CONFIG_USB_XHCI_HCD=y 52CONFIG_USB_XHCI_HCD=y
53CONFIG_USB_XHCI_DWC3=y 53CONFIG_USB_XHCI_DWC3=y
54CONFIG_USB_STORAGE=y
55CONFIG_RSA=y 54CONFIG_RSA=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index 7edb0ad384..0a8d51e43d 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -54,4 +54,3 @@ CONFIG_USB=y
54CONFIG_DM_USB=y 54CONFIG_DM_USB=y
55CONFIG_USB_XHCI_HCD=y 55CONFIG_USB_XHCI_HCD=y
56CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
57CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index d8a5b0e95e..9e11db7d7f 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -59,4 +59,3 @@ CONFIG_USB=y
59CONFIG_DM_USB=y 59CONFIG_DM_USB=y
60CONFIG_USB_XHCI_HCD=y 60CONFIG_USB_XHCI_HCD=y
61CONFIG_USB_XHCI_DWC3=y 61CONFIG_USB_XHCI_DWC3=y
62CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index ab1b549a27..a6bbf106e1 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -49,4 +49,3 @@ CONFIG_USB=y
49CONFIG_DM_USB=y 49CONFIG_DM_USB=y
50CONFIG_USB_XHCI_HCD=y 50CONFIG_USB_XHCI_HCD=y
51CONFIG_USB_XHCI_DWC3=y 51CONFIG_USB_XHCI_DWC3=y
52CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index ff9b0367ae..edf915fdd6 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -68,4 +68,3 @@ CONFIG_USB=y
68CONFIG_DM_USB=y 68CONFIG_DM_USB=y
69CONFIG_USB_XHCI_HCD=y 69CONFIG_USB_XHCI_HCD=y
70CONFIG_USB_XHCI_DWC3=y 70CONFIG_USB_XHCI_DWC3=y
71CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index ab53eb7689..afb76d6900 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -64,4 +64,3 @@ CONFIG_USB=y
64CONFIG_DM_USB=y 64CONFIG_DM_USB=y
65CONFIG_USB_XHCI_HCD=y 65CONFIG_USB_XHCI_HCD=y
66CONFIG_USB_XHCI_DWC3=y 66CONFIG_USB_XHCI_DWC3=y
67CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index e554d2d083..f57dda591a 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -1,15 +1,15 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_TARGET_LS1046AQDS=y 2CONFIG_TARGET_LS1046AQDS=y
3CONFIG_SYS_TEXT_BASE=0x82000000 3CONFIG_SYS_TEXT_BASE=0x82000000
4CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
5CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
6CONFIG_SECURE_BOOT=y 4CONFIG_SECURE_BOOT=y
5CONFIG_TFABOOT=y
6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
7CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
8CONFIG_AHCI=y
7CONFIG_DISTRO_DEFAULTS=y 9CONFIG_DISTRO_DEFAULTS=y
8CONFIG_NR_DRAM_BANKS=2 10CONFIG_NR_DRAM_BANKS=2
9CONFIG_FIT=y
10CONFIG_FIT_VERBOSE=y 11CONFIG_FIT_VERBOSE=y
11CONFIG_OF_BOARD_SETUP=y 12CONFIG_OF_BOARD_SETUP=y
12CONFIG_TFABOOT=y
13CONFIG_BOOTDELAY=10 13CONFIG_BOOTDELAY=10
14CONFIG_USE_BOOTARGS=y 14CONFIG_USE_BOOTARGS=y
15CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" 15CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
@@ -32,9 +32,8 @@ CONFIG_MP=y
32CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" 32CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
33CONFIG_OF_CONTROL=y 33CONFIG_OF_CONTROL=y
34CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" 34CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
35CONFIG_ENV_IS_NOWHERE=y
36CONFIG_DM=y 35CONFIG_DM=y
37CONFIG_FSL_CAAM=y 36CONFIG_SATA_CEVA=y
38CONFIG_DM_MMC=y 37CONFIG_DM_MMC=y
39CONFIG_FSL_ESDHC=y 38CONFIG_FSL_ESDHC=y
40CONFIG_MTD_NOR_FLASH=y 39CONFIG_MTD_NOR_FLASH=y
@@ -48,6 +47,7 @@ CONFIG_PCI=y
48CONFIG_DM_PCI=y 47CONFIG_DM_PCI=y
49CONFIG_DM_PCI_COMPAT=y 48CONFIG_DM_PCI_COMPAT=y
50CONFIG_PCIE_LAYERSCAPE=y 49CONFIG_PCIE_LAYERSCAPE=y
50CONFIG_DM_SCSI=y
51CONFIG_SYS_NS16550=y 51CONFIG_SYS_NS16550=y
52CONFIG_SPI=y 52CONFIG_SPI=y
53CONFIG_DM_SPI=y 53CONFIG_DM_SPI=y
@@ -56,10 +56,4 @@ CONFIG_USB=y
56CONFIG_DM_USB=y 56CONFIG_DM_USB=y
57CONFIG_USB_XHCI_HCD=y 57CONFIG_USB_XHCI_HCD=y
58CONFIG_USB_XHCI_DWC3=y 58CONFIG_USB_XHCI_DWC3=y
59CONFIG_USB_STORAGE=y
60CONFIG_RSA=y 59CONFIG_RSA=y
61CONFIG_DM_SCSI=y
62CONFIG_SATA_CEVA=y
63CONFIG_SCSI_AHCI=y
64CONFIG_SCSI=y
65CONFIG_AHCI=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 44c5ca5b30..48d78b4739 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000
4CONFIG_TFABOOT=y 4CONFIG_TFABOOT=y
5CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y 5CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
6CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y 6CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
7CONFIG_AHCI=y
7CONFIG_DISTRO_DEFAULTS=y 8CONFIG_DISTRO_DEFAULTS=y
8CONFIG_NR_DRAM_BANKS=2 9CONFIG_NR_DRAM_BANKS=2
9CONFIG_FIT_VERBOSE=y 10CONFIG_FIT_VERBOSE=y
@@ -34,6 +35,7 @@ CONFIG_ENV_IS_IN_FLASH=y
34CONFIG_ENV_IS_IN_NAND=y 35CONFIG_ENV_IS_IN_NAND=y
35CONFIG_ENV_IS_IN_SPI_FLASH=y 36CONFIG_ENV_IS_IN_SPI_FLASH=y
36CONFIG_DM=y 37CONFIG_DM=y
38CONFIG_SATA_CEVA=y
37CONFIG_FSL_CAAM=y 39CONFIG_FSL_CAAM=y
38CONFIG_DM_MMC=y 40CONFIG_DM_MMC=y
39CONFIG_FSL_ESDHC=y 41CONFIG_FSL_ESDHC=y
@@ -48,6 +50,7 @@ CONFIG_PCI=y
48CONFIG_DM_PCI=y 50CONFIG_DM_PCI=y
49CONFIG_DM_PCI_COMPAT=y 51CONFIG_DM_PCI_COMPAT=y
50CONFIG_PCIE_LAYERSCAPE=y 52CONFIG_PCIE_LAYERSCAPE=y
53CONFIG_DM_SCSI=y
51CONFIG_SYS_NS16550=y 54CONFIG_SYS_NS16550=y
52CONFIG_SPI=y 55CONFIG_SPI=y
53CONFIG_DM_SPI=y 56CONFIG_DM_SPI=y
@@ -57,9 +60,3 @@ CONFIG_USB=y
57CONFIG_DM_USB=y 60CONFIG_DM_USB=y
58CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
59CONFIG_USB_XHCI_DWC3=y 62CONFIG_USB_XHCI_DWC3=y
60CONFIG_USB_STORAGE=y
61CONFIG_DM_SCSI=y
62CONFIG_SATA_CEVA=y
63CONFIG_SCSI_AHCI=y
64CONFIG_SCSI=y
65CONFIG_AHCI=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index f7a35c7e19..181fa61422 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -60,4 +60,3 @@ CONFIG_USB=y
60CONFIG_DM_USB=y 60CONFIG_DM_USB=y
61CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 62CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 80f52807e1..d8eb7b7ede 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -45,5 +45,4 @@ CONFIG_USB=y
45CONFIG_DM_USB=y 45CONFIG_DM_USB=y
46CONFIG_USB_XHCI_HCD=y 46CONFIG_USB_XHCI_HCD=y
47CONFIG_USB_XHCI_DWC3=y 47CONFIG_USB_XHCI_DWC3=y
48CONFIG_USB_STORAGE=y
49CONFIG_RSA=y 48CONFIG_RSA=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index f7cd33d8af..0a45653b98 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -62,5 +62,4 @@ CONFIG_USB=y
62CONFIG_DM_USB=y 62CONFIG_DM_USB=y
63CONFIG_USB_XHCI_HCD=y 63CONFIG_USB_XHCI_HCD=y
64CONFIG_USB_XHCI_DWC3=y 64CONFIG_USB_XHCI_DWC3=y
65CONFIG_USB_STORAGE=y
66CONFIG_SPL_GZIP=y 65CONFIG_SPL_GZIP=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 24a08b6e01..80c42c5bad 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -59,6 +59,5 @@ CONFIG_USB=y
59CONFIG_DM_USB=y 59CONFIG_DM_USB=y
60CONFIG_USB_XHCI_HCD=y 60CONFIG_USB_XHCI_HCD=y
61CONFIG_USB_XHCI_DWC3=y 61CONFIG_USB_XHCI_DWC3=y
62CONFIG_USB_STORAGE=y
63CONFIG_RSA=y 62CONFIG_RSA=y
64CONFIG_SPL_RSA=y 63CONFIG_SPL_RSA=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 61da6ae517..a1bd39b17c 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -59,4 +59,3 @@ CONFIG_USB=y
59CONFIG_DM_USB=y 59CONFIG_DM_USB=y
60CONFIG_USB_XHCI_HCD=y 60CONFIG_USB_XHCI_HCD=y
61CONFIG_USB_XHCI_DWC3=y 61CONFIG_USB_XHCI_DWC3=y
62CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index bdd87481b8..d570c6de05 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -2,14 +2,14 @@ CONFIG_ARM=y
2CONFIG_TARGET_LS1046ARDB=y 2CONFIG_TARGET_LS1046ARDB=y
3CONFIG_SYS_TEXT_BASE=0x82000000 3CONFIG_SYS_TEXT_BASE=0x82000000
4CONFIG_SECURE_BOOT=y 4CONFIG_SECURE_BOOT=y
5CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
7CONFIG_QSPI_AHB_INIT=y 5CONFIG_QSPI_AHB_INIT=y
6CONFIG_TFABOOT=y
7CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
8CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
8CONFIG_DISTRO_DEFAULTS=y 9CONFIG_DISTRO_DEFAULTS=y
9CONFIG_NR_DRAM_BANKS=2 10CONFIG_NR_DRAM_BANKS=2
10CONFIG_FIT_VERBOSE=y 11CONFIG_FIT_VERBOSE=y
11CONFIG_OF_BOARD_SETUP=y 12CONFIG_OF_BOARD_SETUP=y
12CONFIG_TFABOOT=y
13CONFIG_BOOTDELAY=10 13CONFIG_BOOTDELAY=10
14CONFIG_USE_BOOTARGS=y 14CONFIG_USE_BOOTARGS=y
15CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" 15CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
@@ -27,7 +27,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel
27CONFIG_OF_CONTROL=y 27CONFIG_OF_CONTROL=y
28CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" 28CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
29CONFIG_DM=y 29CONFIG_DM=y
30CONFIG_FSL_CAAM=y 30CONFIG_DM_MMC=y
31CONFIG_FSL_ESDHC=y 31CONFIG_FSL_ESDHC=y
32CONFIG_SPI_FLASH=y 32CONFIG_SPI_FLASH=y
33# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 33# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
@@ -41,13 +41,9 @@ CONFIG_PCIE_LAYERSCAPE=y
41CONFIG_SYS_NS16550=y 41CONFIG_SYS_NS16550=y
42CONFIG_SPI=y 42CONFIG_SPI=y
43CONFIG_DM_SPI=y 43CONFIG_DM_SPI=y
44CONFIG_ENV_IS_NOWHERE=y
45CONFIG_USB=y
46CONFIG_FSL_QSPI=y 44CONFIG_FSL_QSPI=y
45CONFIG_USB=y
47CONFIG_DM_USB=y 46CONFIG_DM_USB=y
48CONFIG_USB_XHCI_HCD=y 47CONFIG_USB_XHCI_HCD=y
49CONFIG_USB_XHCI_DWC3=y 48CONFIG_USB_XHCI_DWC3=y
50CONFIG_USB_STORAGE=y
51CONFIG_RSA=y 49CONFIG_RSA=y
52CONFIG_BLK=y
53CONFIG_DM_MMC=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index d6595eb246..c5d6935b55 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -5,6 +5,7 @@ CONFIG_QSPI_AHB_INIT=y
5CONFIG_TFABOOT=y 5CONFIG_TFABOOT=y
6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y 6CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
7CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y 7CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
8CONFIG_AHCI=y
8CONFIG_DISTRO_DEFAULTS=y 9CONFIG_DISTRO_DEFAULTS=y
9CONFIG_NR_DRAM_BANKS=2 10CONFIG_NR_DRAM_BANKS=2
10CONFIG_FIT_VERBOSE=y 11CONFIG_FIT_VERBOSE=y
@@ -27,7 +28,9 @@ CONFIG_OF_CONTROL=y
27CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" 28CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
28CONFIG_ENV_IS_IN_SPI_FLASH=y 29CONFIG_ENV_IS_IN_SPI_FLASH=y
29CONFIG_DM=y 30CONFIG_DM=y
31CONFIG_SATA_CEVA=y
30CONFIG_FSL_CAAM=y 32CONFIG_FSL_CAAM=y
33CONFIG_DM_MMC=y
31CONFIG_FSL_ESDHC=y 34CONFIG_FSL_ESDHC=y
32CONFIG_SPI_FLASH=y 35CONFIG_SPI_FLASH=y
33# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 36# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
@@ -38,6 +41,7 @@ CONFIG_PCI=y
38CONFIG_DM_PCI=y 41CONFIG_DM_PCI=y
39CONFIG_DM_PCI_COMPAT=y 42CONFIG_DM_PCI_COMPAT=y
40CONFIG_PCIE_LAYERSCAPE=y 43CONFIG_PCIE_LAYERSCAPE=y
44CONFIG_DM_SCSI=y
41CONFIG_SYS_NS16550=y 45CONFIG_SYS_NS16550=y
42CONFIG_SPI=y 46CONFIG_SPI=y
43CONFIG_DM_SPI=y 47CONFIG_DM_SPI=y
@@ -46,11 +50,3 @@ CONFIG_USB=y
46CONFIG_DM_USB=y 50CONFIG_DM_USB=y
47CONFIG_USB_XHCI_HCD=y 51CONFIG_USB_XHCI_HCD=y
48CONFIG_USB_XHCI_DWC3=y 52CONFIG_USB_XHCI_DWC3=y
49CONFIG_USB_STORAGE=y
50CONFIG_BLK=y
51CONFIG_DM_MMC=y
52CONFIG_DM_SCSI=y
53CONFIG_SATA_CEVA=y
54CONFIG_SCSI_AHCI=y
55CONFIG_SCSI=y
56CONFIG_AHCI=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index 28850db8b2..731408c13e 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -51,7 +51,6 @@ CONFIG_DM_USB=y
51CONFIG_USB_XHCI_HCD=y 51CONFIG_USB_XHCI_HCD=y
52CONFIG_USB_XHCI_DWC3=y 52CONFIG_USB_XHCI_DWC3=y
53CONFIG_USB_DWC3=y 53CONFIG_USB_DWC3=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_RSA=y 55CONFIG_RSA=y
57CONFIG_RSA_SOFTWARE_EXP=y 56CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 997bafd086..1a3e74600c 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -51,6 +51,5 @@ CONFIG_DM_USB=y
51CONFIG_USB_XHCI_HCD=y 51CONFIG_USB_XHCI_HCD=y
52CONFIG_USB_XHCI_DWC3=y 52CONFIG_USB_XHCI_DWC3=y
53CONFIG_USB_DWC3=y 53CONFIG_USB_DWC3=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 55CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 02f6613a69..d0319a5b63 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -61,5 +61,4 @@ CONFIG_DM_USB=y
61CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 62CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_DWC3=y 63CONFIG_USB_DWC3=y
64CONFIG_USB_STORAGE=y
65CONFIG_USB_GADGET=y 64CONFIG_USB_GADGET=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index 63ac174dda..0cee141cf1 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -52,7 +52,6 @@ CONFIG_DM_USB=y
52CONFIG_USB_XHCI_HCD=y 52CONFIG_USB_XHCI_HCD=y
53CONFIG_USB_XHCI_DWC3=y 53CONFIG_USB_XHCI_DWC3=y
54CONFIG_USB_DWC3=y 54CONFIG_USB_DWC3=y
55CONFIG_USB_STORAGE=y
56CONFIG_USB_GADGET=y 55CONFIG_USB_GADGET=y
57CONFIG_RSA=y 56CONFIG_RSA=y
58CONFIG_RSA_SOFTWARE_EXP=y 57CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index d839e435d5..b53f212125 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -64,6 +64,5 @@ CONFIG_DM_USB=y
64CONFIG_USB_XHCI_HCD=y 64CONFIG_USB_XHCI_HCD=y
65CONFIG_USB_XHCI_DWC3=y 65CONFIG_USB_XHCI_DWC3=y
66CONFIG_USB_DWC3=y 66CONFIG_USB_DWC3=y
67CONFIG_USB_STORAGE=y
68CONFIG_RSA=y 67CONFIG_RSA=y
69CONFIG_SPL_RSA=y 68CONFIG_SPL_RSA=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 53fa08744b..5b0f1d6d03 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -62,5 +62,4 @@ CONFIG_DM_USB=y
62CONFIG_USB_XHCI_HCD=y 62CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
64CONFIG_USB_DWC3=y 64CONFIG_USB_DWC3=y
65CONFIG_USB_STORAGE=y
66CONFIG_USB_GADGET=y 65CONFIG_USB_GADGET=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 6a2a522046..d7c0db6343 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -54,7 +54,6 @@ CONFIG_USB=y
54CONFIG_DM_USB=y 54CONFIG_DM_USB=y
55CONFIG_USB_XHCI_HCD=y 55CONFIG_USB_XHCI_HCD=y
56CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
57CONFIG_USB_STORAGE=y
58CONFIG_RSA=y 57CONFIG_RSA=y
59CONFIG_RSA_SOFTWARE_EXP=y 58CONFIG_RSA_SOFTWARE_EXP=y
60CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 59CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 1f93a8378c..30b506fafc 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -61,5 +61,4 @@ CONFIG_USB=y
61CONFIG_DM_USB=y 61CONFIG_DM_USB=y
62CONFIG_USB_XHCI_HCD=y 62CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
64CONFIG_USB_STORAGE=y
65CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 64CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 32eec9a99d..44a718e855 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -52,5 +52,4 @@ CONFIG_USB=y
52CONFIG_DM_USB=y 52CONFIG_DM_USB=y
53CONFIG_USB_XHCI_HCD=y 53CONFIG_USB_XHCI_HCD=y
54CONFIG_USB_XHCI_DWC3=y 54CONFIG_USB_XHCI_DWC3=y
55CONFIG_USB_STORAGE=y
56CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 55CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index a71913d65c..d6ca28979f 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -59,5 +59,4 @@ CONFIG_USB=y
59CONFIG_DM_USB=y 59CONFIG_DM_USB=y
60CONFIG_USB_XHCI_HCD=y 60CONFIG_USB_XHCI_HCD=y
61CONFIG_USB_XHCI_DWC3=y 61CONFIG_USB_XHCI_DWC3=y
62CONFIG_USB_STORAGE=y
63CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 62CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 8f18d93667..150693b387 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -55,7 +55,6 @@ CONFIG_USB=y
55CONFIG_DM_USB=y 55CONFIG_DM_USB=y
56CONFIG_USB_XHCI_HCD=y 56CONFIG_USB_XHCI_HCD=y
57CONFIG_USB_XHCI_DWC3=y 57CONFIG_USB_XHCI_DWC3=y
58CONFIG_USB_STORAGE=y
59CONFIG_RSA=y 58CONFIG_RSA=y
60CONFIG_RSA_SOFTWARE_EXP=y 59CONFIG_RSA_SOFTWARE_EXP=y
61CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 60CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 061d5cdc2b..e12c3d5a7e 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -60,5 +60,4 @@ CONFIG_USB=y
60CONFIG_DM_USB=y 60CONFIG_DM_USB=y
61CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 62CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_STORAGE=y
64CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 63CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index 323f63b907..39d431aec1 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -52,5 +52,4 @@ CONFIG_USB=y
52CONFIG_DM_USB=y 52CONFIG_DM_USB=y
53CONFIG_USB_XHCI_HCD=y 53CONFIG_USB_XHCI_HCD=y
54CONFIG_USB_XHCI_DWC3=y 54CONFIG_USB_XHCI_DWC3=y
55CONFIG_USB_STORAGE=y
56CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 55CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index e5712db330..d230e64307 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -50,7 +50,6 @@ CONFIG_USB=y
50CONFIG_DM_USB=y 50CONFIG_DM_USB=y
51CONFIG_USB_XHCI_HCD=y 51CONFIG_USB_XHCI_HCD=y
52CONFIG_USB_XHCI_DWC3=y 52CONFIG_USB_XHCI_DWC3=y
53CONFIG_USB_STORAGE=y
54CONFIG_RSA=y 53CONFIG_RSA=y
55CONFIG_RSA_SOFTWARE_EXP=y 54CONFIG_RSA_SOFTWARE_EXP=y
56CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 55CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 5e5d17f6b4..1c9a39d4b0 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -54,5 +54,4 @@ CONFIG_USB=y
54CONFIG_DM_USB=y 54CONFIG_DM_USB=y
55CONFIG_USB_XHCI_HCD=y 55CONFIG_USB_XHCI_HCD=y
56CONFIG_USB_XHCI_DWC3=y 56CONFIG_USB_XHCI_DWC3=y
57CONFIG_USB_STORAGE=y
58CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 57CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 7466b6108d..8563abc135 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -39,4 +39,3 @@ CONFIG_DM_SPI=y
39CONFIG_KIRKWOOD_SPI=y 39CONFIG_KIRKWOOD_SPI=y
40CONFIG_USB=y 40CONFIG_USB=y
41CONFIG_USB_EHCI_HCD=y 41CONFIG_USB_EHCI_HCD=y
42CONFIG_USB_STORAGE=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index f55a69916e..c3636060a7 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -39,4 +39,3 @@ CONFIG_DM_SPI=y
39CONFIG_KIRKWOOD_SPI=y 39CONFIG_KIRKWOOD_SPI=y
40CONFIG_USB=y 40CONFIG_USB=y
41CONFIG_USB_EHCI_HCD=y 41CONFIG_USB_EHCI_HCD=y
42CONFIG_USB_STORAGE=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index dd7aed324f..5555e05030 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
20CONFIG_VERSION_VARIABLE=y 20CONFIG_VERSION_VARIABLE=y
21CONFIG_SPL_BOARD_INIT=y 21CONFIG_SPL_BOARD_INIT=y
22CONFIG_SPL_NAND_SUPPORT=y 22CONFIG_SPL_NAND_SUPPORT=y
23CONFIG_SPL_WATCHDOG_SUPPORT=y
23CONFIG_HUSH_PARSER=y 24CONFIG_HUSH_PARSER=y
24CONFIG_CMD_ASKENV=y 25CONFIG_CMD_ASKENV=y
25CONFIG_CMD_GREPENV=y 26CONFIG_CMD_GREPENV=y
@@ -33,6 +34,7 @@ CONFIG_CMD_DHCP=y
33CONFIG_CMD_MII=y 34CONFIG_CMD_MII=y
34CONFIG_CMD_PING=y 35CONFIG_CMD_PING=y
35CONFIG_CMD_BMP=y 36CONFIG_CMD_BMP=y
37CONFIG_CMD_BOOTCOUNT=y
36CONFIG_CMD_DATE=y 38CONFIG_CMD_DATE=y
37CONFIG_CMD_BTRFS=y 39CONFIG_CMD_BTRFS=y
38CONFIG_CMD_EXT4=y 40CONFIG_CMD_EXT4=y
@@ -44,6 +46,11 @@ CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand"
44CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)" 46CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)"
45CONFIG_CMD_UBI=y 47CONFIG_CMD_UBI=y
46CONFIG_ENV_IS_IN_NAND=y 48CONFIG_ENV_IS_IN_NAND=y
49CONFIG_BOOTCOUNT_LIMIT=y
50CONFIG_BOOTCOUNT_BOOTLIMIT=3
51CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
52CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
53CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
47CONFIG_FSL_ESDHC=y 54CONFIG_FSL_ESDHC=y
48CONFIG_NAND=y 55CONFIG_NAND=y
49CONFIG_NAND_MXC=y 56CONFIG_NAND_MXC=y
@@ -58,5 +65,6 @@ CONFIG_USB_ETHER_MCS7830=y
58CONFIG_USB_ETHER_SMSC95XX=y 65CONFIG_USB_ETHER_SMSC95XX=y
59CONFIG_VIDEO=y 66CONFIG_VIDEO=y
60# CONFIG_VIDEO_SW_CURSOR is not set 67# CONFIG_VIDEO_SW_CURSOR is not set
68CONFIG_IMX_WATCHDOG=y
61CONFIG_FAT_WRITE=y 69CONFIG_FAT_WRITE=y
62CONFIG_OF_LIBFDT=y 70CONFIG_OF_LIBFDT=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 1bc8894cfc..b77ed9ae64 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -29,7 +29,6 @@ CONFIG_SPI=y
29CONFIG_MXC_SPI=y 29CONFIG_MXC_SPI=y
30CONFIG_DM_THERMAL=y 30CONFIG_DM_THERMAL=y
31CONFIG_USB=y 31CONFIG_USB=y
32CONFIG_USB_STORAGE=y
33CONFIG_USB_HOST_ETHER=y 32CONFIG_USB_HOST_ETHER=y
34CONFIG_USB_ETHER_ASIX=y 33CONFIG_USB_ETHER_ASIX=y
35CONFIG_VIDEO=y 34CONFIG_VIDEO=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 69fab7c779..61231557bf 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -46,5 +46,4 @@ CONFIG_SPI=y
46CONFIG_MXC_SPI=y 46CONFIG_MXC_SPI=y
47CONFIG_DM_THERMAL=y 47CONFIG_DM_THERMAL=y
48CONFIG_USB=y 48CONFIG_USB=y
49CONFIG_USB_STORAGE=y
50CONFIG_OF_LIBFDT=y 49CONFIG_OF_LIBFDT=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 05c6572beb..3047ae6e76 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -47,5 +47,4 @@ CONFIG_SPI=y
47CONFIG_MXC_SPI=y 47CONFIG_MXC_SPI=y
48CONFIG_DM_THERMAL=y 48CONFIG_DM_THERMAL=y
49CONFIG_USB=y 49CONFIG_USB=y
50CONFIG_USB_STORAGE=y
51CONFIG_OF_LIBFDT=y 50CONFIG_OF_LIBFDT=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index c2cd298aaa..a55d8d4cfa 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -32,7 +32,6 @@ CONFIG_SYS_NS16550=y
32CONFIG_USB=y 32CONFIG_USB=y
33CONFIG_DM_USB=y 33CONFIG_DM_USB=y
34CONFIG_USB_EHCI_HCD=y 34CONFIG_USB_EHCI_HCD=y
35CONFIG_USB_STORAGE=y
36CONFIG_USB_HOST_ETHER=y 35CONFIG_USB_HOST_ETHER=y
37CONFIG_USB_ETHER_SMSC95XX=y 36CONFIG_USB_ETHER_SMSC95XX=y
38CONFIG_DM_VIDEO=y 37CONFIG_DM_VIDEO=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index f650a720c7..fcb7163ba1 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -70,7 +70,6 @@ CONFIG_SYSRESET=y
70CONFIG_USB=y 70CONFIG_USB=y
71CONFIG_USB_DWC2=y 71CONFIG_USB_DWC2=y
72CONFIG_ROCKCHIP_USB2_PHY=y 72CONFIG_ROCKCHIP_USB2_PHY=y
73CONFIG_USB_STORAGE=y
74CONFIG_USB_GADGET=y 73CONFIG_USB_GADGET=y
75CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 74CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
76CONFIG_USB_GADGET_VENDOR_NUM=0x2207 75CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
new file mode 100644
index 0000000000..d7476c4863
--- /dev/null
+++ b/configs/mscc_luton_defconfig
@@ -0,0 +1,64 @@
1CONFIG_MIPS=y
2CONFIG_SYS_TEXT_BASE=0x40000000
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_DEBUG_UART_BOARD_INIT=y
5CONFIG_DEBUG_UART_BASE=0x70100000
6CONFIG_DEBUG_UART_CLOCK=208333333
7CONFIG_ARCH_MSCC=y
8CONFIG_TARGET_LUTON_PCB091=y
9CONFIG_DDRTYPE_MT47H128M8HQ=y
10CONFIG_SYS_LITTLE_ENDIAN=y
11CONFIG_MIPS_BOOT_FDT=y
12CONFIG_DEBUG_UART=y
13CONFIG_FIT=y
14CONFIG_BOOTDELAY=3
15CONFIG_USE_BOOTARGS=y
16CONFIG_BOOTARGS="console=ttyS0,115200"
17CONFIG_LOGLEVEL=7
18CONFIG_DISPLAY_CPUINFO=y
19CONFIG_SYS_PROMPT="pcb091 # "
20# CONFIG_CMD_BDI is not set
21# CONFIG_CMD_CONSOLE is not set
22# CONFIG_CMD_ELF is not set
23# CONFIG_CMD_EXPORTENV is not set
24# CONFIG_CMD_IMPORTENV is not set
25# CONFIG_CMD_CRC32 is not set
26CONFIG_CMD_MD5SUM=y
27CONFIG_CMD_MEMINFO=y
28CONFIG_CMD_MEMTEST=y
29# CONFIG_CMD_FLASH is not set
30CONFIG_CMD_GPIO=y
31CONFIG_CMD_SF=y
32CONFIG_CMD_SPI=y
33CONFIG_CMD_DHCP=y
34# CONFIG_NET_TFTP_VARS is not set
35# CONFIG_CMD_NFS is not set
36CONFIG_CMD_PING=y
37CONFIG_CMD_MTDPARTS=y
38CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
39CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)"
40# CONFIG_ISO_PARTITION is not set
41CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
42CONFIG_ENV_IS_IN_SPI_FLASH=y
43CONFIG_NET_RANDOM_ETHADDR=y
44CONFIG_CLK=y
45CONFIG_DM_GPIO=y
46CONFIG_DM_SPI_FLASH=y
47CONFIG_SPI_FLASH=y
48CONFIG_SPI_FLASH_BAR=y
49CONFIG_SPI_FLASH_GIGADEVICE=y
50CONFIG_SPI_FLASH_MACRONIX=y
51CONFIG_SPI_FLASH_SPANSION=y
52CONFIG_SPI_FLASH_STMICRO=y
53CONFIG_SPI_FLASH_WINBOND=y
54CONFIG_SPI_FLASH_MTD=y
55CONFIG_DM_ETH=y
56CONFIG_PINCTRL=y
57CONFIG_PINCONF=y
58CONFIG_DM_SERIAL=y
59CONFIG_DEBUG_UART_SHIFT=2
60CONFIG_SYS_NS16550=y
61CONFIG_SPI=y
62CONFIG_DM_SPI=y
63CONFIG_SOFT_SPI=y
64CONFIG_LZMA=y
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
new file mode 100644
index 0000000000..5fa74db2ff
--- /dev/null
+++ b/configs/mscc_ocelot_defconfig
@@ -0,0 +1,67 @@
1CONFIG_MIPS=y
2CONFIG_SYS_TEXT_BASE=0x40000000
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_DEBUG_UART_BOARD_INIT=y
5CONFIG_DEBUG_UART_BASE=0x70100000
6CONFIG_DEBUG_UART_CLOCK=250000000
7CONFIG_ARCH_MSCC=y
8CONFIG_TARGET_OCELOT_PCB123=y
9CONFIG_SYS_LITTLE_ENDIAN=y
10CONFIG_DEBUG_UART=y
11CONFIG_FIT=y
12CONFIG_BOOTDELAY=3
13CONFIG_USE_BOOTARGS=y
14CONFIG_BOOTARGS="console=ttyS0,115200"
15CONFIG_LOGLEVEL=7
16CONFIG_DISPLAY_CPUINFO=y
17CONFIG_SYS_PROMPT="pcb123 # "
18# CONFIG_CMD_BDI is not set
19# CONFIG_CMD_CONSOLE is not set
20# CONFIG_CMD_ELF is not set
21# CONFIG_CMD_EXPORTENV is not set
22# CONFIG_CMD_IMPORTENV is not set
23# CONFIG_CMD_CRC32 is not set
24CONFIG_CMD_MD5SUM=y
25CONFIG_CMD_MEMINFO=y
26CONFIG_CMD_MEMTEST=y
27# CONFIG_CMD_FLASH is not set
28CONFIG_CMD_GPIO=y
29CONFIG_CMD_MTD=y
30CONFIG_CMD_SF=y
31CONFIG_CMD_SPI=y
32CONFIG_CMD_DHCP=y
33# CONFIG_NET_TFTP_VARS is not set
34# CONFIG_CMD_NFS is not set
35CONFIG_CMD_PING=y
36CONFIG_CMD_MTDPARTS=y
37CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
38CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
39CONFIG_CMD_UBI=y
40# CONFIG_CMD_UBIFS is not set
41# CONFIG_ISO_PARTITION is not set
42CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
43CONFIG_ENV_IS_IN_SPI_FLASH=y
44CONFIG_NET_RANDOM_ETHADDR=y
45CONFIG_CLK=y
46CONFIG_DM_GPIO=y
47CONFIG_MTD=y
48CONFIG_MTD_SPI_NAND=y
49CONFIG_DM_SPI_FLASH=y
50CONFIG_SPI_FLASH=y
51CONFIG_SPI_FLASH_BAR=y
52CONFIG_SPI_FLASH_GIGADEVICE=y
53CONFIG_SPI_FLASH_MACRONIX=y
54CONFIG_SPI_FLASH_SPANSION=y
55CONFIG_SPI_FLASH_WINBOND=y
56CONFIG_SPI_FLASH_MTD=y
57CONFIG_DM_ETH=y
58CONFIG_PINCTRL=y
59CONFIG_PINCONF=y
60CONFIG_DM_SERIAL=y
61CONFIG_DEBUG_UART_SHIFT=2
62CONFIG_DEBUG_UART_ANNOUNCE=y
63CONFIG_SYS_NS16550=y
64CONFIG_SPI=y
65CONFIG_DM_SPI=y
66CONFIG_DESIGNWARE_SPI=y
67CONFIG_LZMA=y
diff --git a/configs/mscc_ocelot_pcb120_defconfig b/configs/mscc_ocelot_pcb120_defconfig
new file mode 100644
index 0000000000..c5a9f96977
--- /dev/null
+++ b/configs/mscc_ocelot_pcb120_defconfig
@@ -0,0 +1,60 @@
1CONFIG_MIPS=y
2CONFIG_SYS_TEXT_BASE=0x40000000
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ARCH_MSCC=y
5CONFIG_SYS_LITTLE_ENDIAN=y
6CONFIG_FIT=y
7CONFIG_BOOTDELAY=3
8CONFIG_USE_BOOTARGS=y
9CONFIG_BOOTARGS="console=ttyS0,115200"
10CONFIG_LOGLEVEL=7
11CONFIG_DISPLAY_CPUINFO=y
12CONFIG_SYS_PROMPT="pcb120 # "
13# CONFIG_CMD_BDI is not set
14# CONFIG_CMD_CONSOLE is not set
15# CONFIG_CMD_ELF is not set
16# CONFIG_CMD_EXPORTENV is not set
17# CONFIG_CMD_IMPORTENV is not set
18# CONFIG_CMD_CRC32 is not set
19CONFIG_CMD_MD5SUM=y
20CONFIG_CMD_MEMINFO=y
21CONFIG_CMD_MEMTEST=y
22# CONFIG_CMD_FLASH is not set
23CONFIG_CMD_GPIO=y
24CONFIG_CMD_MTD=y
25CONFIG_CMD_SF=y
26CONFIG_CMD_SPI=y
27CONFIG_CMD_DHCP=y
28# CONFIG_NET_TFTP_VARS is not set
29# CONFIG_CMD_NFS is not set
30CONFIG_CMD_PING=y
31CONFIG_CMD_MTDPARTS=y
32CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
33CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
34CONFIG_CMD_UBI=y
35# CONFIG_CMD_UBIFS is not set
36# CONFIG_ISO_PARTITION is not set
37CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120"
38CONFIG_ENV_IS_IN_SPI_FLASH=y
39CONFIG_NET_RANDOM_ETHADDR=y
40CONFIG_CLK=y
41CONFIG_DM_GPIO=y
42CONFIG_MTD=y
43CONFIG_MTD_SPI_NAND=y
44CONFIG_DM_SPI_FLASH=y
45CONFIG_SPI_FLASH=y
46CONFIG_SPI_FLASH_BAR=y
47CONFIG_SPI_FLASH_GIGADEVICE=y
48CONFIG_SPI_FLASH_MACRONIX=y
49CONFIG_SPI_FLASH_SPANSION=y
50CONFIG_SPI_FLASH_WINBOND=y
51CONFIG_SPI_FLASH_MTD=y
52CONFIG_DM_ETH=y
53CONFIG_PINCTRL=y
54CONFIG_PINCONF=y
55CONFIG_DM_SERIAL=y
56CONFIG_SYS_NS16550=y
57CONFIG_SPI=y
58CONFIG_DM_SPI=y
59CONFIG_DESIGNWARE_SPI=y
60CONFIG_LZMA=y
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index 3a4de72e23..ae4fb280dc 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYS_THUMB_BUILD=y
3CONFIG_ARCH_MEDIATEK=y 3CONFIG_ARCH_MEDIATEK=y
4CONFIG_SYS_TEXT_BASE=0x81e00000 4CONFIG_SYS_TEXT_BASE=0x81e00000
5CONFIG_SYS_MALLOC_F_LEN=0x4000 5CONFIG_SYS_MALLOC_F_LEN=0x4000
6CONFIG_TARGET_MT7623=y
7CONFIG_NR_DRAM_BANKS=1 6CONFIG_NR_DRAM_BANKS=1
8CONFIG_FIT=y 7CONFIG_FIT=y
9CONFIG_FIT_VERBOSE=y 8CONFIG_FIT_VERBOSE=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 2c7a6a393f..da51868b44 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -68,7 +68,6 @@ CONFIG_USB=y
68CONFIG_DM_USB=y 68CONFIG_DM_USB=y
69CONFIG_USB_XHCI_HCD=y 69CONFIG_USB_XHCI_HCD=y
70CONFIG_USB_EHCI_HCD=y 70CONFIG_USB_EHCI_HCD=y
71CONFIG_USB_STORAGE=y
72CONFIG_USB_HOST_ETHER=y 71CONFIG_USB_HOST_ETHER=y
73CONFIG_USB_ETHER_ASIX=y 72CONFIG_USB_ETHER_ASIX=y
74CONFIG_USB_ETHER_MCS7830=y 73CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index bb29d2574d..424d9765dc 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -62,7 +62,6 @@ CONFIG_USB=y
62CONFIG_DM_USB=y 62CONFIG_DM_USB=y
63CONFIG_USB_XHCI_HCD=y 63CONFIG_USB_XHCI_HCD=y
64CONFIG_USB_EHCI_HCD=y 64CONFIG_USB_EHCI_HCD=y
65CONFIG_USB_STORAGE=y
66CONFIG_USB_HOST_ETHER=y 65CONFIG_USB_HOST_ETHER=y
67CONFIG_USB_ETHER_ASIX=y 66CONFIG_USB_ETHER_ASIX=y
68CONFIG_USB_ETHER_MCS7830=y 67CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 6d1649fb88..8701d1f4c2 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -68,7 +68,6 @@ CONFIG_USB=y
68CONFIG_DM_USB=y 68CONFIG_DM_USB=y
69CONFIG_USB_XHCI_HCD=y 69CONFIG_USB_XHCI_HCD=y
70CONFIG_USB_EHCI_HCD=y 70CONFIG_USB_EHCI_HCD=y
71CONFIG_USB_STORAGE=y
72CONFIG_USB_HOST_ETHER=y 71CONFIG_USB_HOST_ETHER=y
73CONFIG_USB_ETHER_ASIX=y 72CONFIG_USB_ETHER_ASIX=y
74CONFIG_USB_ETHER_MCS7830=y 73CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index 9df4c51c6f..d671f201f6 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -67,7 +67,6 @@ CONFIG_USB=y
67CONFIG_DM_USB=y 67CONFIG_DM_USB=y
68CONFIG_USB_XHCI_HCD=y 68CONFIG_USB_XHCI_HCD=y
69CONFIG_USB_EHCI_HCD=y 69CONFIG_USB_EHCI_HCD=y
70CONFIG_USB_STORAGE=y
71CONFIG_USB_HOST_ETHER=y 70CONFIG_USB_HOST_ETHER=y
72CONFIG_USB_ETHER_ASIX=y 71CONFIG_USB_ETHER_ASIX=y
73CONFIG_USB_ETHER_MCS7830=y 72CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 2eee19dab5..0e552a6ac4 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
14CONFIG_ARCH_MISC_INIT=y 14CONFIG_ARCH_MISC_INIT=y
15# CONFIG_SPL_FRAMEWORK is not set 15# CONFIG_SPL_FRAMEWORK is not set
16CONFIG_HUSH_PARSER=y 16CONFIG_HUSH_PARSER=y
17# CONFIG_CMD_BOOTEFI is not set
17# CONFIG_CMD_FLASH is not set 18# CONFIG_CMD_FLASH is not set
18CONFIG_CMD_GPIO=y 19CONFIG_CMD_GPIO=y
19CONFIG_CMD_MMC=y 20CONFIG_CMD_MMC=y
@@ -27,7 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y
27CONFIG_LED_STATUS=y 28CONFIG_LED_STATUS=y
28CONFIG_LED_STATUS_GPIO=y 29CONFIG_LED_STATUS_GPIO=y
29CONFIG_LED_STATUS0=y 30CONFIG_LED_STATUS0=y
30CONFIG_LED_STATUS_BIT=59 31CONFIG_LED_STATUS_BIT=778
31CONFIG_LED_STATUS_STATE=2 32CONFIG_LED_STATUS_STATE=2
32CONFIG_LED_STATUS_BOOT_ENABLE=y 33CONFIG_LED_STATUS_BOOT_ENABLE=y
33CONFIG_LED_STATUS_BOOT=0 34CONFIG_LED_STATUS_BOOT=0
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 34328fd016..28540719df 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -2,6 +2,9 @@ CONFIG_ARM=y
2CONFIG_ARCH_MX5=y 2CONFIG_ARCH_MX5=y
3CONFIG_SYS_TEXT_BASE=0x77800000 3CONFIG_SYS_TEXT_BASE=0x77800000
4CONFIG_TARGET_MX53PPD=y 4CONFIG_TARGET_MX53PPD=y
5CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50
6CONFIG_SYS_VPD_EEPROM_I2C_BUS=2
7CONFIG_SYS_VPD_EEPROM_SIZE=1024
5CONFIG_NR_DRAM_BANKS=2 8CONFIG_NR_DRAM_BANKS=2
6CONFIG_FIT=y 9CONFIG_FIT=y
7CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg" 10CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg"
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 6e73a9752c..adacd8ca61 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -36,7 +36,6 @@ CONFIG_PHYLIB=y
36CONFIG_MII=y 36CONFIG_MII=y
37CONFIG_DM_THERMAL=y 37CONFIG_DM_THERMAL=y
38CONFIG_USB=y 38CONFIG_USB=y
39CONFIG_USB_STORAGE=y
40CONFIG_USB_KEYBOARD=y 39CONFIG_USB_KEYBOARD=y
41CONFIG_VIDEO=y 40CONFIG_VIDEO=y
42# CONFIG_VIDEO_SW_CURSOR is not set 41# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index 7356debc57..e9e1fc2635 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -11,7 +11,7 @@ CONFIG_NR_DRAM_BANKS=1
11CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL" 11CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
12CONFIG_SUPPORT_RAW_INITRD=y 12CONFIG_SUPPORT_RAW_INITRD=y
13CONFIG_SPL_USB_HOST_SUPPORT=y 13CONFIG_SPL_USB_HOST_SUPPORT=y
14CONFIG_SPL_USB_GADGET_SUPPORT=y 14CONFIG_SPL_USB_GADGET=y
15CONFIG_SPL_USB_ETHER=y 15CONFIG_SPL_USB_ETHER=y
16CONFIG_SPL_USB_SDP_SUPPORT=y 16CONFIG_SPL_USB_SDP_SUPPORT=y
17CONFIG_SPL_WATCHDOG_SUPPORT=y 17CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index c73d0d3931..4c84fa5ab7 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -44,7 +44,6 @@ CONFIG_SPI=y
44CONFIG_MXC_SPI=y 44CONFIG_MXC_SPI=y
45CONFIG_DM_THERMAL=y 45CONFIG_DM_THERMAL=y
46CONFIG_USB=y 46CONFIG_USB=y
47CONFIG_USB_STORAGE=y
48CONFIG_USB_KEYBOARD=y 47CONFIG_USB_KEYBOARD=y
49CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y 48CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
50CONFIG_USB_GADGET=y 49CONFIG_USB_GADGET=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index e0202ef57d..1857c189e3 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -19,7 +19,7 @@ CONFIG_SPL_EXT_SUPPORT=y
19CONFIG_SPL_I2C_SUPPORT=y 19CONFIG_SPL_I2C_SUPPORT=y
20CONFIG_SPL_OS_BOOT=y 20CONFIG_SPL_OS_BOOT=y
21CONFIG_SPL_USB_HOST_SUPPORT=y 21CONFIG_SPL_USB_HOST_SUPPORT=y
22CONFIG_SPL_USB_GADGET_SUPPORT=y 22CONFIG_SPL_USB_GADGET=y
23CONFIG_SPL_USB_SDP_SUPPORT=y 23CONFIG_SPL_USB_SDP_SUPPORT=y
24CONFIG_SPL_WATCHDOG_SUPPORT=y 24CONFIG_SPL_WATCHDOG_SUPPORT=y
25CONFIG_HUSH_PARSER=y 25CONFIG_HUSH_PARSER=y
diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig
index 1abc869856..0f3914fe7e 100644
--- a/configs/netgear_dgnd3700v2_ram_defconfig
+++ b/configs/netgear_dgnd3700v2_ram_defconfig
@@ -27,17 +27,23 @@ CONFIG_CMD_MEMINFO=y
27# CONFIG_CMD_FLASH is not set 27# CONFIG_CMD_FLASH is not set
28# CONFIG_CMD_LOADS is not set 28# CONFIG_CMD_LOADS is not set
29CONFIG_CMD_USB=y 29CONFIG_CMD_USB=y
30# CONFIG_CMD_NET is not set 30CONFIG_CMD_MII=y
31CONFIG_CMD_PING=y
31# CONFIG_CMD_MISC is not set 32# CONFIG_CMD_MISC is not set
32CONFIG_OF_EMBED=y 33CONFIG_OF_EMBED=y
33CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" 34CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2"
35CONFIG_NET_RANDOM_ETHADDR=y
34# CONFIG_DM_DEVICE_REMOVE is not set 36# CONFIG_DM_DEVICE_REMOVE is not set
37CONFIG_BCM6348_IUDMA=y
35CONFIG_DM_GPIO=y 38CONFIG_DM_GPIO=y
36CONFIG_BCM6345_GPIO=y 39CONFIG_BCM6345_GPIO=y
37CONFIG_LED=y 40CONFIG_LED=y
38CONFIG_LED_BCM6328=y 41CONFIG_LED_BCM6328=y
39CONFIG_LED_BLINK=y 42CONFIG_LED_BLINK=y
40CONFIG_LED_GPIO=y 43CONFIG_LED_GPIO=y
44CONFIG_DM_ETH=y
45CONFIG_PHY_GIGE=y
46CONFIG_BCM6368_ETH=y
41CONFIG_PHY=y 47CONFIG_PHY=y
42CONFIG_BCM6368_USBH_PHY=y 48CONFIG_BCM6368_USBH_PHY=y
43CONFIG_POWER_DOMAIN=y 49CONFIG_POWER_DOMAIN=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 7eda3ac49d..c54640df2f 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -47,7 +47,6 @@ CONFIG_PHY_MICREL_KSZ90X1=y
47CONFIG_MII=y 47CONFIG_MII=y
48CONFIG_PCI=y 48CONFIG_PCI=y
49CONFIG_USB=y 49CONFIG_USB=y
50CONFIG_USB_STORAGE=y
51CONFIG_USB_KEYBOARD=y 50CONFIG_USB_KEYBOARD=y
52CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y 51CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
53CONFIG_USB_GADGET=y 52CONFIG_USB_GADGET=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index ae6d76dfb2..13d8f99cbe 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -63,7 +63,6 @@ CONFIG_TPM_TIS_INFINEON=y
63CONFIG_USB=y 63CONFIG_USB=y
64CONFIG_DM_USB=y 64CONFIG_DM_USB=y
65CONFIG_USB_EHCI_HCD=y 65CONFIG_USB_EHCI_HCD=y
66CONFIG_USB_STORAGE=y
67CONFIG_USB_GADGET=y 66CONFIG_USB_GADGET=y
68CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 67CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
69CONFIG_USB_GADGET_VENDOR_NUM=0x0955 68CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 68554ba745..33e6e74fa2 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -1,7 +1,6 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_ARCH_MESON=y 2CONFIG_ARCH_MESON=y
3CONFIG_SYS_TEXT_BASE=0x01000000 3CONFIG_SYS_TEXT_BASE=0x01000000
4CONFIG_MESON_GXBB=y
5CONFIG_DEBUG_UART_BASE=0xc81004c0 4CONFIG_DEBUG_UART_BASE=0xc81004c0
6CONFIG_DEBUG_UART_CLOCK=24000000 5CONFIG_DEBUG_UART_CLOCK=24000000
7CONFIG_IDENT_STRING=" odroid-c2" 6CONFIG_IDENT_STRING=" odroid-c2"
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index d5c7cc7129..11796e5bdf 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -47,7 +47,6 @@ CONFIG_USB_EHCI_HCD=y
47CONFIG_USB_DWC3=y 47CONFIG_USB_DWC3=y
48CONFIG_USB_DWC3_GADGET=y 48CONFIG_USB_DWC3_GADGET=y
49CONFIG_USB_DWC3_PHY_SAMSUNG=y 49CONFIG_USB_DWC3_PHY_SAMSUNG=y
50CONFIG_USB_STORAGE=y
51CONFIG_USB_GADGET=y 50CONFIG_USB_GADGET=y
52CONFIG_USB_GADGET_MANUFACTURER="Samsung" 51CONFIG_USB_GADGET_MANUFACTURER="Samsung"
53CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 52CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 594800fc50..cdb033ba78 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -47,7 +47,6 @@ CONFIG_DM_REGULATOR_MAX77686=y
47CONFIG_USB=y 47CONFIG_USB=y
48CONFIG_DM_USB=y 48CONFIG_DM_USB=y
49CONFIG_USB_EHCI_HCD=y 49CONFIG_USB_EHCI_HCD=y
50CONFIG_USB_STORAGE=y
51CONFIG_USB_GADGET=y 50CONFIG_USB_GADGET=y
52CONFIG_USB_GADGET_MANUFACTURER="Samsung" 51CONFIG_USB_GADGET_MANUFACTURER="Samsung"
53CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 52CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 82ddaa3a2b..d2821b8ceb 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -21,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # "
21CONFIG_CMD_SPL=y 21CONFIG_CMD_SPL=y
22CONFIG_CMD_SPL_NAND_OFS=0x240000 22CONFIG_CMD_SPL_NAND_OFS=0x240000
23CONFIG_CMD_SPL_WRITE_SIZE=0x20000 23CONFIG_CMD_SPL_WRITE_SIZE=0x20000
24# CONFIG_CMD_EEPROM is not set
25# CONFIG_CMD_FLASH is not set 24# CONFIG_CMD_FLASH is not set
26CONFIG_CMD_NAND=y 25CONFIG_CMD_NAND=y
27CONFIG_CMD_NAND_LOCK_UNLOCK=y 26CONFIG_CMD_NAND_LOCK_UNLOCK=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index 94f86efe28..28b35ac80d 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -21,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # "
21CONFIG_CMD_SPL=y 21CONFIG_CMD_SPL=y
22CONFIG_CMD_SPL_NAND_OFS=0x240000 22CONFIG_CMD_SPL_NAND_OFS=0x240000
23CONFIG_CMD_SPL_WRITE_SIZE=0x20000 23CONFIG_CMD_SPL_WRITE_SIZE=0x20000
24# CONFIG_CMD_EEPROM is not set
25# CONFIG_CMD_FLASH is not set 24# CONFIG_CMD_FLASH is not set
26CONFIG_CMD_NAND=y 25CONFIG_CMD_NAND=y
27CONFIG_CMD_NAND_LOCK_UNLOCK=y 26CONFIG_CMD_NAND_LOCK_UNLOCK=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 4fb8aec57d..9581dd9537 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -66,7 +66,6 @@ CONFIG_USB_OMAP3=y
66CONFIG_USB_MUSB_GADGET=y 66CONFIG_USB_MUSB_GADGET=y
67CONFIG_USB_MUSB_OMAP2PLUS=y 67CONFIG_USB_MUSB_OMAP2PLUS=y
68CONFIG_TWL4030_USB=y 68CONFIG_TWL4030_USB=y
69CONFIG_USB_STORAGE=y
70CONFIG_USB_GADGET=y 69CONFIG_USB_GADGET=y
71CONFIG_USB_GADGET_MANUFACTURER="TI" 70CONFIG_USB_GADGET_MANUFACTURER="TI"
72CONFIG_USB_GADGET_VENDOR_NUM=0x0451 71CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index cfb7fd2edc..9c6f442b64 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -21,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # "
21CONFIG_CMD_SPL=y 21CONFIG_CMD_SPL=y
22CONFIG_CMD_SPL_NAND_OFS=0x240000 22CONFIG_CMD_SPL_NAND_OFS=0x240000
23CONFIG_CMD_SPL_WRITE_SIZE=0x20000 23CONFIG_CMD_SPL_WRITE_SIZE=0x20000
24# CONFIG_CMD_EEPROM is not set
25# CONFIG_CMD_FLASH is not set 24# CONFIG_CMD_FLASH is not set
26CONFIG_CMD_NAND=y 25CONFIG_CMD_NAND=y
27CONFIG_CMD_NAND_LOCK_UNLOCK=y 26CONFIG_CMD_NAND_LOCK_UNLOCK=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index c30c43bbda..6602af6abe 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -21,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # "
21CONFIG_CMD_SPL=y 21CONFIG_CMD_SPL=y
22CONFIG_CMD_SPL_NAND_OFS=0x240000 22CONFIG_CMD_SPL_NAND_OFS=0x240000
23CONFIG_CMD_SPL_WRITE_SIZE=0x20000 23CONFIG_CMD_SPL_WRITE_SIZE=0x20000
24# CONFIG_CMD_EEPROM is not set
25CONFIG_CMD_NAND=y 24CONFIG_CMD_NAND=y
26CONFIG_CMD_NAND_LOCK_UNLOCK=y 25CONFIG_CMD_NAND_LOCK_UNLOCK=y
27CONFIG_CMD_CACHE=y 26CONFIG_CMD_CACHE=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index 1e7e5f7d83..b2fb146889 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -45,7 +45,6 @@ CONFIG_SPI=y
45CONFIG_OMAP3_SPI=y 45CONFIG_OMAP3_SPI=y
46CONFIG_USB=y 46CONFIG_USB=y
47CONFIG_USB_EHCI_HCD=y 47CONFIG_USB_EHCI_HCD=y
48CONFIG_USB_STORAGE=y
49CONFIG_FAT_WRITE=y 48CONFIG_FAT_WRITE=y
50CONFIG_BCH=y 49CONFIG_BCH=y
51CONFIG_OF_LIBFDT=y 50CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig
index 325c0020ca..489e6a8ee0 100644
--- a/configs/omap3_zoom1_defconfig
+++ b/configs/omap3_zoom1_defconfig
@@ -35,5 +35,6 @@ CONFIG_USB=y
35CONFIG_USB_MUSB_UDC=y 35CONFIG_USB_MUSB_UDC=y
36CONFIG_USB_OMAP3=y 36CONFIG_USB_OMAP3=y
37CONFIG_TWL4030_USB=y 37CONFIG_TWL4030_USB=y
38CONFIG_USB_GADGET=y
38CONFIG_FAT_WRITE=y 39CONFIG_FAT_WRITE=y
39CONFIG_OF_LIBFDT=y 40CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 41df480be3..7ee9eea06a 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -36,7 +36,7 @@ CONFIG_USB=y
36CONFIG_USB_EHCI_HCD=y 36CONFIG_USB_EHCI_HCD=y
37CONFIG_USB_MUSB_UDC=y 37CONFIG_USB_MUSB_UDC=y
38CONFIG_USB_OMAP3=y 38CONFIG_USB_OMAP3=y
39CONFIG_USB_STORAGE=y 39CONFIG_USB_GADGET=y
40CONFIG_USB_HOST_ETHER=y 40CONFIG_USB_HOST_ETHER=y
41CONFIG_USB_ETHER_SMSC95XX=y 41CONFIG_USB_ETHER_SMSC95XX=y
42CONFIG_OF_LIBFDT=y 42CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 6b2ea202e5..0e01c8edcb 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -33,6 +33,7 @@ CONFIG_OMAP3_SPI=y
33CONFIG_USB=y 33CONFIG_USB=y
34CONFIG_USB_MUSB_UDC=y 34CONFIG_USB_MUSB_UDC=y
35CONFIG_USB_OMAP3=y 35CONFIG_USB_OMAP3=y
36CONFIG_USB_GADGET=y
36CONFIG_FAT_WRITE=y 37CONFIG_FAT_WRITE=y
37# CONFIG_REGEX is not set 38# CONFIG_REGEX is not set
38CONFIG_OF_LIBFDT=y 39CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 52b76e260a..84d4e2b37c 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -41,7 +41,6 @@ CONFIG_USB_DWC3=y
41CONFIG_USB_DWC3_GADGET=y 41CONFIG_USB_DWC3_GADGET=y
42CONFIG_USB_DWC3_OMAP=y 42CONFIG_USB_DWC3_OMAP=y
43CONFIG_USB_DWC3_PHY_OMAP=y 43CONFIG_USB_DWC3_PHY_OMAP=y
44CONFIG_USB_STORAGE=y
45CONFIG_USB_GADGET=y 44CONFIG_USB_GADGET=y
46CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" 45CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
47CONFIG_USB_GADGET_VENDOR_NUM=0x0403 46CONFIG_USB_GADGET_VENDOR_NUM=0x0403
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index a15064da81..2ab47e616f 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -47,5 +47,4 @@ CONFIG_USB_XHCI_HCD=y
47CONFIG_USB_XHCI_DWC3=y 47CONFIG_USB_XHCI_DWC3=y
48CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y 48CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
49CONFIG_USB_DWC3=y 49CONFIG_USB_DWC3=y
50CONFIG_USB_STORAGE=y
51CONFIG_OF_LIBFDT_OVERLAY=y 50CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 02a7569205..015ac05308 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -32,7 +32,6 @@ CONFIG_TEGRA114_SPI=y
32CONFIG_USB=y 32CONFIG_USB=y
33CONFIG_DM_USB=y 33CONFIG_DM_USB=y
34CONFIG_USB_EHCI_HCD=y 34CONFIG_USB_EHCI_HCD=y
35CONFIG_USB_STORAGE=y
36CONFIG_USB_GADGET=y 35CONFIG_USB_GADGET=y
37CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 36CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
38CONFIG_USB_GADGET_VENDOR_NUM=0x0955 37CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index d9dcf7e014..81ce9a2d08 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -39,7 +39,6 @@ CONFIG_TEGRA114_SPI=y
39CONFIG_USB=y 39CONFIG_USB=y
40CONFIG_DM_USB=y 40CONFIG_DM_USB=y
41CONFIG_USB_EHCI_HCD=y 41CONFIG_USB_EHCI_HCD=y
42CONFIG_USB_STORAGE=y
43CONFIG_USB_GADGET=y 42CONFIG_USB_GADGET=y
44CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 43CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
45CONFIG_USB_GADGET_VENDOR_NUM=0x0955 44CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 5cbb1c3201..5482ac2563 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -32,7 +32,6 @@ CONFIG_TEGRA114_SPI=y
32CONFIG_USB=y 32CONFIG_USB=y
33CONFIG_DM_USB=y 33CONFIG_DM_USB=y
34CONFIG_USB_EHCI_HCD=y 34CONFIG_USB_EHCI_HCD=y
35CONFIG_USB_STORAGE=y
36CONFIG_USB_GADGET=y 35CONFIG_USB_GADGET=y
37CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 36CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
38CONFIG_USB_GADGET_VENDOR_NUM=0x0955 37CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index a11e56d7c2..dc785c8865 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYS_NS16550=y
30CONFIG_USB=y 30CONFIG_USB=y
31CONFIG_DM_USB=y 31CONFIG_DM_USB=y
32CONFIG_USB_EHCI_HCD=y 32CONFIG_USB_EHCI_HCD=y
33CONFIG_USB_STORAGE=y
34CONFIG_USB_HOST_ETHER=y 33CONFIG_USB_HOST_ETHER=y
35CONFIG_USB_ETHER_ASIX=y 34CONFIG_USB_ETHER_ASIX=y
36CONFIG_DM_VIDEO=y 35CONFIG_DM_VIDEO=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 0be0caa826..274549f6e3 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -43,15 +43,14 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
43CONFIG_MMC_OMAP_HS=y 43CONFIG_MMC_OMAP_HS=y
44CONFIG_SPI_FLASH=y 44CONFIG_SPI_FLASH=y
45CONFIG_SPI_FLASH_WINBOND=y 45CONFIG_SPI_FLASH_WINBOND=y
46CONFIG_DRIVER_TI_CPSW=y
47CONFIG_MII=y 46CONFIG_MII=y
47CONFIG_DRIVER_TI_CPSW=y
48CONFIG_SPI=y 48CONFIG_SPI=y
49CONFIG_OMAP3_SPI=y 49CONFIG_OMAP3_SPI=y
50CONFIG_USB=y 50CONFIG_USB=y
51CONFIG_USB_MUSB_HOST=y 51CONFIG_USB_MUSB_HOST=y
52CONFIG_USB_MUSB_GADGET=y 52CONFIG_USB_MUSB_GADGET=y
53CONFIG_USB_MUSB_DSPS=y 53CONFIG_USB_MUSB_DSPS=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_USB_ETHER=y 55CONFIG_USB_ETHER=y
57CONFIG_FAT_WRITE=y 56CONFIG_FAT_WRITE=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 33e8225e53..a41ed1481e 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -43,15 +43,14 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
43CONFIG_MMC_OMAP_HS=y 43CONFIG_MMC_OMAP_HS=y
44CONFIG_SPI_FLASH=y 44CONFIG_SPI_FLASH=y
45CONFIG_SPI_FLASH_WINBOND=y 45CONFIG_SPI_FLASH_WINBOND=y
46CONFIG_DRIVER_TI_CPSW=y
47CONFIG_MII=y 46CONFIG_MII=y
47CONFIG_DRIVER_TI_CPSW=y
48CONFIG_SPI=y 48CONFIG_SPI=y
49CONFIG_OMAP3_SPI=y 49CONFIG_OMAP3_SPI=y
50CONFIG_USB=y 50CONFIG_USB=y
51CONFIG_USB_MUSB_HOST=y 51CONFIG_USB_MUSB_HOST=y
52CONFIG_USB_MUSB_GADGET=y 52CONFIG_USB_MUSB_GADGET=y
53CONFIG_USB_MUSB_DSPS=y 53CONFIG_USB_MUSB_DSPS=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_USB_ETHER=y 55CONFIG_USB_ETHER=y
57CONFIG_FAT_WRITE=y 56CONFIG_FAT_WRITE=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 14c835cad8..96ec8fdb0b 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -61,7 +61,6 @@ CONFIG_USB=y
61CONFIG_DM_USB=y 61CONFIG_DM_USB=y
62CONFIG_USB_XHCI_HCD=y 62CONFIG_USB_XHCI_HCD=y
63CONFIG_USB_XHCI_DWC3=y 63CONFIG_USB_XHCI_DWC3=y
64CONFIG_USB_STORAGE=y
65CONFIG_USB_HOST_ETHER=y 64CONFIG_USB_HOST_ETHER=y
66CONFIG_DM_VIDEO=y 65CONFIG_DM_VIDEO=y
67CONFIG_VIDCONSOLE_AS_LCD=y 66CONFIG_VIDCONSOLE_AS_LCD=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 9a3a11504d..792f22fa1f 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -60,7 +60,6 @@ CONFIG_USB=y
60CONFIG_DM_USB=y 60CONFIG_DM_USB=y
61CONFIG_USB_XHCI_HCD=y 61CONFIG_USB_XHCI_HCD=y
62CONFIG_USB_XHCI_DWC3=y 62CONFIG_USB_XHCI_DWC3=y
63CONFIG_USB_STORAGE=y
64CONFIG_USB_HOST_ETHER=y 63CONFIG_USB_HOST_ETHER=y
65CONFIG_DM_VIDEO=y 64CONFIG_DM_VIDEO=y
66CONFIG_VIDCONSOLE_AS_LCD=y 65CONFIG_VIDCONSOLE_AS_LCD=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 3c8684ad95..a0206f6fde 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -48,15 +48,14 @@ CONFIG_ENV_IS_IN_NAND=y
48CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 48CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
49CONFIG_MMC_OMAP_HS=y 49CONFIG_MMC_OMAP_HS=y
50CONFIG_NAND=y 50CONFIG_NAND=y
51CONFIG_DRIVER_TI_CPSW=y
52CONFIG_MII=y 51CONFIG_MII=y
52CONFIG_DRIVER_TI_CPSW=y
53CONFIG_SPI=y 53CONFIG_SPI=y
54CONFIG_OMAP3_SPI=y 54CONFIG_OMAP3_SPI=y
55CONFIG_USB=y 55CONFIG_USB=y
56CONFIG_USB_MUSB_HOST=y 56CONFIG_USB_MUSB_HOST=y
57CONFIG_USB_MUSB_GADGET=y 57CONFIG_USB_MUSB_GADGET=y
58CONFIG_USB_MUSB_DSPS=y 58CONFIG_USB_MUSB_DSPS=y
59CONFIG_USB_STORAGE=y
60CONFIG_USB_GADGET=y 59CONFIG_USB_GADGET=y
61CONFIG_FAT_WRITE=y 60CONFIG_FAT_WRITE=y
62CONFIG_OF_LIBFDT=y 61CONFIG_OF_LIBFDT=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index 1dc3944d05..b5738541f2 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -33,8 +33,8 @@ CONFIG_MMC_OMAP_HS=y
33CONFIG_PHY_ADDR_ENABLE=y 33CONFIG_PHY_ADDR_ENABLE=y
34CONFIG_PHY_MICREL=y 34CONFIG_PHY_MICREL=y
35CONFIG_PHY_MICREL_KSZ90X1=y 35CONFIG_PHY_MICREL_KSZ90X1=y
36CONFIG_DRIVER_TI_CPSW=y
37CONFIG_MII=y 36CONFIG_MII=y
37CONFIG_DRIVER_TI_CPSW=y
38CONFIG_SPI=y 38CONFIG_SPI=y
39CONFIG_OMAP3_SPI=y 39CONFIG_OMAP3_SPI=y
40CONFIG_FAT_WRITE=y 40CONFIG_FAT_WRITE=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index ef7abddbf1..1e33e542ef 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -74,7 +74,6 @@ CONFIG_SYSRESET=y
74CONFIG_USB=y 74CONFIG_USB=y
75CONFIG_USB_DWC2=y 75CONFIG_USB_DWC2=y
76CONFIG_ROCKCHIP_USB2_PHY=y 76CONFIG_ROCKCHIP_USB2_PHY=y
77CONFIG_USB_STORAGE=y
78CONFIG_USB_GADGET=y 77CONFIG_USB_GADGET=y
79CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 78CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
80CONFIG_USB_GADGET_VENDOR_NUM=0x2207 79CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index ce10c64490..de699fc275 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -41,7 +41,6 @@ CONFIG_USB=y
41CONFIG_DM_USB=y 41CONFIG_DM_USB=y
42CONFIG_USB_MUSB_HOST=y 42CONFIG_USB_MUSB_HOST=y
43CONFIG_USB_MUSB_PIC32=y 43CONFIG_USB_MUSB_PIC32=y
44CONFIG_USB_STORAGE=y
45CONFIG_FAT_WRITE=y 44CONFIG_FAT_WRITE=y
46CONFIG_USE_TINY_PRINTF=y 45CONFIG_USE_TINY_PRINTF=y
47CONFIG_CMD_DHRYSTONE=y 46CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index 362c0a251d..299eb37c12 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
18CONFIG_BOARD_EARLY_INIT_F=y 18CONFIG_BOARD_EARLY_INIT_F=y
19CONFIG_SPL_I2C_SUPPORT=y 19CONFIG_SPL_I2C_SUPPORT=y
20CONFIG_SPL_USB_HOST_SUPPORT=y 20CONFIG_SPL_USB_HOST_SUPPORT=y
21CONFIG_SPL_USB_GADGET_SUPPORT=y 21CONFIG_SPL_USB_GADGET=y
22CONFIG_SPL_USB_SDP_SUPPORT=y 22CONFIG_SPL_USB_SDP_SUPPORT=y
23CONFIG_CMD_BOOTMENU=y 23CONFIG_CMD_BOOTMENU=y
24CONFIG_CMD_MEMTEST=y 24CONFIG_CMD_MEMTEST=y
@@ -44,7 +44,6 @@ CONFIG_PHYLIB=y
44CONFIG_PHY_MICREL=y 44CONFIG_PHY_MICREL=y
45CONFIG_MII=y 45CONFIG_MII=y
46CONFIG_USB=y 46CONFIG_USB=y
47CONFIG_USB_STORAGE=y
48CONFIG_USB_GADGET=y 47CONFIG_USB_GADGET=y
49CONFIG_USB_GADGET_MANUFACTURER="FSL" 48CONFIG_USB_GADGET_MANUFACTURER="FSL"
50CONFIG_USB_GADGET_VENDOR_NUM=0x0525 49CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index b02cae5237..4fe7beeaec 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -18,7 +18,7 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
18CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" 18CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
19CONFIG_SPL_I2C_SUPPORT=y 19CONFIG_SPL_I2C_SUPPORT=y
20CONFIG_SPL_USB_HOST_SUPPORT=y 20CONFIG_SPL_USB_HOST_SUPPORT=y
21CONFIG_SPL_USB_GADGET_SUPPORT=y 21CONFIG_SPL_USB_GADGET=y
22CONFIG_SPL_USB_SDP_SUPPORT=y 22CONFIG_SPL_USB_SDP_SUPPORT=y
23# CONFIG_CMD_BOOTD is not set 23# CONFIG_CMD_BOOTD is not set
24CONFIG_CMD_BOOTMENU=y 24CONFIG_CMD_BOOTMENU=y
@@ -51,7 +51,6 @@ CONFIG_MII=y
51CONFIG_USB=y 51CONFIG_USB=y
52CONFIG_USB_EHCI_HCD=y 52CONFIG_USB_EHCI_HCD=y
53CONFIG_MXC_USB_OTG_HACTIVE=y 53CONFIG_MXC_USB_OTG_HACTIVE=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_USB_GADGET_MANUFACTURER="FSL" 55CONFIG_USB_GADGET_MANUFACTURER="FSL"
57CONFIG_USB_GADGET_VENDOR_NUM=0x0525 56CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index c8d58cbe71..0f6cf9353a 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="ask"
18CONFIG_BOARD_EARLY_INIT_F=y 18CONFIG_BOARD_EARLY_INIT_F=y
19CONFIG_SPL_I2C_SUPPORT=y 19CONFIG_SPL_I2C_SUPPORT=y
20CONFIG_SPL_USB_HOST_SUPPORT=y 20CONFIG_SPL_USB_HOST_SUPPORT=y
21CONFIG_SPL_USB_GADGET_SUPPORT=y 21CONFIG_SPL_USB_GADGET=y
22CONFIG_SPL_USB_SDP_SUPPORT=y 22CONFIG_SPL_USB_SDP_SUPPORT=y
23CONFIG_CMD_BOOTMENU=y 23CONFIG_CMD_BOOTMENU=y
24CONFIG_CMD_SPL=y 24CONFIG_CMD_SPL=y
@@ -46,7 +46,6 @@ CONFIG_PHYLIB=y
46CONFIG_PHY_MICREL=y 46CONFIG_PHY_MICREL=y
47CONFIG_MII=y 47CONFIG_MII=y
48CONFIG_USB=y 48CONFIG_USB=y
49CONFIG_USB_STORAGE=y
50CONFIG_USB_GADGET=y 49CONFIG_USB_GADGET=y
51CONFIG_USB_GADGET_MANUFACTURER="FSL" 50CONFIG_USB_GADGET_MANUFACTURER="FSL"
52CONFIG_USB_GADGET_VENDOR_NUM=0x0525 51CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index f355f07be7..542fcd4289 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -18,7 +18,7 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
18CONFIG_DEFAULT_FDT_FILE="ask" 18CONFIG_DEFAULT_FDT_FILE="ask"
19CONFIG_SPL_I2C_SUPPORT=y 19CONFIG_SPL_I2C_SUPPORT=y
20CONFIG_SPL_USB_HOST_SUPPORT=y 20CONFIG_SPL_USB_HOST_SUPPORT=y
21CONFIG_SPL_USB_GADGET_SUPPORT=y 21CONFIG_SPL_USB_GADGET=y
22CONFIG_SPL_USB_SDP_SUPPORT=y 22CONFIG_SPL_USB_SDP_SUPPORT=y
23# CONFIG_CMD_BOOTD is not set 23# CONFIG_CMD_BOOTD is not set
24CONFIG_CMD_BOOTMENU=y 24CONFIG_CMD_BOOTMENU=y
@@ -51,7 +51,6 @@ CONFIG_MII=y
51CONFIG_USB=y 51CONFIG_USB=y
52CONFIG_USB_EHCI_HCD=y 52CONFIG_USB_EHCI_HCD=y
53CONFIG_MXC_USB_OTG_HACTIVE=y 53CONFIG_MXC_USB_OTG_HACTIVE=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_USB_GADGET_MANUFACTURER="FSL" 55CONFIG_USB_GADGET_MANUFACTURER="FSL"
57CONFIG_USB_GADGET_VENDOR_NUM=0x0525 56CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index 680438d265..9049a49ee0 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
18CONFIG_BOARD_EARLY_INIT_F=y 18CONFIG_BOARD_EARLY_INIT_F=y
19CONFIG_SPL_I2C_SUPPORT=y 19CONFIG_SPL_I2C_SUPPORT=y
20CONFIG_SPL_USB_HOST_SUPPORT=y 20CONFIG_SPL_USB_HOST_SUPPORT=y
21CONFIG_SPL_USB_GADGET_SUPPORT=y 21CONFIG_SPL_USB_GADGET=y
22CONFIG_SPL_USB_SDP_SUPPORT=y 22CONFIG_SPL_USB_SDP_SUPPORT=y
23CONFIG_CMD_BOOTMENU=y 23CONFIG_CMD_BOOTMENU=y
24CONFIG_CMD_MEMTEST=y 24CONFIG_CMD_MEMTEST=y
@@ -44,7 +44,6 @@ CONFIG_PHYLIB=y
44CONFIG_PHY_MICREL=y 44CONFIG_PHY_MICREL=y
45CONFIG_MII=y 45CONFIG_MII=y
46CONFIG_USB=y 46CONFIG_USB=y
47CONFIG_USB_STORAGE=y
48CONFIG_USB_GADGET=y 47CONFIG_USB_GADGET=y
49CONFIG_USB_GADGET_MANUFACTURER="FSL" 48CONFIG_USB_GADGET_MANUFACTURER="FSL"
50CONFIG_USB_GADGET_VENDOR_NUM=0x0525 49CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 3a182dcb81..a2d857eeb8 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -18,7 +18,7 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
18CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" 18CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
19CONFIG_SPL_I2C_SUPPORT=y 19CONFIG_SPL_I2C_SUPPORT=y
20CONFIG_SPL_USB_HOST_SUPPORT=y 20CONFIG_SPL_USB_HOST_SUPPORT=y
21CONFIG_SPL_USB_GADGET_SUPPORT=y 21CONFIG_SPL_USB_GADGET=y
22CONFIG_SPL_USB_SDP_SUPPORT=y 22CONFIG_SPL_USB_SDP_SUPPORT=y
23# CONFIG_CMD_BOOTD is not set 23# CONFIG_CMD_BOOTD is not set
24CONFIG_CMD_BOOTMENU=y 24CONFIG_CMD_BOOTMENU=y
@@ -51,7 +51,6 @@ CONFIG_MII=y
51CONFIG_USB=y 51CONFIG_USB=y
52CONFIG_USB_EHCI_HCD=y 52CONFIG_USB_EHCI_HCD=y
53CONFIG_MXC_USB_OTG_HACTIVE=y 53CONFIG_MXC_USB_OTG_HACTIVE=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_USB_GADGET_MANUFACTURER="FSL" 55CONFIG_USB_GADGET_MANUFACTURER="FSL"
57CONFIG_USB_GADGET_VENDOR_NUM=0x0525 56CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 699e2e230a..67cfed67f3 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -35,12 +35,12 @@ CONFIG_CMD_DHCP=y
35CONFIG_CMD_PING=y 35CONFIG_CMD_PING=y
36CONFIG_CMD_FAT=y 36CONFIG_CMD_FAT=y
37CONFIG_ENV_IS_IN_FAT=y 37CONFIG_ENV_IS_IN_FAT=y
38CONFIG_DM=y
39CONFIG_SPL_DM=y
38CONFIG_USB=y 40CONFIG_USB=y
39CONFIG_USB_EHCI_HCD=y 41CONFIG_USB_EHCI_HCD=y
40CONFIG_USB_STORAGE=y 42CONFIG_USB_STORAGE=y
41CONFIG_LCD=y 43CONFIG_LCD=y
42CONFIG_OF_LIBFDT=y
43CONFIG_DM=y
44CONFIG_SPL_DM=y
45CONFIG_WDT=y 44CONFIG_WDT=y
46CONFIG_WDT_AT91=y 45CONFIG_WDT_AT91=y
46CONFIG_OF_LIBFDT=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 73524122de..05b388cce3 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -27,6 +27,5 @@ CONFIG_SYS_NS16550=y
27CONFIG_USB=y 27CONFIG_USB=y
28CONFIG_DM_USB=y 28CONFIG_DM_USB=y
29CONFIG_USB_EHCI_HCD=y 29CONFIG_USB_EHCI_HCD=y
30CONFIG_USB_STORAGE=y
31CONFIG_USB_HOST_ETHER=y 30CONFIG_USB_HOST_ETHER=y
32CONFIG_USB_ETHER_SMSC95XX=y 31CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
index a3ae9a06b2..239783a592 100644
--- a/configs/poplar_defconfig
+++ b/configs/poplar_defconfig
@@ -16,7 +16,6 @@ CONFIG_MMC_DW_K3=y
16CONFIG_USB=y 16CONFIG_USB=y
17CONFIG_USB_EHCI_HCD=y 17CONFIG_USB_EHCI_HCD=y
18CONFIG_USB_EHCI_GENERIC=y 18CONFIG_USB_EHCI_GENERIC=y
19CONFIG_USB_STORAGE=y
20CONFIG_USB_HOST_ETHER=y 19CONFIG_USB_HOST_ETHER=y
21CONFIG_USB_ETHER_ASIX=y 20CONFIG_USB_ETHER_ASIX=y
22CONFIG_FAT_WRITE=y 21CONFIG_FAT_WRITE=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 0e10d1a225..85f4f393e8 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -70,7 +70,6 @@ CONFIG_SYSRESET=y
70CONFIG_USB=y 70CONFIG_USB=y
71CONFIG_USB_DWC2=y 71CONFIG_USB_DWC2=y
72CONFIG_ROCKCHIP_USB2_PHY=y 72CONFIG_ROCKCHIP_USB2_PHY=y
73CONFIG_USB_STORAGE=y
74CONFIG_USB_GADGET=y 73CONFIG_USB_GADGET=y
75CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 74CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
76CONFIG_USB_GADGET_VENDOR_NUM=0x2207 75CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index a45a34be31..fd492312a1 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -75,10 +75,12 @@ CONFIG_GMAC_ROCKCHIP=y
75CONFIG_PINCTRL=y 75CONFIG_PINCTRL=y
76CONFIG_SPL_PINCTRL=y 76CONFIG_SPL_PINCTRL=y
77CONFIG_PINCTRL_ROCKCHIP_RK3399=y 77CONFIG_PINCTRL_ROCKCHIP_RK3399=y
78CONFIG_PINCTRL_ROCKCHIP_RK3399_FULL=y
78CONFIG_DM_PMIC=y 79CONFIG_DM_PMIC=y
79CONFIG_DM_PMIC_FAN53555=y 80CONFIG_DM_PMIC_FAN53555=y
80CONFIG_PMIC_RK8XX=y 81CONFIG_PMIC_RK8XX=y
81CONFIG_SPL_DM_REGULATOR=y 82CONFIG_SPL_DM_REGULATOR=y
83CONFIG_REGULATOR_PWM=y
82CONFIG_DM_REGULATOR_FIXED=y 84CONFIG_DM_REGULATOR_FIXED=y
83CONFIG_SPL_DM_REGULATOR_FIXED=y 85CONFIG_SPL_DM_REGULATOR_FIXED=y
84CONFIG_DM_REGULATOR_GPIO=y 86CONFIG_DM_REGULATOR_GPIO=y
@@ -96,7 +98,6 @@ CONFIG_USB_XHCI_HCD=y
96CONFIG_USB_XHCI_DWC3=y 98CONFIG_USB_XHCI_DWC3=y
97CONFIG_USB_EHCI_HCD=y 99CONFIG_USB_EHCI_HCD=y
98CONFIG_USB_EHCI_GENERIC=y 100CONFIG_USB_EHCI_GENERIC=y
99CONFIG_USB_STORAGE=y
100CONFIG_USB_HOST_ETHER=y 101CONFIG_USB_HOST_ETHER=y
101CONFIG_USB_ETHER_ASIX=y 102CONFIG_USB_ETHER_ASIX=y
102CONFIG_USB_ETHER_ASIX88179=y 103CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 4a5c3c6710..527d4a3842 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -68,8 +68,8 @@ CONFIG_SPI_FLASH=y
68CONFIG_SPI_FLASH_WINBOND=y 68CONFIG_SPI_FLASH_WINBOND=y
69CONFIG_MTD_UBI_FASTMAP=y 69CONFIG_MTD_UBI_FASTMAP=y
70CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 70CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
71CONFIG_DRIVER_TI_CPSW=y
72CONFIG_MII=y 71CONFIG_MII=y
72CONFIG_DRIVER_TI_CPSW=y
73CONFIG_SPI=y 73CONFIG_SPI=y
74CONFIG_OMAP3_SPI=y 74CONFIG_OMAP3_SPI=y
75CONFIG_USB=y 75CONFIG_USB=y
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 0f13716c2e..f2e759cee9 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -1,5 +1,4 @@
1CONFIG_ARM=y 1CONFIG_ARM=y
2CONFIG_ARM_SMCCC=y
3CONFIG_ARCH_QEMU=y 2CONFIG_ARCH_QEMU=y
4CONFIG_TARGET_QEMU_ARM_64BIT=y 3CONFIG_TARGET_QEMU_ARM_64BIT=y
5CONFIG_AHCI=y 4CONFIG_AHCI=y
@@ -11,10 +10,17 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y
11CONFIG_CMD_PCI=y 10CONFIG_CMD_PCI=y
12CONFIG_CMD_USB=y 11CONFIG_CMD_USB=y
13CONFIG_OF_BOARD=y 12CONFIG_OF_BOARD=y
13CONFIG_ENV_IS_IN_FLASH=y
14CONFIG_SCSI_AHCI=y 14CONFIG_SCSI_AHCI=y
15CONFIG_AHCI_PCI=y 15CONFIG_AHCI_PCI=y
16CONFIG_BLK=y 16CONFIG_BLK=y
17# CONFIG_MMC is not set 17# CONFIG_MMC is not set
18CONFIG_MTD=y
19CONFIG_MTD_NOR_FLASH=y
20CONFIG_FLASH_CFI_DRIVER=y
21CONFIG_CFI_FLASH=y
22CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
23CONFIG_SYS_FLASH_CFI=y
18CONFIG_DM_ETH=y 24CONFIG_DM_ETH=y
19CONFIG_E1000=y 25CONFIG_E1000=y
20CONFIG_NVME=y 26CONFIG_NVME=y
@@ -29,10 +35,3 @@ CONFIG_USB=y
29CONFIG_DM_USB=y 35CONFIG_DM_USB=y
30CONFIG_USB_EHCI_HCD=y 36CONFIG_USB_EHCI_HCD=y
31CONFIG_USB_EHCI_PCI=y 37CONFIG_USB_EHCI_PCI=y
32CONFIG_ENV_IS_IN_FLASH=y
33CONFIG_MTD=y
34CONFIG_MTD_NOR_FLASH=y
35CONFIG_FLASH_CFI_DRIVER=y
36CONFIG_CFI_FLASH=y
37CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
38CONFIG_SYS_FLASH_CFI=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index b75363e305..27c427dd82 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -11,10 +11,17 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y
11CONFIG_CMD_PCI=y 11CONFIG_CMD_PCI=y
12CONFIG_CMD_USB=y 12CONFIG_CMD_USB=y
13CONFIG_OF_BOARD=y 13CONFIG_OF_BOARD=y
14CONFIG_ENV_IS_IN_FLASH=y
14CONFIG_SCSI_AHCI=y 15CONFIG_SCSI_AHCI=y
15CONFIG_AHCI_PCI=y 16CONFIG_AHCI_PCI=y
16CONFIG_BLK=y 17CONFIG_BLK=y
17# CONFIG_MMC is not set 18# CONFIG_MMC is not set
19CONFIG_MTD=y
20CONFIG_MTD_NOR_FLASH=y
21CONFIG_FLASH_CFI_DRIVER=y
22CONFIG_CFI_FLASH=y
23CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
24CONFIG_SYS_FLASH_CFI=y
18CONFIG_DM_ETH=y 25CONFIG_DM_ETH=y
19CONFIG_E1000=y 26CONFIG_E1000=y
20CONFIG_NVME=y 27CONFIG_NVME=y
@@ -29,10 +36,3 @@ CONFIG_USB=y
29CONFIG_DM_USB=y 36CONFIG_DM_USB=y
30CONFIG_USB_EHCI_HCD=y 37CONFIG_USB_EHCI_HCD=y
31CONFIG_USB_EHCI_PCI=y 38CONFIG_USB_EHCI_PCI=y
32CONFIG_ENV_IS_IN_FLASH=y
33CONFIG_MTD=y
34CONFIG_MTD_NOR_FLASH=y
35CONFIG_FLASH_CFI_DRIVER=y
36CONFIG_CFI_FLASH=y
37CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
38CONFIG_SYS_FLASH_CFI=y
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig
index 1aa3cef564..019e72eac1 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -42,7 +42,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y
42CONFIG_DM_MMC=y 42CONFIG_DM_MMC=y
43CONFIG_MMC_IO_VOLTAGE=y 43CONFIG_MMC_IO_VOLTAGE=y
44CONFIG_MMC_UHS_SUPPORT=y 44CONFIG_MMC_UHS_SUPPORT=y
45CONFIG_MMC_HS200_SUPPORT=y
46CONFIG_MMC_HS400_SUPPORT=y 45CONFIG_MMC_HS400_SUPPORT=y
47CONFIG_RENESAS_SDHI=y 46CONFIG_RENESAS_SDHI=y
48CONFIG_PHY_MICREL=y 47CONFIG_PHY_MICREL=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index 3280a353dc..b2f1dfe50b 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -42,7 +42,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y
42CONFIG_DM_MMC=y 42CONFIG_DM_MMC=y
43CONFIG_MMC_IO_VOLTAGE=y 43CONFIG_MMC_IO_VOLTAGE=y
44CONFIG_MMC_UHS_SUPPORT=y 44CONFIG_MMC_UHS_SUPPORT=y
45CONFIG_MMC_HS200_SUPPORT=y
46CONFIG_MMC_HS400_SUPPORT=y 45CONFIG_MMC_HS400_SUPPORT=y
47CONFIG_RENESAS_SDHI=y 46CONFIG_RENESAS_SDHI=y
48CONFIG_PHY_MICREL=y 47CONFIG_PHY_MICREL=y
diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig
index 820477164a..3580a44d5e 100644
--- a/configs/r8a77965_salvator-x_defconfig
+++ b/configs/r8a77965_salvator-x_defconfig
@@ -43,7 +43,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y
43CONFIG_DM_MMC=y 43CONFIG_DM_MMC=y
44CONFIG_MMC_IO_VOLTAGE=y 44CONFIG_MMC_IO_VOLTAGE=y
45CONFIG_MMC_UHS_SUPPORT=y 45CONFIG_MMC_UHS_SUPPORT=y
46CONFIG_MMC_HS200_SUPPORT=y
47CONFIG_MMC_HS400_SUPPORT=y 46CONFIG_MMC_HS400_SUPPORT=y
48CONFIG_RENESAS_SDHI=y 47CONFIG_RENESAS_SDHI=y
49CONFIG_PHY_MICREL=y 48CONFIG_PHY_MICREL=y
diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig
index a57e475ca2..9006b9fc3c 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -43,7 +43,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y
43CONFIG_DM_MMC=y 43CONFIG_DM_MMC=y
44CONFIG_MMC_IO_VOLTAGE=y 44CONFIG_MMC_IO_VOLTAGE=y
45CONFIG_MMC_UHS_SUPPORT=y 45CONFIG_MMC_UHS_SUPPORT=y
46CONFIG_MMC_HS200_SUPPORT=y
47CONFIG_MMC_HS400_SUPPORT=y 46CONFIG_MMC_HS400_SUPPORT=y
48CONFIG_RENESAS_SDHI=y 47CONFIG_RENESAS_SDHI=y
49CONFIG_PHY_MICREL=y 48CONFIG_PHY_MICREL=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index 20b2dd9579..37b70b993b 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -43,7 +43,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y
43CONFIG_DM_MMC=y 43CONFIG_DM_MMC=y
44CONFIG_MMC_IO_VOLTAGE=y 44CONFIG_MMC_IO_VOLTAGE=y
45CONFIG_MMC_UHS_SUPPORT=y 45CONFIG_MMC_UHS_SUPPORT=y
46CONFIG_MMC_HS200_SUPPORT=y
47CONFIG_MMC_HS400_SUPPORT=y 46CONFIG_MMC_HS400_SUPPORT=y
48CONFIG_RENESAS_SDHI=y 47CONFIG_RENESAS_SDHI=y
49CONFIG_PHY_MICREL=y 48CONFIG_PHY_MICREL=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 5a8fc04e17..8f6a8f503a 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -41,7 +41,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y
41CONFIG_DM_MMC=y 41CONFIG_DM_MMC=y
42CONFIG_MMC_IO_VOLTAGE=y 42CONFIG_MMC_IO_VOLTAGE=y
43CONFIG_MMC_UHS_SUPPORT=y 43CONFIG_MMC_UHS_SUPPORT=y
44CONFIG_MMC_HS200_SUPPORT=y
45CONFIG_MMC_HS400_SUPPORT=y 44CONFIG_MMC_HS400_SUPPORT=y
46CONFIG_RENESAS_SDHI=y 45CONFIG_RENESAS_SDHI=y
47CONFIG_PHY_MICREL=y 46CONFIG_PHY_MICREL=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 1f00263bb4..32e92a5ca0 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -29,7 +29,6 @@ CONFIG_SPI=y
29CONFIG_MXC_SPI=y 29CONFIG_MXC_SPI=y
30CONFIG_DM_THERMAL=y 30CONFIG_DM_THERMAL=y
31CONFIG_USB=y 31CONFIG_USB=y
32CONFIG_USB_STORAGE=y
33CONFIG_USB_HOST_ETHER=y 32CONFIG_USB_HOST_ETHER=y
34CONFIG_USB_ETHER_ASIX=y 33CONFIG_USB_ETHER_ASIX=y
35CONFIG_VIDEO=y 34CONFIG_VIDEO=y
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
new file mode 100644
index 0000000000..82134698f9
--- /dev/null
+++ b/configs/riotboard_spl_defconfig
@@ -0,0 +1,47 @@
1CONFIG_ARM=y
2CONFIG_ARCH_MX6=y
3CONFIG_SYS_TEXT_BASE=0x17800000
4CONFIG_SPL_GPIO_SUPPORT=y
5CONFIG_SPL_LIBCOMMON_SUPPORT=y
6CONFIG_SPL_LIBGENERIC_SUPPORT=y
7CONFIG_TARGET_EMBESTMX6BOARDS=y
8CONFIG_SPL_MMC_SUPPORT=y
9CONFIG_SPL_SERIAL_SUPPORT=y
10CONFIG_SPL=y
11CONFIG_SPL_LIBDISK_SUPPORT=y
12CONFIG_DISTRO_DEFAULTS=y
13CONFIG_NR_DRAM_BANKS=1
14CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,MX6S,DDR_MB=1024"
15CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
16# CONFIG_CONSOLE_MUX is not set
17CONFIG_SYS_CONSOLE_IS_IN_ENV=y
18CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
19CONFIG_BOARD_EARLY_INIT_F=y
20CONFIG_SPL_RAW_IMAGE_SUPPORT=y
21CONFIG_SPL_EXT_SUPPORT=y
22CONFIG_SPL_OS_BOOT=y
23# CONFIG_CMD_FLASH is not set
24CONFIG_CMD_GPIO=y
25CONFIG_CMD_I2C=y
26CONFIG_CMD_MMC=y
27CONFIG_CMD_SF=y
28CONFIG_CMD_USB=y
29CONFIG_CMD_CACHE=y
30CONFIG_CMD_EXT4_WRITE=y
31CONFIG_ENV_IS_IN_MMC=y
32CONFIG_DM=y
33CONFIG_FSL_ESDHC=y
34CONFIG_SPI_FLASH=y
35CONFIG_SPI_FLASH_SST=y
36CONFIG_PHYLIB=y
37CONFIG_MII=y
38CONFIG_SPI=y
39CONFIG_MXC_SPI=y
40CONFIG_DM_THERMAL=y
41CONFIG_USB=y
42CONFIG_USB_HOST_ETHER=y
43CONFIG_USB_ETHER_ASIX=y
44CONFIG_VIDEO=y
45# CONFIG_VIDEO_SW_CURSOR is not set
46CONFIG_OF_LIBFDT=y
47CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 6289506bdd..702e8e91cb 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -71,7 +71,6 @@ CONFIG_SYSRESET=y
71CONFIG_USB=y 71CONFIG_USB=y
72CONFIG_USB_DWC2=y 72CONFIG_USB_DWC2=y
73CONFIG_ROCKCHIP_USB2_PHY=y 73CONFIG_ROCKCHIP_USB2_PHY=y
74CONFIG_USB_STORAGE=y
75CONFIG_USB_GADGET=y 74CONFIG_USB_GADGET=y
76CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 75CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
77CONFIG_USB_GADGET_VENDOR_NUM=0x2207 76CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index bb10ee9a43..caf0fcc8ff 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -9,22 +9,19 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
9CONFIG_TARGET_ROCK960_RK3399=y 9CONFIG_TARGET_ROCK960_RK3399=y
10CONFIG_DEBUG_UART_BASE=0xFF1A0000 10CONFIG_DEBUG_UART_BASE=0xFF1A0000
11CONFIG_DEBUG_UART_CLOCK=24000000 11CONFIG_DEBUG_UART_CLOCK=24000000
12CONFIG_DEBUG_UART_SHIFT=2
13CONFIG_BAUDRATE=1500000
14CONFIG_SPL_STACK_R_ADDR=0x80000 12CONFIG_SPL_STACK_R_ADDR=0x80000
15CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
16CONFIG_DEBUG_UART=y 13CONFIG_DEBUG_UART=y
17CONFIG_FIT=y 14CONFIG_FIT=y
18CONFIG_SPL_LOAD_FIT=y 15CONFIG_SPL_LOAD_FIT=y
19CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" 16CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
20CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" 17CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
21CONFIG_SYS_PROMPT="rock960 => "
22# CONFIG_DISPLAY_CPUINFO is not set 18# CONFIG_DISPLAY_CPUINFO is not set
23CONFIG_DISPLAY_BOARDINFO_LATE=y 19CONFIG_DISPLAY_BOARDINFO_LATE=y
24CONFIG_SPL_STACK_R=y 20CONFIG_SPL_STACK_R=y
25CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 21CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
26CONFIG_SPL_ATF=y 22CONFIG_SPL_ATF=y
27CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y 23CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
24CONFIG_SYS_PROMPT="rock960 => "
28CONFIG_CMD_BOOTZ=y 25CONFIG_CMD_BOOTZ=y
29CONFIG_CMD_GPT=y 26CONFIG_CMD_GPT=y
30CONFIG_CMD_MMC=y 27CONFIG_CMD_MMC=y
@@ -33,6 +30,7 @@ CONFIG_CMD_USB=y
33# CONFIG_CMD_SETEXPR is not set 30# CONFIG_CMD_SETEXPR is not set
34CONFIG_CMD_TIME=y 31CONFIG_CMD_TIME=y
35CONFIG_SPL_OF_CONTROL=y 32CONFIG_SPL_OF_CONTROL=y
33CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
36CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" 34CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
37CONFIG_ENV_IS_IN_MMC=y 35CONFIG_ENV_IS_IN_MMC=y
38CONFIG_REGMAP=y 36CONFIG_REGMAP=y
@@ -58,12 +56,12 @@ CONFIG_REGULATOR_RK8XX=y
58CONFIG_PWM_ROCKCHIP=y 56CONFIG_PWM_ROCKCHIP=y
59CONFIG_RAM=y 57CONFIG_RAM=y
60CONFIG_SPL_RAM=y 58CONFIG_SPL_RAM=y
59CONFIG_BAUDRATE=1500000
60CONFIG_DEBUG_UART_SHIFT=2
61CONFIG_SYSRESET=y 61CONFIG_SYSRESET=y
62CONFIG_USB=y 62CONFIG_USB=y
63CONFIG_USB_EHCI_HCD=y 63CONFIG_USB_EHCI_HCD=y
64CONFIG_USB_EHCI_GENERIC=y 64CONFIG_USB_EHCI_GENERIC=y
65CONFIG_USB_STORAGE=y
66CONFIG_ROCKCHIP_USB2_PHY=y 65CONFIG_ROCKCHIP_USB2_PHY=y
67CONFIG_USB_ETHER_ASIX=y
68CONFIG_USE_TINY_PRINTF=y 66CONFIG_USE_TINY_PRINTF=y
69CONFIG_ERRNO_STR=y 67CONFIG_ERRNO_STR=y
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index 66b0de31b6..39da54c3e7 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -30,7 +30,6 @@ CONFIG_PINCTRL=y
30CONFIG_USB=y 30CONFIG_USB=y
31CONFIG_DM_USB=y 31CONFIG_DM_USB=y
32CONFIG_USB_DWC2=y 32CONFIG_USB_DWC2=y
33CONFIG_USB_STORAGE=y
34CONFIG_USB_KEYBOARD=y 33CONFIG_USB_KEYBOARD=y
35CONFIG_USB_HOST_ETHER=y 34CONFIG_USB_HOST_ETHER=y
36CONFIG_USB_ETHER_SMSC95XX=y 35CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index ba75e52dda..5f5b40522d 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -30,7 +30,6 @@ CONFIG_PINCTRL=y
30CONFIG_USB=y 30CONFIG_USB=y
31CONFIG_DM_USB=y 31CONFIG_DM_USB=y
32CONFIG_USB_DWC2=y 32CONFIG_USB_DWC2=y
33CONFIG_USB_STORAGE=y
34CONFIG_USB_KEYBOARD=y 33CONFIG_USB_KEYBOARD=y
35CONFIG_USB_HOST_ETHER=y 34CONFIG_USB_HOST_ETHER=y
36CONFIG_USB_ETHER_SMSC95XX=y 35CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index bbcdd91e90..bbf902bb91 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -32,7 +32,6 @@ CONFIG_PINCTRL=y
32CONFIG_USB=y 32CONFIG_USB=y
33CONFIG_DM_USB=y 33CONFIG_DM_USB=y
34CONFIG_USB_DWC2=y 34CONFIG_USB_DWC2=y
35CONFIG_USB_STORAGE=y
36CONFIG_USB_KEYBOARD=y 35CONFIG_USB_KEYBOARD=y
37CONFIG_USB_HOST_ETHER=y 36CONFIG_USB_HOST_ETHER=y
38CONFIG_USB_ETHER_LAN78XX=y 37CONFIG_USB_ETHER_LAN78XX=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 54b6303c2d..ea40351dc4 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -32,7 +32,6 @@ CONFIG_PINCTRL=y
32CONFIG_USB=y 32CONFIG_USB=y
33CONFIG_DM_USB=y 33CONFIG_DM_USB=y
34CONFIG_USB_DWC2=y 34CONFIG_USB_DWC2=y
35CONFIG_USB_STORAGE=y
36CONFIG_USB_KEYBOARD=y 35CONFIG_USB_KEYBOARD=y
37CONFIG_USB_HOST_ETHER=y 36CONFIG_USB_HOST_ETHER=y
38CONFIG_USB_ETHER_LAN78XX=y 37CONFIG_USB_ETHER_LAN78XX=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index e7820cb147..981d17381a 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -30,7 +30,6 @@ CONFIG_PINCTRL=y
30CONFIG_USB=y 30CONFIG_USB=y
31CONFIG_DM_USB=y 31CONFIG_DM_USB=y
32CONFIG_USB_DWC2=y 32CONFIG_USB_DWC2=y
33CONFIG_USB_STORAGE=y
34CONFIG_USB_KEYBOARD=y 33CONFIG_USB_KEYBOARD=y
35CONFIG_USB_HOST_ETHER=y 34CONFIG_USB_HOST_ETHER=y
36CONFIG_USB_ETHER_SMSC95XX=y 35CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 08eafc235e..958d21b59d 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -69,8 +69,8 @@ CONFIG_SPI_FLASH=y
69CONFIG_SPI_FLASH_WINBOND=y 69CONFIG_SPI_FLASH_WINBOND=y
70CONFIG_MTD_UBI_FASTMAP=y 70CONFIG_MTD_UBI_FASTMAP=y
71CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 71CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
72CONFIG_DRIVER_TI_CPSW=y
73CONFIG_MII=y 72CONFIG_MII=y
73CONFIG_DRIVER_TI_CPSW=y
74CONFIG_SPI=y 74CONFIG_SPI=y
75CONFIG_OMAP3_SPI=y 75CONFIG_OMAP3_SPI=y
76CONFIG_USB=y 76CONFIG_USB=y
diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig
index 91a966327a..8c36f5dbf8 100644
--- a/configs/sagem_f@st1704_ram_defconfig
+++ b/configs/sagem_f@st1704_ram_defconfig
@@ -27,11 +27,14 @@ CONFIG_CMD_MEMINFO=y
27# CONFIG_CMD_LOADS is not set 27# CONFIG_CMD_LOADS is not set
28CONFIG_CMD_SF=y 28CONFIG_CMD_SF=y
29CONFIG_CMD_SPI=y 29CONFIG_CMD_SPI=y
30CONFIG_CMD_MII=y
31CONFIG_CMD_PING=y
30# CONFIG_CMD_MISC is not set 32# CONFIG_CMD_MISC is not set
31CONFIG_OF_EMBED=y 33CONFIG_OF_EMBED=y
32CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" 34CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
33# CONFIG_NET is not set 35CONFIG_NET_RANDOM_ETHADDR=y
34# CONFIG_DM_DEVICE_REMOVE is not set 36# CONFIG_DM_DEVICE_REMOVE is not set
37CONFIG_BCM6348_IUDMA=y
35CONFIG_DM_GPIO=y 38CONFIG_DM_GPIO=y
36CONFIG_BCM6345_GPIO=y 39CONFIG_BCM6345_GPIO=y
37CONFIG_LED=y 40CONFIG_LED=y
@@ -40,6 +43,9 @@ CONFIG_DM_SPI_FLASH=y
40CONFIG_SPI_FLASH=y 43CONFIG_SPI_FLASH=y
41CONFIG_SPI_FLASH_WINBOND=y 44CONFIG_SPI_FLASH_WINBOND=y
42CONFIG_SPI_FLASH_MTD=y 45CONFIG_SPI_FLASH_MTD=y
46CONFIG_PHY_FIXED=y
47CONFIG_DM_ETH=y
48CONFIG_BCM6348_ETH=y
43CONFIG_DM_RESET=y 49CONFIG_DM_RESET=y
44CONFIG_RESET_BCM6345=y 50CONFIG_RESET_BCM6345=y
45# CONFIG_SPL_SERIAL_PRESENT is not set 51# CONFIG_SPL_SERIAL_PRESENT is not set
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index aede14569d..236199d2a1 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -180,7 +180,6 @@ CONFIG_SANDBOX_TIMER=y
180CONFIG_USB=y 180CONFIG_USB=y
181CONFIG_DM_USB=y 181CONFIG_DM_USB=y
182CONFIG_USB_EMUL=y 182CONFIG_USB_EMUL=y
183CONFIG_USB_STORAGE=y
184CONFIG_USB_KEYBOARD=y 183CONFIG_USB_KEYBOARD=y
185CONFIG_DM_VIDEO=y 184CONFIG_DM_VIDEO=y
186CONFIG_CONSOLE_ROTATION=y 185CONFIG_CONSOLE_ROTATION=y
@@ -197,9 +196,7 @@ CONFIG_CMD_DHRYSTONE=y
197CONFIG_TPM=y 196CONFIG_TPM=y
198CONFIG_LZ4=y 197CONFIG_LZ4=y
199CONFIG_ERRNO_STR=y 198CONFIG_ERRNO_STR=y
200CONFIG_OF_LIBFDT_OVERLAY=y
201CONFIG_UNIT_TEST=y 199CONFIG_UNIT_TEST=y
202CONFIG_UT_TIME=y 200CONFIG_UT_TIME=y
203CONFIG_UT_DM=y 201CONFIG_UT_DM=y
204CONFIG_UT_ENV=y 202CONFIG_UT_ENV=y
205CONFIG_UT_OVERLAY=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index c5f1ebee04..f628819ed5 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -95,6 +95,9 @@ CONFIG_DM_DEMO_SIMPLE=y
95CONFIG_DM_DEMO_SHAPE=y 95CONFIG_DM_DEMO_SHAPE=y
96CONFIG_BOARD=y 96CONFIG_BOARD=y
97CONFIG_BOARD_SANDBOX=y 97CONFIG_BOARD_SANDBOX=y
98CONFIG_DMA=y
99CONFIG_DMA_CHANNELS=y
100CONFIG_SANDBOX_DMA=y
98CONFIG_PM8916_GPIO=y 101CONFIG_PM8916_GPIO=y
99CONFIG_SANDBOX_GPIO=y 102CONFIG_SANDBOX_GPIO=y
100CONFIG_DM_HWSPINLOCK=y 103CONFIG_DM_HWSPINLOCK=y
@@ -192,7 +195,6 @@ CONFIG_SANDBOX_TIMER=y
192CONFIG_USB=y 195CONFIG_USB=y
193CONFIG_DM_USB=y 196CONFIG_DM_USB=y
194CONFIG_USB_EMUL=y 197CONFIG_USB_EMUL=y
195CONFIG_USB_STORAGE=y
196CONFIG_USB_KEYBOARD=y 198CONFIG_USB_KEYBOARD=y
197CONFIG_DM_VIDEO=y 199CONFIG_DM_VIDEO=y
198CONFIG_CONSOLE_ROTATION=y 200CONFIG_CONSOLE_ROTATION=y
@@ -213,12 +215,7 @@ CONFIG_CMD_DHRYSTONE=y
213CONFIG_TPM=y 215CONFIG_TPM=y
214CONFIG_LZ4=y 216CONFIG_LZ4=y
215CONFIG_ERRNO_STR=y 217CONFIG_ERRNO_STR=y
216CONFIG_OF_LIBFDT_OVERLAY=y
217CONFIG_UNIT_TEST=y 218CONFIG_UNIT_TEST=y
218CONFIG_UT_TIME=y 219CONFIG_UT_TIME=y
219CONFIG_UT_DM=y 220CONFIG_UT_DM=y
220CONFIG_UT_ENV=y 221CONFIG_UT_ENV=y
221CONFIG_UT_OVERLAY=y
222CONFIG_DMA=y
223CONFIG_DMA_CHANNELS=y
224CONFIG_SANDBOX_DMA=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 4f3757c8bc..63e3745522 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -162,7 +162,6 @@ CONFIG_SANDBOX_TIMER=y
162CONFIG_USB=y 162CONFIG_USB=y
163CONFIG_DM_USB=y 163CONFIG_DM_USB=y
164CONFIG_USB_EMUL=y 164CONFIG_USB_EMUL=y
165CONFIG_USB_STORAGE=y
166CONFIG_USB_KEYBOARD=y 165CONFIG_USB_KEYBOARD=y
167CONFIG_DM_VIDEO=y 166CONFIG_DM_VIDEO=y
168CONFIG_CONSOLE_ROTATION=y 167CONFIG_CONSOLE_ROTATION=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 6c7d08e42e..1a30e53f6f 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -161,7 +161,6 @@ CONFIG_SANDBOX_TIMER=y
161CONFIG_USB=y 161CONFIG_USB=y
162CONFIG_DM_USB=y 162CONFIG_DM_USB=y
163CONFIG_USB_EMUL=y 163CONFIG_USB_EMUL=y
164CONFIG_USB_STORAGE=y
165CONFIG_USB_KEYBOARD=y 164CONFIG_USB_KEYBOARD=y
166CONFIG_DM_VIDEO=y 165CONFIG_DM_VIDEO=y
167CONFIG_CONSOLE_ROTATION=y 166CONFIG_CONSOLE_ROTATION=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 2f83812528..012f3342ac 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -180,7 +180,6 @@ CONFIG_SANDBOX_TIMER=y
180CONFIG_USB=y 180CONFIG_USB=y
181CONFIG_DM_USB=y 181CONFIG_DM_USB=y
182CONFIG_USB_EMUL=y 182CONFIG_USB_EMUL=y
183CONFIG_USB_STORAGE=y
184CONFIG_USB_KEYBOARD=y 183CONFIG_USB_KEYBOARD=y
185CONFIG_DM_VIDEO=y 184CONFIG_DM_VIDEO=y
186CONFIG_CONSOLE_ROTATION=y 185CONFIG_CONSOLE_ROTATION=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 69e159b43e..5715665810 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -33,7 +33,6 @@ CONFIG_DM_USB=y
33CONFIG_USB_EHCI_HCD=y 33CONFIG_USB_EHCI_HCD=y
34CONFIG_USB_ULPI_VIEWPORT=y 34CONFIG_USB_ULPI_VIEWPORT=y
35CONFIG_USB_ULPI=y 35CONFIG_USB_ULPI=y
36CONFIG_USB_STORAGE=y
37CONFIG_USB_KEYBOARD=y 36CONFIG_USB_KEYBOARD=y
38CONFIG_USB_HOST_ETHER=y 37CONFIG_USB_HOST_ETHER=y
39CONFIG_USB_ETHER_ASIX=y 38CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig
index 12adfb01e7..39622875b1 100644
--- a/configs/sfr_nb4-ser_ram_defconfig
+++ b/configs/sfr_nb4-ser_ram_defconfig
@@ -26,11 +26,14 @@ CONFIG_CMD_LICENSE=y
26CONFIG_CMD_MEMINFO=y 26CONFIG_CMD_MEMINFO=y
27# CONFIG_CMD_LOADS is not set 27# CONFIG_CMD_LOADS is not set
28CONFIG_CMD_USB=y 28CONFIG_CMD_USB=y
29CONFIG_CMD_MII=y
30CONFIG_CMD_PING=y
29# CONFIG_CMD_MISC is not set 31# CONFIG_CMD_MISC is not set
30CONFIG_OF_EMBED=y 32CONFIG_OF_EMBED=y
31CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" 33CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
32# CONFIG_NET is not set 34CONFIG_NET_RANDOM_ETHADDR=y
33# CONFIG_DM_DEVICE_REMOVE is not set 35# CONFIG_DM_DEVICE_REMOVE is not set
36CONFIG_BCM6348_IUDMA=y
34CONFIG_DM_GPIO=y 37CONFIG_DM_GPIO=y
35CONFIG_BCM6345_GPIO=y 38CONFIG_BCM6345_GPIO=y
36CONFIG_LED=y 39CONFIG_LED=y
@@ -42,6 +45,9 @@ CONFIG_FLASH_CFI_DRIVER=y
42CONFIG_CFI_FLASH=y 45CONFIG_CFI_FLASH=y
43CONFIG_SYS_FLASH_PROTECTION=y 46CONFIG_SYS_FLASH_PROTECTION=y
44CONFIG_SYS_FLASH_CFI=y 47CONFIG_SYS_FLASH_CFI=y
48CONFIG_PHY_FIXED=y
49CONFIG_DM_ETH=y
50CONFIG_BCM6348_ETH=y
45CONFIG_PHY=y 51CONFIG_PHY=y
46CONFIG_BCM6358_USBH_PHY=y 52CONFIG_BCM6358_USBH_PHY=y
47CONFIG_DM_RESET=y 53CONFIG_DM_RESET=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index e9c2b63509..7c7220afc8 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -57,8 +57,8 @@ CONFIG_USB_GADGET_DOWNLOAD=y
57CONFIG_USB_HOST_ETHER=y 57CONFIG_USB_HOST_ETHER=y
58CONFIG_USB_ETHER_ASIX=y 58CONFIG_USB_ETHER_ASIX=y
59CONFIG_USB_ETHER_MCS7830=y 59CONFIG_USB_ETHER_MCS7830=y
60CONFIG_SPL_TINY_MEMSET=y
61# CONFIG_EFI_LOADER is not set
62CONFIG_WDT=y 60CONFIG_WDT=y
63CONFIG_WDT_AT91=y 61CONFIG_WDT_AT91=y
64CONFIG_AT91_HW_WDT_TIMEOUT=y 62CONFIG_AT91_HW_WDT_TIMEOUT=y
63CONFIG_SPL_TINY_MEMSET=y
64# CONFIG_EFI_LOADER is not set
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 21018d8b1b..c86fde7399 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -53,7 +53,6 @@ CONFIG_DM_USB=y
53CONFIG_USB_XHCI_HCD=y 53CONFIG_USB_XHCI_HCD=y
54CONFIG_USB_XHCI_DWC3=y 54CONFIG_USB_XHCI_DWC3=y
55CONFIG_USB_EHCI_HCD=y 55CONFIG_USB_EHCI_HCD=y
56CONFIG_USB_STORAGE=y
57CONFIG_USB_HOST_ETHER=y 56CONFIG_USB_HOST_ETHER=y
58CONFIG_USB_ETHER_ASIX88179=y 57CONFIG_USB_ETHER_ASIX88179=y
59CONFIG_VIDEO_BRIDGE=y 58CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 4e4558944c..e92472ecc7 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -40,6 +40,5 @@ CONFIG_USB=y
40CONFIG_DM_USB=y 40CONFIG_DM_USB=y
41CONFIG_USB_XHCI_HCD=y 41CONFIG_USB_XHCI_HCD=y
42CONFIG_USB_XHCI_DWC3=y 42CONFIG_USB_XHCI_DWC3=y
43CONFIG_USB_STORAGE=y
44CONFIG_USB_HOST_ETHER=y 43CONFIG_USB_HOST_ETHER=y
45CONFIG_VIDEO_BRIDGE=y 44CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index e0c1bf862c..86a668ff33 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -71,7 +71,6 @@ CONFIG_DM_USB=y
71CONFIG_USB_XHCI_HCD=y 71CONFIG_USB_XHCI_HCD=y
72CONFIG_USB_XHCI_DWC3=y 72CONFIG_USB_XHCI_DWC3=y
73CONFIG_USB_EHCI_HCD=y 73CONFIG_USB_EHCI_HCD=y
74CONFIG_USB_STORAGE=y
75CONFIG_USB_HOST_ETHER=y 74CONFIG_USB_HOST_ETHER=y
76CONFIG_USB_ETHER_ASIX88179=y 75CONFIG_USB_ETHER_ASIX88179=y
77CONFIG_DM_VIDEO=y 76CONFIG_DM_VIDEO=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index e7e1121c5c..0e5e74a621 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -67,7 +67,6 @@ CONFIG_DESIGNWARE_SPI=y
67CONFIG_USB=y 67CONFIG_USB=y
68CONFIG_DM_USB=y 68CONFIG_DM_USB=y
69CONFIG_USB_DWC2=y 69CONFIG_USB_DWC2=y
70CONFIG_USB_STORAGE=y
71CONFIG_USB_GADGET=y 70CONFIG_USB_GADGET=y
72CONFIG_USB_GADGET_MANUFACTURER="altera" 71CONFIG_USB_GADGET_MANUFACTURER="altera"
73CONFIG_USB_GADGET_VENDOR_NUM=0x0525 72CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 8989c4dc96..e8de0f5709 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -68,7 +68,6 @@ CONFIG_DESIGNWARE_SPI=y
68CONFIG_USB=y 68CONFIG_USB=y
69CONFIG_DM_USB=y 69CONFIG_DM_USB=y
70CONFIG_USB_DWC2=y 70CONFIG_USB_DWC2=y
71CONFIG_USB_STORAGE=y
72CONFIG_USB_GADGET=y 71CONFIG_USB_GADGET=y
73CONFIG_USB_GADGET_MANUFACTURER="altera" 72CONFIG_USB_GADGET_MANUFACTURER="altera"
74CONFIG_USB_GADGET_VENDOR_NUM=0x0525 73CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 1a9f2b6038..9a89bb5d68 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -62,7 +62,6 @@ CONFIG_DESIGNWARE_SPI=y
62CONFIG_USB=y 62CONFIG_USB=y
63CONFIG_DM_USB=y 63CONFIG_DM_USB=y
64CONFIG_USB_DWC2=y 64CONFIG_USB_DWC2=y
65CONFIG_USB_STORAGE=y
66CONFIG_USB_GADGET=y 65CONFIG_USB_GADGET=y
67CONFIG_USB_GADGET_MANUFACTURER="terasic" 66CONFIG_USB_GADGET_MANUFACTURER="terasic"
68CONFIG_USB_GADGET_VENDOR_NUM=0x0525 67CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index c9490d47a4..db516891ba 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -58,7 +58,6 @@ CONFIG_DESIGNWARE_SPI=y
58CONFIG_USB=y 58CONFIG_USB=y
59CONFIG_DM_USB=y 59CONFIG_DM_USB=y
60CONFIG_USB_DWC2=y 60CONFIG_USB_DWC2=y
61CONFIG_USB_STORAGE=y
62CONFIG_USB_GADGET=y 61CONFIG_USB_GADGET=y
63CONFIG_USB_GADGET_MANUFACTURER="terasic" 62CONFIG_USB_GADGET_MANUFACTURER="terasic"
64CONFIG_USB_GADGET_VENDOR_NUM=0x0525 63CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index b6c8e6c84d..5bed755723 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -55,6 +55,5 @@ CONFIG_SPI=y
55CONFIG_USB=y 55CONFIG_USB=y
56CONFIG_DM_USB=y 56CONFIG_DM_USB=y
57CONFIG_USB_DWC2=y 57CONFIG_USB_DWC2=y
58CONFIG_USB_STORAGE=y
59CONFIG_USE_TINY_PRINTF=y 58CONFIG_USE_TINY_PRINTF=y
60# CONFIG_EFI_LOADER is not set 59# CONFIG_EFI_LOADER is not set
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 66f7733ee8..abbbcb94d3 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -68,7 +68,6 @@ CONFIG_DESIGNWARE_SPI=y
68CONFIG_USB=y 68CONFIG_USB=y
69CONFIG_DM_USB=y 69CONFIG_DM_USB=y
70CONFIG_USB_DWC2=y 70CONFIG_USB_DWC2=y
71CONFIG_USB_STORAGE=y
72CONFIG_USB_GADGET=y 71CONFIG_USB_GADGET=y
73CONFIG_USB_GADGET_MANUFACTURER="terasic" 72CONFIG_USB_GADGET_MANUFACTURER="terasic"
74CONFIG_USB_GADGET_VENDOR_NUM=0x0525 73CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 05f38cbcd2..53f8d3c348 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -68,7 +68,6 @@ CONFIG_DESIGNWARE_SPI=y
68CONFIG_USB=y 68CONFIG_USB=y
69CONFIG_DM_USB=y 69CONFIG_DM_USB=y
70CONFIG_USB_DWC2=y 70CONFIG_USB_DWC2=y
71CONFIG_USB_STORAGE=y
72CONFIG_USB_GADGET=y 71CONFIG_USB_GADGET=y
73CONFIG_USB_GADGET_MANUFACTURER="ebv" 72CONFIG_USB_GADGET_MANUFACTURER="ebv"
74CONFIG_USB_GADGET_VENDOR_NUM=0x0525 73CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 6fcf8c66f8..3eba09dcb1 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -84,7 +84,6 @@ CONFIG_DESIGNWARE_SPI=y
84CONFIG_USB=y 84CONFIG_USB=y
85CONFIG_DM_USB=y 85CONFIG_DM_USB=y
86CONFIG_USB_DWC2=y 86CONFIG_USB_DWC2=y
87CONFIG_USB_STORAGE=y
88CONFIG_USB_GADGET=y 87CONFIG_USB_GADGET=y
89CONFIG_USB_GADGET_MANUFACTURER="samtec" 88CONFIG_USB_GADGET_MANUFACTURER="samtec"
90CONFIG_USB_GADGET_VENDOR_NUM=0x0525 89CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index bc0c3ec091..cb115fecb7 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -27,3 +27,5 @@ CONFIG_PHY_GIGE=y
27CONFIG_ETH_DESIGNWARE=y 27CONFIG_ETH_DESIGNWARE=y
28CONFIG_MII=y 28CONFIG_MII=y
29CONFIG_CONS_INDEX=0 29CONFIG_CONS_INDEX=0
30CONFIG_USB=y
31CONFIG_USB_GADGET=y
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index 9b90cd8638..4064ba36e9 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -28,3 +28,5 @@ CONFIG_PHY_GIGE=y
28CONFIG_ETH_DESIGNWARE=y 28CONFIG_ETH_DESIGNWARE=y
29CONFIG_MII=y 29CONFIG_MII=y
30CONFIG_CONS_INDEX=0 30CONFIG_CONS_INDEX=0
31CONFIG_USB=y
32CONFIG_USB_GADGET=y
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index 7786e66998..9373df83f7 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -27,3 +27,5 @@ CONFIG_PHY_GIGE=y
27CONFIG_ETH_DESIGNWARE=y 27CONFIG_ETH_DESIGNWARE=y
28CONFIG_MII=y 28CONFIG_MII=y
29CONFIG_CONS_INDEX=0 29CONFIG_CONS_INDEX=0
30CONFIG_USB=y
31CONFIG_USB_GADGET=y
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index 1d41522b2a..a4f09a2735 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -28,3 +28,5 @@ CONFIG_PHY_GIGE=y
28CONFIG_ETH_DESIGNWARE=y 28CONFIG_ETH_DESIGNWARE=y
29CONFIG_MII=y 29CONFIG_MII=y
30CONFIG_CONS_INDEX=0 30CONFIG_CONS_INDEX=0
31CONFIG_USB=y
32CONFIG_USB_GADGET=y
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index b5214b5d82..8263454de6 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -30,3 +30,5 @@ CONFIG_PHY_GIGE=y
30CONFIG_ETH_DESIGNWARE=y 30CONFIG_ETH_DESIGNWARE=y
31CONFIG_MII=y 31CONFIG_MII=y
32CONFIG_CONS_INDEX=0 32CONFIG_CONS_INDEX=0
33CONFIG_USB=y
34CONFIG_USB_GADGET=y
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index 3c10f3261e..80acff0cce 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -27,3 +27,5 @@ CONFIG_PHY_GIGE=y
27CONFIG_ETH_DESIGNWARE=y 27CONFIG_ETH_DESIGNWARE=y
28CONFIG_MII=y 28CONFIG_MII=y
29CONFIG_CONS_INDEX=0 29CONFIG_CONS_INDEX=0
30CONFIG_USB=y
31CONFIG_USB_GADGET=y
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index 8fb84bcc60..00534b1c24 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -28,3 +28,5 @@ CONFIG_PHY_GIGE=y
28CONFIG_ETH_DESIGNWARE=y 28CONFIG_ETH_DESIGNWARE=y
29CONFIG_MII=y 29CONFIG_MII=y
30CONFIG_CONS_INDEX=0 30CONFIG_CONS_INDEX=0
31CONFIG_USB=y
32CONFIG_USB_GADGET=y
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index 2cf39b450c..916321c60c 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -30,3 +30,5 @@ CONFIG_PHY_GIGE=y
30CONFIG_ETH_DESIGNWARE=y 30CONFIG_ETH_DESIGNWARE=y
31CONFIG_MII=y 31CONFIG_MII=y
32CONFIG_CONS_INDEX=0 32CONFIG_CONS_INDEX=0
33CONFIG_USB=y
34CONFIG_USB_GADGET=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index 5c7b0a8ab4..d0bdc7587d 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -27,3 +27,5 @@ CONFIG_PHY_GIGE=y
27CONFIG_ETH_DESIGNWARE=y 27CONFIG_ETH_DESIGNWARE=y
28CONFIG_MII=y 28CONFIG_MII=y
29CONFIG_CONS_INDEX=0 29CONFIG_CONS_INDEX=0
30CONFIG_USB=y
31CONFIG_USB_GADGET=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index 078e934bba..ccbfec9298 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -28,3 +28,5 @@ CONFIG_PHY_GIGE=y
28CONFIG_ETH_DESIGNWARE=y 28CONFIG_ETH_DESIGNWARE=y
29CONFIG_MII=y 29CONFIG_MII=y
30CONFIG_CONS_INDEX=0 30CONFIG_CONS_INDEX=0
31CONFIG_USB=y
32CONFIG_USB_GADGET=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index c089517692..5c5569acd2 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -71,7 +71,6 @@ CONFIG_DM_USB=y
71CONFIG_USB_XHCI_HCD=y 71CONFIG_USB_XHCI_HCD=y
72CONFIG_USB_XHCI_DWC3=y 72CONFIG_USB_XHCI_DWC3=y
73CONFIG_USB_EHCI_HCD=y 73CONFIG_USB_EHCI_HCD=y
74CONFIG_USB_STORAGE=y
75CONFIG_USB_HOST_ETHER=y 74CONFIG_USB_HOST_ETHER=y
76CONFIG_USB_ETHER_ASIX88179=y 75CONFIG_USB_ETHER_ASIX88179=y
77CONFIG_DM_VIDEO=y 76CONFIG_DM_VIDEO=y
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index 2df8cc3732..2326bf9481 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -48,7 +48,6 @@ CONFIG_USB_OHCI_HCD=y
48CONFIG_USB_OHCI_GENERIC=y 48CONFIG_USB_OHCI_GENERIC=y
49CONFIG_USB_DWC3=y 49CONFIG_USB_DWC3=y
50CONFIG_USB_DWC3_GADGET=y 50CONFIG_USB_DWC3_GADGET=y
51CONFIG_USB_STORAGE=y
52CONFIG_USB_GADGET=y 51CONFIG_USB_GADGET=y
53CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" 52CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
54CONFIG_USB_GADGET_VENDOR_NUM=0x483 53CONFIG_USB_GADGET_VENDOR_NUM=0x483
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index c8409fd04e..304688e56f 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -58,7 +58,6 @@ CONFIG_DM_USB=y
58CONFIG_USB_EHCI_HCD=y 58CONFIG_USB_EHCI_HCD=y
59CONFIG_USB_EHCI_GENERIC=y 59CONFIG_USB_EHCI_GENERIC=y
60CONFIG_USB_DWC2=y 60CONFIG_USB_DWC2=y
61CONFIG_USB_STORAGE=y
62CONFIG_USB_GADGET=y 61CONFIG_USB_GADGET=y
63CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" 62CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
64CONFIG_USB_GADGET_VENDOR_NUM=0x0483 63CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 05a992e646..c4bca0636f 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -53,7 +53,6 @@ CONFIG_USB=y
53CONFIG_USB_EHCI_HCD=y 53CONFIG_USB_EHCI_HCD=y
54CONFIG_USB_ULPI_VIEWPORT=y 54CONFIG_USB_ULPI_VIEWPORT=y
55CONFIG_USB_ULPI=y 55CONFIG_USB_ULPI=y
56CONFIG_USB_STORAGE=y
57CONFIG_USB_GADGET=y 56CONFIG_USB_GADGET=y
58CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 57CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
59CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 58CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index e53e075d48..022b0b6da1 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -60,7 +60,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
60CONFIG_USB_GADGET_VENDOR_NUM=0x0908 60CONFIG_USB_GADGET_VENDOR_NUM=0x0908
61CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 61CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
62CONFIG_USB_GADGET_DOWNLOAD=y 62CONFIG_USB_GADGET_DOWNLOAD=y
63CONFIG_USE_TINY_PRINTF=y
64CONFIG_WDT=y 63CONFIG_WDT=y
65CONFIG_WDT_AT91=y 64CONFIG_WDT_AT91=y
66CONFIG_AT91_HW_WDT_TIMEOUT=y 65CONFIG_AT91_HW_WDT_TIMEOUT=y
66CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 55cd9bd998..fc15dcf013 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000
5CONFIG_TARGET_TBS2910=y 5CONFIG_TARGET_TBS2910=y
6CONFIG_CMD_HDMIDETECT=y 6CONFIG_CMD_HDMIDETECT=y
7CONFIG_NR_DRAM_BANKS=1 7CONFIG_NR_DRAM_BANKS=1
8CONFIG_FIT=y
9CONFIG_BOOTDELAY=3 8CONFIG_BOOTDELAY=3
10CONFIG_PRE_CONSOLE_BUFFER=y 9CONFIG_PRE_CONSOLE_BUFFER=y
11CONFIG_PRE_CON_BUF_ADDR=0x7c000000 10CONFIG_PRE_CON_BUF_ADDR=0x7c000000
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 65ac1c2e5b..250d7f0250 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -31,6 +31,5 @@ CONFIG_TEGRA20_SLINK=y
31CONFIG_USB=y 31CONFIG_USB=y
32CONFIG_DM_USB=y 32CONFIG_DM_USB=y
33CONFIG_USB_EHCI_HCD=y 33CONFIG_USB_EHCI_HCD=y
34CONFIG_USB_STORAGE=y
35CONFIG_USB_HOST_ETHER=y 34CONFIG_USB_HOST_ETHER=y
36CONFIG_USB_ETHER_SMSC95XX=y 35CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 62526a7470..c5bb4955af 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -32,7 +32,6 @@ CONFIG_SYS_NS16550=y
32CONFIG_USB=y 32CONFIG_USB=y
33CONFIG_DM_USB=y 33CONFIG_DM_USB=y
34CONFIG_USB_EHCI_HCD=y 34CONFIG_USB_EHCI_HCD=y
35CONFIG_USB_STORAGE=y
36CONFIG_USB_HOST_ETHER=y 35CONFIG_USB_HOST_ETHER=y
37CONFIG_USB_ETHER_SMSC95XX=y 36CONFIG_USB_ETHER_SMSC95XX=y
38CONFIG_DM_VIDEO=y 37CONFIG_DM_VIDEO=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index b78dc7e017..8866d6d0e2 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -36,7 +36,7 @@ CONFIG_CMD_EXT2=y
36CONFIG_CMD_FAT=y 36CONFIG_CMD_FAT=y
37CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y 37CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
38CONFIG_MMC_OMAP_HS=y 38CONFIG_MMC_OMAP_HS=y
39CONFIG_DRIVER_TI_CPSW=y
40CONFIG_MII=y 39CONFIG_MII=y
40CONFIG_DRIVER_TI_CPSW=y
41CONFIG_SYS_NS16550=y 41CONFIG_SYS_NS16550=y
42CONFIG_OF_LIBFDT=y 42CONFIG_OF_LIBFDT=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 5a69a68384..e0fc1875ee 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -73,7 +73,6 @@ CONFIG_SYSRESET=y
73CONFIG_USB=y 73CONFIG_USB=y
74CONFIG_USB_DWC2=y 74CONFIG_USB_DWC2=y
75CONFIG_ROCKCHIP_USB2_PHY=y 75CONFIG_ROCKCHIP_USB2_PHY=y
76CONFIG_USB_STORAGE=y
77CONFIG_USB_GADGET=y 76CONFIG_USB_GADGET=y
78CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 77CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
79CONFIG_USB_GADGET_VENDOR_NUM=0x2207 78CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 6bdfd63c8e..70d07ac041 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -50,7 +50,6 @@ CONFIG_USB=y
50CONFIG_USB_EHCI_HCD=y 50CONFIG_USB_EHCI_HCD=y
51CONFIG_USB_ULPI_VIEWPORT=y 51CONFIG_USB_ULPI_VIEWPORT=y
52CONFIG_USB_ULPI=y 52CONFIG_USB_ULPI=y
53CONFIG_USB_STORAGE=y
54CONFIG_USB_GADGET=y 53CONFIG_USB_GADGET=y
55CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 54CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
56CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 55CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 4486975f95..387f4cae08 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -51,7 +51,6 @@ CONFIG_USB=y
51CONFIG_USB_EHCI_HCD=y 51CONFIG_USB_EHCI_HCD=y
52CONFIG_USB_ULPI_VIEWPORT=y 52CONFIG_USB_ULPI_VIEWPORT=y
53CONFIG_USB_ULPI=y 53CONFIG_USB_ULPI=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 55CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
57CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 56CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index ee83f0545b..d820fff501 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -51,7 +51,6 @@ CONFIG_USB=y
51CONFIG_USB_EHCI_HCD=y 51CONFIG_USB_EHCI_HCD=y
52CONFIG_USB_ULPI_VIEWPORT=y 52CONFIG_USB_ULPI_VIEWPORT=y
53CONFIG_USB_ULPI=y 53CONFIG_USB_ULPI=y
54CONFIG_USB_STORAGE=y
55CONFIG_USB_GADGET=y 54CONFIG_USB_GADGET=y
56CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 55CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
57CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 56CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 6dfb3fbda8..71bfbfc54e 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -37,6 +37,5 @@ CONFIG_TEGRA20_SFLASH=y
37CONFIG_USB=y 37CONFIG_USB=y
38CONFIG_DM_USB=y 38CONFIG_DM_USB=y
39CONFIG_USB_EHCI_HCD=y 39CONFIG_USB_EHCI_HCD=y
40CONFIG_USB_STORAGE=y
41CONFIG_USB_HOST_ETHER=y 40CONFIG_USB_HOST_ETHER=y
42CONFIG_USB_ETHER_ASIX=y 41CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index 749ed31acd..c428bba5c9 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -67,7 +67,6 @@ CONFIG_USB=y
67CONFIG_DM_USB=y 67CONFIG_DM_USB=y
68CONFIG_USB_XHCI_HCD=y 68CONFIG_USB_XHCI_HCD=y
69CONFIG_USB_EHCI_HCD=y 69CONFIG_USB_EHCI_HCD=y
70CONFIG_USB_STORAGE=y
71CONFIG_USB_HOST_ETHER=y 70CONFIG_USB_HOST_ETHER=y
72CONFIG_USB_ETHER_ASIX=y 71CONFIG_USB_ETHER_ASIX=y
73CONFIG_USB_ETHER_MCS7830=y 72CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index aad8044782..4a1e23c86c 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -51,6 +51,5 @@ CONFIG_KIRKWOOD_SPI=y
51CONFIG_USB=y 51CONFIG_USB=y
52CONFIG_DM_USB=y 52CONFIG_DM_USB=y
53CONFIG_USB_EHCI_HCD=y 53CONFIG_USB_EHCI_HCD=y
54CONFIG_USB_STORAGE=y
55CONFIG_WDT=y 54CONFIG_WDT=y
56CONFIG_WDT_ORION=y 55CONFIG_WDT_ORION=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 6b9e22ac0e..48f7ac4c87 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -9,6 +9,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
9CONFIG_MICRO_SUPPORT_CARD=y 9CONFIG_MICRO_SUPPORT_CARD=y
10CONFIG_NR_DRAM_BANKS=3 10CONFIG_NR_DRAM_BANKS=3
11# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set 11# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
12CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
12CONFIG_LOGLEVEL=6 13CONFIG_LOGLEVEL=6
13CONFIG_SPL_NAND_SUPPORT=y 14CONFIG_SPL_NAND_SUPPORT=y
14CONFIG_SPL_NOR_SUPPORT=y 15CONFIG_SPL_NOR_SUPPORT=y
@@ -49,6 +50,5 @@ CONFIG_SMC911X_32_BIT=y
49CONFIG_USB=y 50CONFIG_USB=y
50CONFIG_USB_EHCI_HCD=y 51CONFIG_USB_EHCI_HCD=y
51CONFIG_USB_EHCI_GENERIC=y 52CONFIG_USB_EHCI_GENERIC=y
52CONFIG_USB_STORAGE=y
53CONFIG_PANIC_HANG=y 53CONFIG_PANIC_HANG=y
54CONFIG_FDT_FIXUP_PARTITIONS=y 54CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 4c06f272b1..f7abf05c52 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL=y
8CONFIG_MICRO_SUPPORT_CARD=y 8CONFIG_MICRO_SUPPORT_CARD=y
9CONFIG_NR_DRAM_BANKS=3 9CONFIG_NR_DRAM_BANKS=3
10# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set 10# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
11CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
11CONFIG_LOGLEVEL=6 12CONFIG_LOGLEVEL=6
12CONFIG_SPL_NAND_SUPPORT=y 13CONFIG_SPL_NAND_SUPPORT=y
13CONFIG_SPL_NOR_SUPPORT=y 14CONFIG_SPL_NOR_SUPPORT=y
@@ -51,6 +52,5 @@ CONFIG_USB_EHCI_HCD=y
51CONFIG_USB_EHCI_GENERIC=y 52CONFIG_USB_EHCI_GENERIC=y
52CONFIG_USB_DWC3=y 53CONFIG_USB_DWC3=y
53CONFIG_USB_DWC3_UNIPHIER=y 54CONFIG_USB_DWC3_UNIPHIER=y
54CONFIG_USB_STORAGE=y
55CONFIG_PANIC_HANG=y 55CONFIG_PANIC_HANG=y
56CONFIG_FDT_FIXUP_PARTITIONS=y 56CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index f8f9bdf05c..1ba1c7d508 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -7,6 +7,7 @@ CONFIG_ARCH_UNIPHIER_V8_MULTI=y
7CONFIG_MICRO_SUPPORT_CARD=y 7CONFIG_MICRO_SUPPORT_CARD=y
8CONFIG_NR_DRAM_BANKS=3 8CONFIG_NR_DRAM_BANKS=3
9# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set 9# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
10CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
10CONFIG_LOGLEVEL=6 11CONFIG_LOGLEVEL=6
11CONFIG_CMD_CONFIG=y 12CONFIG_CMD_CONFIG=y
12CONFIG_CMD_IMLS=y 13CONFIG_CMD_IMLS=y
@@ -52,6 +53,5 @@ CONFIG_USB_EHCI_HCD=y
52CONFIG_USB_EHCI_GENERIC=y 53CONFIG_USB_EHCI_GENERIC=y
53CONFIG_USB_DWC3=y 54CONFIG_USB_DWC3=y
54CONFIG_USB_DWC3_UNIPHIER=y 55CONFIG_USB_DWC3_UNIPHIER=y
55CONFIG_USB_STORAGE=y
56CONFIG_PANIC_HANG=y 56CONFIG_PANIC_HANG=y
57CONFIG_FDT_FIXUP_PARTITIONS=y 57CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 4bac8f1fe6..b1f872405b 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -15,5 +15,4 @@ CONFIG_CMD_USB=y
15CONFIG_ENV_IS_IN_MMC=y 15CONFIG_ENV_IS_IN_MMC=y
16CONFIG_FSL_ESDHC=y 16CONFIG_FSL_ESDHC=y
17CONFIG_USB=y 17CONFIG_USB=y
18CONFIG_USB_STORAGE=y
19CONFIG_OF_LIBFDT=y 18CONFIG_OF_LIBFDT=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 12043180c0..856398b377 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -35,7 +35,6 @@ CONFIG_TEGRA114_SPI=y
35CONFIG_USB=y 35CONFIG_USB=y
36CONFIG_DM_USB=y 36CONFIG_DM_USB=y
37CONFIG_USB_EHCI_HCD=y 37CONFIG_USB_EHCI_HCD=y
38CONFIG_USB_STORAGE=y
39CONFIG_USB_GADGET=y 38CONFIG_USB_GADGET=y
40CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" 39CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
41CONFIG_USB_GADGET_VENDOR_NUM=0x0955 40CONFIG_USB_GADGET_VENDOR_NUM=0x0955
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index a7c8bcd706..2d63b219cf 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -31,7 +31,6 @@ CONFIG_DM_USB=y
31CONFIG_USB_EHCI_HCD=y 31CONFIG_USB_EHCI_HCD=y
32CONFIG_USB_ULPI_VIEWPORT=y 32CONFIG_USB_ULPI_VIEWPORT=y
33CONFIG_USB_ULPI=y 33CONFIG_USB_ULPI=y
34CONFIG_USB_STORAGE=y
35CONFIG_USB_KEYBOARD=y 34CONFIG_USB_KEYBOARD=y
36CONFIG_USB_HOST_ETHER=y 35CONFIG_USB_HOST_ETHER=y
37CONFIG_USB_ETHER_ASIX=y 36CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index b23cd6a236..989ede35a1 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -69,7 +69,6 @@ CONFIG_SYSRESET=y
69CONFIG_USB=y 69CONFIG_USB=y
70CONFIG_USB_DWC2=y 70CONFIG_USB_DWC2=y
71CONFIG_ROCKCHIP_USB2_PHY=y 71CONFIG_ROCKCHIP_USB2_PHY=y
72CONFIG_USB_STORAGE=y
73CONFIG_USB_KEYBOARD=y 72CONFIG_USB_KEYBOARD=y
74CONFIG_USB_GADGET=y 73CONFIG_USB_GADGET=y
75CONFIG_USB_GADGET_MANUFACTURER="Rockchip" 74CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 4d8ccff675..adcaf93b29 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -40,7 +40,6 @@ CONFIG_PHYLIB=y
40CONFIG_MII=y 40CONFIG_MII=y
41CONFIG_DM_THERMAL=y 41CONFIG_DM_THERMAL=y
42CONFIG_USB=y 42CONFIG_USB=y
43CONFIG_USB_STORAGE=y
44CONFIG_VIDEO=y 43CONFIG_VIDEO=y
45# CONFIG_VIDEO_SW_CURSOR is not set 44# CONFIG_VIDEO_SW_CURSOR is not set
46CONFIG_OF_LIBFDT=y 45CONFIG_OF_LIBFDT=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 955c7af42a..4d443295ba 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -8,6 +8,8 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
8CONFIG_IMX_RDC=y 8CONFIG_IMX_RDC=y
9CONFIG_IMX_BOOTAUX=y 9CONFIG_IMX_BOOTAUX=y
10CONFIG_NR_DRAM_BANKS=1 10CONFIG_NR_DRAM_BANKS=1
11CONFIG_FIT=y
12CONFIG_FIT_VERBOSE=y
11CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" 13CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
12CONFIG_HUSH_PARSER=y 14CONFIG_HUSH_PARSER=y
13# CONFIG_CMD_BOOTD is not set 15# CONFIG_CMD_BOOTD is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index de7bf07955..d037da75b0 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -43,7 +43,6 @@ CONFIG_CMD_SF=y
43# CONFIG_CMD_SOURCE is not set 43# CONFIG_CMD_SOURCE is not set
44# CONFIG_CMD_SETEXPR is not set 44# CONFIG_CMD_SETEXPR is not set
45# CONFIG_CMD_MISC is not set 45# CONFIG_CMD_MISC is not set
46# CONFIG_PARTITIONS is not set
47CONFIG_SPL_OF_CONTROL=y 46CONFIG_SPL_OF_CONTROL=y
48CONFIG_OF_EMBED=y 47CONFIG_OF_EMBED=y
49CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" 48CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index ec26dd70fd..efd933fbc6 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -89,7 +89,6 @@ CONFIG_USB_DWC3_GADGET=y
89CONFIG_USB_DWC3_GENERIC=y 89CONFIG_USB_DWC3_GENERIC=y
90CONFIG_USB_ULPI_VIEWPORT=y 90CONFIG_USB_ULPI_VIEWPORT=y
91CONFIG_USB_ULPI=y 91CONFIG_USB_ULPI=y
92CONFIG_USB_STORAGE=y
93CONFIG_USB_GADGET=y 92CONFIG_USB_GADGET=y
94CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 93CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
95CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 94CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index c2b3d189ec..f9e56055b1 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -82,7 +82,6 @@ CONFIG_USB_DWC3_GADGET=y
82CONFIG_USB_DWC3_GENERIC=y 82CONFIG_USB_DWC3_GENERIC=y
83CONFIG_USB_ULPI_VIEWPORT=y 83CONFIG_USB_ULPI_VIEWPORT=y
84CONFIG_USB_ULPI=y 84CONFIG_USB_ULPI=y
85CONFIG_USB_STORAGE=y
86CONFIG_USB_GADGET=y 85CONFIG_USB_GADGET=y
87CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 86CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
88CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 87CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
index b853e2f56f..4d94a216c8 100644
--- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
@@ -80,7 +80,6 @@ CONFIG_USB_DWC3_GADGET=y
80CONFIG_USB_DWC3_GENERIC=y 80CONFIG_USB_DWC3_GENERIC=y
81CONFIG_USB_ULPI_VIEWPORT=y 81CONFIG_USB_ULPI_VIEWPORT=y
82CONFIG_USB_ULPI=y 82CONFIG_USB_ULPI=y
83CONFIG_USB_STORAGE=y
84CONFIG_USB_GADGET=y 83CONFIG_USB_GADGET=y
85CONFIG_USB_GADGET_DOWNLOAD=y 84CONFIG_USB_GADGET_DOWNLOAD=y
86CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 85CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig
index 429bfd4fd3..53bca780af 100644
--- a/configs/xilinx_zynqmp_zcu100_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig
@@ -83,7 +83,6 @@ CONFIG_USB_DWC3_GADGET=y
83CONFIG_USB_DWC3_GENERIC=y 83CONFIG_USB_DWC3_GENERIC=y
84CONFIG_USB_ULPI_VIEWPORT=y 84CONFIG_USB_ULPI_VIEWPORT=y
85CONFIG_USB_ULPI=y 85CONFIG_USB_ULPI=y
86CONFIG_USB_STORAGE=y
87CONFIG_USB_GADGET=y 86CONFIG_USB_GADGET=y
88CONFIG_USB_GADGET_DOWNLOAD=y 87CONFIG_USB_GADGET_DOWNLOAD=y
89CONFIG_USB_ETHER=y 88CONFIG_USB_ETHER=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index e41366ecf7..905d4672dc 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -108,7 +108,6 @@ CONFIG_USB_DWC3_GADGET=y
108CONFIG_USB_DWC3_GENERIC=y 108CONFIG_USB_DWC3_GENERIC=y
109CONFIG_USB_ULPI_VIEWPORT=y 109CONFIG_USB_ULPI_VIEWPORT=y
110CONFIG_USB_ULPI=y 110CONFIG_USB_ULPI=y
111CONFIG_USB_STORAGE=y
112CONFIG_USB_GADGET=y 111CONFIG_USB_GADGET=y
113CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 112CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
114CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 113CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 41a03371d5..5e4bbf8e8f 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -105,7 +105,6 @@ CONFIG_USB_DWC3_GADGET=y
105CONFIG_USB_DWC3_GENERIC=y 105CONFIG_USB_DWC3_GENERIC=y
106CONFIG_USB_ULPI_VIEWPORT=y 106CONFIG_USB_ULPI_VIEWPORT=y
107CONFIG_USB_ULPI=y 107CONFIG_USB_ULPI=y
108CONFIG_USB_STORAGE=y
109CONFIG_USB_GADGET=y 108CONFIG_USB_GADGET=y
110CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 109CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
111CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 110CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 78deb6a967..29aa07695a 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -105,7 +105,6 @@ CONFIG_USB_DWC3_GADGET=y
105CONFIG_USB_DWC3_GENERIC=y 105CONFIG_USB_DWC3_GENERIC=y
106CONFIG_USB_ULPI_VIEWPORT=y 106CONFIG_USB_ULPI_VIEWPORT=y
107CONFIG_USB_ULPI=y 107CONFIG_USB_ULPI=y
108CONFIG_USB_STORAGE=y
109CONFIG_USB_GADGET=y 108CONFIG_USB_GADGET=y
110CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 109CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
111CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 110CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig
index ff57ca8674..8fe30f931c 100644
--- a/configs/xilinx_zynqmp_zcu104_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig
@@ -88,7 +88,6 @@ CONFIG_USB_DWC3_GADGET=y
88CONFIG_USB_DWC3_GENERIC=y 88CONFIG_USB_DWC3_GENERIC=y
89CONFIG_USB_ULPI_VIEWPORT=y 89CONFIG_USB_ULPI_VIEWPORT=y
90CONFIG_USB_ULPI=y 90CONFIG_USB_ULPI=y
91CONFIG_USB_STORAGE=y
92CONFIG_USB_GADGET=y 91CONFIG_USB_GADGET=y
93CONFIG_USB_GADGET_DOWNLOAD=y 92CONFIG_USB_GADGET_DOWNLOAD=y
94CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 93CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig
index 0357b17445..a3d8ea0bff 100644
--- a/configs/xilinx_zynqmp_zcu104_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig
@@ -89,7 +89,6 @@ CONFIG_USB_DWC3_GADGET=y
89CONFIG_USB_DWC3_GENERIC=y 89CONFIG_USB_DWC3_GENERIC=y
90CONFIG_USB_ULPI_VIEWPORT=y 90CONFIG_USB_ULPI_VIEWPORT=y
91CONFIG_USB_ULPI=y 91CONFIG_USB_ULPI=y
92CONFIG_USB_STORAGE=y
93CONFIG_USB_GADGET=y 92CONFIG_USB_GADGET=y
94CONFIG_USB_GADGET_DOWNLOAD=y 93CONFIG_USB_GADGET_DOWNLOAD=y
95CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 94CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig
index 210c9a347f..6a659f00bf 100644
--- a/configs/xilinx_zynqmp_zcu106_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig
@@ -97,7 +97,6 @@ CONFIG_USB_DWC3_GADGET=y
97CONFIG_USB_DWC3_GENERIC=y 97CONFIG_USB_DWC3_GENERIC=y
98CONFIG_USB_ULPI_VIEWPORT=y 98CONFIG_USB_ULPI_VIEWPORT=y
99CONFIG_USB_ULPI=y 99CONFIG_USB_ULPI=y
100CONFIG_USB_STORAGE=y
101CONFIG_USB_GADGET=y 100CONFIG_USB_GADGET=y
102CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 101CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
103CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 102CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig
index 8bace6d808..fc544381de 100644
--- a/configs/xilinx_zynqmp_zcu111_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig
@@ -90,7 +90,6 @@ CONFIG_USB_DWC3_GADGET=y
90CONFIG_USB_DWC3_GENERIC=y 90CONFIG_USB_DWC3_GENERIC=y
91CONFIG_USB_ULPI_VIEWPORT=y 91CONFIG_USB_ULPI_VIEWPORT=y
92CONFIG_USB_ULPI=y 92CONFIG_USB_ULPI=y
93CONFIG_USB_STORAGE=y
94CONFIG_USB_GADGET=y 93CONFIG_USB_GADGET=y
95CONFIG_USB_GADGET_DOWNLOAD=y 94CONFIG_USB_GADGET_DOWNLOAD=y
96CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 95CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index c06e546e0a..5a930d6a38 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -53,7 +53,6 @@ CONFIG_USB=y
53CONFIG_USB_EHCI_HCD=y 53CONFIG_USB_EHCI_HCD=y
54CONFIG_USB_ULPI_VIEWPORT=y 54CONFIG_USB_ULPI_VIEWPORT=y
55CONFIG_USB_ULPI=y 55CONFIG_USB_ULPI=y
56CONFIG_USB_STORAGE=y
57CONFIG_USB_GADGET=y 56CONFIG_USB_GADGET=y
58CONFIG_CI_UDC=y 57CONFIG_CI_UDC=y
59CONFIG_USB_GADGET_DOWNLOAD=y 58CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 608619e40c..317b35938b 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -41,7 +41,6 @@ CONFIG_SYS_PROMPT="Zynq> "
41# CONFIG_CMD_SOURCE is not set 41# CONFIG_CMD_SOURCE is not set
42# CONFIG_CMD_SETEXPR is not set 42# CONFIG_CMD_SETEXPR is not set
43# CONFIG_CMD_MISC is not set 43# CONFIG_CMD_MISC is not set
44# CONFIG_PARTITIONS is not set
45CONFIG_OF_EMBED=y 44CONFIG_OF_EMBED=y
46CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" 45CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
47# CONFIG_NET is not set 46# CONFIG_NET is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index b4f1e313b1..b3bfc8c9ae 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -40,7 +40,6 @@ CONFIG_SYS_PROMPT="Zynq> "
40# CONFIG_CMD_SOURCE is not set 40# CONFIG_CMD_SOURCE is not set
41# CONFIG_CMD_SETEXPR is not set 41# CONFIG_CMD_SETEXPR is not set
42# CONFIG_CMD_MISC is not set 42# CONFIG_CMD_MISC is not set
43# CONFIG_PARTITIONS is not set
44CONFIG_OF_EMBED=y 43CONFIG_OF_EMBED=y
45CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" 44CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
46# CONFIG_NET is not set 45# CONFIG_NET is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 2aee069bb1..1fc8a597ce 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -48,7 +48,6 @@ CONFIG_CMD_SF=y
48# CONFIG_CMD_SOURCE is not set 48# CONFIG_CMD_SOURCE is not set
49# CONFIG_CMD_SETEXPR is not set 49# CONFIG_CMD_SETEXPR is not set
50# CONFIG_CMD_MISC is not set 50# CONFIG_CMD_MISC is not set
51# CONFIG_PARTITIONS is not set
52CONFIG_OF_EMBED=y 51CONFIG_OF_EMBED=y
53CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single" 52CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
54# CONFIG_NET is not set 53# CONFIG_NET is not set
diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig
index 4b9fdfe186..e39bd131ff 100644
--- a/configs/zynq_dlc20_rev1_0_defconfig
+++ b/configs/zynq_dlc20_rev1_0_defconfig
@@ -64,7 +64,6 @@ CONFIG_USB=y
64CONFIG_USB_EHCI_HCD=y 64CONFIG_USB_EHCI_HCD=y
65CONFIG_USB_ULPI_VIEWPORT=y 65CONFIG_USB_ULPI_VIEWPORT=y
66CONFIG_USB_ULPI=y 66CONFIG_USB_ULPI=y
67CONFIG_USB_STORAGE=y
68CONFIG_USB_GADGET=y 67CONFIG_USB_GADGET=y
69CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 68CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
70CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 69CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 29b8594d8b..206938584b 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -55,7 +55,6 @@ CONFIG_USB=y
55CONFIG_USB_EHCI_HCD=y 55CONFIG_USB_EHCI_HCD=y
56CONFIG_USB_ULPI_VIEWPORT=y 56CONFIG_USB_ULPI_VIEWPORT=y
57CONFIG_USB_ULPI=y 57CONFIG_USB_ULPI=y
58CONFIG_USB_STORAGE=y
59CONFIG_USB_GADGET=y 58CONFIG_USB_GADGET=y
60CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 59CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
61CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 60CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig
index 8597c41ca0..1b86040760 100644
--- a/configs/zynq_minized_defconfig
+++ b/configs/zynq_minized_defconfig
@@ -57,7 +57,6 @@ CONFIG_USB=y
57CONFIG_USB_EHCI_HCD=y 57CONFIG_USB_EHCI_HCD=y
58CONFIG_USB_ULPI_VIEWPORT=y 58CONFIG_USB_ULPI_VIEWPORT=y
59CONFIG_USB_ULPI=y 59CONFIG_USB_ULPI=y
60CONFIG_USB_STORAGE=y
61CONFIG_USB_GADGET=y 60CONFIG_USB_GADGET=y
62CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 61CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
63CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 62CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 585806ad4a..226f0f7f3a 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -42,7 +42,6 @@ CONFIG_USB=y
42CONFIG_USB_EHCI_HCD=y 42CONFIG_USB_EHCI_HCD=y
43CONFIG_USB_ULPI_VIEWPORT=y 43CONFIG_USB_ULPI_VIEWPORT=y
44CONFIG_USB_ULPI=y 44CONFIG_USB_ULPI=y
45CONFIG_USB_STORAGE=y
46CONFIG_USB_GADGET=y 45CONFIG_USB_GADGET=y
47CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 46CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
48CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 47CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index e40afaacf8..ff3322cf85 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -56,7 +56,6 @@ CONFIG_USB=y
56CONFIG_USB_EHCI_HCD=y 56CONFIG_USB_EHCI_HCD=y
57CONFIG_USB_ULPI_VIEWPORT=y 57CONFIG_USB_ULPI_VIEWPORT=y
58CONFIG_USB_ULPI=y 58CONFIG_USB_ULPI=y
59CONFIG_USB_STORAGE=y
60CONFIG_USB_GADGET=y 59CONFIG_USB_GADGET=y
61CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 60CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
62CONFIG_USB_GADGET_VENDOR_NUM=0x03FD 61CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 27e6bd1e0e..9734f24fdf 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -70,7 +70,6 @@ CONFIG_USB=y
70CONFIG_USB_EHCI_HCD=y 70CONFIG_USB_EHCI_HCD=y
71CONFIG_USB_ULPI_VIEWPORT=y 71CONFIG_USB_ULPI_VIEWPORT=y
72CONFIG_USB_ULPI=y 72CONFIG_USB_ULPI=y
73CONFIG_USB_STORAGE=y
74CONFIG_USB_GADGET=y 73CONFIG_USB_GADGET=y
75CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 74CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
76CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 75CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index bcbfa65e41..4a03351d1e 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -71,7 +71,6 @@ CONFIG_USB=y
71CONFIG_USB_EHCI_HCD=y 71CONFIG_USB_EHCI_HCD=y
72CONFIG_USB_ULPI_VIEWPORT=y 72CONFIG_USB_ULPI_VIEWPORT=y
73CONFIG_USB_ULPI=y 73CONFIG_USB_ULPI=y
74CONFIG_USB_STORAGE=y
75CONFIG_USB_GADGET=y 74CONFIG_USB_GADGET=y
76CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 75CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
77CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 76CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index c583c5c83b..dbf5c41739 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -59,7 +59,6 @@ CONFIG_USB=y
59CONFIG_USB_EHCI_HCD=y 59CONFIG_USB_EHCI_HCD=y
60CONFIG_USB_ULPI_VIEWPORT=y 60CONFIG_USB_ULPI_VIEWPORT=y
61CONFIG_USB_ULPI=y 61CONFIG_USB_ULPI=y
62CONFIG_USB_STORAGE=y
63CONFIG_USB_GADGET=y 62CONFIG_USB_GADGET=y
64CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 63CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
65CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 64CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 82931713a2..46b63003b3 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -64,7 +64,6 @@ CONFIG_USB=y
64CONFIG_USB_EHCI_HCD=y 64CONFIG_USB_EHCI_HCD=y
65CONFIG_USB_ULPI_VIEWPORT=y 65CONFIG_USB_ULPI_VIEWPORT=y
66CONFIG_USB_ULPI=y 66CONFIG_USB_ULPI=y
67CONFIG_USB_STORAGE=y
68CONFIG_USB_GADGET=y 67CONFIG_USB_GADGET=y
69CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 68CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
70CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 69CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index 190759fe8b..7985ad6c63 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -59,7 +59,6 @@ CONFIG_USB=y
59CONFIG_USB_EHCI_HCD=y 59CONFIG_USB_EHCI_HCD=y
60CONFIG_USB_ULPI_VIEWPORT=y 60CONFIG_USB_ULPI_VIEWPORT=y
61CONFIG_USB_ULPI=y 61CONFIG_USB_ULPI=y
62CONFIG_USB_STORAGE=y
63CONFIG_USB_GADGET=y 62CONFIG_USB_GADGET=y
64CONFIG_USB_GADGET_MANUFACTURER="Xilinx" 63CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
65CONFIG_USB_GADGET_VENDOR_NUM=0x03fd 64CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
diff --git a/doc/README.ae350 b/doc/README.ae350
index fe75b80eb7..189a6b7ec3 100644
--- a/doc/README.ae350
+++ b/doc/README.ae350
@@ -25,7 +25,7 @@ Build and boot steps
25 25
26build: 26build:
271. Prepare the toolchains and make sure the $PATH to toolchains is correct. 271. Prepare the toolchains and make sure the $PATH to toolchains is correct.
282. Use `make ax25-ae350_defconfig` in u-boot root to build the image. 282. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for 32 or 64 bit.
29 29
30Verification 30Verification
31==================== 31====================
diff --git a/doc/README.commands b/doc/README.commands
index 1d29c4d91d..e03eb44187 100644
--- a/doc/README.commands
+++ b/doc/README.commands
@@ -28,10 +28,46 @@ comp: Pointer to the completion function. May be NULL.
28 entering the command arguments to complete the entry. Command 28 entering the command arguments to complete the entry. Command
29 completion is only available if CONFIG_AUTO_COMPLETE is defined. 29 completion is only available if CONFIG_AUTO_COMPLETE is defined.
30 30
31Sub-command definition
32----------------------
33
34Likewise an array of cmd_tbl_t holding sub-commands can be created using either
35of the following macros:
36
37* U_BOOT_CMD_MKENT(name, maxargs, repeatable, command, "usage", "help")
38* U_BOOT_CMD_MKENTCOMPLETE(name, maxargs, repeatable, command, "usage, "help",
39 comp)
40
41This table has to be evaluated in the command function of the main command, e.g.
42
43 static cmd_tbl_t cmd_sub[] = {
44 U_BOOT_CMD_MKENT(foo, CONFIG_SYS_MAXARGS, 1, do_foo, "", ""),
45 U_BOOT_CMD_MKENT(bar, CONFIG_SYS_MAXARGS, 1, do_bar, "", ""),
46 };
47
48 static int do_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
49 {
50 cmd_tbl_t *cp;
51
52 if (argc < 2)
53 return CMD_RET_USAGE;
54
55 /* drop sub-command argument */
56 argc--;
57 argv++;
58
59 cp = find_cmd_tbl(argv[0], cmd_ut_sub, ARRAY_SIZE(cmd_sub));
60
61 if (cp)
62 return cp->cmd(cmdtp, flag, argc, argv);
63
64 return CMD_RET_USAGE;
65 }
66
31Command function 67Command function
32---------------- 68----------------
33 69
34The commmand function pointer has to be of type 70The command function pointer has to be of type
35int (*cmd)(struct cmd_tbl_s *cmdtp, int flag, int argc, const char *argv[]); 71int (*cmd)(struct cmd_tbl_s *cmdtp, int flag, int argc, const char *argv[]);
36 72
37cmdtp: Table entry describing the command (see above). 73cmdtp: Table entry describing the command (see above).
diff --git a/doc/README.odroid b/doc/README.odroid
index c088ec4cb0..bc77ae3175 100644
--- a/doc/README.odroid
+++ b/doc/README.odroid
@@ -1,11 +1,11 @@
1 U-Boot for Odroid X2/U3/XU3/XU4 1 U-Boot for Odroid X2/U3/XU3/XU4/HC1
2======================== 2========================
3 3
41. Summary 41. Summary
5========== 5==========
6This is a quick instruction for setup Odroid boards. 6This is a quick instruction for setup Odroid boards.
7Board config: odroid_config for X2/U3 7Board config: odroid_config for X2/U3
8Board config: odroid-xu3_config for XU3/XU4 8Board config: odroid-xu3_config for XU3/XU4/HC1
9 9
102. Supported devices 102. Supported devices
11==================== 11====================
@@ -15,6 +15,7 @@ This U-BOOT config can be used on three boards:
15with CPU Exynos 4412 rev 2.0 and 2GB of RAM 15with CPU Exynos 4412 rev 2.0 and 2GB of RAM
16- Odroid XU3 16- Odroid XU3
17- Odroid XU4 17- Odroid XU4
18- Odroid HC1
18with CPU Exynos5422 and 2GB of RAM 19with CPU Exynos5422 and 2GB of RAM
19 20
203. Boot sequence 213. Boot sequence
@@ -121,7 +122,9 @@ Supported fdt files are:
121- exynos4412-odroidx2.dtb 122- exynos4412-odroidx2.dtb
122- exynos4412-odroidu3.dtb 123- exynos4412-odroidu3.dtb
123- exynos5422-odroidxu3.dtb 124- exynos5422-odroidxu3.dtb
125- exynos5422-odroidxu3-lite.dtb
124- exynos5422-odroidxu4.dtb 126- exynos5422-odroidxu4.dtb
127- exynos5422-odroidhc1.dtb
125 128
126Supported kernel files are: 129Supported kernel files are:
127- Image.itb 130- Image.itb
diff --git a/doc/README.video b/doc/README.video
index 09a26b1793..ced35bd2db 100644
--- a/doc/README.video
+++ b/doc/README.video
@@ -75,3 +75,23 @@ The sunxi U-Boot driver supports the following video-mode options:
75For example to always use the hdmi connector, even if no cable is inserted, 75For example to always use the hdmi connector, even if no cable is inserted,
76using edid info when available and otherwise initalizing it at 1024x768@60Hz, 76using edid info when available and otherwise initalizing it at 1024x768@60Hz,
77use: "setenv video-mode sunxi:1024x768-24@60,monitor=dvi,hpd=0,edid=1". 77use: "setenv video-mode sunxi:1024x768-24@60,monitor=dvi,hpd=0,edid=1".
78
79
80TrueType fonts
81--------------
82
83U-Boot supports the use of antialiased TrueType fonts on some platforms. This
84has been tested in x86, ARMv7 and sandbox.
85
86To enable this, select CONFIG_CONSOLE_TRUETYPE. You can choose between several
87fonts, with CONSOLE_TRUETYPE_NIMBUS being the default.
88
89TrueType support requires floating point at present. On ARMv7 platforms you
90need to disable use of the private libgcc. You can do this by disabling
91CONFIG_USE_PRIVATE_LIBGCC. See chromebook_jerry for an example. Note that this
92increases U-Boot's size by about 70KB at present.
93
94On ARM you should also make sure your toolchain supports hardfp. This is
95normally given in the name of your toolchain, e.g. arm-linux-gnueabihf (hf
96means hardware floating point). You can also run gcc with -v to see if it has
97this option.
diff --git a/doc/device-tree-bindings/w1/mxc-w1.txt b/doc/device-tree-bindings/w1/mxc-w1.txt
new file mode 100644
index 0000000000..1fb49cc111
--- /dev/null
+++ b/doc/device-tree-bindings/w1/mxc-w1.txt
@@ -0,0 +1,37 @@
1NXP i.MX (MXC) One wire bus master controller
2=======================
3
4Child nodes are required in device tree. The driver will detect
5the devices serial number and then search in the child nodes in the device tree
6for the proper node and try to match it with the device.
7
8Also check doc/device-tree-bindings/w1-eeprom for possible child nodes drivers
9
10Driver:
11- drivers/w1/mxc_w1.c
12
13Required properties:
14- compatible : should be one of
15 "fsl,imx21-owire", "fsl,imx27-owire", "fsl,imx31-owire", "fsl,imx25-owire"
16 "fsl,imx25-owire", "fsl,imx35-owire", "fsl,imx50-owire", "fsl,imx53-owire"
17
18- reg : Address and length of the register set for the device
19
20Optional:
21* none
22
23Example:
24 onewire {
25 compatible = "fsl,imx53-owire";
26 reg = <0x63fa4000 0x4000>;
27 };
28
29Example with child:
30 onewire {
31 compatible = "fsl,imx53-owire";
32 reg = <0x63fa4000 0x4000>;
33
34 eeprom1: eeprom@0 {
35 compatible = "maxim,ds24xxx";
36 };
37 };
diff --git a/doc/driver-model/MIGRATION.txt b/doc/driver-model/MIGRATION.txt
index dce4aa3e1d..957529202b 100644
--- a/doc/driver-model/MIGRATION.txt
+++ b/doc/driver-model/MIGRATION.txt
@@ -55,9 +55,6 @@ CONFIG_DM_SPI_FLASH
55Board Maintainers should submit the patches for enabling DM_SPI and DM_SPI_FLASH 55Board Maintainers should submit the patches for enabling DM_SPI and DM_SPI_FLASH
56to move the migration with in the deadline. 56to move the migration with in the deadline.
57 57
58Status: In progress
59Deadline: 2018.09
60
61No dm conversion yet: 58No dm conversion yet:
62 drivers/spi/cf_spi.c 59 drivers/spi/cf_spi.c
63 drivers/spi/fsl_espi.c 60 drivers/spi/fsl_espi.c
@@ -69,6 +66,9 @@ No dm conversion yet:
69 drivers/spi/sh_spi.c 66 drivers/spi/sh_spi.c
70 drivers/spi/soft_spi_legacy.c 67 drivers/spi/soft_spi_legacy.c
71 68
69 Status: In progress
70 Deadline: 2019.04
71
72Partially converted: 72Partially converted:
73 drivers/spi/atcspi200_spi.c 73 drivers/spi/atcspi200_spi.c
74 drivers/spi/davinci_spi.c 74 drivers/spi/davinci_spi.c
@@ -79,6 +79,28 @@ Partially converted:
79 drivers/spi/omap3_spi.c 79 drivers/spi/omap3_spi.c
80 drivers/spi/ti_qspi.c 80 drivers/spi/ti_qspi.c
81 81
82 Status: In progress
83 Deadline: 2019.07
84
82-- 85--
83Jagan Teki <jagan@openedev.com> 86Jagan Teki <jagan@openedev.com>
8712/24/2018
8403/14/2018 8803/14/2018
89
90
91CONFIG_DM_PCI
92-------------
93Deadline: 2019.07
94
95The PCI subsystem has supported driver model since mid 2015. Maintainers should
96submit patches switching over to using CONFIG_DM_PCI and other base driver
97model options in time for inclusion in the 2019.07 release.
98
99
100CONFIG_DM_VIDEO
101---------------
102Deadline: 2019.07
103
104The video subsystem has supported driver model since early 2016. Maintainers
105should submit patches switching over to using CONFIG_DM_VIDEO and other base
106driver model options in time for inclusion in the 2019.07 release.
diff --git a/doc/imx/mkimage/imximage.txt b/doc/imx/mkimage/imximage.txt
index 803682f558..f2cf23c5da 100644
--- a/doc/imx/mkimage/imximage.txt
+++ b/doc/imx/mkimage/imximage.txt
@@ -175,7 +175,7 @@ Warning: setting sector offset for DOS compatiblity
175We have set 255 heads, 63 sector. We have to set the cylinder. 175We have set 255 heads, 63 sector. We have to set the cylinder.
176The value to be set can be calculated with: 176The value to be set can be calculated with:
177 177
178 cilynder = <total size> / <heads> / <sectors> / <blocksize> 178 cylinder = <total size> / <heads> / <sectors> / <blocksize>
179 179
180in this example, 180in this example,
181 1981284352 / 255 / 63 / 512 = 239.x = 239 181 1981284352 / 255 / 63 / 512 = 239.x = 239
diff --git a/doc/imx/mkimage/mxsimage.txt b/doc/imx/mkimage/mxsimage.txt
index c3975ee5e6..9159f93a97 100644
--- a/doc/imx/mkimage/mxsimage.txt
+++ b/doc/imx/mkimage/mxsimage.txt
@@ -46,7 +46,7 @@ These semantics and rules will be outlined now.
46 TAG [LAST] 46 TAG [LAST]
47 - LAST :: Flag denoting the last section in the file 47 - LAST :: Flag denoting the last section in the file
48 48
49 - After a "TAG" unstruction, any of the following instructions may follow 49 - After a "TAG" instruction, any of the following instructions may follow
50 in any order and any quantity: 50 in any order and any quantity:
51 51
52 NOOP 52 NOOP
@@ -142,7 +142,7 @@ These semantics and rules will be outlined now.
142 - An optional flags lines can be one of the following: 142 - An optional flags lines can be one of the following:
143 143
144 DISPLAYPROGRESS 144 DISPLAYPROGRESS
145 - Enable boot progress output form the BootROM. 145 - Enable boot progress output from the BootROM.
146 146
147- If the boot progress output from the BootROM is enabled, the BootROM will 147- If the boot progress output from the BootROM is enabled, the BootROM will
148 produce a letter on the Debug UART for each instruction it started processing. 148 produce a letter on the Debug UART for each instruction it started processing.
diff --git a/drivers/Makefile b/drivers/Makefile
index 5e3b122769..4105864e2b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
34obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ 34obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
35obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ 35obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
36obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ 36obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
37obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
37obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ 38obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
38obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ 39obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
39obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ 40obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
@@ -46,9 +47,9 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
46obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ 47obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
47obj-$(CONFIG_SPL_USB_ETHER) += net/phy/ 48obj-$(CONFIG_SPL_USB_ETHER) += net/phy/
48obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ 49obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
49obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/ 50obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
50obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/common/ 51obj-$(CONFIG_SPL_USB_GADGET) += usb/common/
51obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/ 52obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/
52obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu/ 53obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu/
53obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/ 54obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/
54obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/ 55obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index fcb8090d35..d03fcc2fdd 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -18,6 +18,7 @@ struct imx8_clks {
18 const char *name; 18 const char *name;
19}; 19};
20 20
21#if CONFIG_IS_ENABLED(CMD_CLK)
21static struct imx8_clks imx8_clk_names[] = { 22static struct imx8_clks imx8_clk_names[] = {
22 { IMX8QXP_A35_DIV, "A35_DIV" }, 23 { IMX8QXP_A35_DIV, "A35_DIV" },
23 { IMX8QXP_I2C0_CLK, "I2C0" }, 24 { IMX8QXP_I2C0_CLK, "I2C0" },
@@ -39,6 +40,7 @@ static struct imx8_clks imx8_clk_names[] = {
39 { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" }, 40 { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
40 { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" }, 41 { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
41}; 42};
43#endif
42 44
43static ulong imx8_clk_get_rate(struct clk *clk) 45static ulong imx8_clk_get_rate(struct clk *clk)
44{ 46{
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 9e087b6bd2..487b43ebda 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -6,13 +6,12 @@
6 6
7#include "clk-uniphier.h" 7#include "clk-uniphier.h"
8 8
9/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
10#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ 9#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
11 UNIPHIER_CLK_RATE(128, 200000000), \ 10 UNIPHIER_CLK_RATE(128, 50000000), \
12 UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) 11 UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
13 12
14#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ 13#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \
15 UNIPHIER_CLK_RATE(128, 200000000), \ 14 UNIPHIER_CLK_RATE(128, 50000000), \
16 UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) 15 UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
17 16
18const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { 17const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
@@ -20,6 +19,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
20 defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ 19 defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
21 defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) 20 defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
22 UNIPHIER_LD4_SYS_CLK_NAND(2), 21 UNIPHIER_LD4_SYS_CLK_NAND(2),
22 UNIPHIER_CLK_RATE(3, 200000000),
23 UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ 23 UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
24 UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ 24 UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
25 UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ 25 UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
@@ -36,6 +36,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
36const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 36const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
37#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) 37#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
38 UNIPHIER_LD11_SYS_CLK_NAND(2), 38 UNIPHIER_LD11_SYS_CLK_NAND(2),
39 UNIPHIER_CLK_RATE(3, 200000000),
39 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ 40 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
40 UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ 41 UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
41 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ 42 UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
@@ -48,6 +49,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
48const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { 49const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
49#if defined(CONFIG_ARCH_UNIPHIER_PXS3) 50#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
50 UNIPHIER_LD11_SYS_CLK_NAND(2), 51 UNIPHIER_LD11_SYS_CLK_NAND(2),
52 UNIPHIER_CLK_RATE(3, 200000000),
51 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ 53 UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
52 UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ 54 UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
53 UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ 55 UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index d4052005e2..3d5729f6dc 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -13,3 +13,9 @@ config CPU_MPC83XX
13 select CLK_MPC83XX 13 select CLK_MPC83XX
14 help 14 help
15 Support CPU cores for SoCs of the MPC83xx series. 15 Support CPU cores for SoCs of the MPC83xx series.
16
17config CPU_RISCV
18 bool "Enable RISC-V CPU driver"
19 depends on CPU && RISCV
20 help
21 Support CPU cores for RISC-V architecture.
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index 858b03755f..be0300cd4a 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
8 8
9obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o 9obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
10obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o 10obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
11obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
11obj-$(CONFIG_SANDBOX) += cpu_sandbox.o 12obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
new file mode 100644
index 0000000000..5e15df590e
--- /dev/null
+++ b/drivers/cpu/riscv_cpu.c
@@ -0,0 +1,116 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <common.h>
7#include <cpu.h>
8#include <dm.h>
9#include <errno.h>
10#include <dm/device-internal.h>
11#include <dm/lists.h>
12
13static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
14{
15 const char *isa;
16
17 isa = dev_read_string(dev, "riscv,isa");
18 if (size < (strlen(isa) + 1))
19 return -ENOSPC;
20
21 strcpy(buf, isa);
22
23 return 0;
24}
25
26static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
27{
28 const char *mmu;
29
30 dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
31
32 mmu = dev_read_string(dev, "mmu-type");
33 if (!mmu)
34 info->features |= BIT(CPU_FEAT_MMU);
35
36 return 0;
37}
38
39static int riscv_cpu_get_count(struct udevice *dev)
40{
41 ofnode node;
42 int num = 0;
43
44 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
45 const char *device_type;
46
47 device_type = ofnode_read_string(node, "device_type");
48 if (!device_type)
49 continue;
50 if (strcmp(device_type, "cpu") == 0)
51 num++;
52 }
53
54 return num;
55}
56
57static int riscv_cpu_bind(struct udevice *dev)
58{
59 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
60 struct driver *drv;
61 int ret;
62
63 /* save the hart id */
64 plat->cpu_id = dev_read_addr(dev);
65
66 /* first examine the property in current cpu node */
67 ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
68 /* if not found, then look at the parent /cpus node */
69 if (ret)
70 dev_read_u32(dev->parent, "timebase-frequency",
71 &plat->timebase_freq);
72
73 /*
74 * Bind riscv-timer driver on hart 0
75 *
76 * We only instantiate one timer device which is enough for U-Boot.
77 * Pass the "timebase-frequency" value as the driver data for the
78 * timer device.
79 *
80 * Return value is not checked since it's possible that the timer
81 * driver is not included.
82 */
83 if (!plat->cpu_id && plat->timebase_freq) {
84 drv = lists_driver_lookup_name("riscv_timer");
85 if (!drv) {
86 debug("Cannot find the timer driver, not included?\n");
87 return 0;
88 }
89
90 device_bind_with_driver_data(dev, drv, "riscv_timer",
91 plat->timebase_freq, ofnode_null(),
92 NULL);
93 }
94
95 return 0;
96}
97
98static const struct cpu_ops riscv_cpu_ops = {
99 .get_desc = riscv_cpu_get_desc,
100 .get_info = riscv_cpu_get_info,
101 .get_count = riscv_cpu_get_count,
102};
103
104static const struct udevice_id riscv_cpu_ids[] = {
105 { .compatible = "riscv" },
106 { }
107};
108
109U_BOOT_DRIVER(riscv_cpu) = {
110 .name = "riscv_cpu",
111 .id = UCLASS_CPU,
112 .of_match = riscv_cpu_ids,
113 .bind = riscv_cpu_bind,
114 .ops = &riscv_cpu_ops,
115 .flags = DM_FLAG_PRE_RELOC,
116};
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
index b764add060..d4b393d25e 100644
--- a/drivers/ddr/Kconfig
+++ b/drivers/ddr/Kconfig
@@ -1 +1,2 @@
1source "drivers/ddr/altera/Kconfig" 1source "drivers/ddr/altera/Kconfig"
2source "drivers/ddr/imx/Kconfig"
diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig
new file mode 100644
index 0000000000..7e06fb2f7d
--- /dev/null
+++ b/drivers/ddr/imx/Kconfig
@@ -0,0 +1 @@
source "drivers/ddr/imx/imx8m/Kconfig"
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
new file mode 100644
index 0000000000..71f466f5ec
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -0,0 +1,22 @@
1config IMX8M_DRAM
2 bool "imx8m dram"
3
4config IMX8M_LPDDR4
5 bool "imx8m lpddr4"
6 select IMX8M_DRAM
7 help
8 Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
9
10config IMX8M_DDR4
11 bool "imx8m ddr4"
12 select IMX8M_DRAM
13 help
14 Select the i.MX8M DDR4 driver support on i.MX8M SOC.
15
16config SAVED_DRAM_TIMING_BASE
17 hex "Define the base address for saved dram timing"
18 help
19 after DRAM is trained, need to save the dram related timming
20 info into memory for low power use. OCRAM_S is used for this
21 purpose on i.MX8MM.
22 default 0x180000
diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
new file mode 100644
index 0000000000..64f9ab20e6
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/Makefile
@@ -0,0 +1,11 @@
1#
2# Copyright 2018 NXP
3#
4# SPDX-License-Identifier: GPL-2.0+
5#
6
7ifdef CONFIG_SPL_BUILD
8obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
9obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
10obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
11endif
diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c
new file mode 100644
index 0000000000..031cdc57e1
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddr4_init.c
@@ -0,0 +1,113 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <errno.h>
8#include <asm/io.h>
9#include <asm/arch/ddr.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx8m_ddr.h>
12#include <asm/arch/sys_proto.h>
13
14void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
15{
16 int i = 0;
17
18 for (i = 0; i < num; i++) {
19 reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
20 ddrc_cfg++;
21 }
22}
23
24void ddr_init(struct dram_timing_info *dram_timing)
25{
26 volatile unsigned int tmp_t;
27 /*
28 * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
29 * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
30 * [4]src_system_rst_b!
31 */
32 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F);
33 /* deassert [4]src_system_rst_b! */
34 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
35
36 /*
37 * change the clock source of dram_apb_clk_root
38 * to source 4 --800MHz/4
39 */
40 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
41 CLK_ROOT_SOURCE_SEL(4) |
42 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
43
44 dram_pll_init(DRAM_PLL_OUT_600M);
45
46 reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
47 reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
48
49 /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
50 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
51
52 reg32_write(DDRC_DBG1(0), 0x00000001);
53 reg32_write(DDRC_PWRCTL(0), 0x00000001);
54
55 while (0 != (0x7 & reg32_read(DDRC_STAT(0))))
56 ;
57
58 /* config the uMCTL2's registers */
59 ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
60
61 reg32_write(DDRC_RFSHCTL3(0), 0x00000001);
62 /* RESET: <ctn> DEASSERTED */
63 /* RESET: <a Port 0 DEASSERTED(0) */
64 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
65 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
66
67 reg32_write(DDRC_DBG1(0), 0x00000000);
68 reg32_write(DDRC_PWRCTL(0), 0x00000aa);
69 reg32_write(DDRC_SWCTL(0), 0x00000000);
70
71 reg32_write(DDRC_DFIMISC(0), 0x00000000);
72
73 /* config the DDR PHY's registers */
74 ddr_cfg_phy(dram_timing);
75
76 do {
77 tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
78 4 * 0x00020097);
79 } while (tmp_t != 0);
80
81 reg32_write(DDRC_DFIMISC(0), 0x00000020);
82
83 /* wait DFISTAT.dfi_init_complete to 1 */
84 while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
85 ;
86
87 /* clear DFIMISC.dfi_init_complete_en */
88 reg32_write(DDRC_DFIMISC(0), 0x00000000);
89 /* set DFIMISC.dfi_init_complete_en again */
90 reg32_write(DDRC_DFIMISC(0), 0x00000001);
91 reg32_write(DDRC_PWRCTL(0), 0x0000088);
92
93 /*
94 * set SWCTL.sw_done to enable quasi-dynamic register
95 * programming outside reset.
96 */
97 reg32_write(DDRC_SWCTL(0), 0x00000001);
98 /* wait SWSTAT.sw_done_ack to 1 */
99 while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
100 ;
101
102 /* wait STAT to normal state */
103 while (0x1 != (0x7 & reg32_read(DDRC_STAT(0))))
104 ;
105
106 reg32_write(DDRC_PWRCTL(0), 0x0000088);
107 reg32_write(DDRC_PCTRL_0(0), 0x00000001);
108 /* dis_auto-refresh is set to 0 */
109 reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
110
111 /* save the dram timing config into memory */
112 dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
113}
diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/imx8m/ddrphy_csr.c
new file mode 100644
index 0000000000..67dd4e7059
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddrphy_csr.c
@@ -0,0 +1,732 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <linux/kernel.h>
7#include <asm/arch/ddr.h>
8
9/* ddr phy trained csr */
10struct dram_cfg_param ddrphy_trained_csr[] = {
11 { 0x200b2, 0x0 },
12 { 0x1200b2, 0x0 },
13 { 0x2200b2, 0x0 },
14 { 0x200cb, 0x0 },
15 { 0x10043, 0x0 },
16 { 0x110043, 0x0 },
17 { 0x210043, 0x0 },
18 { 0x10143, 0x0 },
19 { 0x110143, 0x0 },
20 { 0x210143, 0x0 },
21 { 0x11043, 0x0 },
22 { 0x111043, 0x0 },
23 { 0x211043, 0x0 },
24 { 0x11143, 0x0 },
25 { 0x111143, 0x0 },
26 { 0x211143, 0x0 },
27 { 0x12043, 0x0 },
28 { 0x112043, 0x0 },
29 { 0x212043, 0x0 },
30 { 0x12143, 0x0 },
31 { 0x112143, 0x0 },
32 { 0x212143, 0x0 },
33 { 0x13043, 0x0 },
34 { 0x113043, 0x0 },
35 { 0x213043, 0x0 },
36 { 0x13143, 0x0 },
37 { 0x113143, 0x0 },
38 { 0x213143, 0x0 },
39 { 0x80, 0x0 },
40 { 0x100080, 0x0 },
41 { 0x200080, 0x0 },
42 { 0x1080, 0x0 },
43 { 0x101080, 0x0 },
44 { 0x201080, 0x0 },
45 { 0x2080, 0x0 },
46 { 0x102080, 0x0 },
47 { 0x202080, 0x0 },
48 { 0x3080, 0x0 },
49 { 0x103080, 0x0 },
50 { 0x203080, 0x0 },
51 { 0x4080, 0x0 },
52 { 0x104080, 0x0 },
53 { 0x204080, 0x0 },
54 { 0x5080, 0x0 },
55 { 0x105080, 0x0 },
56 { 0x205080, 0x0 },
57 { 0x6080, 0x0 },
58 { 0x106080, 0x0 },
59 { 0x206080, 0x0 },
60 { 0x7080, 0x0 },
61 { 0x107080, 0x0 },
62 { 0x207080, 0x0 },
63 { 0x8080, 0x0 },
64 { 0x108080, 0x0 },
65 { 0x208080, 0x0 },
66 { 0x9080, 0x0 },
67 { 0x109080, 0x0 },
68 { 0x209080, 0x0 },
69 { 0x10080, 0x0 },
70 { 0x110080, 0x0 },
71 { 0x210080, 0x0 },
72 { 0x10180, 0x0 },
73 { 0x110180, 0x0 },
74 { 0x210180, 0x0 },
75 { 0x11080, 0x0 },
76 { 0x111080, 0x0 },
77 { 0x211080, 0x0 },
78 { 0x11180, 0x0 },
79 { 0x111180, 0x0 },
80 { 0x211180, 0x0 },
81 { 0x12080, 0x0 },
82 { 0x112080, 0x0 },
83 { 0x212080, 0x0 },
84 { 0x12180, 0x0 },
85 { 0x112180, 0x0 },
86 { 0x212180, 0x0 },
87 { 0x13080, 0x0 },
88 { 0x113080, 0x0 },
89 { 0x213080, 0x0 },
90 { 0x13180, 0x0 },
91 { 0x113180, 0x0 },
92 { 0x213180, 0x0 },
93 { 0x10081, 0x0 },
94 { 0x110081, 0x0 },
95 { 0x210081, 0x0 },
96 { 0x10181, 0x0 },
97 { 0x110181, 0x0 },
98 { 0x210181, 0x0 },
99 { 0x11081, 0x0 },
100 { 0x111081, 0x0 },
101 { 0x211081, 0x0 },
102 { 0x11181, 0x0 },
103 { 0x111181, 0x0 },
104 { 0x211181, 0x0 },
105 { 0x12081, 0x0 },
106 { 0x112081, 0x0 },
107 { 0x212081, 0x0 },
108 { 0x12181, 0x0 },
109 { 0x112181, 0x0 },
110 { 0x212181, 0x0 },
111 { 0x13081, 0x0 },
112 { 0x113081, 0x0 },
113 { 0x213081, 0x0 },
114 { 0x13181, 0x0 },
115 { 0x113181, 0x0 },
116 { 0x213181, 0x0 },
117 { 0x100d0, 0x0 },
118 { 0x1100d0, 0x0 },
119 { 0x2100d0, 0x0 },
120 { 0x101d0, 0x0 },
121 { 0x1101d0, 0x0 },
122 { 0x2101d0, 0x0 },
123 { 0x110d0, 0x0 },
124 { 0x1110d0, 0x0 },
125 { 0x2110d0, 0x0 },
126 { 0x111d0, 0x0 },
127 { 0x1111d0, 0x0 },
128 { 0x2111d0, 0x0 },
129 { 0x120d0, 0x0 },
130 { 0x1120d0, 0x0 },
131 { 0x2120d0, 0x0 },
132 { 0x121d0, 0x0 },
133 { 0x1121d0, 0x0 },
134 { 0x2121d0, 0x0 },
135 { 0x130d0, 0x0 },
136 { 0x1130d0, 0x0 },
137 { 0x2130d0, 0x0 },
138 { 0x131d0, 0x0 },
139 { 0x1131d0, 0x0 },
140 { 0x2131d0, 0x0 },
141 { 0x100d1, 0x0 },
142 { 0x1100d1, 0x0 },
143 { 0x2100d1, 0x0 },
144 { 0x101d1, 0x0 },
145 { 0x1101d1, 0x0 },
146 { 0x2101d1, 0x0 },
147 { 0x110d1, 0x0 },
148 { 0x1110d1, 0x0 },
149 { 0x2110d1, 0x0 },
150 { 0x111d1, 0x0 },
151 { 0x1111d1, 0x0 },
152 { 0x2111d1, 0x0 },
153 { 0x120d1, 0x0 },
154 { 0x1120d1, 0x0 },
155 { 0x2120d1, 0x0 },
156 { 0x121d1, 0x0 },
157 { 0x1121d1, 0x0 },
158 { 0x2121d1, 0x0 },
159 { 0x130d1, 0x0 },
160 { 0x1130d1, 0x0 },
161 { 0x2130d1, 0x0 },
162 { 0x131d1, 0x0 },
163 { 0x1131d1, 0x0 },
164 { 0x2131d1, 0x0 },
165 { 0x10068, 0x0 },
166 { 0x10168, 0x0 },
167 { 0x10268, 0x0 },
168 { 0x10368, 0x0 },
169 { 0x10468, 0x0 },
170 { 0x10568, 0x0 },
171 { 0x10668, 0x0 },
172 { 0x10768, 0x0 },
173 { 0x10868, 0x0 },
174 { 0x11068, 0x0 },
175 { 0x11168, 0x0 },
176 { 0x11268, 0x0 },
177 { 0x11368, 0x0 },
178 { 0x11468, 0x0 },
179 { 0x11568, 0x0 },
180 { 0x11668, 0x0 },
181 { 0x11768, 0x0 },
182 { 0x11868, 0x0 },
183 { 0x12068, 0x0 },
184 { 0x12168, 0x0 },
185 { 0x12268, 0x0 },
186 { 0x12368, 0x0 },
187 { 0x12468, 0x0 },
188 { 0x12568, 0x0 },
189 { 0x12668, 0x0 },
190 { 0x12768, 0x0 },
191 { 0x12868, 0x0 },
192 { 0x13068, 0x0 },
193 { 0x13168, 0x0 },
194 { 0x13268, 0x0 },
195 { 0x13368, 0x0 },
196 { 0x13468, 0x0 },
197 { 0x13568, 0x0 },
198 { 0x13668, 0x0 },
199 { 0x13768, 0x0 },
200 { 0x13868, 0x0 },
201 { 0x10069, 0x0 },
202 { 0x10169, 0x0 },
203 { 0x10269, 0x0 },
204 { 0x10369, 0x0 },
205 { 0x10469, 0x0 },
206 { 0x10569, 0x0 },
207 { 0x10669, 0x0 },
208 { 0x10769, 0x0 },
209 { 0x10869, 0x0 },
210 { 0x11069, 0x0 },
211 { 0x11169, 0x0 },
212 { 0x11269, 0x0 },
213 { 0x11369, 0x0 },
214 { 0x11469, 0x0 },
215 { 0x11569, 0x0 },
216 { 0x11669, 0x0 },
217 { 0x11769, 0x0 },
218 { 0x11869, 0x0 },
219 { 0x12069, 0x0 },
220 { 0x12169, 0x0 },
221 { 0x12269, 0x0 },
222 { 0x12369, 0x0 },
223 { 0x12469, 0x0 },
224 { 0x12569, 0x0 },
225 { 0x12669, 0x0 },
226 { 0x12769, 0x0 },
227 { 0x12869, 0x0 },
228 { 0x13069, 0x0 },
229 { 0x13169, 0x0 },
230 { 0x13269, 0x0 },
231 { 0x13369, 0x0 },
232 { 0x13469, 0x0 },
233 { 0x13569, 0x0 },
234 { 0x13669, 0x0 },
235 { 0x13769, 0x0 },
236 { 0x13869, 0x0 },
237 { 0x1008c, 0x0 },
238 { 0x11008c, 0x0 },
239 { 0x21008c, 0x0 },
240 { 0x1018c, 0x0 },
241 { 0x11018c, 0x0 },
242 { 0x21018c, 0x0 },
243 { 0x1108c, 0x0 },
244 { 0x11108c, 0x0 },
245 { 0x21108c, 0x0 },
246 { 0x1118c, 0x0 },
247 { 0x11118c, 0x0 },
248 { 0x21118c, 0x0 },
249 { 0x1208c, 0x0 },
250 { 0x11208c, 0x0 },
251 { 0x21208c, 0x0 },
252 { 0x1218c, 0x0 },
253 { 0x11218c, 0x0 },
254 { 0x21218c, 0x0 },
255 { 0x1308c, 0x0 },
256 { 0x11308c, 0x0 },
257 { 0x21308c, 0x0 },
258 { 0x1318c, 0x0 },
259 { 0x11318c, 0x0 },
260 { 0x21318c, 0x0 },
261 { 0x1008d, 0x0 },
262 { 0x11008d, 0x0 },
263 { 0x21008d, 0x0 },
264 { 0x1018d, 0x0 },
265 { 0x11018d, 0x0 },
266 { 0x21018d, 0x0 },
267 { 0x1108d, 0x0 },
268 { 0x11108d, 0x0 },
269 { 0x21108d, 0x0 },
270 { 0x1118d, 0x0 },
271 { 0x11118d, 0x0 },
272 { 0x21118d, 0x0 },
273 { 0x1208d, 0x0 },
274 { 0x11208d, 0x0 },
275 { 0x21208d, 0x0 },
276 { 0x1218d, 0x0 },
277 { 0x11218d, 0x0 },
278 { 0x21218d, 0x0 },
279 { 0x1308d, 0x0 },
280 { 0x11308d, 0x0 },
281 { 0x21308d, 0x0 },
282 { 0x1318d, 0x0 },
283 { 0x11318d, 0x0 },
284 { 0x21318d, 0x0 },
285 { 0x100c0, 0x0 },
286 { 0x1100c0, 0x0 },
287 { 0x2100c0, 0x0 },
288 { 0x101c0, 0x0 },
289 { 0x1101c0, 0x0 },
290 { 0x2101c0, 0x0 },
291 { 0x102c0, 0x0 },
292 { 0x1102c0, 0x0 },
293 { 0x2102c0, 0x0 },
294 { 0x103c0, 0x0 },
295 { 0x1103c0, 0x0 },
296 { 0x2103c0, 0x0 },
297 { 0x104c0, 0x0 },
298 { 0x1104c0, 0x0 },
299 { 0x2104c0, 0x0 },
300 { 0x105c0, 0x0 },
301 { 0x1105c0, 0x0 },
302 { 0x2105c0, 0x0 },
303 { 0x106c0, 0x0 },
304 { 0x1106c0, 0x0 },
305 { 0x2106c0, 0x0 },
306 { 0x107c0, 0x0 },
307 { 0x1107c0, 0x0 },
308 { 0x2107c0, 0x0 },
309 { 0x108c0, 0x0 },
310 { 0x1108c0, 0x0 },
311 { 0x2108c0, 0x0 },
312 { 0x110c0, 0x0 },
313 { 0x1110c0, 0x0 },
314 { 0x2110c0, 0x0 },
315 { 0x111c0, 0x0 },
316 { 0x1111c0, 0x0 },
317 { 0x2111c0, 0x0 },
318 { 0x112c0, 0x0 },
319 { 0x1112c0, 0x0 },
320 { 0x2112c0, 0x0 },
321 { 0x113c0, 0x0 },
322 { 0x1113c0, 0x0 },
323 { 0x2113c0, 0x0 },
324 { 0x114c0, 0x0 },
325 { 0x1114c0, 0x0 },
326 { 0x2114c0, 0x0 },
327 { 0x115c0, 0x0 },
328 { 0x1115c0, 0x0 },
329 { 0x2115c0, 0x0 },
330 { 0x116c0, 0x0 },
331 { 0x1116c0, 0x0 },
332 { 0x2116c0, 0x0 },
333 { 0x117c0, 0x0 },
334 { 0x1117c0, 0x0 },
335 { 0x2117c0, 0x0 },
336 { 0x118c0, 0x0 },
337 { 0x1118c0, 0x0 },
338 { 0x2118c0, 0x0 },
339 { 0x120c0, 0x0 },
340 { 0x1120c0, 0x0 },
341 { 0x2120c0, 0x0 },
342 { 0x121c0, 0x0 },
343 { 0x1121c0, 0x0 },
344 { 0x2121c0, 0x0 },
345 { 0x122c0, 0x0 },
346 { 0x1122c0, 0x0 },
347 { 0x2122c0, 0x0 },
348 { 0x123c0, 0x0 },
349 { 0x1123c0, 0x0 },
350 { 0x2123c0, 0x0 },
351 { 0x124c0, 0x0 },
352 { 0x1124c0, 0x0 },
353 { 0x2124c0, 0x0 },
354 { 0x125c0, 0x0 },
355 { 0x1125c0, 0x0 },
356 { 0x2125c0, 0x0 },
357 { 0x126c0, 0x0 },
358 { 0x1126c0, 0x0 },
359 { 0x2126c0, 0x0 },
360 { 0x127c0, 0x0 },
361 { 0x1127c0, 0x0 },
362 { 0x2127c0, 0x0 },
363 { 0x128c0, 0x0 },
364 { 0x1128c0, 0x0 },
365 { 0x2128c0, 0x0 },
366 { 0x130c0, 0x0 },
367 { 0x1130c0, 0x0 },
368 { 0x2130c0, 0x0 },
369 { 0x131c0, 0x0 },
370 { 0x1131c0, 0x0 },
371 { 0x2131c0, 0x0 },
372 { 0x132c0, 0x0 },
373 { 0x1132c0, 0x0 },
374 { 0x2132c0, 0x0 },
375 { 0x133c0, 0x0 },
376 { 0x1133c0, 0x0 },
377 { 0x2133c0, 0x0 },
378 { 0x134c0, 0x0 },
379 { 0x1134c0, 0x0 },
380 { 0x2134c0, 0x0 },
381 { 0x135c0, 0x0 },
382 { 0x1135c0, 0x0 },
383 { 0x2135c0, 0x0 },
384 { 0x136c0, 0x0 },
385 { 0x1136c0, 0x0 },
386 { 0x2136c0, 0x0 },
387 { 0x137c0, 0x0 },
388 { 0x1137c0, 0x0 },
389 { 0x2137c0, 0x0 },
390 { 0x138c0, 0x0 },
391 { 0x1138c0, 0x0 },
392 { 0x2138c0, 0x0 },
393 { 0x100c1, 0x0 },
394 { 0x1100c1, 0x0 },
395 { 0x2100c1, 0x0 },
396 { 0x101c1, 0x0 },
397 { 0x1101c1, 0x0 },
398 { 0x2101c1, 0x0 },
399 { 0x102c1, 0x0 },
400 { 0x1102c1, 0x0 },
401 { 0x2102c1, 0x0 },
402 { 0x103c1, 0x0 },
403 { 0x1103c1, 0x0 },
404 { 0x2103c1, 0x0 },
405 { 0x104c1, 0x0 },
406 { 0x1104c1, 0x0 },
407 { 0x2104c1, 0x0 },
408 { 0x105c1, 0x0 },
409 { 0x1105c1, 0x0 },
410 { 0x2105c1, 0x0 },
411 { 0x106c1, 0x0 },
412 { 0x1106c1, 0x0 },
413 { 0x2106c1, 0x0 },
414 { 0x107c1, 0x0 },
415 { 0x1107c1, 0x0 },
416 { 0x2107c1, 0x0 },
417 { 0x108c1, 0x0 },
418 { 0x1108c1, 0x0 },
419 { 0x2108c1, 0x0 },
420 { 0x110c1, 0x0 },
421 { 0x1110c1, 0x0 },
422 { 0x2110c1, 0x0 },
423 { 0x111c1, 0x0 },
424 { 0x1111c1, 0x0 },
425 { 0x2111c1, 0x0 },
426 { 0x112c1, 0x0 },
427 { 0x1112c1, 0x0 },
428 { 0x2112c1, 0x0 },
429 { 0x113c1, 0x0 },
430 { 0x1113c1, 0x0 },
431 { 0x2113c1, 0x0 },
432 { 0x114c1, 0x0 },
433 { 0x1114c1, 0x0 },
434 { 0x2114c1, 0x0 },
435 { 0x115c1, 0x0 },
436 { 0x1115c1, 0x0 },
437 { 0x2115c1, 0x0 },
438 { 0x116c1, 0x0 },
439 { 0x1116c1, 0x0 },
440 { 0x2116c1, 0x0 },
441 { 0x117c1, 0x0 },
442 { 0x1117c1, 0x0 },
443 { 0x2117c1, 0x0 },
444 { 0x118c1, 0x0 },
445 { 0x1118c1, 0x0 },
446 { 0x2118c1, 0x0 },
447 { 0x120c1, 0x0 },
448 { 0x1120c1, 0x0 },
449 { 0x2120c1, 0x0 },
450 { 0x121c1, 0x0 },
451 { 0x1121c1, 0x0 },
452 { 0x2121c1, 0x0 },
453 { 0x122c1, 0x0 },
454 { 0x1122c1, 0x0 },
455 { 0x2122c1, 0x0 },
456 { 0x123c1, 0x0 },
457 { 0x1123c1, 0x0 },
458 { 0x2123c1, 0x0 },
459 { 0x124c1, 0x0 },
460 { 0x1124c1, 0x0 },
461 { 0x2124c1, 0x0 },
462 { 0x125c1, 0x0 },
463 { 0x1125c1, 0x0 },
464 { 0x2125c1, 0x0 },
465 { 0x126c1, 0x0 },
466 { 0x1126c1, 0x0 },
467 { 0x2126c1, 0x0 },
468 { 0x127c1, 0x0 },
469 { 0x1127c1, 0x0 },
470 { 0x2127c1, 0x0 },
471 { 0x128c1, 0x0 },
472 { 0x1128c1, 0x0 },
473 { 0x2128c1, 0x0 },
474 { 0x130c1, 0x0 },
475 { 0x1130c1, 0x0 },
476 { 0x2130c1, 0x0 },
477 { 0x131c1, 0x0 },
478 { 0x1131c1, 0x0 },
479 { 0x2131c1, 0x0 },
480 { 0x132c1, 0x0 },
481 { 0x1132c1, 0x0 },
482 { 0x2132c1, 0x0 },
483 { 0x133c1, 0x0 },
484 { 0x1133c1, 0x0 },
485 { 0x2133c1, 0x0 },
486 { 0x134c1, 0x0 },
487 { 0x1134c1, 0x0 },
488 { 0x2134c1, 0x0 },
489 { 0x135c1, 0x0 },
490 { 0x1135c1, 0x0 },
491 { 0x2135c1, 0x0 },
492 { 0x136c1, 0x0 },
493 { 0x1136c1, 0x0 },
494 { 0x2136c1, 0x0 },
495 { 0x137c1, 0x0 },
496 { 0x1137c1, 0x0 },
497 { 0x2137c1, 0x0 },
498 { 0x138c1, 0x0 },
499 { 0x1138c1, 0x0 },
500 { 0x2138c1, 0x0 },
501 { 0x10020, 0x0 },
502 { 0x110020, 0x0 },
503 { 0x210020, 0x0 },
504 { 0x11020, 0x0 },
505 { 0x111020, 0x0 },
506 { 0x211020, 0x0 },
507 { 0x12020, 0x0 },
508 { 0x112020, 0x0 },
509 { 0x212020, 0x0 },
510 { 0x13020, 0x0 },
511 { 0x113020, 0x0 },
512 { 0x213020, 0x0 },
513 { 0x20072, 0x0 },
514 { 0x20073, 0x0 },
515 { 0x20074, 0x0 },
516 { 0x100aa, 0x0 },
517 { 0x110aa, 0x0 },
518 { 0x120aa, 0x0 },
519 { 0x130aa, 0x0 },
520 { 0x20010, 0x0 },
521 { 0x120010, 0x0 },
522 { 0x220010, 0x0 },
523 { 0x20011, 0x0 },
524 { 0x120011, 0x0 },
525 { 0x220011, 0x0 },
526 { 0x100ae, 0x0 },
527 { 0x1100ae, 0x0 },
528 { 0x2100ae, 0x0 },
529 { 0x100af, 0x0 },
530 { 0x1100af, 0x0 },
531 { 0x2100af, 0x0 },
532 { 0x110ae, 0x0 },
533 { 0x1110ae, 0x0 },
534 { 0x2110ae, 0x0 },
535 { 0x110af, 0x0 },
536 { 0x1110af, 0x0 },
537 { 0x2110af, 0x0 },
538 { 0x120ae, 0x0 },
539 { 0x1120ae, 0x0 },
540 { 0x2120ae, 0x0 },
541 { 0x120af, 0x0 },
542 { 0x1120af, 0x0 },
543 { 0x2120af, 0x0 },
544 { 0x130ae, 0x0 },
545 { 0x1130ae, 0x0 },
546 { 0x2130ae, 0x0 },
547 { 0x130af, 0x0 },
548 { 0x1130af, 0x0 },
549 { 0x2130af, 0x0 },
550 { 0x20020, 0x0 },
551 { 0x120020, 0x0 },
552 { 0x220020, 0x0 },
553 { 0x100a0, 0x0 },
554 { 0x100a1, 0x0 },
555 { 0x100a2, 0x0 },
556 { 0x100a3, 0x0 },
557 { 0x100a4, 0x0 },
558 { 0x100a5, 0x0 },
559 { 0x100a6, 0x0 },
560 { 0x100a7, 0x0 },
561 { 0x110a0, 0x0 },
562 { 0x110a1, 0x0 },
563 { 0x110a2, 0x0 },
564 { 0x110a3, 0x0 },
565 { 0x110a4, 0x0 },
566 { 0x110a5, 0x0 },
567 { 0x110a6, 0x0 },
568 { 0x110a7, 0x0 },
569 { 0x120a0, 0x0 },
570 { 0x120a1, 0x0 },
571 { 0x120a2, 0x0 },
572 { 0x120a3, 0x0 },
573 { 0x120a4, 0x0 },
574 { 0x120a5, 0x0 },
575 { 0x120a6, 0x0 },
576 { 0x120a7, 0x0 },
577 { 0x130a0, 0x0 },
578 { 0x130a1, 0x0 },
579 { 0x130a2, 0x0 },
580 { 0x130a3, 0x0 },
581 { 0x130a4, 0x0 },
582 { 0x130a5, 0x0 },
583 { 0x130a6, 0x0 },
584 { 0x130a7, 0x0 },
585 { 0x2007c, 0x0 },
586 { 0x12007c, 0x0 },
587 { 0x22007c, 0x0 },
588 { 0x2007d, 0x0 },
589 { 0x12007d, 0x0 },
590 { 0x22007d, 0x0 },
591 { 0x400fd, 0x0 },
592 { 0x400c0, 0x0 },
593 { 0x90201, 0x0 },
594 { 0x190201, 0x0 },
595 { 0x290201, 0x0 },
596 { 0x90202, 0x0 },
597 { 0x190202, 0x0 },
598 { 0x290202, 0x0 },
599 { 0x90203, 0x0 },
600 { 0x190203, 0x0 },
601 { 0x290203, 0x0 },
602 { 0x90204, 0x0 },
603 { 0x190204, 0x0 },
604 { 0x290204, 0x0 },
605 { 0x90205, 0x0 },
606 { 0x190205, 0x0 },
607 { 0x290205, 0x0 },
608 { 0x90206, 0x0 },
609 { 0x190206, 0x0 },
610 { 0x290206, 0x0 },
611 { 0x90207, 0x0 },
612 { 0x190207, 0x0 },
613 { 0x290207, 0x0 },
614 { 0x90208, 0x0 },
615 { 0x190208, 0x0 },
616 { 0x290208, 0x0 },
617 { 0x10062, 0x0 },
618 { 0x10162, 0x0 },
619 { 0x10262, 0x0 },
620 { 0x10362, 0x0 },
621 { 0x10462, 0x0 },
622 { 0x10562, 0x0 },
623 { 0x10662, 0x0 },
624 { 0x10762, 0x0 },
625 { 0x10862, 0x0 },
626 { 0x11062, 0x0 },
627 { 0x11162, 0x0 },
628 { 0x11262, 0x0 },
629 { 0x11362, 0x0 },
630 { 0x11462, 0x0 },
631 { 0x11562, 0x0 },
632 { 0x11662, 0x0 },
633 { 0x11762, 0x0 },
634 { 0x11862, 0x0 },
635 { 0x12062, 0x0 },
636 { 0x12162, 0x0 },
637 { 0x12262, 0x0 },
638 { 0x12362, 0x0 },
639 { 0x12462, 0x0 },
640 { 0x12562, 0x0 },
641 { 0x12662, 0x0 },
642 { 0x12762, 0x0 },
643 { 0x12862, 0x0 },
644 { 0x13062, 0x0 },
645 { 0x13162, 0x0 },
646 { 0x13262, 0x0 },
647 { 0x13362, 0x0 },
648 { 0x13462, 0x0 },
649 { 0x13562, 0x0 },
650 { 0x13662, 0x0 },
651 { 0x13762, 0x0 },
652 { 0x13862, 0x0 },
653 { 0x20077, 0x0 },
654 { 0x10001, 0x0 },
655 { 0x11001, 0x0 },
656 { 0x12001, 0x0 },
657 { 0x13001, 0x0 },
658 { 0x10040, 0x0 },
659 { 0x10140, 0x0 },
660 { 0x10240, 0x0 },
661 { 0x10340, 0x0 },
662 { 0x10440, 0x0 },
663 { 0x10540, 0x0 },
664 { 0x10640, 0x0 },
665 { 0x10740, 0x0 },
666 { 0x10840, 0x0 },
667 { 0x10030, 0x0 },
668 { 0x10130, 0x0 },
669 { 0x10230, 0x0 },
670 { 0x10330, 0x0 },
671 { 0x10430, 0x0 },
672 { 0x10530, 0x0 },
673 { 0x10630, 0x0 },
674 { 0x10730, 0x0 },
675 { 0x10830, 0x0 },
676 { 0x11040, 0x0 },
677 { 0x11140, 0x0 },
678 { 0x11240, 0x0 },
679 { 0x11340, 0x0 },
680 { 0x11440, 0x0 },
681 { 0x11540, 0x0 },
682 { 0x11640, 0x0 },
683 { 0x11740, 0x0 },
684 { 0x11840, 0x0 },
685 { 0x11030, 0x0 },
686 { 0x11130, 0x0 },
687 { 0x11230, 0x0 },
688 { 0x11330, 0x0 },
689 { 0x11430, 0x0 },
690 { 0x11530, 0x0 },
691 { 0x11630, 0x0 },
692 { 0x11730, 0x0 },
693 { 0x11830, 0x0 },
694 { 0x12040, 0x0 },
695 { 0x12140, 0x0 },
696 { 0x12240, 0x0 },
697 { 0x12340, 0x0 },
698 { 0x12440, 0x0 },
699 { 0x12540, 0x0 },
700 { 0x12640, 0x0 },
701 { 0x12740, 0x0 },
702 { 0x12840, 0x0 },
703 { 0x12030, 0x0 },
704 { 0x12130, 0x0 },
705 { 0x12230, 0x0 },
706 { 0x12330, 0x0 },
707 { 0x12430, 0x0 },
708 { 0x12530, 0x0 },
709 { 0x12630, 0x0 },
710 { 0x12730, 0x0 },
711 { 0x12830, 0x0 },
712 { 0x13040, 0x0 },
713 { 0x13140, 0x0 },
714 { 0x13240, 0x0 },
715 { 0x13340, 0x0 },
716 { 0x13440, 0x0 },
717 { 0x13540, 0x0 },
718 { 0x13640, 0x0 },
719 { 0x13740, 0x0 },
720 { 0x13840, 0x0 },
721 { 0x13030, 0x0 },
722 { 0x13130, 0x0 },
723 { 0x13230, 0x0 },
724 { 0x13330, 0x0 },
725 { 0x13430, 0x0 },
726 { 0x13530, 0x0 },
727 { 0x13630, 0x0 },
728 { 0x13730, 0x0 },
729 { 0x13830, 0x0 },
730};
731
732uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr);
diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c
new file mode 100644
index 0000000000..18f7ed7fea
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddrphy_train.c
@@ -0,0 +1,86 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <linux/kernel.h>
8#include <asm/arch/ddr.h>
9#include <asm/arch/lpddr4_define.h>
10
11void ddr_cfg_phy(struct dram_timing_info *dram_timing)
12{
13 struct dram_cfg_param *dram_cfg;
14 struct dram_fsp_msg *fsp_msg;
15 unsigned int num;
16 int i = 0;
17 int j = 0;
18
19 /* initialize PHY configuration */
20 dram_cfg = dram_timing->ddrphy_cfg;
21 num = dram_timing->ddrphy_cfg_num;
22 for (i = 0; i < num; i++) {
23 /* config phy reg */
24 dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
25 dram_cfg++;
26 }
27
28 /* load the frequency setpoint message block config */
29 fsp_msg = dram_timing->fsp_msg;
30 for (i = 0; i < dram_timing->fsp_msg_num; i++) {
31 debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
32 /* set dram PHY input clocks to desired frequency */
33 ddrphy_init_set_dfi_clk(fsp_msg->drate);
34
35 /* load the dram training firmware image */
36 dwc_ddrphy_apb_wr(0xd0000, 0x0);
37 ddr_load_train_firmware(fsp_msg->fw_type);
38
39 /* load the frequency set point message block parameter */
40 dram_cfg = fsp_msg->fsp_cfg;
41 num = fsp_msg->fsp_cfg_num;
42 for (j = 0; j < num; j++) {
43 dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
44 dram_cfg++;
45 }
46
47 /*
48 * -------------------- excute the firmware --------------------
49 * Running the firmware is a simply process to taking the
50 * PMU out of reset and stall, then the firwmare will be run
51 * 1. reset the PMU;
52 * 2. begin the excution;
53 * 3. wait for the training done;
54 * 4. read the message block result.
55 * -------------------------------------------------------------
56 */
57 dwc_ddrphy_apb_wr(0xd0000, 0x1);
58 dwc_ddrphy_apb_wr(0xd0099, 0x9);
59 dwc_ddrphy_apb_wr(0xd0099, 0x1);
60 dwc_ddrphy_apb_wr(0xd0099, 0x0);
61
62 /* Wait for the training firmware to complete */
63 wait_ddrphy_training_complete();
64
65 /* Halt the microcontroller. */
66 dwc_ddrphy_apb_wr(0xd0099, 0x1);
67
68 /* Read the Message Block results */
69 dwc_ddrphy_apb_wr(0xd0000, 0x0);
70 ddrphy_init_read_msg_block(fsp_msg->fw_type);
71 dwc_ddrphy_apb_wr(0xd0000, 0x1);
72
73 fsp_msg++;
74 }
75
76 /* Load PHY Init Engine Image */
77 dram_cfg = dram_timing->ddrphy_pie;
78 num = dram_timing->ddrphy_pie_num;
79 for (i = 0; i < num; i++) {
80 dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
81 dram_cfg++;
82 }
83
84 /* save the ddr PHY trained CSR in memory for low power use */
85 ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
86}
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
new file mode 100644
index 0000000000..4732539764
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -0,0 +1,186 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3* Copyright 2018 NXP
4*/
5
6#include <common.h>
7#include <errno.h>
8#include <asm/io.h>
9#include <asm/arch/ddr.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/ddr.h>
12#include <asm/arch/lpddr4_define.h>
13
14static inline void poll_pmu_message_ready(void)
15{
16 unsigned int reg;
17
18 do {
19 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
20 } while (reg & 0x1);
21}
22
23static inline void ack_pmu_message_receive(void)
24{
25 unsigned int reg;
26
27 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
28
29 do {
30 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
31 } while (!(reg & 0x1));
32
33 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
34}
35
36static inline unsigned int get_mail(void)
37{
38 unsigned int reg;
39
40 poll_pmu_message_ready();
41
42 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
43
44 ack_pmu_message_receive();
45
46 return reg;
47}
48
49static inline unsigned int get_stream_message(void)
50{
51 unsigned int reg, reg2;
52
53 poll_pmu_message_ready();
54
55 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
56
57 reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
58
59 reg2 = (reg2 << 16) | reg;
60
61 ack_pmu_message_receive();
62
63 return reg2;
64}
65
66static inline void decode_major_message(unsigned int mail)
67{
68 debug("[PMU Major message = 0x%08x]\n", mail);
69}
70
71static inline void decode_streaming_message(void)
72{
73 unsigned int string_index, arg __maybe_unused;
74 int i = 0;
75
76 string_index = get_stream_message();
77 debug("PMU String index = 0x%08x\n", string_index);
78 while (i < (string_index & 0xffff)) {
79 arg = get_stream_message();
80 debug("arg[%d] = 0x%08x\n", i, arg);
81 i++;
82 }
83
84 debug("\n");
85}
86
87void wait_ddrphy_training_complete(void)
88{
89 unsigned int mail;
90
91 while (1) {
92 mail = get_mail();
93 decode_major_message(mail);
94 if (mail == 0x08) {
95 decode_streaming_message();
96 } else if (mail == 0x07) {
97 debug("Training PASS\n");
98 break;
99 } else if (mail == 0xff) {
100 printf("Training FAILED\n");
101 break;
102 }
103 }
104}
105
106void ddrphy_init_set_dfi_clk(unsigned int drate)
107{
108 switch (drate) {
109 case 3200:
110 dram_pll_init(MHZ(800));
111 dram_disable_bypass();
112 break;
113 case 3000:
114 dram_pll_init(MHZ(750));
115 dram_disable_bypass();
116 break;
117 case 2400:
118 dram_pll_init(MHZ(600));
119 dram_disable_bypass();
120 break;
121 case 1600:
122 dram_pll_init(MHZ(400));
123 dram_disable_bypass();
124 break;
125 case 667:
126 dram_pll_init(MHZ(167));
127 dram_disable_bypass();
128 break;
129 case 400:
130 dram_enable_bypass(MHZ(400));
131 break;
132 case 100:
133 dram_enable_bypass(MHZ(100));
134 break;
135 default:
136 return;
137 }
138}
139
140void ddrphy_init_read_msg_block(enum fw_type type)
141{
142}
143
144void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
145 unsigned int mr_data)
146{
147 unsigned int tmp;
148 /*
149 * 1. Poll MRSTAT.mr_wr_busy until it is 0.
150 * This checks that there is no outstanding MR transaction.
151 * No writes should be performed to MRCTRL0 and MRCTRL1 if
152 * MRSTAT.mr_wr_busy = 1.
153 */
154 do {
155 tmp = reg32_read(DDRC_MRSTAT(0));
156 } while (tmp & 0x1);
157 /*
158 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
159 * (for MRWs) MRCTRL1.mr_data to define the MR transaction.
160 */
161 reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
162 reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
163 reg32setbit(DDRC_MRCTRL0(0), 31);
164}
165
166unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
167{
168 unsigned int tmp;
169
170 reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
171 do {
172 tmp = reg32_read(DDRC_MRSTAT(0));
173 } while (tmp & 0x1);
174
175 reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
176 reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
177 reg32setbit(DDRC_MRCTRL0(0), 31);
178 do {
179 tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
180 } while ((tmp & 0x8) == 0);
181 tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
182 tmp = tmp & 0xff;
183 reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
184
185 return tmp;
186}
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
new file mode 100644
index 0000000000..61cd4f6db1
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -0,0 +1,170 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <spl.h>
8#include <asm/io.h>
9#include <errno.h>
10#include <asm/io.h>
11#include <asm/arch/ddr.h>
12#include <asm/arch/ddr.h>
13#include <asm/arch/lpddr4_define.h>
14#include <asm/sections.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define IMEM_LEN 32768 /* byte */
19#define DMEM_LEN 16384 /* byte */
20#define IMEM_2D_OFFSET 49152
21
22#define IMEM_OFFSET_ADDR 0x00050000
23#define DMEM_OFFSET_ADDR 0x00054000
24#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
25
26/* We need PHY iMEM PHY is 32KB padded */
27void ddr_load_train_firmware(enum fw_type type)
28{
29 u32 tmp32, i;
30 u32 error = 0;
31 unsigned long pr_to32, pr_from32;
32 unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
33 unsigned long imem_start = (unsigned long)&_end + fw_offset;
34 unsigned long dmem_start = imem_start + IMEM_LEN;
35
36 pr_from32 = imem_start;
37 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
38 for (i = 0x0; i < IMEM_LEN; ) {
39 tmp32 = readl(pr_from32);
40 writew(tmp32 & 0x0000ffff, pr_to32);
41 pr_to32 += 4;
42 writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
43 pr_to32 += 4;
44 pr_from32 += 4;
45 i += 4;
46 }
47
48 pr_from32 = dmem_start;
49 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
50 for (i = 0x0; i < DMEM_LEN; ) {
51 tmp32 = readl(pr_from32);
52 writew(tmp32 & 0x0000ffff, pr_to32);
53 pr_to32 += 4;
54 writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
55 pr_to32 += 4;
56 pr_from32 += 4;
57 i += 4;
58 }
59
60 debug("check ddr4_pmu_train_imem code\n");
61 pr_from32 = imem_start;
62 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
63 for (i = 0x0; i < IMEM_LEN; ) {
64 tmp32 = (readw(pr_to32) & 0x0000ffff);
65 pr_to32 += 4;
66 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
67
68 if (tmp32 != readl(pr_from32)) {
69 debug("%lx %lx\n", pr_from32, pr_to32);
70 error++;
71 }
72 pr_from32 += 4;
73 pr_to32 += 4;
74 i += 4;
75 }
76 if (error)
77 printf("check ddr4_pmu_train_imem code fail=%d\n", error);
78 else
79 debug("check ddr4_pmu_train_imem code pass\n");
80
81 debug("check ddr4_pmu_train_dmem code\n");
82 pr_from32 = dmem_start;
83 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
84 for (i = 0x0; i < DMEM_LEN;) {
85 tmp32 = (readw(pr_to32) & 0x0000ffff);
86 pr_to32 += 4;
87 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
88 if (tmp32 != readl(pr_from32)) {
89 debug("%lx %lx\n", pr_from32, pr_to32);
90 error++;
91 }
92 pr_from32 += 4;
93 pr_to32 += 4;
94 i += 4;
95 }
96
97 if (error)
98 printf("check ddr4_pmu_train_dmem code fail=%d", error);
99 else
100 debug("check ddr4_pmu_train_dmem code pass\n");
101}
102
103void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
104 unsigned int num)
105{
106 int i = 0;
107
108 /* enable the ddrphy apb */
109 dwc_ddrphy_apb_wr(0xd0000, 0x0);
110 dwc_ddrphy_apb_wr(0xc0080, 0x3);
111 for (i = 0; i < num; i++) {
112 ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
113 ddrphy_csr++;
114 }
115 /* disable the ddrphy apb */
116 dwc_ddrphy_apb_wr(0xc0080, 0x2);
117 dwc_ddrphy_apb_wr(0xd0000, 0x1);
118}
119
120void dram_config_save(struct dram_timing_info *timing_info,
121 unsigned long saved_timing_base)
122{
123 int i = 0;
124 struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
125 struct dram_cfg_param *cfg;
126
127 saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
128 saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
129 saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
130 saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
131
132 /* save the fsp table */
133 for (i = 0; i < 4; i++)
134 saved_timing->fsp_table[i] = timing_info->fsp_table[i];
135
136 cfg = (struct dram_cfg_param *)(saved_timing_base +
137 sizeof(*timing_info));
138
139 /* save ddrc config */
140 saved_timing->ddrc_cfg = cfg;
141 for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
142 cfg->reg = timing_info->ddrc_cfg[i].reg;
143 cfg->val = timing_info->ddrc_cfg[i].val;
144 cfg++;
145 }
146
147 /* save ddrphy config */
148 saved_timing->ddrphy_cfg = cfg;
149 for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
150 cfg->reg = timing_info->ddrphy_cfg[i].reg;
151 cfg->val = timing_info->ddrphy_cfg[i].val;
152 cfg++;
153 }
154
155 /* save the ddrphy csr */
156 saved_timing->ddrphy_trained_csr = cfg;
157 for (i = 0; i < ddrphy_trained_csr_num; i++) {
158 cfg->reg = ddrphy_trained_csr[i].reg;
159 cfg->val = ddrphy_trained_csr[i].val;
160 cfg++;
161 }
162
163 /* save the ddrphy pie */
164 saved_timing->ddrphy_pie = cfg;
165 for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
166 cfg->reg = timing_info->ddrphy_pie[i].reg;
167 cfg->val = timing_info->ddrphy_pie[i].val;
168 cfg++;
169 }
170}
diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c
new file mode 100644
index 0000000000..a4bc1de8eb
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/lpddr4_init.c
@@ -0,0 +1,188 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3* Copyright 2018 NXP
4*
5*/
6
7#include <common.h>
8#include <errno.h>
9#include <asm/io.h>
10#include <asm/arch/ddr.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/ddr.h>
13#include <asm/arch/lpddr4_define.h>
14#include <asm/arch/sys_proto.h>
15
16void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
17{
18 int i = 0;
19
20 for (i = 0; i < num; i++) {
21 reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
22 ddrc_cfg++;
23 }
24}
25
26void ddr_init(struct dram_timing_info *dram_timing)
27{
28 unsigned int tmp;
29
30 debug("DDRINFO: start lpddr4 ddr init\n");
31 /* step 1: reset */
32 if (is_imx8mq()) {
33 reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
34 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
35 reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
36 } else {
37 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
38 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
39 }
40
41 mdelay(100);
42
43 debug("DDRINFO: reset done\n");
44 /*
45 * change the clock source of dram_apb_clk_root:
46 * source 4 800MHz /4 = 200MHz
47 */
48 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
49 CLK_ROOT_SOURCE_SEL(4) |
50 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
51
52 /* disable iso */
53 reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
54 reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
55
56 debug("DDRINFO: cfg clk\n");
57 dram_pll_init(MHZ(750));
58
59 /*
60 * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
61 * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
62 */
63 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
64
65 /*step2 Configure uMCTL2's registers */
66 debug("DDRINFO: ddrc config start\n");
67 lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
68 debug("DDRINFO: ddrc config done\n");
69
70 /*
71 * step3 de-assert all reset
72 * RESET: <core_ddrc_rstn> DEASSERTED
73 * RESET: <aresetn> for Port 0 DEASSERT(0)ED
74 */
75 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
76 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
77
78 reg32_write(DDRC_DBG1(0), 0x00000000);
79 /* step4 */
80 /* [0]dis_auto_refresh=1 */
81 reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
82
83 /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */
84 reg32_write(DDRC_PWRCTL(0), 0x000000a8);
85
86 do {
87 tmp = reg32_read(DDRC_STAT(0));
88 } while ((tmp & 0x33f) != 0x223);
89
90 reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
91
92 /* step5 */
93 reg32_write(DDRC_SWCTL(0), 0x00000000);
94
95 /* step6 */
96 tmp = reg32_read(DDRC_MSTR2(0));
97 if (tmp == 0x2)
98 reg32_write(DDRC_DFIMISC(0), 0x00000210);
99 else if (tmp == 0x1)
100 reg32_write(DDRC_DFIMISC(0), 0x00000110);
101 else
102 reg32_write(DDRC_DFIMISC(0), 0x00000010);
103
104 /* step7 [0]--1: disable quasi-dynamic programming */
105 reg32_write(DDRC_SWCTL(0), 0x00000001);
106
107 /* step8 Configure LPDDR4 PHY's registers */
108 debug("DDRINFO:ddrphy config start\n");
109 ddr_cfg_phy(dram_timing);
110 debug("DDRINFO: ddrphy config done\n");
111
112 /*
113 * step14 CalBusy.0 =1, indicates the calibrator is actively
114 * calibrating. Wait Calibrating done.
115 */
116 do {
117 tmp = reg32_read(DDRPHY_CalBusy(0));
118 } while ((tmp & 0x1));
119
120 debug("DDRINFO:ddrphy calibration done\n");
121
122 /* step15 [0]--0: to enable quasi-dynamic programming */
123 reg32_write(DDRC_SWCTL(0), 0x00000000);
124
125 /* step16 */
126 tmp = reg32_read(DDRC_MSTR2(0));
127 if (tmp == 0x2)
128 reg32_write(DDRC_DFIMISC(0), 0x00000230);
129 else if (tmp == 0x1)
130 reg32_write(DDRC_DFIMISC(0), 0x00000130);
131 else
132 reg32_write(DDRC_DFIMISC(0), 0x00000030);
133
134 /* step17 [0]--1: disable quasi-dynamic programming */
135 reg32_write(DDRC_SWCTL(0), 0x00000001);
136 /* step18 wait DFISTAT.dfi_init_complete to 1 */
137 do {
138 tmp = reg32_read(DDRC_DFISTAT(0));
139 } while ((tmp & 0x1) == 0x0);
140
141 /* step19 */
142 reg32_write(DDRC_SWCTL(0), 0x00000000);
143
144 /* step20~22 */
145 tmp = reg32_read(DDRC_MSTR2(0));
146 if (tmp == 0x2) {
147 reg32_write(DDRC_DFIMISC(0), 0x00000210);
148 /* set DFIMISC.dfi_init_complete_en again */
149 reg32_write(DDRC_DFIMISC(0), 0x00000211);
150 } else if (tmp == 0x1) {
151 reg32_write(DDRC_DFIMISC(0), 0x00000110);
152 /* set DFIMISC.dfi_init_complete_en again */
153 reg32_write(DDRC_DFIMISC(0), 0x00000111);
154 } else {
155 /* clear DFIMISC.dfi_init_complete_en */
156 reg32_write(DDRC_DFIMISC(0), 0x00000010);
157 /* set DFIMISC.dfi_init_complete_en again */
158 reg32_write(DDRC_DFIMISC(0), 0x00000011);
159 }
160
161 /* step23 [5]selfref_sw=0; */
162 reg32_write(DDRC_PWRCTL(0), 0x00000008);
163 /* step24 sw_done=1 */
164 reg32_write(DDRC_SWCTL(0), 0x00000001);
165
166 /* step25 wait SWSTAT.sw_done_ack to 1 */
167 do {
168 tmp = reg32_read(DDRC_SWSTAT(0));
169 } while ((tmp & 0x1) == 0x0);
170
171#ifdef DFI_BUG_WR
172 reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
173#endif
174 /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
175 do {
176 tmp = reg32_read(DDRC_STAT(0));
177 } while ((tmp & 0x3) != 0x1);
178
179 /* step26 */
180 reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
181
182 /* enable port 0 */
183 reg32_write(DDRC_PCTRL_0(0), 0x00000001);
184 debug("DDRINFO: ddrmix config done\n");
185
186 /* save the dram timing config into memory */
187 dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
188}
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8a4162eccd..1820676d7a 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -26,6 +26,15 @@ config SANDBOX_DMA
26 Enable support for a test DMA uclass implementation. It stimulates 26 Enable support for a test DMA uclass implementation. It stimulates
27 DMA transfer by simple copying data between channels. 27 DMA transfer by simple copying data between channels.
28 28
29config BCM6348_IUDMA
30 bool "BCM6348 IUDMA driver"
31 depends on ARCH_BMIPS
32 select DMA_CHANNELS
33 help
34 Enable the BCM6348 IUDMA driver.
35 This driver support data transfer from devices to
36 memory and from memory to devices.
37
29config TI_EDMA3 38config TI_EDMA3
30 bool "TI EDMA3 driver" 39 bool "TI EDMA3 driver"
31 help 40 help
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index aff31f986a..b5f9147e0a 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_DMA) += dma-uclass.o
7 7
8obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o 8obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
9obj-$(CONFIG_APBH_DMA) += apbh_dma.o 9obj-$(CONFIG_APBH_DMA) += apbh_dma.o
10obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o
10obj-$(CONFIG_FSL_DMA) += fsl_dma.o 11obj-$(CONFIG_FSL_DMA) += fsl_dma.o
11obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o 12obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o
12obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o 13obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c
new file mode 100644
index 0000000000..1d3c192cfe
--- /dev/null
+++ b/drivers/dma/bcm6348-iudma.c
@@ -0,0 +1,642 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/dma/bcm63xx-iudma.c:
6 * Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu>
7 *
8 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
9 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
10 *
11 * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
12 * Copyright (C) 2000-2010 Broadcom Corporation
13 *
14 * Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c:
15 * Copyright (C) 2010 Broadcom Corporation
16 */
17
18#include <common.h>
19#include <clk.h>
20#include <dm.h>
21#include <dma-uclass.h>
22#include <memalign.h>
23#include <reset.h>
24#include <asm/io.h>
25
26#define DMA_RX_DESC 6
27#define DMA_TX_DESC 1
28
29/* DMA Channels */
30#define DMA_CHAN_FLOWC(x) ((x) >> 1)
31#define DMA_CHAN_MAX 16
32#define DMA_CHAN_SIZE 0x10
33#define DMA_CHAN_TOUT 500
34
35/* DMA Global Configuration register */
36#define DMA_CFG_REG 0x00
37#define DMA_CFG_ENABLE_SHIFT 0
38#define DMA_CFG_ENABLE_MASK (1 << DMA_CFG_ENABLE_SHIFT)
39#define DMA_CFG_FLOWC_ENABLE(x) BIT(DMA_CHAN_FLOWC(x) + 1)
40#define DMA_CFG_NCHANS_SHIFT 24
41#define DMA_CFG_NCHANS_MASK (0xf << DMA_CFG_NCHANS_SHIFT)
42
43/* DMA Global Flow Control registers */
44#define DMA_FLOWC_THR_LO_REG(x) (0x04 + DMA_CHAN_FLOWC(x) * 0x0c)
45#define DMA_FLOWC_THR_HI_REG(x) (0x08 + DMA_CHAN_FLOWC(x) * 0x0c)
46#define DMA_FLOWC_ALLOC_REG(x) (0x0c + DMA_CHAN_FLOWC(x) * 0x0c)
47#define DMA_FLOWC_ALLOC_FORCE_SHIFT 31
48#define DMA_FLOWC_ALLOC_FORCE_MASK (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT)
49
50/* DMA Global Reset register */
51#define DMA_RST_REG 0x34
52#define DMA_RST_CHAN_SHIFT 0
53#define DMA_RST_CHAN_MASK(x) (1 << x)
54
55/* DMA Channel Configuration register */
56#define DMAC_CFG_REG(x) (DMA_CHAN_SIZE * (x) + 0x00)
57#define DMAC_CFG_ENABLE_SHIFT 0
58#define DMAC_CFG_ENABLE_MASK (1 << DMAC_CFG_ENABLE_SHIFT)
59#define DMAC_CFG_PKT_HALT_SHIFT 1
60#define DMAC_CFG_PKT_HALT_MASK (1 << DMAC_CFG_PKT_HALT_SHIFT)
61#define DMAC_CFG_BRST_HALT_SHIFT 2
62#define DMAC_CFG_BRST_HALT_MASK (1 << DMAC_CFG_BRST_HALT_SHIFT)
63
64/* DMA Channel Max Burst Length register */
65#define DMAC_BURST_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c)
66
67/* DMA SRAM Descriptor Ring Start register */
68#define DMAS_RSTART_REG(x) (DMA_CHAN_SIZE * (x) + 0x00)
69
70/* DMA SRAM State/Bytes done/ring offset register */
71#define DMAS_STATE_DATA_REG(x) (DMA_CHAN_SIZE * (x) + 0x04)
72
73/* DMA SRAM Buffer Descriptor status and length register */
74#define DMAS_DESC_LEN_STATUS_REG(x) (DMA_CHAN_SIZE * (x) + 0x08)
75
76/* DMA SRAM Buffer Descriptor status and length register */
77#define DMAS_DESC_BASE_BUFPTR_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c)
78
79/* DMA Descriptor Status */
80#define DMAD_ST_CRC_SHIFT 8
81#define DMAD_ST_CRC_MASK (1 << DMAD_ST_CRC_SHIFT)
82#define DMAD_ST_WRAP_SHIFT 12
83#define DMAD_ST_WRAP_MASK (1 << DMAD_ST_WRAP_SHIFT)
84#define DMAD_ST_SOP_SHIFT 13
85#define DMAD_ST_SOP_MASK (1 << DMAD_ST_SOP_SHIFT)
86#define DMAD_ST_EOP_SHIFT 14
87#define DMAD_ST_EOP_MASK (1 << DMAD_ST_EOP_SHIFT)
88#define DMAD_ST_OWN_SHIFT 15
89#define DMAD_ST_OWN_MASK (1 << DMAD_ST_OWN_SHIFT)
90
91#define DMAD6348_ST_OV_ERR_SHIFT 0
92#define DMAD6348_ST_OV_ERR_MASK (1 << DMAD6348_ST_OV_ERR_SHIFT)
93#define DMAD6348_ST_CRC_ERR_SHIFT 1
94#define DMAD6348_ST_CRC_ERR_MASK (1 << DMAD6348_ST_CRC_ERR_SHIFT)
95#define DMAD6348_ST_RX_ERR_SHIFT 2
96#define DMAD6348_ST_RX_ERR_MASK (1 << DMAD6348_ST_RX_ERR_SHIFT)
97#define DMAD6348_ST_OS_ERR_SHIFT 4
98#define DMAD6348_ST_OS_ERR_MASK (1 << DMAD6348_ST_OS_ERR_SHIFT)
99#define DMAD6348_ST_UN_ERR_SHIFT 9
100#define DMAD6348_ST_UN_ERR_MASK (1 << DMAD6348_ST_UN_ERR_SHIFT)
101
102struct bcm6348_dma_desc {
103 uint16_t length;
104 uint16_t status;
105 uint32_t address;
106};
107
108struct bcm6348_chan_priv {
109 void __iomem *dma_ring;
110 uint8_t dma_ring_size;
111 uint8_t desc_id;
112 uint8_t desc_cnt;
113 bool *busy_desc;
114 bool running;
115};
116
117struct bcm6348_iudma_hw {
118 uint16_t err_mask;
119};
120
121struct bcm6348_iudma_priv {
122 const struct bcm6348_iudma_hw *hw;
123 void __iomem *base;
124 void __iomem *chan;
125 void __iomem *sram;
126 struct bcm6348_chan_priv **ch_priv;
127 uint8_t n_channels;
128};
129
130static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch)
131{
132 return !(ch & 1);
133}
134
135static inline void bcm6348_iudma_fdc(void *ptr, ulong size)
136{
137 ulong start = (ulong) ptr;
138
139 flush_dcache_range(start, start + size);
140}
141
142static inline void bcm6348_iudma_idc(void *ptr, ulong size)
143{
144 ulong start = (ulong) ptr;
145
146 invalidate_dcache_range(start, start + size);
147}
148
149static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv,
150 uint8_t ch)
151{
152 unsigned int timeout = DMA_CHAN_TOUT;
153
154 do {
155 uint32_t cfg, halt;
156
157 if (timeout > DMA_CHAN_TOUT / 2)
158 halt = DMAC_CFG_PKT_HALT_MASK;
159 else
160 halt = DMAC_CFG_BRST_HALT_MASK;
161
162 /* try to stop dma channel */
163 writel_be(halt, priv->chan + DMAC_CFG_REG(ch));
164 mb();
165
166 /* check if channel was stopped */
167 cfg = readl_be(priv->chan + DMAC_CFG_REG(ch));
168 if (!(cfg & DMAC_CFG_ENABLE_MASK))
169 break;
170
171 udelay(1);
172 } while (--timeout);
173
174 if (!timeout)
175 pr_err("unable to stop channel %u\n", ch);
176
177 /* reset dma channel */
178 setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
179 mb();
180 clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
181}
182
183static int bcm6348_iudma_disable(struct dma *dma)
184{
185 struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
186 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
187
188 /* stop dma channel */
189 bcm6348_iudma_chan_stop(priv, dma->id);
190
191 /* dma flow control */
192 if (bcm6348_iudma_chan_is_rx(dma->id))
193 writel_be(DMA_FLOWC_ALLOC_FORCE_MASK,
194 DMA_FLOWC_ALLOC_REG(dma->id));
195
196 /* init channel config */
197 ch_priv->running = false;
198 ch_priv->desc_id = 0;
199 if (bcm6348_iudma_chan_is_rx(dma->id))
200 ch_priv->desc_cnt = 0;
201 else
202 ch_priv->desc_cnt = ch_priv->dma_ring_size;
203
204 return 0;
205}
206
207static int bcm6348_iudma_enable(struct dma *dma)
208{
209 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
210 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
211 struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
212 uint8_t i;
213
214 /* dma ring init */
215 for (i = 0; i < ch_priv->desc_cnt; i++) {
216 if (bcm6348_iudma_chan_is_rx(dma->id)) {
217 ch_priv->busy_desc[i] = false;
218 dma_desc->status |= DMAD_ST_OWN_MASK;
219 } else {
220 dma_desc->status = 0;
221 dma_desc->length = 0;
222 dma_desc->address = 0;
223 }
224
225 if (i == ch_priv->desc_cnt - 1)
226 dma_desc->status |= DMAD_ST_WRAP_MASK;
227
228 dma_desc++;
229 }
230
231 /* init to first descriptor */
232 ch_priv->desc_id = 0;
233
234 /* force cache writeback */
235 bcm6348_iudma_fdc(ch_priv->dma_ring,
236 sizeof(*dma_desc) * ch_priv->desc_cnt);
237
238 /* clear sram */
239 writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id));
240 writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id));
241 writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id));
242
243 /* set dma ring start */
244 writel_be(virt_to_phys(ch_priv->dma_ring),
245 priv->sram + DMAS_RSTART_REG(dma->id));
246
247 /* set flow control */
248 if (bcm6348_iudma_chan_is_rx(dma->id)) {
249 u32 val;
250
251 setbits_be32(priv->base + DMA_CFG_REG,
252 DMA_CFG_FLOWC_ENABLE(dma->id));
253
254 val = ch_priv->desc_cnt / 3;
255 writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id));
256
257 val = (ch_priv->desc_cnt * 2) / 3;
258 writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id));
259
260 writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id));
261 }
262
263 /* set dma max burst */
264 writel_be(ch_priv->desc_cnt,
265 priv->chan + DMAC_BURST_REG(dma->id));
266
267 /* kick rx dma channel */
268 if (bcm6348_iudma_chan_is_rx(dma->id))
269 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
270 DMAC_CFG_ENABLE_MASK);
271
272 /* channel is now enabled */
273 ch_priv->running = true;
274
275 return 0;
276}
277
278static int bcm6348_iudma_request(struct dma *dma)
279{
280 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
281 struct bcm6348_chan_priv *ch_priv;
282
283 /* check if channel is valid */
284 if (dma->id >= priv->n_channels)
285 return -ENODEV;
286
287 /* alloc channel private data */
288 priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv));
289 if (!priv->ch_priv[dma->id])
290 return -ENOMEM;
291 ch_priv = priv->ch_priv[dma->id];
292
293 /* alloc dma ring */
294 if (bcm6348_iudma_chan_is_rx(dma->id))
295 ch_priv->dma_ring_size = DMA_RX_DESC;
296 else
297 ch_priv->dma_ring_size = DMA_TX_DESC;
298
299 ch_priv->dma_ring =
300 malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) *
301 ch_priv->dma_ring_size);
302 if (!ch_priv->dma_ring)
303 return -ENOMEM;
304
305 /* init channel config */
306 ch_priv->running = false;
307 ch_priv->desc_id = 0;
308 if (bcm6348_iudma_chan_is_rx(dma->id)) {
309 ch_priv->desc_cnt = 0;
310 ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
311 } else {
312 ch_priv->desc_cnt = ch_priv->dma_ring_size;
313 ch_priv->busy_desc = NULL;
314 }
315
316 return 0;
317}
318
319static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata)
320{
321 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
322 const struct bcm6348_iudma_hw *hw = priv->hw;
323 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
324 struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring;
325 int ret;
326
327 /* get dma ring descriptor address */
328 dma_desc += ch_priv->desc_id;
329
330 /* invalidate cache data */
331 bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
332
333 /* check dma own */
334 if (dma_desc->status & DMAD_ST_OWN_MASK)
335 return -EAGAIN;
336
337 /* check pkt */
338 if (!(dma_desc->status & DMAD_ST_EOP_MASK) ||
339 !(dma_desc->status & DMAD_ST_SOP_MASK) ||
340 (dma_desc->status & hw->err_mask)) {
341 pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n",
342 dma->id, ch_priv->desc_id, dma_desc->status);
343 ret = -EAGAIN;
344 } else {
345 /* set dma buffer address */
346 *dst = phys_to_virt(dma_desc->address);
347
348 /* invalidate cache data */
349 bcm6348_iudma_idc(*dst, dma_desc->length);
350
351 /* return packet length */
352 ret = dma_desc->length;
353 }
354
355 /* busy dma descriptor */
356 ch_priv->busy_desc[ch_priv->desc_id] = true;
357
358 /* increment dma descriptor */
359 ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
360
361 return ret;
362}
363
364static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len,
365 void *metadata)
366{
367 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
368 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
369 struct bcm6348_dma_desc *dma_desc;
370 uint16_t status;
371
372 /* flush cache */
373 bcm6348_iudma_fdc(src, len);
374
375 /* get dma ring descriptor address */
376 dma_desc = ch_priv->dma_ring;
377 dma_desc += ch_priv->desc_id;
378
379 /* config dma descriptor */
380 status = (DMAD_ST_OWN_MASK |
381 DMAD_ST_EOP_MASK |
382 DMAD_ST_CRC_MASK |
383 DMAD_ST_SOP_MASK);
384 if (ch_priv->desc_id == ch_priv->desc_cnt - 1)
385 status |= DMAD_ST_WRAP_MASK;
386
387 /* set dma descriptor */
388 dma_desc->address = virt_to_phys(src);
389 dma_desc->length = len;
390 dma_desc->status = status;
391
392 /* flush cache */
393 bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
394
395 /* kick tx dma channel */
396 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK);
397
398 /* poll dma status */
399 do {
400 /* invalidate cache */
401 bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
402
403 if (!(dma_desc->status & DMAD_ST_OWN_MASK))
404 break;
405 } while(1);
406
407 /* increment dma descriptor */
408 ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
409
410 return 0;
411}
412
413static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size)
414{
415 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
416 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
417 struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
418 uint16_t status;
419 uint8_t i;
420 u32 cfg;
421
422 /* get dirty dma descriptor */
423 for (i = 0; i < ch_priv->desc_cnt; i++) {
424 if (phys_to_virt(dma_desc->address) == dst)
425 break;
426
427 dma_desc++;
428 }
429
430 /* dma descriptor not found */
431 if (i == ch_priv->desc_cnt) {
432 pr_err("dirty dma descriptor not found\n");
433 return -ENOENT;
434 }
435
436 /* invalidate cache */
437 bcm6348_iudma_idc(ch_priv->dma_ring,
438 sizeof(*dma_desc) * ch_priv->desc_cnt);
439
440 /* free dma descriptor */
441 ch_priv->busy_desc[i] = false;
442
443 status = DMAD_ST_OWN_MASK;
444 if (i == ch_priv->desc_cnt - 1)
445 status |= DMAD_ST_WRAP_MASK;
446
447 dma_desc->status |= status;
448 dma_desc->length = PKTSIZE_ALIGN;
449
450 /* tell dma we allocated one buffer */
451 writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id));
452
453 /* flush cache */
454 bcm6348_iudma_fdc(ch_priv->dma_ring,
455 sizeof(*dma_desc) * ch_priv->desc_cnt);
456
457 /* kick rx dma channel if disabled */
458 cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id));
459 if (!(cfg & DMAC_CFG_ENABLE_MASK))
460 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
461 DMAC_CFG_ENABLE_MASK);
462
463 return 0;
464}
465
466static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size)
467{
468 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
469 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
470 struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
471
472 /* no more dma descriptors available */
473 if (ch_priv->desc_cnt == ch_priv->dma_ring_size) {
474 pr_err("max number of buffers reached\n");
475 return -EINVAL;
476 }
477
478 /* get next dma descriptor */
479 dma_desc += ch_priv->desc_cnt;
480
481 /* init dma descriptor */
482 dma_desc->address = virt_to_phys(dst);
483 dma_desc->length = size;
484 dma_desc->status = 0;
485
486 /* flush cache */
487 bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
488
489 /* increment dma descriptors */
490 ch_priv->desc_cnt++;
491
492 return 0;
493}
494
495static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst,
496 size_t size)
497{
498 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
499 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
500
501 /* only add new rx buffers if channel isn't running */
502 if (ch_priv->running)
503 return bcm6348_iudma_free_rcv_buf(dma, dst, size);
504 else
505 return bcm6348_iudma_add_rcv_buf(dma, dst, size);
506}
507
508static const struct dma_ops bcm6348_iudma_ops = {
509 .disable = bcm6348_iudma_disable,
510 .enable = bcm6348_iudma_enable,
511 .prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf,
512 .request = bcm6348_iudma_request,
513 .receive = bcm6348_iudma_receive,
514 .send = bcm6348_iudma_send,
515};
516
517static const struct bcm6348_iudma_hw bcm6348_hw = {
518 .err_mask = (DMAD6348_ST_OV_ERR_MASK |
519 DMAD6348_ST_CRC_ERR_MASK |
520 DMAD6348_ST_RX_ERR_MASK |
521 DMAD6348_ST_OS_ERR_MASK |
522 DMAD6348_ST_UN_ERR_MASK),
523};
524
525static const struct bcm6348_iudma_hw bcm6368_hw = {
526 .err_mask = 0,
527};
528
529static const struct udevice_id bcm6348_iudma_ids[] = {
530 {
531 .compatible = "brcm,bcm6348-iudma",
532 .data = (ulong)&bcm6348_hw,
533 }, {
534 .compatible = "brcm,bcm6368-iudma",
535 .data = (ulong)&bcm6368_hw,
536 }, { /* sentinel */ }
537};
538
539static int bcm6348_iudma_probe(struct udevice *dev)
540{
541 struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
542 struct bcm6348_iudma_priv *priv = dev_get_priv(dev);
543 const struct bcm6348_iudma_hw *hw =
544 (const struct bcm6348_iudma_hw *)dev_get_driver_data(dev);
545 uint8_t ch;
546 int i;
547
548 uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM |
549 DMA_SUPPORTS_MEM_TO_DEV);
550 priv->hw = hw;
551
552 /* dma global base address */
553 priv->base = dev_remap_addr_name(dev, "dma");
554 if (!priv->base)
555 return -EINVAL;
556
557 /* dma channels base address */
558 priv->chan = dev_remap_addr_name(dev, "dma-channels");
559 if (!priv->chan)
560 return -EINVAL;
561
562 /* dma sram base address */
563 priv->sram = dev_remap_addr_name(dev, "dma-sram");
564 if (!priv->sram)
565 return -EINVAL;
566
567 /* get number of channels */
568 priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8);
569 if (priv->n_channels > DMA_CHAN_MAX)
570 return -EINVAL;
571
572 /* try to enable clocks */
573 for (i = 0; ; i++) {
574 struct clk clk;
575 int ret;
576
577 ret = clk_get_by_index(dev, i, &clk);
578 if (ret < 0)
579 break;
580
581 ret = clk_enable(&clk);
582 if (ret < 0) {
583 pr_err("error enabling clock %d\n", i);
584 return ret;
585 }
586
587 ret = clk_free(&clk);
588 if (ret < 0) {
589 pr_err("error freeing clock %d\n", i);
590 return ret;
591 }
592 }
593
594 /* try to perform resets */
595 for (i = 0; ; i++) {
596 struct reset_ctl reset;
597 int ret;
598
599 ret = reset_get_by_index(dev, i, &reset);
600 if (ret < 0)
601 break;
602
603 ret = reset_deassert(&reset);
604 if (ret < 0) {
605 pr_err("error deasserting reset %d\n", i);
606 return ret;
607 }
608
609 ret = reset_free(&reset);
610 if (ret < 0) {
611 pr_err("error freeing reset %d\n", i);
612 return ret;
613 }
614 }
615
616 /* disable dma controller */
617 clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
618
619 /* alloc channel private data pointers */
620 priv->ch_priv = calloc(priv->n_channels,
621 sizeof(struct bcm6348_chan_priv*));
622 if (!priv->ch_priv)
623 return -ENOMEM;
624
625 /* stop dma channels */
626 for (ch = 0; ch < priv->n_channels; ch++)
627 bcm6348_iudma_chan_stop(priv, ch);
628
629 /* enable dma controller */
630 setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
631
632 return 0;
633}
634
635U_BOOT_DRIVER(bcm6348_iudma) = {
636 .name = "bcm6348_iudma",
637 .id = UCLASS_DMA,
638 .of_match = bcm6348_iudma_ids,
639 .ops = &bcm6348_iudma_ops,
640 .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv),
641 .probe = bcm6348_iudma_probe,
642};
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 50e901973d..8f59193e3c 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -31,6 +31,17 @@ config FPGA_CYCLON2
31 Enable FPGA driver for loading bitstream in BIT and BIN format 31 Enable FPGA driver for loading bitstream in BIT and BIN format
32 on Altera Cyclone II device. 32 on Altera Cyclone II device.
33 33
34config FPGA_STRATIX10
35 bool "Enable Altera FPGA driver for Stratix 10"
36 depends on TARGET_SOCFPGA_STRATIX10
37 select FPGA_ALTERA
38 help
39 Say Y here to enable the Altera Stratix 10 FPGA specific driver
40
41 This provides common functionality for Altera Stratix 10 devices.
42 Enable FPGA driver for writing bitstream into Altera Stratix10
43 device.
44
34config FPGA_XILINX 45config FPGA_XILINX
35 bool "Enable Xilinx FPGA drivers" 46 bool "Enable Xilinx FPGA drivers"
36 select FPGA 47 select FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 97d7d5d9be..5a778c10e8 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
17obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o 17obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
18obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o 18obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
19obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o 19obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
20obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
20obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o 21obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
21obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o 22obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
22obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o 23obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 9605554c6a..7c8f518509 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -39,6 +39,9 @@ static const struct altera_fpga {
39#if defined(CONFIG_FPGA_STRATIX_V) 39#if defined(CONFIG_FPGA_STRATIX_V)
40 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, 40 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
41#endif 41#endif
42#if defined(CONFIG_FPGA_STRATIX10)
43 { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
44#endif
42#if defined(CONFIG_FPGA_SOCFPGA) 45#if defined(CONFIG_FPGA_SOCFPGA)
43 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, 46 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
44#endif 47#endif
@@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc)
154 case fast_passive_parallel_security: 157 case fast_passive_parallel_security:
155 printf("Fast Passive Parallel with Security (FPPS)\n"); 158 printf("Fast Passive Parallel with Security (FPPS)\n");
156 break; 159 break;
160 case secure_device_manager_mailbox:
161 puts("Secure Device Manager (SDM) Mailbox\n");
162 break;
157 /* Add new interface types here */ 163 /* Add new interface types here */
158 default: 164 default:
159 printf("Unsupported interface type, %d\n", desc->iface); 165 printf("Unsupported interface type, %d\n", desc->iface);
diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c
new file mode 100644
index 0000000000..aae052130e
--- /dev/null
+++ b/drivers/fpga/stratix10.c
@@ -0,0 +1,288 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Intel Corporation <www.intel.com>
4 */
5
6#include <common.h>
7#include <altera.h>
8#include <asm/arch/mailbox_s10.h>
9
10#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
11#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
12
13static const struct mbox_cfgstat_state {
14 int err_no;
15 const char *error_name;
16} mbox_cfgstat_state[] = {
17 {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
18 {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
19 {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
20 {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
21 {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
22 {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
23 {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
24 {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
25 {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
26 {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
27 {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
28 {MBOX_RESP_ERROR, "Mailbox general error!"},
29 {-ETIMEDOUT, "I/O timeout error"},
30 {-1, "Unknown error!"}
31};
32
33#define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
34
35static const char *mbox_cfgstat_to_str(int err)
36{
37 int i;
38
39 for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
40 if (mbox_cfgstat_state[i].err_no == err)
41 return mbox_cfgstat_state[i].error_name;
42 }
43
44 return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
45}
46
47/*
48 * Add the ongoing transaction's command ID into pending list and return
49 * the command ID for next transfer.
50 */
51static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
52{
53 int i;
54
55 for (i = 0; i < list_size; i++) {
56 if (xfer_pending_list[i])
57 continue;
58 xfer_pending_list[i] = id;
59 debug("ID(%d) added to transaction pending list\n", id);
60 /*
61 * Increment command ID for next transaction.
62 * Valid command ID (4 bits) is from 1 to 15.
63 */
64 id = (id % 15) + 1;
65 break;
66 }
67
68 return id;
69}
70
71/*
72 * Check whether response ID match the command ID in the transfer
73 * pending list. If a match is found in the transfer pending list,
74 * it clears the transfer pending list and return the matched
75 * command ID.
76 */
77static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
78 u8 id)
79{
80 int i;
81
82 for (i = 0; i < list_size; i++) {
83 if (id != xfer_pending_list[i])
84 continue;
85 xfer_pending_list[i] = 0;
86 return id;
87 }
88
89 return 0;
90}
91
92/*
93 * Polling the FPGA configuration status.
94 * Return 0 for success, non-zero for error.
95 */
96static int reconfig_status_polling_resp(void)
97{
98 int ret;
99 unsigned long start = get_timer(0);
100
101 while (1) {
102 ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
103 if (!ret)
104 return 0; /* configuration success */
105
106 if (ret != MBOX_CFGSTAT_STATE_CONFIG)
107 return ret;
108
109 if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
110 break; /* time out */
111
112 puts(".");
113 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
114 }
115
116 return -ETIMEDOUT;
117}
118
119static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
120 u32 *resp_buf, u32 buf_size, u32 client_id)
121{
122 u32 buf[MBOX_RESP_BUFFER_SIZE];
123 u32 mbox_hdr;
124 u32 resp_len;
125 u32 hdr_len;
126 u32 i;
127
128 if (*resp_count < buf_size) {
129 u32 rcv_len_max = buf_size - *resp_count;
130
131 if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
132 rcv_len_max = MBOX_RESP_BUFFER_SIZE;
133 resp_len = mbox_rcv_resp(buf, rcv_len_max);
134
135 for (i = 0; i < resp_len; i++) {
136 resp_buf[(*w_index)++] = buf[i];
137 *w_index %= buf_size;
138 (*resp_count)++;
139 }
140 }
141
142 /* No response in buffer */
143 if (*resp_count == 0)
144 return 0;
145
146 mbox_hdr = resp_buf[*r_index];
147
148 hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
149
150 /* Insufficient header length to return a mailbox header */
151 if ((*resp_count - 1) < hdr_len)
152 return 0;
153
154 *r_index += (hdr_len + 1);
155 *r_index %= buf_size;
156 *resp_count -= (hdr_len + 1);
157
158 /* Make sure response belongs to us */
159 if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
160 return 0;
161
162 return mbox_hdr;
163}
164
165/* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
166static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
167 u32 xfer_max, u32 buf_size_max)
168{
169 u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
170 u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
171 u32 resp_rindex = 0;
172 u32 resp_windex = 0;
173 u32 resp_count = 0;
174 u32 xfer_count = 0;
175 u8 resp_err = 0;
176 u8 cmd_id = 1;
177 u32 args[3];
178 int ret;
179
180 debug("SDM xfer_max = %d\n", xfer_max);
181 debug("SDM buf_size_max = %x\n\n", buf_size_max);
182
183 memset(xfer_pending, 0, sizeof(xfer_pending));
184
185 while (rbf_size || xfer_count) {
186 if (!resp_err && rbf_size && xfer_count < xfer_max) {
187 args[0] = MBOX_ARG_DESC_COUNT(1);
188 args[1] = (u64)rbf_data;
189 if (rbf_size >= buf_size_max) {
190 args[2] = buf_size_max;
191 rbf_size -= buf_size_max;
192 rbf_data += buf_size_max;
193 } else {
194 args[2] = (u64)rbf_size;
195 rbf_size = 0;
196 }
197
198 ret = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
199 MBOX_CMD_INDIRECT, 3, args);
200 if (ret) {
201 resp_err = 1;
202 } else {
203 xfer_count++;
204 cmd_id = add_transfer(xfer_pending,
205 MBOX_RESP_BUFFER_SIZE,
206 cmd_id);
207 }
208 puts(".");
209 } else {
210 u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
211 &resp_count,
212 response_buffer,
213 MBOX_RESP_BUFFER_SIZE,
214 MBOX_CLIENT_ID_UBOOT);
215
216 /*
217 * If no valid response header found or
218 * non-zero length from RECONFIG_DATA
219 */
220 if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
221 continue;
222
223 /* Check for response's status */
224 if (!resp_err) {
225 ret = MBOX_RESP_ERR_GET(resp_hdr);
226 debug("Response error code: %08x\n", ret);
227 /* Error in response */
228 if (ret)
229 resp_err = 1;
230 }
231
232 ret = get_and_clr_transfer(xfer_pending,
233 MBOX_RESP_BUFFER_SIZE,
234 MBOX_RESP_ID_GET(resp_hdr));
235 if (ret) {
236 /* Claim and reuse the ID */
237 cmd_id = (u8)ret;
238 xfer_count--;
239 }
240
241 if (resp_err && !xfer_count)
242 return ret;
243 }
244 }
245
246 return 0;
247}
248
249/*
250 * This is the interface used by FPGA driver.
251 * Return 0 for success, non-zero for error.
252 */
253int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
254{
255 int ret;
256 u32 resp_len = 2;
257 u32 resp_buf[2];
258
259 debug("Sending MBOX_RECONFIG...\n");
260 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
261 NULL, 0, &resp_len, resp_buf);
262 if (ret) {
263 puts("Failure in RECONFIG mailbox command!\n");
264 return ret;
265 }
266
267 ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
268 if (ret) {
269 printf("RECONFIG_DATA error: %08x, %s\n", ret,
270 mbox_cfgstat_to_str(ret));
271 return ret;
272 }
273
274 /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
275 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
276
277 debug("Polling with MBOX_RECONFIG_STATUS...\n");
278 ret = reconfig_status_polling_resp();
279 if (ret) {
280 printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
281 mbox_cfgstat_to_str(ret));
282 return ret;
283 }
284
285 puts("FPGA reconfiguration OK!\n");
286
287 return ret;
288}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 35344e57c6..c8c6c60623 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,6 +99,13 @@ config LPC32XX_GPIO
99 help 99 help
100 Support for the LPC32XX GPIO driver. 100 Support for the LPC32XX GPIO driver.
101 101
102config MSCC_BITBANG_SPI_GPIO
103 bool "Microsemi bitbang spi GPIO driver"
104 depends on DM_GPIO && SOC_VCOREIII
105 help
106 Support controlling the GPIO used for SPI bitbang by software. Can
107 be used by the VCoreIII SoCs, but it was mainly useful for Luton.
108
102config MSM_GPIO 109config MSM_GPIO
103 bool "Qualcomm GPIO driver" 110 bool "Qualcomm GPIO driver"
104 depends on DM_GPIO 111 depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7ed9a4ec42..61feda1537 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,3 +59,4 @@ obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
59obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o 59obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
60obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o 60obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
61obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o 61obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
62obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO) += gpio-mscc-bitbang-spi.o
diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c b/drivers/gpio/gpio-mscc-bitbang-spi.c
new file mode 100644
index 0000000000..b675f9052c
--- /dev/null
+++ b/drivers/gpio/gpio-mscc-bitbang-spi.c
@@ -0,0 +1,122 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <gregory.clement@bootlin.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2018 Microsemi Corporation
8 */
9
10#include <common.h>
11#include <asm-generic/gpio.h>
12#include <asm/io.h>
13#include <dm.h>
14#include <errno.h>
15
16enum {
17 SDI,
18 CS0,
19 CS1,
20 CS2,
21 CS3,
22 SDO,
23 SCK
24};
25
26static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
27
28#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
29#define SW_SPI_CS0_OE BIT(1)
30#define SW_SPI_SDO_OE BIT(9)
31#define SW_SPI_SCK_OE BIT(11)
32#define SW_PIN_CTRL_MODE BIT(13)
33
34struct mscc_bb_spi_gpio {
35 void __iomem *regs;
36 u32 cache_val;
37};
38
39static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
40{
41 struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
42
43 if (val)
44 gpio->cache_val |= BIT(pinmap[oft]);
45 else
46 gpio->cache_val &= ~BIT(pinmap[oft]);
47
48 writel(gpio->cache_val, gpio->regs);
49
50 return 0;
51}
52
53static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
54 int val)
55{
56 if (oft == 0) {
57 pr_err("SW_SPI_DSI can't be used as output\n");
58 return -ENOTSUPP;
59 }
60
61 mscc_bb_spi_gpio_set(dev, oft, val);
62
63 return 0;
64}
65
66static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
67{
68 return 0;
69}
70
71static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
72{
73 struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
74 u32 val = readl(gpio->regs);
75
76 return !!(val & BIT(pinmap[oft]));
77}
78
79static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
80 .direction_output = mscc_bb_spi_gpio_direction_output,
81 .direction_input = mscc_bb_spi_gpio_direction_input,
82 .set_value = mscc_bb_spi_gpio_set,
83 .get_value = mscc_bb_spi_gpio_get,
84};
85
86static int mscc_bb_spi_gpio_probe(struct udevice *dev)
87{
88 struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
89 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
90
91 gpio->regs = dev_remap_addr(dev);
92 if (!gpio->regs)
93 return -EINVAL;
94
95 uc_priv->bank_name = dev->name;
96 uc_priv->gpio_count = ARRAY_SIZE(pinmap);
97 /*
98 * Enable software mode to control the SPI pin, enables the
99 * output mode for most of the pin and initialize the cache
100 * value in the same time
101 */
102
103 gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
104 SW_SPI_CS0_OE;
105 writel(gpio->cache_val, gpio->regs);
106
107 return 0;
108}
109
110static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
111 {.compatible = "mscc,spi-bitbang-gpio"},
112 {}
113};
114
115U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
116 .name = "gpio-mscc-spi-bitbang",
117 .id = UCLASS_GPIO,
118 .ops = &mscc_bb_spi_gpio_ops,
119 .probe = mscc_bb_spi_gpio_probe,
120 .of_match = of_match_ptr(mscc_bb_spi_gpio_ids),
121 .priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio),
122};
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index b820160ae7..8bd30c75b2 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = {
40 [2] = GPIO3_BASE_ADDR, 40 [2] = GPIO3_BASE_ADDR,
41#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ 41#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
42 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ 42 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
43 defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ 43 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
44 defined(CONFIG_ARCH_IMX8) 44 defined(CONFIG_ARCH_IMX8)
45 [3] = GPIO4_BASE_ADDR, 45 [3] = GPIO4_BASE_ADDR,
46#endif 46#endif
47#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ 47#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
48 defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ 48 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
49 defined(CONFIG_ARCH_IMX8) 49 defined(CONFIG_ARCH_IMX8)
50 [4] = GPIO5_BASE_ADDR, 50 [4] = GPIO5_BASE_ADDR,
51#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) 51#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
52 [5] = GPIO6_BASE_ADDR, 52 [5] = GPIO6_BASE_ADDR,
53#endif 53#endif
54#endif 54#endif
@@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = {
353 { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, 353 { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
354#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ 354#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
355 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ 355 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
356 defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) 356 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
357 { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, 357 { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
358#endif 358#endif
359#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ 359#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
360 defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) 360 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
361 { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, 361 { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
362#ifndef CONFIG_MX8M 362#ifndef CONFIG_IMX8M
363 { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, 363 { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
364#endif 364#endif
365#endif 365#endif
@@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = {
377 { "gpio_mxc", &mxc_plat[2] }, 377 { "gpio_mxc", &mxc_plat[2] },
378#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ 378#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
379 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ 379 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
380 defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) 380 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
381 { "gpio_mxc", &mxc_plat[3] }, 381 { "gpio_mxc", &mxc_plat[3] },
382#endif 382#endif
383#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ 383#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
384 defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) 384 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
385 { "gpio_mxc", &mxc_plat[4] }, 385 { "gpio_mxc", &mxc_plat[4] },
386#ifndef CONFIG_MX8M 386#ifndef CONFIG_IMX8M
387 { "gpio_mxc", &mxc_plat[5] }, 387 { "gpio_mxc", &mxc_plat[5] },
388#endif 388#endif
389#endif 389#endif
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
index f160b4e689..5c9f2fe64d 100644
--- a/drivers/gpio/stm32f7_gpio.c
+++ b/drivers/gpio/stm32f7_gpio.c
@@ -19,6 +19,7 @@
19#define MODE_BITS_MASK 3 19#define MODE_BITS_MASK 3
20#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16)) 20#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
21 21
22#ifndef CONFIG_SPL_BUILD
22/* 23/*
23 * convert gpio offset to gpio index taking into account gpio holes 24 * convert gpio offset to gpio index taking into account gpio holes
24 * into gpio bank 25 * into gpio bank
@@ -145,23 +146,27 @@ static const struct dm_gpio_ops gpio_stm32_ops = {
145 .set_value = stm32_gpio_set_value, 146 .set_value = stm32_gpio_set_value,
146 .get_function = stm32_gpio_get_function, 147 .get_function = stm32_gpio_get_function,
147}; 148};
149#endif
148 150
149static int gpio_stm32_probe(struct udevice *dev) 151static int gpio_stm32_probe(struct udevice *dev)
150{ 152{
151 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
152 struct stm32_gpio_priv *priv = dev_get_priv(dev); 153 struct stm32_gpio_priv *priv = dev_get_priv(dev);
153 struct ofnode_phandle_args args;
154 struct clk clk; 154 struct clk clk;
155 fdt_addr_t addr; 155 fdt_addr_t addr;
156 const char *name;
157 int ret; 156 int ret;
158 int i;
159 157
160 addr = dev_read_addr(dev); 158 addr = dev_read_addr(dev);
161 if (addr == FDT_ADDR_T_NONE) 159 if (addr == FDT_ADDR_T_NONE)
162 return -EINVAL; 160 return -EINVAL;
163 161
164 priv->regs = (struct stm32_gpio_regs *)addr; 162 priv->regs = (struct stm32_gpio_regs *)addr;
163
164#ifndef CONFIG_SPL_BUILD
165 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
166 struct ofnode_phandle_args args;
167 const char *name;
168 int i;
169
165 name = dev_read_string(dev, "st,bank-name"); 170 name = dev_read_string(dev, "st,bank-name");
166 if (!name) 171 if (!name)
167 return -EINVAL; 172 return -EINVAL;
@@ -171,6 +176,11 @@ static int gpio_stm32_probe(struct udevice *dev)
171 ret = dev_read_phandle_with_args(dev, "gpio-ranges", 176 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
172 NULL, 3, i, &args); 177 NULL, 3, i, &args);
173 178
179 if (ret == -ENOENT) {
180 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
181 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
182 }
183
174 while (ret != -ENOENT) { 184 while (ret != -ENOENT) {
175 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1, 185 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
176 args.args[0]); 186 args.args[0]);
@@ -184,7 +194,7 @@ static int gpio_stm32_probe(struct udevice *dev)
184 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n", 194 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
185 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count, 195 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
186 priv->gpio_range); 196 priv->gpio_range);
187 197#endif
188 ret = clk_get_by_index(dev, 0, &clk); 198 ret = clk_get_by_index(dev, 0, &clk);
189 if (ret < 0) 199 if (ret < 0)
190 return ret; 200 return ret;
@@ -210,7 +220,9 @@ U_BOOT_DRIVER(gpio_stm32) = {
210 .id = UCLASS_GPIO, 220 .id = UCLASS_GPIO,
211 .of_match = stm32_gpio_ids, 221 .of_match = stm32_gpio_ids,
212 .probe = gpio_stm32_probe, 222 .probe = gpio_stm32_probe,
223#ifndef CONFIG_SPL_BUILD
213 .ops = &gpio_stm32_ops, 224 .ops = &gpio_stm32_ops,
225#endif
214 .flags = DM_UC_FLAG_SEQ_ALIAS, 226 .flags = DM_UC_FLAG_SEQ_ALIAS,
215 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv), 227 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
216}; 228};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 48febc47d2..704c8dd195 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -120,6 +120,12 @@ config FSL_SEC_MON
120 Security Monitor can be transitioned on any security failures, 120 Security Monitor can be transitioned on any security failures,
121 like software violations or hardware security violations. 121 like software violations or hardware security violations.
122 122
123config JZ4780_EFUSE
124 bool "Ingenic JZ4780 eFUSE support"
125 depends on ARCH_JZ47XX
126 help
127 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
128
123config MXC_OCOTP 129config MXC_OCOTP
124 bool "Enable MXC OCOTP Driver" 130 bool "Enable MXC OCOTP Driver"
125 help 131 help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 302d441592..6bdf5054f4 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -62,3 +62,4 @@ obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
62obj-$(CONFIG_TWL4030_LED) += twl4030_led.o 62obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
63obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o 63obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
64obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o 64obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
65obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index b824ac79e6..15101b3e5f 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -158,7 +158,7 @@ static int sc_ipc_write(struct mu_type *base, void *data)
158static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg, 158static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
159 int tx_size, void *rx_msg, int rx_size) 159 int tx_size, void *rx_msg, int rx_size)
160{ 160{
161 struct imx8_scu *priv = dev_get_priv(dev); 161 struct imx8_scu *plat = dev_get_platdata(dev);
162 sc_err_t result; 162 sc_err_t result;
163 int ret; 163 int ret;
164 164
@@ -166,11 +166,11 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
166 if (rx_msg && tx_msg != rx_msg) 166 if (rx_msg && tx_msg != rx_msg)
167 printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg); 167 printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
168 168
169 ret = sc_ipc_write(priv->base, tx_msg); 169 ret = sc_ipc_write(plat->base, tx_msg);
170 if (ret) 170 if (ret)
171 return ret; 171 return ret;
172 if (!no_resp) { 172 if (!no_resp) {
173 ret = sc_ipc_read(priv->base, rx_msg); 173 ret = sc_ipc_read(plat->base, rx_msg);
174 if (ret) 174 if (ret)
175 return ret; 175 return ret;
176 } 176 }
@@ -182,24 +182,24 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
182 182
183static int imx8_scu_probe(struct udevice *dev) 183static int imx8_scu_probe(struct udevice *dev)
184{ 184{
185 struct imx8_scu *priv = dev_get_priv(dev); 185 struct imx8_scu *plat = dev_get_platdata(dev);
186 fdt_addr_t addr; 186 fdt_addr_t addr;
187 187
188 debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); 188 debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
189 189
190 addr = devfdt_get_addr(dev); 190 addr = devfdt_get_addr(dev);
191 if (addr == FDT_ADDR_T_NONE) 191 if (addr == FDT_ADDR_T_NONE)
192 return -EINVAL; 192 return -EINVAL;
193 193
194 priv->base = (struct mu_type *)addr; 194 plat->base = (struct mu_type *)addr;
195 195
196 /* U-Boot not enable interrupts, so need to enable RX interrupts */ 196 /* U-Boot not enable interrupts, so need to enable RX interrupts */
197 mu_hal_init(priv->base); 197 mu_hal_init(plat->base);
198 198
199 gd->arch.scu_dev = dev; 199 gd->arch.scu_dev = dev;
200 200
201 device_probe(priv->clk); 201 device_probe(plat->clk);
202 device_probe(priv->pinclk); 202 device_probe(plat->pinclk);
203 203
204 return 0; 204 return 0;
205} 205}
@@ -211,7 +211,7 @@ static int imx8_scu_remove(struct udevice *dev)
211 211
212static int imx8_scu_bind(struct udevice *dev) 212static int imx8_scu_bind(struct udevice *dev)
213{ 213{
214 struct imx8_scu *priv = dev_get_priv(dev); 214 struct imx8_scu *plat = dev_get_platdata(dev);
215 int ret; 215 int ret;
216 struct udevice *child; 216 struct udevice *child;
217 int node; 217 int node;
@@ -227,7 +227,7 @@ static int imx8_scu_bind(struct udevice *dev)
227 if (ret) 227 if (ret)
228 return ret; 228 return ret;
229 229
230 priv->clk = child; 230 plat->clk = child;
231 231
232 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 232 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
233 "fsl,imx8qxp-iomuxc"); 233 "fsl,imx8qxp-iomuxc");
@@ -238,7 +238,7 @@ static int imx8_scu_bind(struct udevice *dev)
238 if (ret) 238 if (ret)
239 return ret; 239 return ret;
240 240
241 priv->pinclk = child; 241 plat->pinclk = child;
242 242
243 return 0; 243 return 0;
244} 244}
@@ -261,6 +261,6 @@ U_BOOT_DRIVER(imx8_scu) = {
261 .bind = imx8_scu_bind, 261 .bind = imx8_scu_bind,
262 .remove = imx8_scu_remove, 262 .remove = imx8_scu_remove,
263 .ops = &imx8_scu_ops, 263 .ops = &imx8_scu_ops,
264 .priv_auto_alloc_size = sizeof(struct imx8_scu), 264 .platdata_auto_alloc_size = sizeof(struct imx8_scu),
265 .flags = DM_FLAG_PRE_RELOC, 265 .flags = DM_FLAG_PRE_RELOC,
266}; 266};
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 65080d7544..d9c4d5d784 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -169,7 +169,7 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
169 printf("%s: ctrl:%d resource:%d: res:%d\n", 169 printf("%s: ctrl:%d resource:%d: res:%d\n",
170 __func__, ctrl, resource, RPC_R8(&msg)); 170 __func__, ctrl, resource, RPC_R8(&msg));
171 171
172 if (!val) 172 if (val)
173 *val = RPC_U32(&msg, 0U); 173 *val = RPC_U32(&msg, 0U);
174 174
175 return ret; 175 return ret;
@@ -194,7 +194,7 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev)
194 if (ret) 194 if (ret)
195 printf("%s: res:%d\n", __func__, RPC_R8(&msg)); 195 printf("%s: res:%d\n", __func__, RPC_R8(&msg));
196 196
197 if (!boot_dev) 197 if (boot_dev)
198 *boot_dev = RPC_U16(&msg, 0U); 198 *boot_dev = RPC_U16(&msg, 0U);
199} 199}
200 200
diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c
new file mode 100644
index 0000000000..bc3dc93af2
--- /dev/null
+++ b/drivers/misc/jz4780_efuse.c
@@ -0,0 +1,103 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * JZ4780 EFUSE driver
4 *
5 * Copyright (c) 2014 Imagination Technologies
6 * Author: Alex Smith <alex.smith@imgtec.com>
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/unaligned.h>
12#include <errno.h>
13#include <mach/jz4780.h>
14#include <wait_bit.h>
15
16#define EFUSE_EFUCTRL 0xd0
17#define EFUSE_EFUCFG 0xd4
18#define EFUSE_EFUSTATE 0xd8
19#define EFUSE_EFUDATA(n) (0xdc + ((n) * 4))
20
21#define EFUSE_EFUCTRL_RD_EN BIT(0)
22#define EFUSE_EFUCTRL_LEN_BIT 16
23#define EFUSE_EFUCTRL_LEN_MASK 0x1f
24#define EFUSE_EFUCTRL_ADDR_BIT 21
25#define EFUSE_EFUCTRL_ADDR_MASK 0x1ff
26#define EFUSE_EFUCTRL_CS BIT(30)
27
28#define EFUSE_EFUCFG_RD_STROBE_BIT 16
29#define EFUSE_EFUCFG_RD_STROBE_MASK 0xf
30#define EFUSE_EFUCFG_RD_ADJ_BIT 20
31#define EFUSE_EFUCFG_RD_ADJ_MASK 0xf
32
33#define EFUSE_EFUSTATE_RD_DONE BIT(0)
34
35static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
36{
37 void __iomem *regs = (void __iomem *)NEMC_BASE;
38 size_t i;
39 u32 val;
40 int ret;
41
42 val = EFUSE_EFUCTRL_RD_EN |
43 ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
44 (addr << EFUSE_EFUCTRL_ADDR_BIT) |
45 ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
46 writel(val, regs + EFUSE_EFUCTRL);
47
48 ret = wait_for_bit_le32(regs + EFUSE_EFUSTATE,
49 EFUSE_EFUSTATE_RD_DONE, true, 10000, false);
50 if (ret)
51 return;
52
53 if ((count % 4) == 0) {
54 for (i = 0; i < count / 4; i++) {
55 val = readl(regs + EFUSE_EFUDATA(i));
56 put_unaligned(val, (u32 *)(buf + (i * 4)));
57 }
58 } else {
59 val = readl(regs + EFUSE_EFUDATA(0));
60 if (count > 2)
61 buf[2] = (val >> 16) & 0xff;
62 if (count > 1)
63 buf[1] = (val >> 8) & 0xff;
64 buf[0] = val & 0xff;
65 }
66}
67
68static inline int jz4780_efuse_chunk_size(size_t count)
69{
70 if (count >= 32)
71 return 32;
72 else if ((count / 4) > 0)
73 return (count / 4) * 4;
74 else
75 return count % 4;
76}
77
78void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
79{
80 size_t chunk;
81
82 while (count > 0) {
83 chunk = jz4780_efuse_chunk_size(count);
84 jz4780_efuse_read_chunk(addr, chunk, buf);
85 addr += chunk;
86 buf += chunk;
87 count -= chunk;
88 }
89}
90
91void jz4780_efuse_init(u32 ahb2_rate)
92{
93 void __iomem *regs = (void __iomem *)NEMC_BASE;
94 u32 rd_adj, rd_strobe, tmp;
95
96 rd_adj = (((6500 * (ahb2_rate / 1000000)) / 1000000) + 0xf) / 2;
97 tmp = (((35000 * (ahb2_rate / 1000000)) / 1000000) - 4) - rd_adj;
98 rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;
99
100 tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
101 (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
102 writel(tmp, regs + EFUSE_EFUCFG);
103}
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 9ff475d925..f84fe88db1 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -34,7 +34,7 @@
34#define BM_OUT_STATUS_DED 0x00000400 34#define BM_OUT_STATUS_DED 0x00000400
35#define BM_OUT_STATUS_LOCKED 0x00000800 35#define BM_OUT_STATUS_LOCKED 0x00000800
36#define BM_OUT_STATUS_PROGFAIL 0x00001000 36#define BM_OUT_STATUS_PROGFAIL 0x00001000
37#elif defined(CONFIG_MX8M) 37#elif defined(CONFIG_IMX8M)
38#define BM_CTRL_ADDR 0x000000ff 38#define BM_CTRL_ADDR 0x000000ff
39#else 39#else
40#define BM_CTRL_ADDR 0x0000007f 40#define BM_CTRL_ADDR 0x0000007f
@@ -80,7 +80,7 @@
80#elif defined(CONFIG_MX7ULP) 80#elif defined(CONFIG_MX7ULP)
81#define FUSE_BANK_SIZE 0x80 81#define FUSE_BANK_SIZE 0x80
82#define FUSE_BANKS 31 82#define FUSE_BANKS 31
83#elif defined(CONFIG_MX8M) 83#elif defined(CONFIG_IMX8M)
84#define FUSE_BANK_SIZE 0x40 84#define FUSE_BANK_SIZE 0x40
85#define FUSE_BANKS 64 85#define FUSE_BANKS 64
86#else 86#else
@@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
298 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; 298 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
299#ifdef CONFIG_MX7 299#ifdef CONFIG_MX7
300 u32 addr = bank; 300 u32 addr = bank;
301#elif defined CONFIG_MX8M 301#elif defined CONFIG_IMX8M
302 u32 addr = bank << 2 | word; 302 u32 addr = bank << 2 | word;
303#else 303#else
304 u32 addr; 304 u32 addr;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index fbd13964a0..496b2cba64 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -332,6 +332,12 @@ config MMC_BCM2835
332 332
333 If unsure, say N. 333 If unsure, say N.
334 334
335config JZ47XX_MMC
336 bool "Ingenic JZ47xx SD/MMC Host Controller support"
337 depends on ARCH_JZ47XX
338 help
339 This selects support for the SD Card Controller on Ingenic JZ47xx SoCs.
340
335config MMC_SANDBOX 341config MMC_SANDBOX
336 bool "Sandbox MMC support" 342 bool "Sandbox MMC support"
337 depends on SANDBOX 343 depends on SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 801a26d821..7892c468f0 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
40obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o 40obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
41obj-$(CONFIG_SH_SDHI) += sh_sdhi.o 41obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
42obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o 42obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
43obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
43 44
44# SDHCI 45# SDHCI
45obj-$(CONFIG_MMC_SDHCI) += sdhci.o 46obj-$(CONFIG_MMC_SDHCI) += sdhci.o
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3cdfa7f5a6..99e5882866 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
259 int timeout; 259 int timeout;
260 struct fsl_esdhc *regs = priv->esdhc_regs; 260 struct fsl_esdhc *regs = priv->esdhc_regs;
261#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 261#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
262 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 262 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
263 dma_addr_t addr; 263 dma_addr_t addr;
264#endif 264#endif
265 uint wml_value; 265 uint wml_value;
@@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
273 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value); 273 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
274#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 274#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
275#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 275#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
276 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 276 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
277 addr = virt_to_phys((void *)(data->dest)); 277 addr = virt_to_phys((void *)(data->dest));
278 if (upper_32_bits(addr)) 278 if (upper_32_bits(addr))
279 printf("Error found for upper 32 bits\n"); 279 printf("Error found for upper 32 bits\n");
@@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
303 wml_value << 16); 303 wml_value << 16);
304#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 304#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
305#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 305#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
306 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 306 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
307 addr = virt_to_phys((void *)(data->src)); 307 addr = virt_to_phys((void *)(data->src));
308 if (upper_32_bits(addr)) 308 if (upper_32_bits(addr))
309 printf("Error found for upper 32 bits\n"); 309 printf("Error found for upper 32 bits\n");
@@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range
369 unsigned size = roundup(ARCH_DMA_MINALIGN, 369 unsigned size = roundup(ARCH_DMA_MINALIGN,
370 data->blocks*data->blocksize); 370 data->blocks*data->blocksize);
371#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 371#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
372 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 372 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
373 dma_addr_t addr; 373 dma_addr_t addr;
374 374
375 addr = virt_to_phys((void *)(data->dest)); 375 addr = virt_to_phys((void *)(data->dest));
@@ -396,6 +396,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
396 uint irqstat; 396 uint irqstat;
397 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; 397 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
398 struct fsl_esdhc *regs = priv->esdhc_regs; 398 struct fsl_esdhc *regs = priv->esdhc_regs;
399 unsigned long start;
399 400
400#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 401#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
401 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 402 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
@@ -453,8 +454,13 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
453 flags = IRQSTAT_BRR; 454 flags = IRQSTAT_BRR;
454 455
455 /* Wait for the command to complete */ 456 /* Wait for the command to complete */
456 while (!(esdhc_read32(&regs->irqstat) & flags)) 457 start = get_timer(0);
457 ; 458 while (!(esdhc_read32(&regs->irqstat) & flags)) {
459 if (get_timer(start) > 1000) {
460 err = -ETIMEDOUT;
461 goto out;
462 }
463 }
458 464
459 irqstat = esdhc_read32(&regs->irqstat); 465 irqstat = esdhc_read32(&regs->irqstat);
460 466
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index 0000000000..3132c3e191
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,488 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Ingenic JZ MMC driver
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include <mmc.h>
12#include <asm/io.h>
13#include <asm/unaligned.h>
14#include <errno.h>
15#include <mach/jz4780.h>
16#include <wait_bit.h>
17
18/* Registers */
19#define MSC_STRPCL 0x000
20#define MSC_STAT 0x004
21#define MSC_CLKRT 0x008
22#define MSC_CMDAT 0x00c
23#define MSC_RESTO 0x010
24#define MSC_RDTO 0x014
25#define MSC_BLKLEN 0x018
26#define MSC_NOB 0x01c
27#define MSC_SNOB 0x020
28#define MSC_IMASK 0x024
29#define MSC_IREG 0x028
30#define MSC_CMD 0x02c
31#define MSC_ARG 0x030
32#define MSC_RES 0x034
33#define MSC_RXFIFO 0x038
34#define MSC_TXFIFO 0x03c
35#define MSC_LPM 0x040
36#define MSC_DMAC 0x044
37#define MSC_DMANDA 0x048
38#define MSC_DMADA 0x04c
39#define MSC_DMALEN 0x050
40#define MSC_DMACMD 0x054
41#define MSC_CTRL2 0x058
42#define MSC_RTCNT 0x05c
43#define MSC_DBG 0x0fc
44
45/* MSC Clock and Control Register (MSC_STRPCL) */
46#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
47#define MSC_STRPCL_EXIT_TRANSFER BIT(6)
48#define MSC_STRPCL_START_READWAIT BIT(5)
49#define MSC_STRPCL_STOP_READWAIT BIT(4)
50#define MSC_STRPCL_RESET BIT(3)
51#define MSC_STRPCL_START_OP BIT(2)
52#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
53#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
54
55/* MSC Status Register (MSC_STAT) */
56#define MSC_STAT_AUTO_CMD_DONE BIT(31)
57#define MSC_STAT_IS_RESETTING BIT(15)
58#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
59#define MSC_STAT_PRG_DONE BIT(13)
60#define MSC_STAT_DATA_TRAN_DONE BIT(12)
61#define MSC_STAT_END_CMD_RES BIT(11)
62#define MSC_STAT_DATA_FIFO_AFULL BIT(10)
63#define MSC_STAT_IS_READWAIT BIT(9)
64#define MSC_STAT_CLK_EN BIT(8)
65#define MSC_STAT_DATA_FIFO_FULL BIT(7)
66#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
67#define MSC_STAT_CRC_RES_ERR BIT(5)
68#define MSC_STAT_CRC_READ_ERROR BIT(4)
69#define MSC_STAT_CRC_WRITE_ERROR BIT(2)
70#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
71#define MSC_STAT_TIME_OUT_RES BIT(1)
72#define MSC_STAT_TIME_OUT_READ BIT(0)
73
74/* MSC Bus Clock Control Register (MSC_CLKRT) */
75#define MSC_CLKRT_CLK_RATE_MASK 0x7
76
77/* MSC Command Sequence Control Register (MSC_CMDAT) */
78#define MSC_CMDAT_IO_ABORT BIT(11)
79#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
80#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
81#define MSC_CMDAT_DMA_EN BIT(8)
82#define MSC_CMDAT_INIT BIT(7)
83#define MSC_CMDAT_BUSY BIT(6)
84#define MSC_CMDAT_STREAM_BLOCK BIT(5)
85#define MSC_CMDAT_WRITE BIT(4)
86#define MSC_CMDAT_DATA_EN BIT(3)
87#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
88#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
89#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
90#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
91#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
92#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
93#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
94#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
95
96/* MSC Interrupts Mask Register (MSC_IMASK) */
97#define MSC_IMASK_TIME_OUT_RES BIT(9)
98#define MSC_IMASK_TIME_OUT_READ BIT(8)
99#define MSC_IMASK_SDIO BIT(7)
100#define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
101#define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
102#define MSC_IMASK_END_CMD_RES BIT(2)
103#define MSC_IMASK_PRG_DONE BIT(1)
104#define MSC_IMASK_DATA_TRAN_DONE BIT(0)
105
106/* MSC Interrupts Status Register (MSC_IREG) */
107#define MSC_IREG_TIME_OUT_RES BIT(9)
108#define MSC_IREG_TIME_OUT_READ BIT(8)
109#define MSC_IREG_SDIO BIT(7)
110#define MSC_IREG_TXFIFO_WR_REQ BIT(6)
111#define MSC_IREG_RXFIFO_RD_REQ BIT(5)
112#define MSC_IREG_END_CMD_RES BIT(2)
113#define MSC_IREG_PRG_DONE BIT(1)
114#define MSC_IREG_DATA_TRAN_DONE BIT(0)
115
116struct jz_mmc_plat {
117 struct mmc_config cfg;
118 struct mmc mmc;
119};
120
121struct jz_mmc_priv {
122 void __iomem *regs;
123 u32 flags;
124/* priv flags */
125#define JZ_MMC_BUS_WIDTH_MASK 0x3
126#define JZ_MMC_BUS_WIDTH_1 0x0
127#define JZ_MMC_BUS_WIDTH_4 0x2
128#define JZ_MMC_BUS_WIDTH_8 0x3
129#define JZ_MMC_SENT_INIT BIT(2)
130};
131
132static int jz_mmc_clock_rate(void)
133{
134 return 24000000;
135}
136
137static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
138 struct mmc_cmd *cmd, struct mmc_data *data)
139{
140 u32 stat, mask, cmdat = 0;
141 int i, ret;
142
143 /* stop the clock */
144 writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
145 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
146 MSC_STAT_CLK_EN, false, 10000, false);
147 if (ret)
148 return ret;
149
150 writel(0, priv->regs + MSC_DMAC);
151
152 /* setup command */
153 writel(cmd->cmdidx, priv->regs + MSC_CMD);
154 writel(cmd->cmdarg, priv->regs + MSC_ARG);
155
156 if (data) {
157 /* setup data */
158 cmdat |= MSC_CMDAT_DATA_EN;
159 if (data->flags & MMC_DATA_WRITE)
160 cmdat |= MSC_CMDAT_WRITE;
161
162 writel(data->blocks, priv->regs + MSC_NOB);
163 writel(data->blocksize, priv->regs + MSC_BLKLEN);
164 } else {
165 writel(0, priv->regs + MSC_NOB);
166 writel(0, priv->regs + MSC_BLKLEN);
167 }
168
169 /* setup response */
170 switch (cmd->resp_type) {
171 case MMC_RSP_NONE:
172 break;
173 case MMC_RSP_R1:
174 case MMC_RSP_R1b:
175 cmdat |= MSC_CMDAT_RESPONSE_R1;
176 break;
177 case MMC_RSP_R2:
178 cmdat |= MSC_CMDAT_RESPONSE_R2;
179 break;
180 case MMC_RSP_R3:
181 cmdat |= MSC_CMDAT_RESPONSE_R3;
182 break;
183 default:
184 break;
185 }
186
187 if (cmd->resp_type & MMC_RSP_BUSY)
188 cmdat |= MSC_CMDAT_BUSY;
189
190 /* set init for the first command only */
191 if (!(priv->flags & JZ_MMC_SENT_INIT)) {
192 cmdat |= MSC_CMDAT_INIT;
193 priv->flags |= JZ_MMC_SENT_INIT;
194 }
195
196 cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
197
198 /* write the data setup */
199 writel(cmdat, priv->regs + MSC_CMDAT);
200
201 /* unmask interrupts */
202 mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
203 if (data) {
204 mask &= ~MSC_IMASK_DATA_TRAN_DONE;
205 if (data->flags & MMC_DATA_WRITE) {
206 mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
207 } else {
208 mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
209 MSC_IMASK_TIME_OUT_READ);
210 }
211 }
212 writel(mask, priv->regs + MSC_IMASK);
213
214 /* clear interrupts */
215 writel(0xffffffff, priv->regs + MSC_IREG);
216
217 /* start the command (& the clock) */
218 writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
219 priv->regs + MSC_STRPCL);
220
221 /* wait for completion */
222 for (i = 0; i < 100; i++) {
223 stat = readl(priv->regs + MSC_IREG);
224 stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
225 if (stat)
226 break;
227 mdelay(1);
228 }
229 writel(stat, priv->regs + MSC_IREG);
230 if (stat & MSC_IREG_TIME_OUT_RES)
231 return -ETIMEDOUT;
232
233 if (cmd->resp_type & MMC_RSP_PRESENT) {
234 /* read the response */
235 if (cmd->resp_type & MMC_RSP_136) {
236 u16 a, b, c, i;
237
238 a = readw(priv->regs + MSC_RES);
239 for (i = 0; i < 4; i++) {
240 b = readw(priv->regs + MSC_RES);
241 c = readw(priv->regs + MSC_RES);
242 cmd->response[i] =
243 (a << 24) | (b << 8) | (c >> 8);
244 a = c;
245 }
246 } else {
247 cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
248 cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
249 cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
250 }
251 }
252
253 if (data && (data->flags & MMC_DATA_WRITE)) {
254 /* write the data */
255 int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
256 const void *buf = data->src;
257
258 while (sz--) {
259 u32 val = get_unaligned_le32(buf);
260
261 wait_for_bit_le32(priv->regs + MSC_IREG,
262 MSC_IREG_TXFIFO_WR_REQ,
263 true, 10000, false);
264 writel(val, priv->regs + MSC_TXFIFO);
265 buf += 4;
266 }
267 } else if (data && (data->flags & MMC_DATA_READ)) {
268 /* read the data */
269 int sz = data->blocks * data->blocksize;
270 void *buf = data->dest;
271
272 do {
273 stat = readl(priv->regs + MSC_STAT);
274
275 if (stat & MSC_STAT_TIME_OUT_READ)
276 return -ETIMEDOUT;
277 if (stat & MSC_STAT_CRC_READ_ERROR)
278 return -EINVAL;
279 if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
280 udelay(10);
281 continue;
282 }
283 do {
284 u32 val = readl(priv->regs + MSC_RXFIFO);
285
286 if (sz == 1)
287 *(u8 *)buf = (u8)val;
288 else if (sz == 2)
289 put_unaligned_le16(val, buf);
290 else if (sz >= 4)
291 put_unaligned_le32(val, buf);
292 buf += 4;
293 sz -= 4;
294 stat = readl(priv->regs + MSC_STAT);
295 } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
296 } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
297 }
298
299 return 0;
300}
301
302static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
303{
304 u32 real_rate = jz_mmc_clock_rate();
305 u8 clk_div = 0;
306
307 /* calculate clock divide */
308 while ((real_rate > mmc->clock) && (clk_div < 7)) {
309 real_rate >>= 1;
310 clk_div++;
311 }
312 writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
313
314 /* set the bus width for the next command */
315 priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
316 if (mmc->bus_width == 8)
317 priv->flags |= JZ_MMC_BUS_WIDTH_8;
318 else if (mmc->bus_width == 4)
319 priv->flags |= JZ_MMC_BUS_WIDTH_4;
320 else
321 priv->flags |= JZ_MMC_BUS_WIDTH_1;
322
323 return 0;
324}
325
326static int jz_mmc_core_init(struct mmc *mmc)
327{
328 struct jz_mmc_priv *priv = mmc->priv;
329 int ret;
330
331 /* Reset */
332 writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
333 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
334 MSC_STAT_IS_RESETTING, false, 10000, false);
335 if (ret)
336 return ret;
337
338 /* Maximum timeouts */
339 writel(0xffff, priv->regs + MSC_RESTO);
340 writel(0xffffffff, priv->regs + MSC_RDTO);
341
342 /* Enable low power mode */
343 writel(0x1, priv->regs + MSC_LPM);
344
345 return 0;
346}
347
348#if !CONFIG_IS_ENABLED(DM_MMC)
349
350static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
351 struct mmc_data *data)
352{
353 struct jz_mmc_priv *priv = mmc->priv;
354
355 return jz_mmc_send_cmd(mmc, priv, cmd, data);
356}
357
358static int jz_mmc_legacy_set_ios(struct mmc *mmc)
359{
360 struct jz_mmc_priv *priv = mmc->priv;
361
362 return jz_mmc_set_ios(mmc, priv);
363};
364
365static const struct mmc_ops jz_msc_ops = {
366 .send_cmd = jz_mmc_legacy_send_cmd,
367 .set_ios = jz_mmc_legacy_set_ios,
368 .init = jz_mmc_core_init,
369};
370
371static struct jz_mmc_priv jz_mmc_priv_static;
372static struct jz_mmc_plat jz_mmc_plat_static = {
373 .cfg = {
374 .name = "MSC",
375 .ops = &jz_msc_ops,
376
377 .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
378 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
379 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
380 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
381
382 .f_min = 375000,
383 .f_max = 48000000,
384 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
385 },
386};
387
388int jz_mmc_init(void __iomem *base)
389{
390 struct mmc *mmc;
391
392 jz_mmc_priv_static.regs = base;
393
394 mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
395
396 return mmc ? 0 : -ENODEV;
397}
398
399#else /* CONFIG_DM_MMC */
400
401#include <dm.h>
402DECLARE_GLOBAL_DATA_PTR;
403
404static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
405 struct mmc_data *data)
406{
407 struct jz_mmc_priv *priv = dev_get_priv(dev);
408 struct mmc *mmc = mmc_get_mmc_dev(dev);
409
410 return jz_mmc_send_cmd(mmc, priv, cmd, data);
411}
412
413static int jz_mmc_dm_set_ios(struct udevice *dev)
414{
415 struct jz_mmc_priv *priv = dev_get_priv(dev);
416 struct mmc *mmc = mmc_get_mmc_dev(dev);
417
418 return jz_mmc_set_ios(mmc, priv);
419};
420
421static const struct dm_mmc_ops jz_msc_ops = {
422 .send_cmd = jz_mmc_dm_send_cmd,
423 .set_ios = jz_mmc_dm_set_ios,
424};
425
426static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
427{
428 struct jz_mmc_priv *priv = dev_get_priv(dev);
429 struct jz_mmc_plat *plat = dev_get_platdata(dev);
430 struct mmc_config *cfg;
431 int ret;
432
433 priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
434 cfg = &plat->cfg;
435
436 cfg->name = "MSC";
437 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
438
439 ret = mmc_of_parse(dev, cfg);
440 if (ret < 0) {
441 dev_err(dev, "failed to parse host caps\n");
442 return ret;
443 }
444
445 cfg->f_min = 400000;
446 cfg->f_max = 52000000;
447
448 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
449 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
450
451 return 0;
452}
453
454static int jz_mmc_bind(struct udevice *dev)
455{
456 struct jz_mmc_plat *plat = dev_get_platdata(dev);
457
458 return mmc_bind(dev, &plat->mmc, &plat->cfg);
459}
460
461static int jz_mmc_probe(struct udevice *dev)
462{
463 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
464 struct jz_mmc_priv *priv = dev_get_priv(dev);
465 struct jz_mmc_plat *plat = dev_get_platdata(dev);
466
467 plat->mmc.priv = priv;
468 upriv->mmc = &plat->mmc;
469 return jz_mmc_core_init(&plat->mmc);
470}
471
472static const struct udevice_id jz_mmc_ids[] = {
473 { .compatible = "ingenic,jz4780-mmc" },
474 { }
475};
476
477U_BOOT_DRIVER(jz_mmc_drv) = {
478 .name = "jz_mmc",
479 .id = UCLASS_MMC,
480 .of_match = jz_mmc_ids,
481 .ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
482 .bind = jz_mmc_bind,
483 .probe = jz_mmc_probe,
484 .priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
485 .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
486 .ops = &jz_msc_ops,
487};
488#endif /* CONFIG_DM_MMC */
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f5c821e308..d858127132 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2449,6 +2449,10 @@ static int mmc_startup(struct mmc *mmc)
2449 bdesc->revision[0] = 0; 2449 bdesc->revision[0] = 0;
2450#endif 2450#endif
2451 2451
2452#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2453 part_init(bdesc);
2454#endif
2455
2452 return 0; 2456 return 0;
2453} 2457}
2454 2458
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 9bf040cb40..302332bf97 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -19,6 +19,13 @@
19#include <asm/arch/mmc.h> 19#include <asm/arch/mmc.h>
20#include <asm-generic/gpio.h> 20#include <asm-generic/gpio.h>
21 21
22#ifdef CONFIG_DM_MMC
23struct sunxi_mmc_variant {
24 u16 gate_offset;
25 u16 mclk_offset;
26};
27#endif
28
22struct sunxi_mmc_plat { 29struct sunxi_mmc_plat {
23 struct mmc_config cfg; 30 struct mmc_config cfg;
24 struct mmc mmc; 31 struct mmc mmc;
@@ -32,6 +39,9 @@ struct sunxi_mmc_priv {
32 int cd_inverted; /* Inverted Card Detect */ 39 int cd_inverted; /* Inverted Card Detect */
33 struct sunxi_mmc *reg; 40 struct sunxi_mmc *reg;
34 struct mmc_config cfg; 41 struct mmc_config cfg;
42#ifdef CONFIG_DM_MMC
43 const struct sunxi_mmc_variant *variant;
44#endif
35}; 45};
36 46
37#if !CONFIG_IS_ENABLED(DM_MMC) 47#if !CONFIG_IS_ENABLED(DM_MMC)
@@ -599,7 +609,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
599 struct sunxi_mmc_priv *priv = dev_get_priv(dev); 609 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
600 struct mmc_config *cfg = &plat->cfg; 610 struct mmc_config *cfg = &plat->cfg;
601 struct ofnode_phandle_args args; 611 struct ofnode_phandle_args args;
602 u32 *gate_reg; 612 u32 *gate_reg, *ccu_reg;
603 int bus_width, ret; 613 int bus_width, ret;
604 614
605 cfg->name = dev->name; 615 cfg->name = dev->name;
@@ -618,21 +628,21 @@ static int sunxi_mmc_probe(struct udevice *dev)
618 cfg->f_max = 52000000; 628 cfg->f_max = 52000000;
619 629
620 priv->reg = (void *)dev_read_addr(dev); 630 priv->reg = (void *)dev_read_addr(dev);
631 priv->variant =
632 (const struct sunxi_mmc_variant *)dev_get_driver_data(dev);
621 633
622 /* We don't have a sunxi clock driver so find the clock address here */ 634 /* We don't have a sunxi clock driver so find the clock address here */
623 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, 635 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
624 1, &args); 636 1, &args);
625 if (ret) 637 if (ret)
626 return ret; 638 return ret;
627 priv->mclkreg = (u32 *)ofnode_get_addr(args.node); 639 ccu_reg = (u32 *)ofnode_get_addr(args.node);
628 640
629 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, 641 priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
630 0, &args); 642 priv->mclkreg = (void *)ccu_reg +
631 if (ret) 643 (priv->variant->mclk_offset + (priv->mmc_no * 4));
632 return ret; 644 gate_reg = (void *)ccu_reg + priv->variant->gate_offset;
633 gate_reg = (u32 *)ofnode_get_addr(args.node); 645 setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
634 setbits_le32(gate_reg, 1 << args.args[0]);
635 priv->mmc_no = args.args[0] - 8;
636 646
637 ret = mmc_set_mod_clk(priv, 24000000); 647 ret = mmc_set_mod_clk(priv, 24000000);
638 if (ret) 648 if (ret)
@@ -665,11 +675,25 @@ static int sunxi_mmc_bind(struct udevice *dev)
665 return mmc_bind(dev, &plat->mmc, &plat->cfg); 675 return mmc_bind(dev, &plat->mmc, &plat->cfg);
666} 676}
667 677
678static const struct sunxi_mmc_variant sun4i_a10_variant = {
679 .gate_offset = 0x60,
680 .mclk_offset = 0x88,
681};
682
668static const struct udevice_id sunxi_mmc_ids[] = { 683static const struct udevice_id sunxi_mmc_ids[] = {
669 { .compatible = "allwinner,sun4i-a10-mmc" }, 684 {
670 { .compatible = "allwinner,sun5i-a13-mmc" }, 685 .compatible = "allwinner,sun4i-a10-mmc",
671 { .compatible = "allwinner,sun7i-a20-mmc" }, 686 .data = (ulong)&sun4i_a10_variant,
672 { } 687 },
688 {
689 .compatible = "allwinner,sun5i-a13-mmc",
690 .data = (ulong)&sun4i_a10_variant,
691 },
692 {
693 .compatible = "allwinner,sun7i-a20-mmc",
694 .data = (ulong)&sun4i_a10_variant,
695 },
696 { /* sentinel */ }
673}; 697};
674 698
675U_BOOT_DRIVER(sunxi_mmc_drv) = { 699U_BOOT_DRIVER(sunxi_mmc_drv) = {
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 008f7b4b4b..fd1723feda 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -88,6 +88,15 @@ config NAND_VF610_NFC
88 The driver supports a maximum 2k page size. The driver 88 The driver supports a maximum 2k page size. The driver
89 currently does not support hardware ECC. 89 currently does not support hardware ECC.
90 90
91if NAND_VF610_NFC
92
93config NAND_VF610_NFC_DT
94 bool "Support Vybrid's vf610 NAND controller as a DT device"
95 depends on OF_CONTROL && MTD
96 help
97 Enable the driver for Vybrid's vf610 NAND flash on platforms
98 using device tree.
99
91choice 100choice
92 prompt "Hardware ECC strength" 101 prompt "Hardware ECC strength"
93 depends on NAND_VF610_NFC 102 depends on NAND_VF610_NFC
@@ -103,6 +112,8 @@ config SYS_NAND_VF610_NFC_60_ECC_BYTES
103 112
104endchoice 113endchoice
105 114
115endif
116
106config NAND_PXA3XX 117config NAND_PXA3XX
107 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 118 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
108 select SYS_NAND_SELF_INIT 119 select SYS_NAND_SELF_INIT
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index d1cac063f4..e0eb1339ec 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -69,14 +69,6 @@ static int dma_mapping_error(void *dev, dma_addr_t addr)
69#define DENALI_INVALID_BANK -1 69#define DENALI_INVALID_BANK -1
70#define DENALI_NR_BANKS 4 70#define DENALI_NR_BANKS 4
71 71
72/*
73 * The bus interface clock, clk_x, is phase aligned with the core clock. The
74 * clk_x is an integral multiple N of the core clk. The value N is configured
75 * at IP delivery time, and its available value is 4, 5, or 6. We need to align
76 * to the largest value to make it work with any possible configuration.
77 */
78#define DENALI_CLK_X_MULT 6
79
80static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) 72static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
81{ 73{
82 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); 74 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
@@ -595,6 +587,12 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
595 } 587 }
596 588
597 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); 589 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
590 /*
591 * The ->setup_dma() hook kicks DMA by using the data/command
592 * interface, which belongs to a different AXI port from the
593 * register interface. Read back the register to avoid a race.
594 */
595 ioread32(denali->reg + DMA_ENABLE);
598 596
599 denali_reset_irq(denali); 597 denali_reset_irq(denali);
600 denali->setup_dma(denali, dma_addr, page, write); 598 denali->setup_dma(denali, dma_addr, page, write);
@@ -946,7 +944,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
946{ 944{
947 struct denali_nand_info *denali = mtd_to_denali(mtd); 945 struct denali_nand_info *denali = mtd_to_denali(mtd);
948 const struct nand_sdr_timings *timings; 946 const struct nand_sdr_timings *timings;
949 unsigned long t_clk; 947 unsigned long t_x, mult_x;
950 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; 948 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
951 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; 949 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
952 int addr_2_data_mask; 950 int addr_2_data_mask;
@@ -957,15 +955,24 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
957 return PTR_ERR(timings); 955 return PTR_ERR(timings);
958 956
959 /* clk_x period in picoseconds */ 957 /* clk_x period in picoseconds */
960 t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); 958 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
961 if (!t_clk) 959 if (!t_x)
960 return -EINVAL;
961
962 /*
963 * The bus interface clock, clk_x, is phase aligned with the core clock.
964 * The clk_x is an integral multiple N of the core clk. The value N is
965 * configured at IP delivery time, and its available value is 4, 5, 6.
966 */
967 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
968 if (mult_x < 4 || mult_x > 6)
962 return -EINVAL; 969 return -EINVAL;
963 970
964 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 971 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
965 return 0; 972 return 0;
966 973
967 /* tREA -> ACC_CLKS */ 974 /* tREA -> ACC_CLKS */
968 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); 975 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
969 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); 976 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
970 977
971 tmp = ioread32(denali->reg + ACC_CLKS); 978 tmp = ioread32(denali->reg + ACC_CLKS);
@@ -974,7 +981,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
974 iowrite32(tmp, denali->reg + ACC_CLKS); 981 iowrite32(tmp, denali->reg + ACC_CLKS);
975 982
976 /* tRWH -> RE_2_WE */ 983 /* tRWH -> RE_2_WE */
977 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); 984 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
978 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); 985 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
979 986
980 tmp = ioread32(denali->reg + RE_2_WE); 987 tmp = ioread32(denali->reg + RE_2_WE);
@@ -983,7 +990,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
983 iowrite32(tmp, denali->reg + RE_2_WE); 990 iowrite32(tmp, denali->reg + RE_2_WE);
984 991
985 /* tRHZ -> RE_2_RE */ 992 /* tRHZ -> RE_2_RE */
986 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); 993 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
987 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); 994 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
988 995
989 tmp = ioread32(denali->reg + RE_2_RE); 996 tmp = ioread32(denali->reg + RE_2_RE);
@@ -997,8 +1004,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
997 * With WE_2_RE properly set, the Denali controller automatically takes 1004 * With WE_2_RE properly set, the Denali controller automatically takes
998 * care of the delay; the driver need not set NAND_WAIT_TCCS. 1005 * care of the delay; the driver need not set NAND_WAIT_TCCS.
999 */ 1006 */
1000 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), 1007 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
1001 t_clk);
1002 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); 1008 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
1003 1009
1004 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); 1010 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
@@ -1013,7 +1019,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
1013 if (denali->revision < 0x0501) 1019 if (denali->revision < 0x0501)
1014 addr_2_data_mask >>= 1; 1020 addr_2_data_mask >>= 1;
1015 1021
1016 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); 1022 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
1017 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); 1023 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
1018 1024
1019 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); 1025 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
@@ -1023,7 +1029,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
1023 1029
1024 /* tREH, tWH -> RDWR_EN_HI_CNT */ 1030 /* tREH, tWH -> RDWR_EN_HI_CNT */
1025 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), 1031 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
1026 t_clk); 1032 t_x);
1027 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); 1033 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
1028 1034
1029 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); 1035 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
@@ -1032,11 +1038,10 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
1032 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); 1038 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
1033 1039
1034 /* tRP, tWP -> RDWR_EN_LO_CNT */ 1040 /* tRP, tWP -> RDWR_EN_LO_CNT */
1035 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), 1041 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
1036 t_clk);
1037 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), 1042 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
1038 t_clk); 1043 t_x);
1039 rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT); 1044 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
1040 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); 1045 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
1041 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); 1046 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
1042 1047
@@ -1046,8 +1051,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
1046 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); 1051 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
1047 1052
1048 /* tCS, tCEA -> CS_SETUP_CNT */ 1053 /* tCS, tCEA -> CS_SETUP_CNT */
1049 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, 1054 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
1050 (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks, 1055 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
1051 0); 1056 0);
1052 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); 1057 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
1053 1058
diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h
index 9b797beffa..019deda094 100644
--- a/drivers/mtd/nand/raw/denali.h
+++ b/drivers/mtd/nand/raw/denali.h
@@ -292,6 +292,7 @@ struct udevice;
292 292
293struct denali_nand_info { 293struct denali_nand_info {
294 struct nand_chip nand; 294 struct nand_chip nand;
295 unsigned long clk_rate; /* core clock rate */
295 unsigned long clk_x_rate; /* bus interface clock rate */ 296 unsigned long clk_x_rate; /* bus interface clock rate */
296 int active_bank; /* currently selected bank */ 297 int active_bank; /* currently selected bank */
297 struct udevice *dev; 298 struct udevice *dev;
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c
index 65a7797f0f..d384b974df 100644
--- a/drivers/mtd/nand/raw/denali_dt.c
+++ b/drivers/mtd/nand/raw/denali_dt.c
@@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev)
62{ 62{
63 struct denali_nand_info *denali = dev_get_priv(dev); 63 struct denali_nand_info *denali = dev_get_priv(dev);
64 const struct denali_dt_data *data; 64 const struct denali_dt_data *data;
65 struct clk clk; 65 struct clk clk, clk_x, clk_ecc;
66 struct resource res; 66 struct resource res;
67 int ret; 67 int ret;
68 68
@@ -87,15 +87,49 @@ static int denali_dt_probe(struct udevice *dev)
87 87
88 denali->host = devm_ioremap(dev, res.start, resource_size(&res)); 88 denali->host = devm_ioremap(dev, res.start, resource_size(&res));
89 89
90 ret = clk_get_by_index(dev, 0, &clk); 90 ret = clk_get_by_name(dev, "nand", &clk);
91 if (ret)
92 ret = clk_get_by_index(dev, 0, &clk);
91 if (ret) 93 if (ret)
92 return ret; 94 return ret;
93 95
96 ret = clk_get_by_name(dev, "nand_x", &clk_x);
97 if (ret)
98 clk_x.dev = NULL;
99
100 ret = clk_get_by_name(dev, "ecc", &clk_ecc);
101 if (ret)
102 clk_ecc.dev = NULL;
103
94 ret = clk_enable(&clk); 104 ret = clk_enable(&clk);
95 if (ret) 105 if (ret)
96 return ret; 106 return ret;
97 107
98 denali->clk_x_rate = clk_get_rate(&clk); 108 if (clk_x.dev) {
109 ret = clk_enable(&clk_x);
110 if (ret)
111 return ret;
112 }
113
114 if (clk_ecc.dev) {
115 ret = clk_enable(&clk_ecc);
116 if (ret)
117 return ret;
118 }
119
120 if (clk_x.dev) {
121 denali->clk_rate = clk_get_rate(&clk);
122 denali->clk_x_rate = clk_get_rate(&clk_x);
123 } else {
124 /*
125 * Hardcode the clock rates for the backward compatibility.
126 * This works for both SOCFPGA and UniPhier.
127 */
128 dev_notice(dev,
129 "necessary clock is missing. default clock rates are used.\n");
130 denali->clk_rate = 50000000;
131 denali->clk_x_rate = 200000000;
132 }
99 133
100 return denali_init(denali); 134 return denali_init(denali);
101} 135}
diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
index 4009d64123..3104f879f6 100644
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -61,6 +61,10 @@ struct nand_flash_dev nand_flash_ids[] = {
61 {"SDTNRGAMA 64G 3.3V 8-bit", 61 {"SDTNRGAMA 64G 3.3V 8-bit",
62 { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, 62 { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
63 SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, 63 SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
64 {"H27UBG8T2BTR-BC 32G 3.3V 8-bit",
65 { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
66 SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
67 NAND_ECC_INFO(40, SZ_1K), 0 },
64 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", 68 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
65 { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, 69 { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
66 SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, 70 SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index 619d0403e9..3326c2b096 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -31,6 +31,11 @@
31#include <nand.h> 31#include <nand.h>
32#include <errno.h> 32#include <errno.h>
33#include <asm/io.h> 33#include <asm/io.h>
34#if CONFIG_NAND_VF610_NFC_DT
35#include <dm.h>
36#include <linux/io.h>
37#include <linux/ioport.h>
38#endif
34 39
35/* Register Offsets */ 40/* Register Offsets */
36#define NFC_FLASH_CMD1 0x3F00 41#define NFC_FLASH_CMD1 0x3F00
@@ -641,7 +646,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
641 .flash_bbt = 1, 646 .flash_bbt = 1,
642 }; 647 };
643 648
644 nfc = malloc(sizeof(*nfc)); 649 nfc = calloc(1, sizeof(*nfc));
645 if (!nfc) { 650 if (!nfc) {
646 printf(KERN_ERR "%s: Memory exhausted!\n", __func__); 651 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
647 return -ENOMEM; 652 return -ENOMEM;
@@ -760,9 +765,51 @@ error:
760 return err; 765 return err;
761} 766}
762 767
768#if CONFIG_NAND_VF610_NFC_DT
769static const struct udevice_id vf610_nfc_dt_ids[] = {
770 {
771 .compatible = "fsl,vf610-nfc",
772 },
773 { /* sentinel */ }
774};
775
776static int vf610_nfc_dt_probe(struct udevice *dev)
777{
778 struct resource res;
779 int ret;
780
781 ret = dev_read_resource(dev, 0, &res);
782 if (ret)
783 return ret;
784
785 return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start,
786 resource_size(&res)));
787}
788
789U_BOOT_DRIVER(vf610_nfc_dt) = {
790 .name = "vf610-nfc-dt",
791 .id = UCLASS_MTD,
792 .of_match = vf610_nfc_dt_ids,
793 .probe = vf610_nfc_dt_probe,
794};
795
796void board_nand_init(void)
797{
798 struct udevice *dev;
799 int ret;
800
801 ret = uclass_get_device_by_driver(UCLASS_MTD,
802 DM_GET_DRIVER(vf610_nfc_dt),
803 &dev);
804 if (ret && ret != -ENODEV)
805 pr_err("Failed to initialize NAND controller. (error %d)\n",
806 ret);
807}
808#else
763void board_nand_init(void) 809void board_nand_init(void)
764{ 810{
765 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE); 811 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
766 if (err) 812 if (err)
767 printf("VF610 NAND init failed (err %d)\n", err); 813 printf("VF610 NAND init failed (err %d)\n", err);
768} 814}
815#endif /* CONFIG_NAND_VF610_NFC_DT */
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 8fb365fc5d..7044c6adf3 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -72,6 +72,24 @@ config BCM_SF2_ETH_GMAC
72 by the BCM_SF2_ETH driver. 72 by the BCM_SF2_ETH driver.
73 Say Y to any bcmcygnus based platforms. 73 Say Y to any bcmcygnus based platforms.
74 74
75config BCM6348_ETH
76 bool "BCM6348 EMAC support"
77 depends on DM_ETH && ARCH_BMIPS
78 select DMA
79 select DMA_CHANNELS
80 select MII
81 select PHYLIB
82 help
83 This driver supports the BCM6348 Ethernet MAC.
84
85config BCM6368_ETH
86 bool "BCM6368 EMAC support"
87 depends on DM_ETH && ARCH_BMIPS
88 select DMA
89 select MII
90 help
91 This driver supports the BCM6368 Ethernet MAC.
92
75config DWC_ETH_QOS 93config DWC_ETH_QOS
76 bool "Synopsys DWC Ethernet QOS device support" 94 bool "Synopsys DWC Ethernet QOS device support"
77 depends on DM_ETH 95 depends on DM_ETH
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 99056aa041..0dbfa03306 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -6,6 +6,8 @@
6obj-$(CONFIG_ALTERA_TSE) += altera_tse.o 6obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
7obj-$(CONFIG_AG7XXX) += ag7xxx.o 7obj-$(CONFIG_AG7XXX) += ag7xxx.o
8obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o 8obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
9obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
10obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
9obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o 11obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
10obj-$(CONFIG_DRIVER_AX88180) += ax88180.o 12obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
11obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o 13obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c
new file mode 100644
index 0000000000..7100e68bd2
--- /dev/null
+++ b/drivers/net/bcm6348-eth.c
@@ -0,0 +1,537 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <common.h>
10#include <clk.h>
11#include <dm.h>
12#include <dma.h>
13#include <miiphy.h>
14#include <net.h>
15#include <phy.h>
16#include <reset.h>
17#include <wait_bit.h>
18#include <asm/io.h>
19
20#define ETH_RX_DESC PKTBUFSRX
21#define ETH_MAX_MTU_SIZE 1518
22#define ETH_TIMEOUT 100
23#define ETH_TX_WATERMARK 32
24
25/* ETH Receiver Configuration register */
26#define ETH_RXCFG_REG 0x00
27#define ETH_RXCFG_ENFLOW_SHIFT 5
28#define ETH_RXCFG_ENFLOW_MASK (1 << ETH_RXCFG_ENFLOW_SHIFT)
29
30/* ETH Receive Maximum Length register */
31#define ETH_RXMAXLEN_REG 0x04
32#define ETH_RXMAXLEN_SHIFT 0
33#define ETH_RXMAXLEN_MASK (0x7ff << ETH_RXMAXLEN_SHIFT)
34
35/* ETH Transmit Maximum Length register */
36#define ETH_TXMAXLEN_REG 0x08
37#define ETH_TXMAXLEN_SHIFT 0
38#define ETH_TXMAXLEN_MASK (0x7ff << ETH_TXMAXLEN_SHIFT)
39
40/* MII Status/Control register */
41#define MII_SC_REG 0x10
42#define MII_SC_MDCFREQDIV_SHIFT 0
43#define MII_SC_MDCFREQDIV_MASK (0x7f << MII_SC_MDCFREQDIV_SHIFT)
44#define MII_SC_PREAMBLE_EN_SHIFT 7
45#define MII_SC_PREAMBLE_EN_MASK (1 << MII_SC_PREAMBLE_EN_SHIFT)
46
47/* MII Data register */
48#define MII_DAT_REG 0x14
49#define MII_DAT_DATA_SHIFT 0
50#define MII_DAT_DATA_MASK (0xffff << MII_DAT_DATA_SHIFT)
51#define MII_DAT_TA_SHIFT 16
52#define MII_DAT_TA_MASK (0x3 << MII_DAT_TA_SHIFT)
53#define MII_DAT_REG_SHIFT 18
54#define MII_DAT_REG_MASK (0x1f << MII_DAT_REG_SHIFT)
55#define MII_DAT_PHY_SHIFT 23
56#define MII_DAT_PHY_MASK (0x1f << MII_DAT_PHY_SHIFT)
57#define MII_DAT_OP_SHIFT 28
58#define MII_DAT_OP_WRITE (0x5 << MII_DAT_OP_SHIFT)
59#define MII_DAT_OP_READ (0x6 << MII_DAT_OP_SHIFT)
60
61/* ETH Interrupts Mask register */
62#define ETH_IRMASK_REG 0x18
63
64/* ETH Interrupts register */
65#define ETH_IR_REG 0x1c
66#define ETH_IR_MII_SHIFT 0
67#define ETH_IR_MII_MASK (1 << ETH_IR_MII_SHIFT)
68
69/* ETH Control register */
70#define ETH_CTL_REG 0x2c
71#define ETH_CTL_ENABLE_SHIFT 0
72#define ETH_CTL_ENABLE_MASK (1 << ETH_CTL_ENABLE_SHIFT)
73#define ETH_CTL_DISABLE_SHIFT 1
74#define ETH_CTL_DISABLE_MASK (1 << ETH_CTL_DISABLE_SHIFT)
75#define ETH_CTL_RESET_SHIFT 2
76#define ETH_CTL_RESET_MASK (1 << ETH_CTL_RESET_SHIFT)
77#define ETH_CTL_EPHY_SHIFT 3
78#define ETH_CTL_EPHY_MASK (1 << ETH_CTL_EPHY_SHIFT)
79
80/* ETH Transmit Control register */
81#define ETH_TXCTL_REG 0x30
82#define ETH_TXCTL_FD_SHIFT 0
83#define ETH_TXCTL_FD_MASK (1 << ETH_TXCTL_FD_SHIFT)
84
85/* ETH Transmit Watermask register */
86#define ETH_TXWMARK_REG 0x34
87#define ETH_TXWMARK_WM_SHIFT 0
88#define ETH_TXWMARK_WM_MASK (0x3f << ETH_TXWMARK_WM_SHIFT)
89
90/* MIB Control register */
91#define MIB_CTL_REG 0x38
92#define MIB_CTL_RDCLEAR_SHIFT 0
93#define MIB_CTL_RDCLEAR_MASK (1 << MIB_CTL_RDCLEAR_SHIFT)
94
95/* ETH Perfect Match registers */
96#define ETH_PM_CNT 4
97#define ETH_PML_REG(x) (0x58 + (x) * 0x8)
98#define ETH_PMH_REG(x) (0x5c + (x) * 0x8)
99#define ETH_PMH_VALID_SHIFT 16
100#define ETH_PMH_VALID_MASK (1 << ETH_PMH_VALID_SHIFT)
101
102/* MIB Counters registers */
103#define MIB_REG_CNT 55
104#define MIB_REG(x) (0x200 + (x) * 4)
105
106/* ETH data */
107struct bcm6348_eth_priv {
108 void __iomem *base;
109 /* DMA */
110 struct dma rx_dma;
111 struct dma tx_dma;
112 /* PHY */
113 int phy_id;
114 struct phy_device *phy_dev;
115};
116
117static void bcm6348_eth_mac_disable(struct bcm6348_eth_priv *priv)
118{
119 /* disable emac */
120 clrsetbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK,
121 ETH_CTL_DISABLE_MASK);
122
123 /* wait until emac is disabled */
124 if (wait_for_bit_be32(priv->base + ETH_CTL_REG,
125 ETH_CTL_DISABLE_MASK, false,
126 ETH_TIMEOUT, false))
127 pr_err("%s: error disabling emac\n", __func__);
128}
129
130static void bcm6348_eth_mac_enable(struct bcm6348_eth_priv *priv)
131{
132 setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK);
133}
134
135static void bcm6348_eth_mac_reset(struct bcm6348_eth_priv *priv)
136{
137 /* reset emac */
138 writel_be(ETH_CTL_RESET_MASK, priv->base + ETH_CTL_REG);
139 wmb();
140
141 /* wait until emac is reset */
142 if (wait_for_bit_be32(priv->base + ETH_CTL_REG,
143 ETH_CTL_RESET_MASK, false,
144 ETH_TIMEOUT, false))
145 pr_err("%s: error resetting emac\n", __func__);
146}
147
148static int bcm6348_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
149{
150 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
151
152 return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
153}
154
155static int bcm6348_eth_recv(struct udevice *dev, int flags, uchar **packetp)
156{
157 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
158
159 return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
160}
161
162static int bcm6348_eth_send(struct udevice *dev, void *packet, int length)
163{
164 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
165
166 return dma_send(&priv->tx_dma, packet, length, NULL);
167}
168
169static int bcm6348_eth_adjust_link(struct udevice *dev,
170 struct phy_device *phydev)
171{
172 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
173
174 /* mac duplex parameters */
175 if (phydev->duplex)
176 setbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK);
177 else
178 clrbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK);
179
180 /* rx flow control (pause frame handling) */
181 if (phydev->pause)
182 setbits_be32(priv->base + ETH_RXCFG_REG,
183 ETH_RXCFG_ENFLOW_MASK);
184 else
185 clrbits_be32(priv->base + ETH_RXCFG_REG,
186 ETH_RXCFG_ENFLOW_MASK);
187
188 return 0;
189}
190
191static int bcm6348_eth_start(struct udevice *dev)
192{
193 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
194 int ret, i;
195
196 /* prepare rx dma buffers */
197 for (i = 0; i < ETH_RX_DESC; i++) {
198 ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
199 PKTSIZE_ALIGN);
200 if (ret < 0)
201 break;
202 }
203
204 /* enable dma rx channel */
205 dma_enable(&priv->rx_dma);
206
207 /* enable dma tx channel */
208 dma_enable(&priv->tx_dma);
209
210 ret = phy_startup(priv->phy_dev);
211 if (ret) {
212 pr_err("%s: could not initialize phy\n", __func__);
213 return ret;
214 }
215
216 if (!priv->phy_dev->link) {
217 pr_err("%s: no phy link\n", __func__);
218 return -EIO;
219 }
220
221 bcm6348_eth_adjust_link(dev, priv->phy_dev);
222
223 /* zero mib counters */
224 for (i = 0; i < MIB_REG_CNT; i++)
225 writel_be(0, MIB_REG(i));
226
227 /* enable rx flow control */
228 setbits_be32(priv->base + ETH_RXCFG_REG, ETH_RXCFG_ENFLOW_MASK);
229
230 /* set max rx/tx length */
231 writel_be((ETH_MAX_MTU_SIZE << ETH_RXMAXLEN_SHIFT) &
232 ETH_RXMAXLEN_MASK, priv->base + ETH_RXMAXLEN_REG);
233 writel_be((ETH_MAX_MTU_SIZE << ETH_TXMAXLEN_SHIFT) &
234 ETH_TXMAXLEN_MASK, priv->base + ETH_TXMAXLEN_REG);
235
236 /* set correct transmit fifo watermark */
237 writel_be((ETH_TX_WATERMARK << ETH_TXWMARK_WM_SHIFT) &
238 ETH_TXWMARK_WM_MASK, priv->base + ETH_TXWMARK_REG);
239
240 /* enable emac */
241 bcm6348_eth_mac_enable(priv);
242
243 /* clear interrupts */
244 writel_be(0, priv->base + ETH_IRMASK_REG);
245
246 return 0;
247}
248
249static void bcm6348_eth_stop(struct udevice *dev)
250{
251 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
252
253 /* disable dma rx channel */
254 dma_disable(&priv->rx_dma);
255
256 /* disable dma tx channel */
257 dma_disable(&priv->tx_dma);
258
259 /* disable emac */
260 bcm6348_eth_mac_disable(priv);
261}
262
263static int bcm6348_eth_write_hwaddr(struct udevice *dev)
264{
265 struct eth_pdata *pdata = dev_get_platdata(dev);
266 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
267 bool running = false;
268
269 /* check if emac is running */
270 if (readl_be(priv->base + ETH_CTL_REG) & ETH_CTL_ENABLE_MASK)
271 running = true;
272
273 /* disable emac */
274 if (running)
275 bcm6348_eth_mac_disable(priv);
276
277 /* set mac address */
278 writel_be((pdata->enetaddr[2] << 24) | (pdata->enetaddr[3]) << 16 |
279 (pdata->enetaddr[4]) << 8 | (pdata->enetaddr[5]),
280 priv->base + ETH_PML_REG(0));
281 writel_be((pdata->enetaddr[1]) | (pdata->enetaddr[0] << 8) |
282 ETH_PMH_VALID_MASK, priv->base + ETH_PMH_REG(0));
283
284 /* enable emac */
285 if (running)
286 bcm6348_eth_mac_enable(priv);
287
288 return 0;
289}
290
291static const struct eth_ops bcm6348_eth_ops = {
292 .free_pkt = bcm6348_eth_free_pkt,
293 .recv = bcm6348_eth_recv,
294 .send = bcm6348_eth_send,
295 .start = bcm6348_eth_start,
296 .stop = bcm6348_eth_stop,
297 .write_hwaddr = bcm6348_eth_write_hwaddr,
298};
299
300static const struct udevice_id bcm6348_eth_ids[] = {
301 { .compatible = "brcm,bcm6348-enet", },
302 { /* sentinel */ }
303};
304
305static int bcm6348_mdio_op(void __iomem *base, uint32_t data)
306{
307 /* make sure mii interrupt status is cleared */
308 writel_be(ETH_IR_MII_MASK, base + ETH_IR_REG);
309
310 /* issue mii op */
311 writel_be(data, base + MII_DAT_REG);
312
313 /* wait until emac is disabled */
314 return wait_for_bit_be32(base + ETH_IR_REG,
315 ETH_IR_MII_MASK, true,
316 ETH_TIMEOUT, false);
317}
318
319static int bcm6348_mdio_read(struct mii_dev *bus, int addr, int devaddr,
320 int reg)
321{
322 void __iomem *base = bus->priv;
323 uint32_t val;
324
325 val = MII_DAT_OP_READ;
326 val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK;
327 val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK;
328 val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK;
329
330 if (bcm6348_mdio_op(base, val)) {
331 pr_err("%s: timeout\n", __func__);
332 return -EINVAL;
333 }
334
335 val = readl_be(base + MII_DAT_REG) & MII_DAT_DATA_MASK;
336 val >>= MII_DAT_DATA_SHIFT;
337
338 return val;
339}
340
341static int bcm6348_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
342 int reg, u16 value)
343{
344 void __iomem *base = bus->priv;
345 uint32_t val;
346
347 val = MII_DAT_OP_WRITE;
348 val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK;
349 val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK;
350 val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK;
351 val |= (value << MII_DAT_DATA_SHIFT) & MII_DAT_DATA_MASK;
352
353 if (bcm6348_mdio_op(base, val)) {
354 pr_err("%s: timeout\n", __func__);
355 return -EINVAL;
356 }
357
358 return 0;
359}
360
361static int bcm6348_mdio_init(const char *name, void __iomem *base)
362{
363 struct mii_dev *bus;
364
365 bus = mdio_alloc();
366 if (!bus) {
367 pr_err("%s: failed to allocate MDIO bus\n", __func__);
368 return -ENOMEM;
369 }
370
371 bus->read = bcm6348_mdio_read;
372 bus->write = bcm6348_mdio_write;
373 bus->priv = base;
374 snprintf(bus->name, sizeof(bus->name), "%s", name);
375
376 return mdio_register(bus);
377}
378
379static int bcm6348_phy_init(struct udevice *dev)
380{
381 struct eth_pdata *pdata = dev_get_platdata(dev);
382 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
383 struct mii_dev *bus;
384
385 /* get mii bus */
386 bus = miiphy_get_dev_by_name(dev->name);
387
388 /* phy connect */
389 priv->phy_dev = phy_connect(bus, priv->phy_id, dev,
390 pdata->phy_interface);
391 if (!priv->phy_dev) {
392 pr_err("%s: no phy device\n", __func__);
393 return -ENODEV;
394 }
395
396 priv->phy_dev->supported = (SUPPORTED_10baseT_Half |
397 SUPPORTED_10baseT_Full |
398 SUPPORTED_100baseT_Half |
399 SUPPORTED_100baseT_Full |
400 SUPPORTED_Autoneg |
401 SUPPORTED_Pause |
402 SUPPORTED_MII);
403 priv->phy_dev->advertising = priv->phy_dev->supported;
404
405 /* phy config */
406 phy_config(priv->phy_dev);
407
408 return 0;
409}
410
411static int bcm6348_eth_probe(struct udevice *dev)
412{
413 struct eth_pdata *pdata = dev_get_platdata(dev);
414 struct bcm6348_eth_priv *priv = dev_get_priv(dev);
415 struct ofnode_phandle_args phy;
416 const char *phy_mode;
417 int ret, i;
418
419 /* get base address */
420 priv->base = dev_remap_addr(dev);
421 if (!priv->base)
422 return -EINVAL;
423 pdata->iobase = (phys_addr_t) priv->base;
424
425 /* get phy mode */
426 pdata->phy_interface = PHY_INTERFACE_MODE_NONE;
427 phy_mode = dev_read_string(dev, "phy-mode");
428 if (phy_mode)
429 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
430 if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
431 return -ENODEV;
432
433 /* get phy */
434 if (dev_read_phandle_with_args(dev, "phy", NULL, 0, 0, &phy))
435 return -ENOENT;
436 priv->phy_id = ofnode_read_u32_default(phy.node, "reg", -1);
437
438 /* get dma channels */
439 ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
440 if (ret)
441 return -EINVAL;
442
443 ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
444 if (ret)
445 return -EINVAL;
446
447 /* try to enable clocks */
448 for (i = 0; ; i++) {
449 struct clk clk;
450 int ret;
451
452 ret = clk_get_by_index(dev, i, &clk);
453 if (ret < 0)
454 break;
455
456 ret = clk_enable(&clk);
457 if (ret < 0) {
458 pr_err("%s: error enabling clock %d\n", __func__, i);
459 return ret;
460 }
461
462 ret = clk_free(&clk);
463 if (ret < 0) {
464 pr_err("%s: error freeing clock %d\n", __func__, i);
465 return ret;
466 }
467 }
468
469 /* try to perform resets */
470 for (i = 0; ; i++) {
471 struct reset_ctl reset;
472 int ret;
473
474 ret = reset_get_by_index(dev, i, &reset);
475 if (ret < 0)
476 break;
477
478 ret = reset_deassert(&reset);
479 if (ret < 0) {
480 pr_err("%s: error deasserting reset %d\n", __func__, i);
481 return ret;
482 }
483
484 ret = reset_free(&reset);
485 if (ret < 0) {
486 pr_err("%s: error freeing reset %d\n", __func__, i);
487 return ret;
488 }
489 }
490
491 /* disable emac */
492 bcm6348_eth_mac_disable(priv);
493
494 /* reset emac */
495 bcm6348_eth_mac_reset(priv);
496
497 /* select correct mii interface */
498 if (pdata->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
499 clrbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK);
500 else
501 setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK);
502
503 /* turn on mdc clock */
504 writel_be((0x1f << MII_SC_MDCFREQDIV_SHIFT) |
505 MII_SC_PREAMBLE_EN_MASK, priv->base + MII_SC_REG);
506
507 /* set mib counters to not clear when read */
508 clrbits_be32(priv->base + MIB_CTL_REG, MIB_CTL_RDCLEAR_MASK);
509
510 /* initialize perfect match registers */
511 for (i = 0; i < ETH_PM_CNT; i++) {
512 writel_be(0, priv->base + ETH_PML_REG(i));
513 writel_be(0, priv->base + ETH_PMH_REG(i));
514 }
515
516 /* init mii bus */
517 ret = bcm6348_mdio_init(dev->name, priv->base);
518 if (ret)
519 return ret;
520
521 /* init phy */
522 ret = bcm6348_phy_init(dev);
523 if (ret)
524 return ret;
525
526 return 0;
527}
528
529U_BOOT_DRIVER(bcm6348_eth) = {
530 .name = "bcm6348_eth",
531 .id = UCLASS_ETH,
532 .of_match = bcm6348_eth_ids,
533 .ops = &bcm6348_eth_ops,
534 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
535 .priv_auto_alloc_size = sizeof(struct bcm6348_eth_priv),
536 .probe = bcm6348_eth_probe,
537};
diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c
new file mode 100644
index 0000000000..a31efba9d1
--- /dev/null
+++ b/drivers/net/bcm6368-eth.c
@@ -0,0 +1,625 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <common.h>
10#include <clk.h>
11#include <dm.h>
12#include <dma.h>
13#include <miiphy.h>
14#include <net.h>
15#include <reset.h>
16#include <wait_bit.h>
17#include <asm/io.h>
18
19#define ETH_PORT_STR "brcm,enetsw-port"
20
21#define ETH_RX_DESC PKTBUFSRX
22#define ETH_ZLEN 60
23#define ETH_TIMEOUT 100
24
25#define ETH_MAX_PORT 8
26#define ETH_RGMII_PORT0 4
27
28/* Port traffic control */
29#define ETH_PTCTRL_REG(x) (0x0 + (x))
30#define ETH_PTCTRL_RXDIS_SHIFT 0
31#define ETH_PTCTRL_RXDIS_MASK (1 << ETH_PTCTRL_RXDIS_SHIFT)
32#define ETH_PTCTRL_TXDIS_SHIFT 1
33#define ETH_PTCTRL_TXDIS_MASK (1 << ETH_PTCTRL_TXDIS_SHIFT)
34
35/* Switch mode register */
36#define ETH_SWMODE_REG 0xb
37#define ETH_SWMODE_FWD_EN_SHIFT 1
38#define ETH_SWMODE_FWD_EN_MASK (1 << ETH_SWMODE_FWD_EN_SHIFT)
39
40/* IMP override Register */
41#define ETH_IMPOV_REG 0xe
42#define ETH_IMPOV_LINKUP_SHIFT 0
43#define ETH_IMPOV_LINKUP_MASK (1 << ETH_IMPOV_LINKUP_SHIFT)
44#define ETH_IMPOV_FDX_SHIFT 1
45#define ETH_IMPOV_FDX_MASK (1 << ETH_IMPOV_FDX_SHIFT)
46#define ETH_IMPOV_100_SHIFT 2
47#define ETH_IMPOV_100_MASK (1 << ETH_IMPOV_100_SHIFT)
48#define ETH_IMPOV_1000_SHIFT 3
49#define ETH_IMPOV_1000_MASK (1 << ETH_IMPOV_1000_SHIFT)
50#define ETH_IMPOV_RXFLOW_SHIFT 4
51#define ETH_IMPOV_RXFLOW_MASK (1 << ETH_IMPOV_RXFLOW_SHIFT)
52#define ETH_IMPOV_TXFLOW_SHIFT 5
53#define ETH_IMPOV_TXFLOW_MASK (1 << ETH_IMPOV_TXFLOW_SHIFT)
54#define ETH_IMPOV_FORCE_SHIFT 7
55#define ETH_IMPOV_FORCE_MASK (1 << ETH_IMPOV_FORCE_SHIFT)
56
57/* Port override Register */
58#define ETH_PORTOV_REG(x) (0x58 + (x))
59#define ETH_PORTOV_LINKUP_SHIFT 0
60#define ETH_PORTOV_LINKUP_MASK (1 << ETH_PORTOV_LINKUP_SHIFT)
61#define ETH_PORTOV_FDX_SHIFT 1
62#define ETH_PORTOV_FDX_MASK (1 << ETH_PORTOV_FDX_SHIFT)
63#define ETH_PORTOV_100_SHIFT 2
64#define ETH_PORTOV_100_MASK (1 << ETH_PORTOV_100_SHIFT)
65#define ETH_PORTOV_1000_SHIFT 3
66#define ETH_PORTOV_1000_MASK (1 << ETH_PORTOV_1000_SHIFT)
67#define ETH_PORTOV_RXFLOW_SHIFT 4
68#define ETH_PORTOV_RXFLOW_MASK (1 << ETH_PORTOV_RXFLOW_SHIFT)
69#define ETH_PORTOV_TXFLOW_SHIFT 5
70#define ETH_PORTOV_TXFLOW_MASK (1 << ETH_PORTOV_TXFLOW_SHIFT)
71#define ETH_PORTOV_ENABLE_SHIFT 6
72#define ETH_PORTOV_ENABLE_MASK (1 << ETH_PORTOV_ENABLE_SHIFT)
73
74/* Port RGMII control register */
75#define ETH_RGMII_CTRL_REG(x) (0x60 + (x))
76#define ETH_RGMII_CTRL_GMII_CLK_EN (1 << 7)
77#define ETH_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6)
78#define ETH_RGMII_CTRL_MII_MODE_MASK (3 << 4)
79#define ETH_RGMII_CTRL_RGMII_MODE (0 << 4)
80#define ETH_RGMII_CTRL_MII_MODE (1 << 4)
81#define ETH_RGMII_CTRL_RVMII_MODE (2 << 4)
82#define ETH_RGMII_CTRL_TIMING_SEL_EN (1 << 0)
83
84/* Port RGMII timing register */
85#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x))
86
87/* MDIO control register */
88#define MII_SC_REG 0xb0
89#define MII_SC_EXT_SHIFT 16
90#define MII_SC_EXT_MASK (1 << MII_SC_EXT_SHIFT)
91#define MII_SC_REG_SHIFT 20
92#define MII_SC_PHYID_SHIFT 25
93#define MII_SC_RD_SHIFT 30
94#define MII_SC_RD_MASK (1 << MII_SC_RD_SHIFT)
95#define MII_SC_WR_SHIFT 31
96#define MII_SC_WR_MASK (1 << MII_SC_WR_SHIFT)
97
98/* MDIO data register */
99#define MII_DAT_REG 0xb4
100
101/* Global Management Configuration Register */
102#define ETH_GMCR_REG 0x200
103#define ETH_GMCR_RST_MIB_SHIFT 0
104#define ETH_GMCR_RST_MIB_MASK (1 << ETH_GMCR_RST_MIB_SHIFT)
105
106/* Jumbo control register port mask register */
107#define ETH_JMBCTL_PORT_REG 0x4004
108
109/* Jumbo control mib good frame register */
110#define ETH_JMBCTL_MAXSIZE_REG 0x4008
111
112/* ETH port data */
113struct bcm_enetsw_port {
114 bool used;
115 const char *name;
116 /* Config */
117 bool bypass_link;
118 int force_speed;
119 bool force_duplex_full;
120 /* PHY */
121 int phy_id;
122};
123
124/* ETH data */
125struct bcm6368_eth_priv {
126 void __iomem *base;
127 /* DMA */
128 struct dma rx_dma;
129 struct dma tx_dma;
130 /* Ports */
131 uint8_t num_ports;
132 struct bcm_enetsw_port used_ports[ETH_MAX_PORT];
133 int sw_port_link[ETH_MAX_PORT];
134 bool rgmii_override;
135 bool rgmii_timing;
136 /* PHY */
137 int phy_id;
138};
139
140static inline bool bcm_enet_port_is_rgmii(int portid)
141{
142 return portid >= ETH_RGMII_PORT0;
143}
144
145static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext,
146 int phy_id, int reg)
147{
148 uint32_t val;
149
150 writel_be(0, priv->base + MII_SC_REG);
151
152 val = MII_SC_RD_MASK |
153 (phy_id << MII_SC_PHYID_SHIFT) |
154 (reg << MII_SC_REG_SHIFT);
155
156 if (ext)
157 val |= MII_SC_EXT_MASK;
158
159 writel_be(val, priv->base + MII_SC_REG);
160 udelay(50);
161
162 return readw_be(priv->base + MII_DAT_REG);
163}
164
165static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext,
166 int phy_id, int reg, u16 data)
167{
168 uint32_t val;
169
170 writel_be(0, priv->base + MII_SC_REG);
171
172 val = MII_SC_WR_MASK |
173 (phy_id << MII_SC_PHYID_SHIFT) |
174 (reg << MII_SC_REG_SHIFT);
175
176 if (ext)
177 val |= MII_SC_EXT_MASK;
178
179 val |= data;
180
181 writel_be(val, priv->base + MII_SC_REG);
182 udelay(50);
183
184 return 0;
185}
186
187static int bcm6368_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
188{
189 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
190
191 return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
192}
193
194static int bcm6368_eth_recv(struct udevice *dev, int flags, uchar **packetp)
195{
196 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
197
198 return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
199}
200
201static int bcm6368_eth_send(struct udevice *dev, void *packet, int length)
202{
203 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
204
205 /* pad packets smaller than ETH_ZLEN */
206 if (length < ETH_ZLEN) {
207 memset(packet + length, 0, ETH_ZLEN - length);
208 length = ETH_ZLEN;
209 }
210
211 return dma_send(&priv->tx_dma, packet, length, NULL);
212}
213
214static int bcm6368_eth_adjust_link(struct udevice *dev)
215{
216 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
217 unsigned int i;
218
219 for (i = 0; i < priv->num_ports; i++) {
220 struct bcm_enetsw_port *port;
221 int val, j, up, adv, lpa, speed, duplex, media;
222 int external_phy = bcm_enet_port_is_rgmii(i);
223 u8 override;
224
225 port = &priv->used_ports[i];
226 if (!port->used)
227 continue;
228
229 if (port->bypass_link)
230 continue;
231
232 /* dummy read to clear */
233 for (j = 0; j < 2; j++)
234 val = bcm6368_mdio_read(priv, external_phy,
235 port->phy_id, MII_BMSR);
236
237 if (val == 0xffff)
238 continue;
239
240 up = (val & BMSR_LSTATUS) ? 1 : 0;
241 if (!(up ^ priv->sw_port_link[i]))
242 continue;
243
244 priv->sw_port_link[i] = up;
245
246 /* link changed */
247 if (!up) {
248 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
249 port->name);
250 writeb_be(ETH_PORTOV_ENABLE_MASK,
251 priv->base + ETH_PORTOV_REG(i));
252 writeb_be(ETH_PTCTRL_RXDIS_MASK |
253 ETH_PTCTRL_TXDIS_MASK,
254 priv->base + ETH_PTCTRL_REG(i));
255 continue;
256 }
257
258 adv = bcm6368_mdio_read(priv, external_phy,
259 port->phy_id, MII_ADVERTISE);
260
261 lpa = bcm6368_mdio_read(priv, external_phy, port->phy_id,
262 MII_LPA);
263
264 /* figure out media and duplex from advertise and LPA values */
265 media = mii_nway_result(lpa & adv);
266 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
267
268 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
269 speed = 100;
270 else
271 speed = 10;
272
273 if (val & BMSR_ESTATEN) {
274 adv = bcm6368_mdio_read(priv, external_phy,
275 port->phy_id, MII_CTRL1000);
276
277 lpa = bcm6368_mdio_read(priv, external_phy,
278 port->phy_id, MII_STAT1000);
279
280 if ((adv & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
281 (lpa & (LPA_1000FULL | LPA_1000HALF))) {
282 speed = 1000;
283 duplex = (lpa & LPA_1000FULL);
284 }
285 }
286
287 pr_alert("link UP on %s, %dMbps, %s-duplex\n",
288 port->name, speed, duplex ? "full" : "half");
289
290 override = ETH_PORTOV_ENABLE_MASK |
291 ETH_PORTOV_LINKUP_MASK;
292
293 if (speed == 1000)
294 override |= ETH_PORTOV_1000_MASK;
295 else if (speed == 100)
296 override |= ETH_PORTOV_100_MASK;
297 if (duplex)
298 override |= ETH_PORTOV_FDX_MASK;
299
300 writeb_be(override, priv->base + ETH_PORTOV_REG(i));
301 writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
302 }
303
304 return 0;
305}
306
307static int bcm6368_eth_start(struct udevice *dev)
308{
309 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
310 uint8_t i;
311
312 /* prepare rx dma buffers */
313 for (i = 0; i < ETH_RX_DESC; i++) {
314 int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
315 PKTSIZE_ALIGN);
316 if (ret < 0)
317 break;
318 }
319
320 /* enable dma rx channel */
321 dma_enable(&priv->rx_dma);
322
323 /* enable dma tx channel */
324 dma_enable(&priv->tx_dma);
325
326 /* apply override config for bypass_link ports here. */
327 for (i = 0; i < priv->num_ports; i++) {
328 struct bcm_enetsw_port *port;
329 u8 override;
330
331 port = &priv->used_ports[i];
332 if (!port->used)
333 continue;
334
335 if (!port->bypass_link)
336 continue;
337
338 override = ETH_PORTOV_ENABLE_MASK |
339 ETH_PORTOV_LINKUP_MASK;
340
341 switch (port->force_speed) {
342 case 1000:
343 override |= ETH_PORTOV_1000_MASK;
344 break;
345 case 100:
346 override |= ETH_PORTOV_100_MASK;
347 break;
348 case 10:
349 break;
350 default:
351 pr_warn("%s: invalid forced speed on port %s\n",
352 __func__, port->name);
353 break;
354 }
355
356 if (port->force_duplex_full)
357 override |= ETH_PORTOV_FDX_MASK;
358
359 writeb_be(override, priv->base + ETH_PORTOV_REG(i));
360 writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
361 }
362
363 bcm6368_eth_adjust_link(dev);
364
365 return 0;
366}
367
368static void bcm6368_eth_stop(struct udevice *dev)
369{
370 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
371
372 /* disable dma rx channel */
373 dma_disable(&priv->rx_dma);
374
375 /* disable dma tx channel */
376 dma_disable(&priv->tx_dma);
377}
378
379static const struct eth_ops bcm6368_eth_ops = {
380 .free_pkt = bcm6368_eth_free_pkt,
381 .recv = bcm6368_eth_recv,
382 .send = bcm6368_eth_send,
383 .start = bcm6368_eth_start,
384 .stop = bcm6368_eth_stop,
385};
386
387static const struct udevice_id bcm6368_eth_ids[] = {
388 { .compatible = "brcm,bcm6368-enet", },
389 { /* sentinel */ }
390};
391
392static bool bcm6368_phy_is_external(struct bcm6368_eth_priv *priv, int phy_id)
393{
394 uint8_t i;
395
396 for (i = 0; i < priv->num_ports; ++i) {
397 if (!priv->used_ports[i].used)
398 continue;
399 if (priv->used_ports[i].phy_id == phy_id)
400 return bcm_enet_port_is_rgmii(i);
401 }
402
403 return true;
404}
405
406static int bcm6368_mii_mdio_read(struct mii_dev *bus, int addr, int devaddr,
407 int reg)
408{
409 struct bcm6368_eth_priv *priv = bus->priv;
410 bool ext = bcm6368_phy_is_external(priv, addr);
411
412 return bcm6368_mdio_read(priv, ext, addr, reg);
413}
414
415static int bcm6368_mii_mdio_write(struct mii_dev *bus, int addr, int devaddr,
416 int reg, u16 data)
417{
418 struct bcm6368_eth_priv *priv = bus->priv;
419 bool ext = bcm6368_phy_is_external(priv, addr);
420
421 return bcm6368_mdio_write(priv, ext, addr, reg, data);
422}
423
424static int bcm6368_mdio_init(const char *name, struct bcm6368_eth_priv *priv)
425{
426 struct mii_dev *bus;
427
428 bus = mdio_alloc();
429 if (!bus) {
430 pr_err("%s: failed to allocate MDIO bus\n", __func__);
431 return -ENOMEM;
432 }
433
434 bus->read = bcm6368_mii_mdio_read;
435 bus->write = bcm6368_mii_mdio_write;
436 bus->priv = priv;
437 snprintf(bus->name, sizeof(bus->name), "%s", name);
438
439 return mdio_register(bus);
440}
441
442static int bcm6368_eth_probe(struct udevice *dev)
443{
444 struct eth_pdata *pdata = dev_get_platdata(dev);
445 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
446 int num_ports, ret, i;
447 uint32_t val;
448 ofnode node;
449
450 /* get base address */
451 priv->base = dev_remap_addr(dev);
452 if (!priv->base)
453 return -EINVAL;
454 pdata->iobase = (phys_addr_t) priv->base;
455
456 /* get number of ports */
457 num_ports = dev_read_u32_default(dev, "brcm,num-ports", ETH_MAX_PORT);
458 if (!num_ports || num_ports > ETH_MAX_PORT)
459 return -EINVAL;
460
461 /* get dma channels */
462 ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
463 if (ret)
464 return -EINVAL;
465
466 ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
467 if (ret)
468 return -EINVAL;
469
470 /* try to enable clocks */
471 for (i = 0; ; i++) {
472 struct clk clk;
473 int ret;
474
475 ret = clk_get_by_index(dev, i, &clk);
476 if (ret < 0)
477 break;
478
479 ret = clk_enable(&clk);
480 if (ret < 0) {
481 pr_err("%s: error enabling clock %d\n", __func__, i);
482 return ret;
483 }
484
485 ret = clk_free(&clk);
486 if (ret < 0) {
487 pr_err("%s: error freeing clock %d\n", __func__, i);
488 return ret;
489 }
490 }
491
492 /* try to perform resets */
493 for (i = 0; ; i++) {
494 struct reset_ctl reset;
495 int ret;
496
497 ret = reset_get_by_index(dev, i, &reset);
498 if (ret < 0)
499 break;
500
501 ret = reset_deassert(&reset);
502 if (ret < 0) {
503 pr_err("%s: error deasserting reset %d\n", __func__, i);
504 return ret;
505 }
506
507 ret = reset_free(&reset);
508 if (ret < 0) {
509 pr_err("%s: error freeing reset %d\n", __func__, i);
510 return ret;
511 }
512 }
513
514 /* set priv data */
515 priv->num_ports = num_ports;
516 if (dev_read_bool(dev, "brcm,rgmii-override"))
517 priv->rgmii_override = true;
518 if (dev_read_bool(dev, "brcm,rgmii-timing"))
519 priv->rgmii_timing = true;
520
521 /* get ports */
522 dev_for_each_subnode(node, dev) {
523 const char *comp;
524 const char *label;
525 unsigned int p;
526 int phy_id;
527 int speed;
528
529 comp = ofnode_read_string(node, "compatible");
530 if (!comp || memcmp(comp, ETH_PORT_STR, sizeof(ETH_PORT_STR)))
531 continue;
532
533 p = ofnode_read_u32_default(node, "reg", ETH_MAX_PORT);
534 if (p >= num_ports)
535 return -EINVAL;
536
537 label = ofnode_read_string(node, "label");
538 if (!label) {
539 debug("%s: node %s has no label\n", __func__,
540 ofnode_get_name(node));
541 return -EINVAL;
542 }
543
544 phy_id = ofnode_read_u32_default(node, "brcm,phy-id", -1);
545
546 priv->used_ports[p].used = true;
547 priv->used_ports[p].name = label;
548 priv->used_ports[p].phy_id = phy_id;
549
550 if (ofnode_read_bool(node, "full-duplex"))
551 priv->used_ports[p].force_duplex_full = true;
552 if (ofnode_read_bool(node, "bypass-link"))
553 priv->used_ports[p].bypass_link = true;
554 speed = ofnode_read_u32_default(node, "speed", 0);
555 if (speed)
556 priv->used_ports[p].force_speed = speed;
557 }
558
559 /* init mii bus */
560 ret = bcm6368_mdio_init(dev->name, priv);
561 if (ret)
562 return ret;
563
564 /* disable all ports */
565 for (i = 0; i < priv->num_ports; i++) {
566 writeb_be(ETH_PORTOV_ENABLE_MASK,
567 priv->base + ETH_PORTOV_REG(i));
568 writeb_be(ETH_PTCTRL_RXDIS_MASK |
569 ETH_PTCTRL_TXDIS_MASK,
570 priv->base + ETH_PTCTRL_REG(i));
571
572 priv->sw_port_link[i] = 0;
573 }
574
575 /* enable external ports */
576 for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
577 u8 rgmii_ctrl;
578
579 if (!priv->used_ports[i].used)
580 continue;
581
582 rgmii_ctrl = readb_be(priv->base + ETH_RGMII_CTRL_REG(i));
583 rgmii_ctrl |= ETH_RGMII_CTRL_GMII_CLK_EN;
584 if (priv->rgmii_override)
585 rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
586 if (priv->rgmii_timing)
587 rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
588 writeb_be(rgmii_ctrl, priv->base + ETH_RGMII_CTRL_REG(i));
589 }
590
591 /* reset mib */
592 val = readb_be(priv->base + ETH_GMCR_REG);
593 val |= ETH_GMCR_RST_MIB_MASK;
594 writeb_be(val, priv->base + ETH_GMCR_REG);
595 mdelay(1);
596 val &= ~ETH_GMCR_RST_MIB_MASK;
597 writeb_be(val, priv->base + ETH_GMCR_REG);
598 mdelay(1);
599
600 /* force CPU port state */
601 val = readb_be(priv->base + ETH_IMPOV_REG);
602 val |= ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK;
603 writeb_be(val, priv->base + ETH_IMPOV_REG);
604
605 /* enable switch forward engine */
606 val = readb_be(priv->base + ETH_SWMODE_REG);
607 val |= ETH_SWMODE_FWD_EN_MASK;
608 writeb_be(val, priv->base + ETH_SWMODE_REG);
609
610 /* enable jumbo on all ports */
611 writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG);
612 writew_be(9728, priv->base + ETH_JMBCTL_MAXSIZE_REG);
613
614 return 0;
615}
616
617U_BOOT_DRIVER(bcm6368_eth) = {
618 .name = "bcm6368_eth",
619 .id = UCLASS_ETH,
620 .of_match = bcm6368_eth_ids,
621 .ops = &bcm6368_eth_ops,
622 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
623 .priv_auto_alloc_size = sizeof(struct bcm6368_eth_priv),
624 .probe = bcm6368_eth_probe,
625};
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 99c5c649a0..32fb34b793 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
604 writel(0x00000000, &fec->eth->gaddr2); 604 writel(0x00000000, &fec->eth->gaddr2);
605 605
606 /* Do not access reserved register */ 606 /* Do not access reserved register */
607 if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { 607 if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) {
608 /* clear MIB RAM */ 608 /* clear MIB RAM */
609 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) 609 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
610 writel(0, i); 610 writel(0, i);
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index e837eb7688..cda4caa803 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -656,7 +656,8 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
656 656
657 phy_probe(dev); 657 phy_probe(dev);
658 658
659 bus->phymap[addr] = dev; 659 if (addr >= 0 && addr < PHY_MAX_ADDR)
660 bus->phymap[addr] = dev;
660 661
661 return dev; 662 return dev;
662} 663}
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7e6fad305a..30a6aa6ee8 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -238,6 +238,16 @@ config PINCTRL_ROCKCHIP_RK3399
238 the GPIO definitions and pin control functions for each available 238 the GPIO definitions and pin control functions for each available
239 multiplex function. 239 multiplex function.
240 240
241config PINCTRL_ROCKCHIP_RK3399_FULL
242 bool "Rockchip rk3399 pin control driver (full)"
243 depends on PINCTRL_FULL && PINCTRL_ROCKCHIP_RK3399
244 help
245 Support full pin multiplexing control on Rockchip rk3399 SoCs.
246
247 This enables the full pinctrl driver for the RK3399.
248 Contrary to the non-full pinctrl driver, this will evaluate
249 the board DTB to get the pinctrl settings.
250
241config PINCTRL_ROCKCHIP_RV1108 251config PINCTRL_ROCKCHIP_RV1108
242 bool "Rockchip rv1108 pin control driver" 252 bool "Rockchip rv1108 pin control driver"
243 depends on DM 253 depends on DM
@@ -306,6 +316,7 @@ source "drivers/pinctrl/nxp/Kconfig"
306source "drivers/pinctrl/renesas/Kconfig" 316source "drivers/pinctrl/renesas/Kconfig"
307source "drivers/pinctrl/uniphier/Kconfig" 317source "drivers/pinctrl/uniphier/Kconfig"
308source "drivers/pinctrl/exynos/Kconfig" 318source "drivers/pinctrl/exynos/Kconfig"
319source "drivers/pinctrl/mscc/Kconfig"
309source "drivers/pinctrl/mvebu/Kconfig" 320source "drivers/pinctrl/mvebu/Kconfig"
310source "drivers/pinctrl/broadcom/Kconfig" 321source "drivers/pinctrl/broadcom/Kconfig"
311 322
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 293bad3a95..66d36b99d1 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o
17obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ 17obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
18obj-$(CONFIG_PINCTRL_MESON) += meson/ 18obj-$(CONFIG_PINCTRL_MESON) += meson/
19obj-$(CONFIG_PINCTRL_MTK) += mediatek/ 19obj-$(CONFIG_PINCTRL_MTK) += mediatek/
20obj-$(CONFIG_PINCTRL_MSCC) += mscc/
20obj-$(CONFIG_ARCH_MVEBU) += mvebu/ 21obj-$(CONFIG_ARCH_MVEBU) += mvebu/
21obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 22obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
22obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o 23obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
new file mode 100644
index 0000000000..cfc6c06076
--- /dev/null
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -0,0 +1,22 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3config PINCTRL_MSCC
4 bool
5
6config PINCTRL_MSCC_OCELOT
7 depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
8 select PINCTRL_MSCC
9 default y
10 bool "Microsemi ocelot family pin control driver"
11 help
12 Support pin multiplexing and pin configuration control on
13 Microsemi ocelot SoCs.
14
15config PINCTRL_MSCC_LUTON
16 depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
17 select PINCTRL_MSCC
18 default y
19 bool "Microsemi luton family pin control driver"
20 help
21 Support pin multiplexing and pin configuration control on
22 Microsemi luton SoCs.
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
new file mode 100644
index 0000000000..6910671728
--- /dev/null
+++ b/drivers/pinctrl/mscc/Makefile
@@ -0,0 +1,5 @@
1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3obj-y += mscc-common.o
4obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
5obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c
new file mode 100644
index 0000000000..d74b8a6649
--- /dev/null
+++ b/drivers/pinctrl/mscc/mscc-common.c
@@ -0,0 +1,236 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * Author: <gregory.clement@bootlin.com>
7 * License: Dual MIT/GPL
8 * Copyright (c) 2017 Microsemi Corporation
9 */
10
11#include <asm/gpio.h>
12#include <asm/system.h>
13#include <common.h>
14#include <config.h>
15#include <dm.h>
16#include <dm/device-internal.h>
17#include <dm/lists.h>
18#include <dm/pinctrl.h>
19#include <dm/root.h>
20#include <errno.h>
21#include <fdtdec.h>
22#include <linux/io.h>
23#include "mscc-common.h"
24
25#define MSCC_GPIO_OUT_SET 0x0
26#define MSCC_GPIO_OUT_CLR 0x4
27#define MSCC_GPIO_OUT 0x8
28#define MSCC_GPIO_IN 0xc
29#define MSCC_GPIO_OE 0x10
30#define MSCC_GPIO_INTR 0x14
31#define MSCC_GPIO_INTR_ENA 0x18
32#define MSCC_GPIO_INTR_IDENT 0x1c
33#define MSCC_GPIO_ALT0 0x20
34#define MSCC_GPIO_ALT1 0x24
35
36static int mscc_get_functions_count(struct udevice *dev)
37{
38 struct mscc_pinctrl *info = dev_get_priv(dev);
39
40 return info->num_func;
41}
42
43static const char *mscc_get_function_name(struct udevice *dev,
44 unsigned int function)
45{
46 struct mscc_pinctrl *info = dev_get_priv(dev);
47
48 return info->function_names[function];
49}
50
51static int mscc_pin_function_idx(unsigned int pin, unsigned int function,
52 const struct mscc_pin_data *mscc_pins)
53{
54 struct mscc_pin_caps *p = mscc_pins[pin].drv_data;
55 int i;
56
57 for (i = 0; i < MSCC_FUNC_PER_PIN; i++) {
58 if (function == p->functions[i])
59 return i;
60 }
61
62 return -1;
63}
64
65static int mscc_pinmux_set_mux(struct udevice *dev,
66 unsigned int pin_selector, unsigned int selector)
67{
68 struct mscc_pinctrl *info = dev_get_priv(dev);
69 struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
70 int f;
71
72 f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
73 if (f < 0)
74 return -EINVAL;
75 /*
76 * f is encoded on two bits.
77 * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
78 * ALT1
79 * This is racy because both registers can't be updated at the same time
80 * but it doesn't matter much for now.
81 */
82 if (f & BIT(0))
83 setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
84 else
85 clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
86
87 if (f & BIT(1))
88 setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
89 else
90 clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
91
92 return 0;
93}
94
95static int mscc_pctl_get_groups_count(struct udevice *dev)
96{
97 struct mscc_pinctrl *info = dev_get_priv(dev);
98
99 return info->num_pins;
100}
101
102static const char *mscc_pctl_get_group_name(struct udevice *dev,
103 unsigned int group)
104{
105 struct mscc_pinctrl *info = dev_get_priv(dev);
106
107 return info->mscc_pins[group].name;
108}
109
110static int mscc_create_group_func_map(struct udevice *dev,
111 struct mscc_pinctrl *info)
112{
113 u16 pins[info->num_pins];
114 int f, npins, i;
115
116 for (f = 0; f < info->num_func; f++) {
117 for (npins = 0, i = 0; i < info->num_pins; i++) {
118 if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0)
119 pins[npins++] = i;
120 }
121
122 info->func[f].ngroups = npins;
123 info->func[f].groups = devm_kzalloc(dev, npins *
124 sizeof(char *), GFP_KERNEL);
125 if (!info->func[f].groups)
126 return -ENOMEM;
127
128 for (i = 0; i < npins; i++)
129 info->func[f].groups[i] = info->mscc_pins[pins[i]].name;
130 }
131
132 return 0;
133}
134
135static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info)
136{
137 int ret;
138
139 ret = mscc_create_group_func_map(dev, info);
140 if (ret) {
141 dev_err(dev, "Unable to create group func map.\n");
142 return ret;
143 }
144
145 return 0;
146}
147
148static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
149{
150 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
151 unsigned int val;
152
153 val = readl(info->regs + MSCC_GPIO_IN);
154
155 return !!(val & BIT(offset));
156}
157
158static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
159{
160 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
161
162 if (value)
163 writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
164 else
165 writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
166
167 return 0;
168}
169
170static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
171{
172 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
173 unsigned int val;
174
175 val = readl(info->regs + MSCC_GPIO_OE);
176
177 return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;
178}
179
180static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
181{
182 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
183
184 clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
185
186 return 0;
187}
188
189static int mscc_gpio_direction_output(struct udevice *dev,
190 unsigned int offset, int value)
191{
192 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
193
194 setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
195
196 return mscc_gpio_set(dev, offset, value);
197}
198
199const struct dm_gpio_ops mscc_gpio_ops = {
200 .set_value = mscc_gpio_set,
201 .get_value = mscc_gpio_get,
202 .get_function = mscc_gpio_get_direction,
203 .direction_input = mscc_gpio_direction_input,
204 .direction_output = mscc_gpio_direction_output,
205};
206
207const struct pinctrl_ops mscc_pinctrl_ops = {
208 .get_pins_count = mscc_pctl_get_groups_count,
209 .get_pin_name = mscc_pctl_get_group_name,
210 .get_functions_count = mscc_get_functions_count,
211 .get_function_name = mscc_get_function_name,
212 .pinmux_set = mscc_pinmux_set_mux,
213 .set_state = pinctrl_generic_set_state,
214};
215
216int mscc_pinctrl_probe(struct udevice *dev, int num_func,
217 const struct mscc_pin_data *mscc_pins, int num_pins,
218 char *const *function_names)
219{
220 struct mscc_pinctrl *priv = dev_get_priv(dev);
221 int ret;
222
223 priv->regs = dev_remap_addr(dev);
224 if (!priv->regs)
225 return -EINVAL;
226
227 priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func),
228 GFP_KERNEL);
229 priv->num_func = num_func;
230 priv->mscc_pins = mscc_pins;
231 priv->num_pins = num_pins;
232 priv->function_names = function_names;
233 ret = mscc_pinctrl_register(dev, priv);
234
235 return ret;
236}
diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h
new file mode 100644
index 0000000000..b0001db44c
--- /dev/null
+++ b/drivers/pinctrl/mscc/mscc-common.h
@@ -0,0 +1,51 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */
9
10#define MSCC_FUNC_PER_PIN 4
11
12struct mscc_pin_caps {
13 unsigned int pin;
14 unsigned char functions[MSCC_FUNC_PER_PIN];
15};
16
17struct mscc_pin_data {
18 const char *name;
19 struct mscc_pin_caps *drv_data;
20};
21
22#define MSCC_P(p, f0, f1, f2) \
23static struct mscc_pin_caps mscc_pin_##p = { \
24 .pin = p, \
25 .functions = { \
26 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
27 }, \
28}
29
30struct mscc_pmx_func {
31 const char **groups;
32 unsigned int ngroups;
33};
34
35struct mscc_pinctrl {
36 struct udevice *dev;
37 struct pinctrl_dev *pctl;
38 void __iomem *regs;
39 struct mscc_pmx_func *func;
40 int num_func;
41 const struct mscc_pin_data *mscc_pins;
42 int num_pins;
43 char * const *function_names;
44};
45
46int mscc_pinctrl_probe(struct udevice *dev, int num_func,
47 const struct mscc_pin_data *mscc_pins, int num_pins,
48 char * const *function_names);
49const struct pinctrl_ops mscc_pinctrl_ops;
50
51const struct dm_gpio_ops mscc_gpio_ops;
diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c b/drivers/pinctrl/mscc/pinctrl-luton.c
new file mode 100644
index 0000000000..7166588e3c
--- /dev/null
+++ b/drivers/pinctrl/mscc/pinctrl-luton.c
@@ -0,0 +1,172 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <gregory.clement@bootlin.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2018 Microsemi Corporation
8 */
9
10#include <common.h>
11#include <config.h>
12#include <dm.h>
13#include <dm/device-internal.h>
14#include <dm/lists.h>
15#include <dm/pinctrl.h>
16#include <dm/root.h>
17#include <errno.h>
18#include <fdtdec.h>
19#include <linux/io.h>
20#include <asm/gpio.h>
21#include <asm/system.h>
22#include "mscc-common.h"
23
24enum {
25 FUNC_NONE,
26 FUNC_GPIO,
27 FUNC_SIO,
28 FUNC_TACHO,
29 FUNC_TWI,
30 FUNC_PHY_LED,
31 FUNC_EXT_IRQ,
32 FUNC_SFP,
33 FUNC_SI,
34 FUNC_PWM,
35 FUNC_UART,
36 FUNC_MAX
37};
38
39static char * const luton_function_names[] = {
40 [FUNC_NONE] = "none",
41 [FUNC_GPIO] = "gpio",
42 [FUNC_SIO] = "sio",
43 [FUNC_TACHO] = "tacho",
44 [FUNC_TWI] = "twi",
45 [FUNC_PHY_LED] = "phy_led",
46 [FUNC_EXT_IRQ] = "ext_irq",
47 [FUNC_SFP] = "sfp",
48 [FUNC_SI] = "si",
49 [FUNC_PWM] = "pwm",
50 [FUNC_UART] = "uart",
51};
52
53MSCC_P(0, SIO, NONE, NONE);
54MSCC_P(1, SIO, NONE, NONE);
55MSCC_P(2, SIO, NONE, NONE);
56MSCC_P(3, SIO, NONE, NONE);
57MSCC_P(4, TACHO, NONE, NONE);
58MSCC_P(5, TWI, PHY_LED, NONE);
59MSCC_P(6, TWI, PHY_LED, NONE);
60MSCC_P(7, NONE, PHY_LED, NONE);
61MSCC_P(8, EXT_IRQ, PHY_LED, NONE);
62MSCC_P(9, EXT_IRQ, PHY_LED, NONE);
63MSCC_P(10, SFP, PHY_LED, NONE);
64MSCC_P(11, SFP, PHY_LED, NONE);
65MSCC_P(12, SFP, PHY_LED, NONE);
66MSCC_P(13, SFP, PHY_LED, NONE);
67MSCC_P(14, SI, PHY_LED, NONE);
68MSCC_P(15, SI, PHY_LED, NONE);
69MSCC_P(16, SI, PHY_LED, NONE);
70MSCC_P(17, SFP, PHY_LED, NONE);
71MSCC_P(18, SFP, PHY_LED, NONE);
72MSCC_P(19, SFP, PHY_LED, NONE);
73MSCC_P(20, SFP, PHY_LED, NONE);
74MSCC_P(21, SFP, PHY_LED, NONE);
75MSCC_P(22, SFP, PHY_LED, NONE);
76MSCC_P(23, SFP, PHY_LED, NONE);
77MSCC_P(24, SFP, PHY_LED, NONE);
78MSCC_P(25, SFP, PHY_LED, NONE);
79MSCC_P(26, SFP, PHY_LED, NONE);
80MSCC_P(27, SFP, PHY_LED, NONE);
81MSCC_P(28, SFP, PHY_LED, NONE);
82MSCC_P(29, PWM, NONE, NONE);
83MSCC_P(30, UART, NONE, NONE);
84MSCC_P(31, UART, NONE, NONE);
85
86#define LUTON_PIN(n) { \
87 .name = "GPIO_"#n, \
88 .drv_data = &mscc_pin_##n \
89}
90
91static const struct mscc_pin_data luton_pins[] = {
92 LUTON_PIN(0),
93 LUTON_PIN(1),
94 LUTON_PIN(2),
95 LUTON_PIN(3),
96 LUTON_PIN(4),
97 LUTON_PIN(5),
98 LUTON_PIN(6),
99 LUTON_PIN(7),
100 LUTON_PIN(8),
101 LUTON_PIN(9),
102 LUTON_PIN(10),
103 LUTON_PIN(11),
104 LUTON_PIN(12),
105 LUTON_PIN(13),
106 LUTON_PIN(14),
107 LUTON_PIN(15),
108 LUTON_PIN(16),
109 LUTON_PIN(17),
110 LUTON_PIN(18),
111 LUTON_PIN(19),
112 LUTON_PIN(20),
113 LUTON_PIN(21),
114 LUTON_PIN(22),
115 LUTON_PIN(23),
116 LUTON_PIN(24),
117 LUTON_PIN(25),
118 LUTON_PIN(26),
119 LUTON_PIN(27),
120 LUTON_PIN(28),
121 LUTON_PIN(29),
122 LUTON_PIN(30),
123 LUTON_PIN(31),
124};
125
126static int luton_gpio_probe(struct udevice *dev)
127{
128 struct gpio_dev_priv *uc_priv;
129
130 uc_priv = dev_get_uclass_priv(dev);
131 uc_priv->bank_name = "luton-gpio";
132 uc_priv->gpio_count = ARRAY_SIZE(luton_pins);
133
134 return 0;
135}
136
137static struct driver luton_gpio_driver = {
138 .name = "luton-gpio",
139 .id = UCLASS_GPIO,
140 .probe = luton_gpio_probe,
141 .ops = &mscc_gpio_ops,
142};
143
144int luton_pinctrl_probe(struct udevice *dev)
145{
146 int ret;
147
148 ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
149 ARRAY_SIZE(luton_pins), luton_function_names);
150
151 if (ret)
152 return ret;
153
154 ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL,
155 dev_of_offset(dev), NULL);
156
157 return 0;
158}
159
160static const struct udevice_id luton_pinctrl_of_match[] = {
161 {.compatible = "mscc,luton-pinctrl"},
162 {},
163};
164
165U_BOOT_DRIVER(luton_pinctrl) = {
166 .name = "luton-pinctrl",
167 .id = UCLASS_PINCTRL,
168 .of_match = of_match_ptr(luton_pinctrl_of_match),
169 .probe = luton_pinctrl_probe,
170 .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
171 .ops = &mscc_pinctrl_ops,
172};
diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c b/drivers/pinctrl/mscc/pinctrl-ocelot.c
new file mode 100644
index 0000000000..10f9b90aad
--- /dev/null
+++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c
@@ -0,0 +1,188 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * Author: <gregory.clement@bootlin.com>
7 * License: Dual MIT/GPL
8 * Copyright (c) 2017 Microsemi Corporation
9 */
10
11#include <asm/gpio.h>
12#include <asm/system.h>
13#include <common.h>
14#include <config.h>
15#include <dm.h>
16#include <dm/device-internal.h>
17#include <dm/lists.h>
18#include <dm/pinctrl.h>
19#include <dm/root.h>
20#include <errno.h>
21#include <fdtdec.h>
22#include <linux/io.h>
23#include "mscc-common.h"
24
25enum {
26 FUNC_NONE,
27 FUNC_GPIO,
28 FUNC_IRQ0_IN,
29 FUNC_IRQ0_OUT,
30 FUNC_IRQ1_IN,
31 FUNC_IRQ1_OUT,
32 FUNC_MIIM1,
33 FUNC_PCI_WAKE,
34 FUNC_PTP0,
35 FUNC_PTP1,
36 FUNC_PTP2,
37 FUNC_PTP3,
38 FUNC_PWM,
39 FUNC_RECO_CLK0,
40 FUNC_RECO_CLK1,
41 FUNC_SFP0,
42 FUNC_SFP1,
43 FUNC_SFP2,
44 FUNC_SFP3,
45 FUNC_SFP4,
46 FUNC_SFP5,
47 FUNC_SG0,
48 FUNC_SI,
49 FUNC_TACHO,
50 FUNC_TWI,
51 FUNC_TWI_SCL_M,
52 FUNC_UART,
53 FUNC_UART2,
54 FUNC_MAX
55};
56
57static char * const ocelot_function_names[] = {
58 [FUNC_NONE] = "none",
59 [FUNC_GPIO] = "gpio",
60 [FUNC_IRQ0_IN] = "irq0_in",
61 [FUNC_IRQ0_OUT] = "irq0_out",
62 [FUNC_IRQ1_IN] = "irq1_in",
63 [FUNC_IRQ1_OUT] = "irq1_out",
64 [FUNC_MIIM1] = "miim1",
65 [FUNC_PCI_WAKE] = "pci_wake",
66 [FUNC_PTP0] = "ptp0",
67 [FUNC_PTP1] = "ptp1",
68 [FUNC_PTP2] = "ptp2",
69 [FUNC_PTP3] = "ptp3",
70 [FUNC_PWM] = "pwm",
71 [FUNC_RECO_CLK0] = "reco_clk0",
72 [FUNC_RECO_CLK1] = "reco_clk1",
73 [FUNC_SFP0] = "sfp0",
74 [FUNC_SFP1] = "sfp1",
75 [FUNC_SFP2] = "sfp2",
76 [FUNC_SFP3] = "sfp3",
77 [FUNC_SFP4] = "sfp4",
78 [FUNC_SFP5] = "sfp5",
79 [FUNC_SG0] = "sg0",
80 [FUNC_SI] = "si",
81 [FUNC_TACHO] = "tacho",
82 [FUNC_TWI] = "twi",
83 [FUNC_TWI_SCL_M] = "twi_scl_m",
84 [FUNC_UART] = "uart",
85 [FUNC_UART2] = "uart2",
86};
87
88MSCC_P(0, SG0, NONE, NONE);
89MSCC_P(1, SG0, NONE, NONE);
90MSCC_P(2, SG0, NONE, NONE);
91MSCC_P(3, SG0, NONE, NONE);
92MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI);
93MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
94MSCC_P(6, UART, TWI_SCL_M, NONE);
95MSCC_P(7, UART, TWI_SCL_M, NONE);
96MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT);
97MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT);
98MSCC_P(10, PTP2, TWI_SCL_M, SFP0);
99MSCC_P(11, PTP3, TWI_SCL_M, SFP1);
100MSCC_P(12, UART2, TWI_SCL_M, SFP2);
101MSCC_P(13, UART2, TWI_SCL_M, SFP3);
102MSCC_P(14, MIIM1, TWI_SCL_M, SFP4);
103MSCC_P(15, MIIM1, TWI_SCL_M, SFP5);
104MSCC_P(16, TWI, NONE, SI);
105MSCC_P(17, TWI, TWI_SCL_M, SI);
106MSCC_P(18, PTP0, TWI_SCL_M, NONE);
107MSCC_P(19, PTP1, TWI_SCL_M, NONE);
108MSCC_P(20, RECO_CLK0, TACHO, NONE);
109MSCC_P(21, RECO_CLK1, PWM, NONE);
110
111#define OCELOT_PIN(n) { \
112 .name = "GPIO_"#n, \
113 .drv_data = &mscc_pin_##n \
114}
115
116static const struct mscc_pin_data ocelot_pins[] = {
117 OCELOT_PIN(0),
118 OCELOT_PIN(1),
119 OCELOT_PIN(2),
120 OCELOT_PIN(3),
121 OCELOT_PIN(4),
122 OCELOT_PIN(5),
123 OCELOT_PIN(6),
124 OCELOT_PIN(7),
125 OCELOT_PIN(8),
126 OCELOT_PIN(9),
127 OCELOT_PIN(10),
128 OCELOT_PIN(11),
129 OCELOT_PIN(12),
130 OCELOT_PIN(13),
131 OCELOT_PIN(14),
132 OCELOT_PIN(15),
133 OCELOT_PIN(16),
134 OCELOT_PIN(17),
135 OCELOT_PIN(18),
136 OCELOT_PIN(19),
137 OCELOT_PIN(20),
138 OCELOT_PIN(21),
139};
140
141static int ocelot_gpio_probe(struct udevice *dev)
142{
143 struct gpio_dev_priv *uc_priv;
144
145 uc_priv = dev_get_uclass_priv(dev);
146 uc_priv->bank_name = "ocelot-gpio";
147 uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins);
148
149 return 0;
150}
151
152static struct driver ocelot_gpio_driver = {
153 .name = "ocelot-gpio",
154 .id = UCLASS_GPIO,
155 .probe = ocelot_gpio_probe,
156 .ops = &mscc_gpio_ops,
157};
158
159int ocelot_pinctrl_probe(struct udevice *dev)
160{
161 int ret;
162
163 ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
164 ARRAY_SIZE(ocelot_pins),
165 ocelot_function_names);
166
167 if (ret)
168 return ret;
169
170 ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
171 dev_of_offset(dev), NULL);
172
173 return ret;
174}
175
176static const struct udevice_id ocelot_pinctrl_of_match[] = {
177 {.compatible = "mscc,ocelot-pinctrl"},
178 {},
179};
180
181U_BOOT_DRIVER(ocelot_pinctrl) = {
182 .name = "ocelot-pinctrl",
183 .id = UCLASS_PINCTRL,
184 .of_match = of_match_ptr(ocelot_pinctrl_of_match),
185 .probe = ocelot_pinctrl_probe,
186 .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
187 .ops = &mscc_pinctrl_ops,
188};
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 799d1d2465..f1d5a5c50d 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -74,3 +74,17 @@ config PINCTRL_IMX8
74 is different from the linux one, this is a simple implementation, 74 is different from the linux one, this is a simple implementation,
75 only parses the 'fsl,pins' property and configures related 75 only parses the 'fsl,pins' property and configures related
76 registers. 76 registers.
77
78config PINCTRL_VYBRID
79 bool "Vybrid (vf610) pinctrl driver"
80 depends on ARCH_VF610 && PINCTRL_FULL
81 select DEVRES
82 select PINCTRL_IMX
83 help
84 Say Y here to enable the Vybrid (vf610) pinctrl driver
85
86 This provides a simple pinctrl driver for Vybrid SoC familiy,
87 vf610. This feature depends on device tree
88 configuration. This driver is different from the linux one,
89 this is a simple implementation, only parses the 'fsl,pins'
90 property and configure related registers.
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 310b3b3a2e..891ee6e477 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
5obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o 5obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
6obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o 6obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
7obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o 7obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
8obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c
new file mode 100644
index 0000000000..e795b5fd8a
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-vf610.c
@@ -0,0 +1,40 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <dm/pinctrl.h>
10
11#include "pinctrl-imx.h"
12
13static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = {
14 .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
15};
16
17static int vf610_pinctrl_probe(struct udevice *dev)
18{
19 struct imx_pinctrl_soc_info *info =
20 (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
21
22 return imx_pinctrl_probe(dev, info);
23}
24
25static const struct udevice_id vf610_pinctrl_match[] = {
26 { .compatible = "fsl,vf610-iomuxc",
27 .data = (ulong)&vf610_pinctrl_soc_info },
28 { /* sentinel */ }
29};
30
31U_BOOT_DRIVER(vf610_pinctrl) = {
32 .name = "vf610-pinctrl",
33 .id = UCLASS_PINCTRL,
34 .of_match = of_match_ptr(vf610_pinctrl_match),
35 .probe = vf610_pinctrl_probe,
36 .remove = imx_pinctrl_remove,
37 .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
38 .ops = &imx_pinctrl_ops,
39 .flags = DM_FLAG_PRE_RELOC,
40};
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index 6db0445067..0e3260afd1 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -27,6 +27,28 @@ int pinctrl_decode_pin_config(const void *blob, int node)
27 return flags; 27 return flags;
28} 28}
29 29
30/*
31 * TODO: this function is temporary for v2019.01.
32 * It should be renamed to pinctrl_decode_pin_config(),
33 * the original pinctrl_decode_pin_config() function should
34 * be removed and all callers of the original function should
35 * be migrated to use the new one.
36 */
37int pinctrl_decode_pin_config_dm(struct udevice *dev)
38{
39 int pinconfig = 0;
40
41 if (dev->uclass->uc_drv->id != UCLASS_PINCONFIG)
42 return -EINVAL;
43
44 if (dev_read_bool(dev, "bias-pull-up"))
45 pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_UP;
46 else if (dev_read_bool(dev, "bias-pull-down"))
47 pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_DOWN;
48
49 return pinconfig;
50}
51
30#if CONFIG_IS_ENABLED(PINCTRL_FULL) 52#if CONFIG_IS_ENABLED(PINCTRL_FULL)
31/** 53/**
32 * pinctrl_config_one() - apply pinctrl settings for a single node 54 * pinctrl_config_one() - apply pinctrl settings for a single node
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index bc92dd7c06..5c5af3a0bd 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -1,6 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0+ 1// SPDX-License-Identifier: GPL-2.0+
2/* 2/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * (C) 2018 Theobroma Systems Design und Consulting GmbH
4 */ 5 */
5 6
6#include <common.h> 7#include <common.h>
@@ -14,11 +15,241 @@
14#include <asm/arch/clock.h> 15#include <asm/arch/clock.h>
15#include <dm/pinctrl.h> 16#include <dm/pinctrl.h>
16 17
18#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
19static const u32 RK_GRF_P_PULLUP = 1;
20static const u32 RK_GRF_P_PULLDOWN = 2;
21#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
22
17struct rk3399_pinctrl_priv { 23struct rk3399_pinctrl_priv {
18 struct rk3399_grf_regs *grf; 24 struct rk3399_grf_regs *grf;
19 struct rk3399_pmugrf_regs *pmugrf; 25 struct rk3399_pmugrf_regs *pmugrf;
26 struct rockchip_pin_bank *banks;
27};
28
29#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
30/* Location of pinctrl/pinconf registers. */
31enum rk_grf_location {
32 RK_GRF,
33 RK_PMUGRF,
34};
35
36/**
37 * @nr_pins: number of pins in this bank
38 * @grf_location: location of pinctrl/pinconf registers
39 * @bank_num: number of the bank, to account for holes
40 * @iomux: array describing the 4 iomux sources of the bank
41 */
42struct rockchip_pin_bank {
43 u8 nr_pins;
44 enum rk_grf_location grf_location;
45 size_t iomux_offset;
46 size_t pupd_offset;
20}; 47};
21 48
49#define PIN_BANK(pins, grf, iomux, pupd) \
50 { \
51 .nr_pins = pins, \
52 .grf_location = grf, \
53 .iomux_offset = iomux, \
54 .pupd_offset = pupd, \
55 }
56
57static struct rockchip_pin_bank rk3399_pin_banks[] = {
58 PIN_BANK(16, RK_PMUGRF,
59 offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
60 offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
61 PIN_BANK(32, RK_PMUGRF,
62 offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
63 offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
64 PIN_BANK(32, RK_GRF,
65 offsetof(struct rk3399_grf_regs, gpio2a_iomux),
66 offsetof(struct rk3399_grf_regs, gpio2_p)),
67 PIN_BANK(32, RK_GRF,
68 offsetof(struct rk3399_grf_regs, gpio3a_iomux),
69 offsetof(struct rk3399_grf_regs, gpio3_p)),
70 PIN_BANK(32, RK_GRF,
71 offsetof(struct rk3399_grf_regs, gpio4a_iomux),
72 offsetof(struct rk3399_grf_regs, gpio4_p)),
73};
74
75static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
76 u32 *shift, u32 *mask)
77{
78 /*
79 * In general we four subsequent 32-bit configuration registers
80 * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
81 * The configuration for each pin has two bits.
82 *
83 * @base...contains the address to the first register.
84 * @index...defines the pin within the bank (0..31).
85 * @addr...will be the address of the actual register to use
86 * @shift...will be the bit position in the configuration register
87 * @mask...will be the (unshifted) mask
88 */
89
90 const u32 pins_per_register = 8;
91 const u32 config_bits_per_pin = 2;
92
93 /* Get the address of the configuration register. */
94 *addr = base + (index / pins_per_register) * sizeof(u32);
95
96 /* Get the bit offset within the configuration register. */
97 *shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
98
99 /* Get the (unshifted) mask for the configuration pins. */
100 *mask = ((1 << config_bits_per_pin) - 1);
101
102 pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
103 __func__, *addr, *mask, *shift);
104}
105
106static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
107 struct rockchip_pin_bank *bank,
108 u32 index, u32 muxval)
109{
110 uintptr_t iomux_base, addr;
111 u32 shift, mask;
112
113 iomux_base = grf_addr + bank->iomux_offset;
114 rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask);
115
116 /* Set pinmux register */
117 rk_clrsetreg(addr, mask << shift, muxval << shift);
118}
119
120static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr,
121 struct rockchip_pin_bank *bank,
122 u32 index, int pinconfig)
123{
124 uintptr_t pupd_base, addr;
125 u32 shift, mask, pupdval;
126
127 /* Fast path in case there's nothing to do. */
128 if (!pinconfig)
129 return;
130
131 if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP))
132 pupdval = RK_GRF_P_PULLUP;
133 else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) {
134 pupdval = RK_GRF_P_PULLDOWN;
135 } else {
136 /* Flag not supported. */
137 pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__,
138 pinconfig);
139 return;
140 }
141
142 pupd_base = grf_addr + (uintptr_t)bank->pupd_offset;
143 rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask);
144
145 /* Set pull-up/pull-down regisrer */
146 rk_clrsetreg(addr, mask << shift, pupdval << shift);
147}
148
149static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index,
150 u32 muxval, int pinconfig)
151{
152 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
153 struct rockchip_pin_bank *bank = &priv->banks[banknum];
154 uintptr_t grf_addr;
155
156 pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval,
157 pinconfig);
158
159 if (bank->grf_location == RK_GRF)
160 grf_addr = (uintptr_t)priv->grf;
161 else if (bank->grf_location == RK_PMUGRF)
162 grf_addr = (uintptr_t)priv->pmugrf;
163 else
164 return -EINVAL;
165
166 rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval);
167
168 rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig);
169 return 0;
170}
171
172static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config)
173{
174 /*
175 * The order of the fields in this struct must match the order of
176 * the fields in the "rockchip,pins" property.
177 */
178 struct rk_pin {
179 u32 banknum;
180 u32 index;
181 u32 muxval;
182 u32 phandle;
183 } __packed;
184
185 u32 *fields = NULL;
186 const int fields_per_pin = 4;
187 int num_fields, num_pins;
188 int ret;
189 int size;
190 int i;
191 struct rk_pin *pin;
192
193 pr_debug("%s: %s\n", __func__, config->name);
194
195 size = dev_read_size(config, "rockchip,pins");
196 if (size < 0)
197 return -EINVAL;
198
199 num_fields = size / sizeof(u32);
200 num_pins = num_fields / fields_per_pin;
201
202 if (num_fields * sizeof(u32) != size ||
203 num_pins * fields_per_pin != num_fields) {
204 pr_warn("Invalid number of rockchip,pins fields.\n");
205 return -EINVAL;
206 }
207
208 fields = calloc(num_fields, sizeof(u32));
209 if (!fields)
210 return -ENOMEM;
211
212 ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields);
213 if (ret) {
214 pr_warn("%s: Failed to read rockchip,pins fields.\n",
215 config->name);
216 goto end;
217 }
218
219 pin = (struct rk_pin *)fields;
220 for (i = 0; i < num_pins; i++, pin++) {
221 struct udevice *dev_pinconfig;
222 int pinconfig;
223
224 ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG,
225 pin->phandle,
226 &dev_pinconfig);
227 if (ret) {
228 pr_debug("Could not get pinconfig device\n");
229 goto end;
230 }
231
232 pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig);
233 if (pinconfig < 0) {
234 pr_warn("Could not parse pinconfig\n");
235 goto end;
236 }
237
238 ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index,
239 pin->muxval, pinconfig);
240 if (ret) {
241 pr_warn("Could not set pinctrl settings\n");
242 goto end;
243 }
244 }
245
246end:
247 free(fields);
248 return ret;
249}
250
251#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
252
22static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, 253static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
23 struct rk3399_pmugrf_regs *pmugrf, int pwm_id) 254 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
24{ 255{
@@ -468,6 +699,9 @@ static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
468} 699}
469 700
470static struct pinctrl_ops rk3399_pinctrl_ops = { 701static struct pinctrl_ops rk3399_pinctrl_ops = {
702#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
703 .set_state = rk3399_pinctrl_set_state,
704#endif
471 .set_state_simple = rk3399_pinctrl_set_state_simple, 705 .set_state_simple = rk3399_pinctrl_set_state_simple,
472 .request = rk3399_pinctrl_request, 706 .request = rk3399_pinctrl_request,
473 .get_periph_id = rk3399_pinctrl_get_periph_id, 707 .get_periph_id = rk3399_pinctrl_get_periph_id,
@@ -481,6 +715,9 @@ static int rk3399_pinctrl_probe(struct udevice *dev)
481 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 715 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
482 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 716 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
483 debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); 717 debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
718#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
719 priv->banks = rk3399_pin_banks;
720#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
484 721
485 return ret; 722 return ret;
486} 723}
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 09b311de8b..3ed0dd2264 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -61,6 +61,13 @@ config REGULATOR_PWM
61 This driver is controlled by a device tree node 61 This driver is controlled by a device tree node
62 which includes voltage limits. 62 which includes voltage limits.
63 63
64config SPL_REGULATOR_PWM
65 bool "Enable Driver for PWM regulators in SPL"
66 depends on REGULATOR_PWM
67 help
68 This config enables implementation of driver-model regulator uclass
69 features for PWM regulators in SPL.
70
64config DM_REGULATOR_MAX77686 71config DM_REGULATOR_MAX77686
65 bool "Enable Driver Model for REGULATOR MAX77686" 72 bool "Enable Driver Model for REGULATOR MAX77686"
66 depends on DM_REGULATOR && DM_PMIC_MAX77686 73 depends on DM_REGULATOR && DM_PMIC_MAX77686
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 8017045d54..f617ce723a 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
9obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o 9obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
10obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o 10obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
11obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o 11obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
12obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o 12obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o
13obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o 13obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o
14obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o 14obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
15obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o 15obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 4511625ff2..39e46279d5 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -113,7 +113,7 @@ int regulator_set_enable(struct udevice *dev, bool enable)
113 113
114 uc_pdata = dev_get_uclass_platdata(dev); 114 uc_pdata = dev_get_uclass_platdata(dev);
115 if (!enable && uc_pdata->always_on) 115 if (!enable && uc_pdata->always_on)
116 return -EACCES; 116 return 0;
117 117
118 return ops->set_enable(dev, enable); 118 return ops->set_enable(dev, enable);
119} 119}
diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c
index 4968900211..df7b988703 100644
--- a/drivers/ram/rockchip/sdram_rk3128.c
+++ b/drivers/ram/rockchip/sdram_rk3128.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/* 2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 */ 4 */
diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c
index 3774abfa98..fdd500aa47 100644
--- a/drivers/ram/rockchip/sdram_rk3188.c
+++ b/drivers/ram/rockchip/sdram_rk3188.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/* 2/*
3 * (C) Copyright 2015 Google, Inc 3 * (C) Copyright 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc. 4 * Copyright 2014 Rockchip Inc.
diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c
index e079ef7a70..53835a9cd0 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/* 2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */ 4 */
diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index bb3cf48788..d1e52d84e7 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/* 2/*
3 * (C) Copyright 2015 Google, Inc 3 * (C) Copyright 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc. 4 * Copyright 2014 Rockchip Inc.
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c
index 89d95b4f89..e8b234d866 100644
--- a/drivers/ram/rockchip/sdram_rk3328.c
+++ b/drivers/ram/rockchip/sdram_rk3328.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/* 2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 */ 4 */
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 49ebd8809f..94dd01156a 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/* 2/*
3 * (C) Copyright 2016-2017 Rockchip Inc. 3 * (C) Copyright 2016-2017 Rockchip Inc.
4 * 4 *
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6252dd8c4b..b7ff2960ab 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -343,6 +343,13 @@ config DEBUG_UART_SANDBOX
343 start up driver model. The driver will be available until the real 343 start up driver model. The driver will be available until the real
344 driver model serial is running. 344 driver model serial is running.
345 345
346config DEBUG_UART_SIFIVE
347 bool "SiFive UART"
348 help
349 Select this to enable a debug UART using the serial_sifive driver. You
350 will need to provide parameters to make this work. The driver will
351 be available until the real driver-model serial is running.
352
346config DEBUG_UART_STM32 353config DEBUG_UART_STM32
347 bool "STMicroelectronics STM32" 354 bool "STMicroelectronics STM32"
348 depends on STM32_SERIAL 355 depends on STM32_SERIAL
@@ -679,6 +686,12 @@ config PXA_SERIAL
679 If you have a machine based on a Marvell XScale PXA2xx CPU you 686 If you have a machine based on a Marvell XScale PXA2xx CPU you
680 can enable its onboard serial ports by enabling this option. 687 can enable its onboard serial ports by enabling this option.
681 688
689config SIFIVE_SERIAL
690 bool "SiFive UART support"
691 depends on DM_SERIAL
692 help
693 This driver supports the SiFive UART. If unsure say N.
694
682config STI_ASC_SERIAL 695config STI_ASC_SERIAL
683 bool "STMicroelectronics on-chip UART" 696 bool "STMicroelectronics on-chip UART"
684 depends on DM_SERIAL && ARCH_STI 697 depends on DM_SERIAL && ARCH_STI
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 2f8d065a4c..06ee30697d 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
67obj-$(CONFIG_OWL_SERIAL) += serial_owl.o 67obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
68obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o 68obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
69obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o 69obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
70obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
70 71
71ifndef CONFIG_SPL_BUILD 72ifndef CONFIG_SPL_BUILD
72obj-$(CONFIG_USB_TTY) += usbtty.o 73obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
new file mode 100644
index 0000000000..341728a690
--- /dev/null
+++ b/drivers/serial/serial_sifive.c
@@ -0,0 +1,215 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Anup Patel <anup@brainfault.org>
4 */
5
6#include <clk.h>
7#include <common.h>
8#include <debug_uart.h>
9#include <dm.h>
10#include <errno.h>
11#include <fdtdec.h>
12#include <watchdog.h>
13#include <asm/io.h>
14#include <linux/compiler.h>
15#include <serial.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19#define UART_TXFIFO_FULL 0x80000000
20#define UART_RXFIFO_EMPTY 0x80000000
21#define UART_RXFIFO_DATA 0x000000ff
22#define UART_TXCTRL_TXEN 0x1
23#define UART_RXCTRL_RXEN 0x1
24
25struct uart_sifive {
26 u32 txfifo;
27 u32 rxfifo;
28 u32 txctrl;
29 u32 rxctrl;
30 u32 ie;
31 u32 ip;
32 u32 div;
33};
34
35struct sifive_uart_platdata {
36 unsigned int clock;
37 int saved_input_char;
38 struct uart_sifive *regs;
39};
40
41/* Set up the baud rate in gd struct */
42static void _sifive_serial_setbrg(struct uart_sifive *regs,
43 unsigned long clock, unsigned long baud)
44{
45 writel((u32)((clock / baud) - 1), &regs->div);
46}
47
48static void _sifive_serial_init(struct uart_sifive *regs)
49{
50 writel(UART_TXCTRL_TXEN, &regs->txctrl);
51 writel(UART_RXCTRL_RXEN, &regs->rxctrl);
52 writel(0, &regs->ie);
53}
54
55static int _sifive_serial_putc(struct uart_sifive *regs, const char c)
56{
57 if (readl(&regs->txfifo) & UART_TXFIFO_FULL)
58 return -EAGAIN;
59
60 writel(c, &regs->txfifo);
61
62 return 0;
63}
64
65static int _sifive_serial_getc(struct uart_sifive *regs)
66{
67 int ch = readl(&regs->rxfifo);
68
69 if (ch & UART_RXFIFO_EMPTY)
70 return -EAGAIN;
71 ch &= UART_RXFIFO_DATA;
72
73 return (!ch) ? -EAGAIN : ch;
74}
75
76static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
77{
78 int err;
79 struct clk clk;
80 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
81
82 err = clk_get_by_index(dev, 0, &clk);
83 if (!err) {
84 err = clk_get_rate(&clk);
85 if (!IS_ERR_VALUE(err))
86 platdata->clock = err;
87 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
88 debug("SiFive UART failed to get clock\n");
89 return err;
90 }
91
92 if (!platdata->clock)
93 platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0);
94 if (!platdata->clock) {
95 debug("SiFive UART clock not defined\n");
96 return -EINVAL;
97 }
98
99 _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
100
101 return 0;
102}
103
104static int sifive_serial_probe(struct udevice *dev)
105{
106 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
107
108 /* No need to reinitialize the UART after relocation */
109 if (gd->flags & GD_FLG_RELOC)
110 return 0;
111
112 platdata->saved_input_char = 0;
113 _sifive_serial_init(platdata->regs);
114
115 return 0;
116}
117
118static int sifive_serial_getc(struct udevice *dev)
119{
120 int c;
121 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
122 struct uart_sifive *regs = platdata->regs;
123
124 if (platdata->saved_input_char > 0) {
125 c = platdata->saved_input_char;
126 platdata->saved_input_char = 0;
127 return c;
128 }
129
130 while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
131
132 return c;
133}
134
135static int sifive_serial_putc(struct udevice *dev, const char ch)
136{
137 int rc;
138 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
139
140 while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ;
141
142 return rc;
143}
144
145static int sifive_serial_pending(struct udevice *dev, bool input)
146{
147 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
148 struct uart_sifive *regs = platdata->regs;
149
150 if (input) {
151 if (platdata->saved_input_char > 0)
152 return 1;
153 platdata->saved_input_char = _sifive_serial_getc(regs);
154 return (platdata->saved_input_char > 0) ? 1 : 0;
155 } else {
156 return !!(readl(&regs->txfifo) & UART_TXFIFO_FULL);
157 }
158}
159
160static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
161{
162 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
163
164 platdata->regs = (struct uart_sifive *)dev_read_addr(dev);
165 if (IS_ERR(platdata->regs))
166 return PTR_ERR(platdata->regs);
167
168 return 0;
169}
170
171static const struct dm_serial_ops sifive_serial_ops = {
172 .putc = sifive_serial_putc,
173 .getc = sifive_serial_getc,
174 .pending = sifive_serial_pending,
175 .setbrg = sifive_serial_setbrg,
176};
177
178static const struct udevice_id sifive_serial_ids[] = {
179 { .compatible = "sifive,uart0" },
180 { }
181};
182
183U_BOOT_DRIVER(serial_sifive) = {
184 .name = "serial_sifive",
185 .id = UCLASS_SERIAL,
186 .of_match = sifive_serial_ids,
187 .ofdata_to_platdata = sifive_serial_ofdata_to_platdata,
188 .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata),
189 .probe = sifive_serial_probe,
190 .ops = &sifive_serial_ops,
191};
192
193#ifdef CONFIG_DEBUG_UART_SIFIVE
194static inline void _debug_uart_init(void)
195{
196 struct uart_sifive *regs =
197 (struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
198
199 _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
200 CONFIG_BAUDRATE);
201 _sifive_serial_init(regs);
202}
203
204static inline void _debug_uart_putc(int ch)
205{
206 struct uart_sifive *regs =
207 (struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
208
209 while (_sifive_serial_putc(regs, ch) == -EAGAIN)
210 WATCHDOG_RESET();
211}
212
213DEBUG_UART_FUNCS
214
215#endif
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 5cca414486..02d93763d4 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -369,7 +369,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
369 return 0; 369 return 0;
370} 370}
371 371
372static void external_cs_manage(struct udevice *dev, bool on) 372/*
373 * We define external_cs_manage function as 'weak' as some targets
374 * (like MSCC Ocelot) don't control the external CS pin using a GPIO
375 * controller. These SoCs use specific registers to control by
376 * software the SPI pins (and especially the CS).
377 */
378__weak void external_cs_manage(struct udevice *dev, bool on)
373{ 379{
374#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 380#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
375 struct dw_spi_priv *priv = dev_get_priv(dev->parent); 381 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5a00ad..38cc743c61 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
129 129
130 while (len--) { 130 while (len--) {
131 byte = readb(&priv->regs->rxdata); 131 byte = readb(&priv->regs->rxdata);
132 *priv->rx_buf++ = byte; 132 if (priv->rx_buf)
133 *priv->rx_buf++ = byte;
133 } 134 }
134} 135}
135 136
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index b0e6f32f0b..df37a798bd 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -126,6 +126,13 @@ config OMAP_TIMER
126 help 126 help
127 Select this to enable an timer for Omap devices. 127 Select this to enable an timer for Omap devices.
128 128
129config RISCV_TIMER
130 bool "RISC-V timer support"
131 depends on TIMER && RISCV
132 help
133 Select this to enable support for the timer as defined
134 by the RISC-V privileged architecture spec.
135
129config ROCKCHIP_TIMER 136config ROCKCHIP_TIMER
130 bool "Rockchip timer support" 137 bool "Rockchip timer support"
131 depends on TIMER 138 depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index c4fbab2aac..d0bf218b11 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
13obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o 13obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
14obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o 14obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
15obj-$(CONFIG_OMAP_TIMER) += omap-timer.o 15obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
16obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
16obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o 17obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
17obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o 18obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
18obj-$(CONFIG_STI_TIMER) += sti-timer.o 19obj-$(CONFIG_STI_TIMER) += sti-timer.o
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
new file mode 100644
index 0000000000..9f9f070e0b
--- /dev/null
+++ b/drivers/timer/riscv_timer.c
@@ -0,0 +1,56 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * RISC-V privileged architecture defined generic timer driver
6 *
7 * This driver relies on RISC-V platform codes to provide the essential API
8 * riscv_get_time() which is supposed to return the timer counter as defined
9 * by the RISC-V privileged architecture spec.
10 *
11 * This driver can be used in both M-mode and S-mode U-Boot.
12 */
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <timer.h>
18#include <asm/io.h>
19
20/**
21 * riscv_get_time() - get the timer counter
22 *
23 * Platform codes should provide this API in order to make this driver function.
24 *
25 * @time: the 64-bit timer count as defined by the RISC-V privileged
26 * architecture spec.
27 * @return: 0 on success, -ve on error.
28 */
29extern int riscv_get_time(u64 *time);
30
31static int riscv_timer_get_count(struct udevice *dev, u64 *count)
32{
33 return riscv_get_time(count);
34}
35
36static int riscv_timer_probe(struct udevice *dev)
37{
38 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
39
40 /* clock frequency was passed from the cpu driver as driver data */
41 uc_priv->clock_rate = dev->driver_data;
42
43 return 0;
44}
45
46static const struct timer_ops riscv_timer_ops = {
47 .get_count = riscv_timer_get_count,
48};
49
50U_BOOT_DRIVER(riscv_timer) = {
51 .name = "riscv_timer",
52 .id = UCLASS_TIMER,
53 .probe = riscv_timer_probe,
54 .ops = &riscv_timer_ops,
55 .flags = DM_FLAG_PRE_RELOC,
56};
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index b74c1fdce9..01e2b3abf2 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o
7obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o 7obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
8 8
9ifdef CONFIG_SPL_BUILD 9ifdef CONFIG_SPL_BUILD
10obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += g_dnl.o 10obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o
11obj-$(CONFIG_SPL_DFU_SUPPORT) += f_dfu.o 11obj-$(CONFIG_SPL_DFU_SUPPORT) += f_dfu.o
12obj-$(CONFIG_SPL_USB_SDP_SUPPORT) += f_sdp.o 12obj-$(CONFIG_SPL_USB_SDP_SUPPORT) += f_sdp.o
13endif 13endif
diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile
index 38ac2dd475..95dbf0c82e 100644
--- a/drivers/usb/gadget/udc/Makefile
+++ b/drivers/usb/gadget/udc/Makefile
@@ -6,4 +6,5 @@ ifndef CONFIG_$(SPL_)DM_USB_GADGET
6obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o 6obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o
7endif 7endif
8 8
9obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-uclass.o udc-core.o 9obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-core.o
10obj-$(CONFIG_$(SPL_)DM) += udc-uclass.o
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index 062051857a..8d7864797a 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -9,6 +9,7 @@
9#include <dm/device-internal.h> 9#include <dm/device-internal.h>
10#include <linux/usb/gadget.h> 10#include <linux/usb/gadget.h>
11 11
12#if CONFIG_IS_ENABLED(DM_USB_GADGET)
12#define MAX_UDC_DEVICES 4 13#define MAX_UDC_DEVICES 4
13static struct udevice *dev_array[MAX_UDC_DEVICES]; 14static struct udevice *dev_array[MAX_UDC_DEVICES];
14int usb_gadget_initialize(int index) 15int usb_gadget_initialize(int index)
@@ -20,7 +21,7 @@ int usb_gadget_initialize(int index)
20 return -EINVAL; 21 return -EINVAL;
21 if (dev_array[index]) 22 if (dev_array[index])
22 return 0; 23 return 0;
23 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, index, &dev); 24 ret = uclass_get_device_by_seq(UCLASS_USB_GADGET_GENERIC, index, &dev);
24 if (!dev || ret) { 25 if (!dev || ret) {
25 pr_err("No USB device found\n"); 26 pr_err("No USB device found\n");
26 return -ENODEV; 27 return -ENODEV;
@@ -51,8 +52,10 @@ int usb_gadget_handle_interrupts(int index)
51 return -EINVAL; 52 return -EINVAL;
52 return dm_usb_gadget_handle_interrupts(dev_array[index]); 53 return dm_usb_gadget_handle_interrupts(dev_array[index]);
53} 54}
55#endif
54 56
55UCLASS_DRIVER(usb_gadget_generic) = { 57UCLASS_DRIVER(usb_gadget_generic) = {
56 .id = UCLASS_USB_GADGET_GENERIC, 58 .id = UCLASS_USB_GADGET_GENERIC,
57 .name = "usb_gadget_generic", 59 .name = "usb",
60 .flags = DM_UC_FLAG_SEQ_ALIAS,
58}; 61};
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 04ab540695..84c2c3344a 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -369,6 +369,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
369 ctrl->dcbaa->dev_context_ptrs[0] = 369 ctrl->dcbaa->dev_context_ptrs[0] =
370 cpu_to_le64((uintptr_t)scratchpad->sp_array); 370 cpu_to_le64((uintptr_t)scratchpad->sp_array);
371 371
372 xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[0],
373 sizeof(ctrl->dcbaa->dev_context_ptrs[0]));
374
372 page_size = xhci_readl(&hcor->or_pagesize) & 0xffff; 375 page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
373 for (i = 0; i < 16; i++) { 376 for (i = 0; i < 16; i++) {
374 if ((0x1 & page_size) != 0) 377 if ((0x1 & page_size) != 0)
diff --git a/drivers/video/fonts/Kconfig b/drivers/video/fonts/Kconfig
index 3f1398db50..c692fa9602 100644
--- a/drivers/video/fonts/Kconfig
+++ b/drivers/video/fonts/Kconfig
@@ -7,6 +7,7 @@ menu "TrueType Fonts"
7config CONSOLE_TRUETYPE_NIMBUS 7config CONSOLE_TRUETYPE_NIMBUS
8 bool "Nimbus Sans Regular" 8 bool "Nimbus Sans Regular"
9 depends on CONSOLE_TRUETYPE 9 depends on CONSOLE_TRUETYPE
10 default y
10 help 11 help
11 Nimbus Sans L is a version of Nimbus Sans using Adobe font sources. 12 Nimbus Sans L is a version of Nimbus Sans using Adobe font sources.
12 It was designed in 1987. A subset of Nimbus Sans L were released 13 It was designed in 1987. A subset of Nimbus Sans L were released
diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig
index d6e045739d..031bab25ae 100644
--- a/drivers/w1/Kconfig
+++ b/drivers/w1/Kconfig
@@ -20,6 +20,20 @@ config W1_GPIO
20 help 20 help
21 Emulate a 1-wire bus using a GPIO. 21 Emulate a 1-wire bus using a GPIO.
22 22
23config W1_MXC
24 bool "Enable 1-wire controller on i.MX processors"
25 default no
26 depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5
27 help
28 Support the one wire controller found in some members of the NXP
29 i.MX SoC family.
30 There are currently two silicon variants:
31 V1: i.MX21, i.MX27, i.MX31, i.MX51
32 V2: i.MX25, i.MX35, i.MX50, i.MX53
33 Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
34
35 The driver supports both silicon variants.
36
23endif 37endif
24 38
25endmenu 39endmenu
diff --git a/drivers/w1/Makefile b/drivers/w1/Makefile
index 7fd8697f84..9825187b65 100644
--- a/drivers/w1/Makefile
+++ b/drivers/w1/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_W1) += w1-uclass.o 1obj-$(CONFIG_W1) += w1-uclass.o
2 2
3obj-$(CONFIG_W1_GPIO) += w1-gpio.o 3obj-$(CONFIG_W1_GPIO) += w1-gpio.o
4obj-$(CONFIG_W1_MXC) += mxc_w1.o
diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c
new file mode 100644
index 0000000000..9279ba32b8
--- /dev/null
+++ b/drivers/w1/mxc_w1.c
@@ -0,0 +1,232 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for one wire controller in some i.MX Socs
4 *
5 * There are currently two silicon variants:
6 * V1: i.MX21, i.MX27, i.MX31, i.MX51
7 * V2: i.MX25, i.MX35, i.MX50, i.MX53
8 * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
9 *
10 * The V1 controller only supports single bit operations.
11 * The V2 controller is backwards compatible on the register level but adds
12 * byte size operations and a "search ROM accelerator mode"
13 *
14 * This driver does not currently support the search ROM accelerator
15 *
16 * Copyright (c) 2018 Flowbird
17 * Martin Fuzzey <martin.fuzzey@flowbird.group>
18 */
19
20#include <asm/arch/clock.h>
21#include <common.h>
22#include <dm.h>
23#include <linux/io.h>
24#include <w1.h>
25
26struct mxc_w1_regs {
27 u16 control;
28#define MXC_W1_CONTROL_RPP BIT(7)
29#define MXC_W1_CONTROL_PST BIT(6)
30#define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
31#define MXC_W1_CONTROL_RDST BIT(3)
32
33 u16 time_divider;
34 u16 reset;
35
36 /* Registers below on V2 silicon only */
37 u16 command;
38 u16 tx_rx;
39 u16 interrupt;
40#define MXC_W1_INTERRUPT_TBE BIT(2)
41#define MXC_W1_INTERRUPT_TSRE BIT(3)
42#define MXC_W1_INTERRUPT_RBF BIT(4)
43#define MXC_W1_INTERRUPT_RSRF BIT(5)
44
45 u16 interrupt_en;
46};
47
48struct mxc_w1_pdata {
49 struct mxc_w1_regs *regs;
50};
51
52/*
53 * this is the low level routine to read/write a bit on the One Wire
54 * interface on the hardware. It does write 0 if parameter bit is set
55 * to 0, otherwise a write 1/read.
56 */
57static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
58{
59 u16 *ctrl_addr = &pdata->regs->control;
60 u16 mask = MXC_W1_CONTROL_WR(bit);
61 unsigned int timeout_cnt = 400; /* Takes max. 120us according to
62 * datasheet.
63 */
64
65 writew(mask, ctrl_addr);
66
67 while (timeout_cnt--) {
68 if (!(readw(ctrl_addr) & mask))
69 break;
70
71 udelay(1);
72 }
73
74 return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
75}
76
77static u8 mxc_w1_read_byte(struct udevice *dev)
78{
79 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
80 struct mxc_w1_regs *regs = pdata->regs;
81 u16 status;
82
83 if (dev_get_driver_data(dev) < 2) {
84 int i;
85 u8 ret = 0;
86
87 for (i = 0; i < 8; i++)
88 ret |= (mxc_w1_touch_bit(pdata, 1) << i);
89
90 return ret;
91 }
92
93 readw(&regs->tx_rx);
94 writew(0xFF, &regs->tx_rx);
95
96 do {
97 udelay(1); /* Without this bytes are sometimes duplicated... */
98 status = readw(&regs->interrupt);
99 } while (!(status & MXC_W1_INTERRUPT_RBF));
100
101 return (u8)readw(&regs->tx_rx);
102}
103
104static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
105{
106 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
107 struct mxc_w1_regs *regs = pdata->regs;
108 u16 status;
109
110 if (dev_get_driver_data(dev) < 2) {
111 int i;
112
113 for (i = 0; i < 8; i++)
114 mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
115
116 return;
117 }
118
119 readw(&regs->tx_rx);
120 writew(byte, &regs->tx_rx);
121
122 do {
123 udelay(1);
124 status = readw(&regs->interrupt);
125 } while (!(status & MXC_W1_INTERRUPT_TSRE));
126}
127
128static bool mxc_w1_reset(struct udevice *dev)
129{
130 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
131 u16 reg_val;
132
133 writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
134
135 do {
136 reg_val = readw(&pdata->regs->control);
137 } while (reg_val & MXC_W1_CONTROL_RPP);
138
139 return !(reg_val & MXC_W1_CONTROL_PST);
140}
141
142static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
143{
144 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
145 u8 id_bit = mxc_w1_touch_bit(pdata, 1);
146 u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
147 u8 retval;
148
149 if (id_bit && comp_bit)
150 return 0x03; /* error */
151
152 if (!id_bit && !comp_bit) {
153 /* Both bits are valid, take the direction given */
154 retval = bdir ? 0x04 : 0;
155 } else {
156 /* Only one bit is valid, take that direction */
157 bdir = id_bit;
158 retval = id_bit ? 0x05 : 0x02;
159 }
160
161 mxc_w1_touch_bit(pdata, bdir);
162
163 return retval;
164}
165
166static int mxc_w1_ofdata_to_platdata(struct udevice *dev)
167{
168 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
169 fdt_addr_t addr;
170
171 addr = devfdt_get_addr(dev);
172 if (addr == FDT_ADDR_T_NONE)
173 return -EINVAL;
174
175 pdata->regs = (struct mxc_w1_regs *)addr;
176
177 return 0;
178};
179
180static int mxc_w1_probe(struct udevice *dev)
181{
182 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
183 unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
184 unsigned int clkdiv;
185
186 if (clkrate < 10000000) {
187 dev_err(dev, "input clock frequency (%u Hz) too low\n",
188 clkrate);
189 return -EINVAL;
190 }
191
192 clkdiv = clkrate / 1000000;
193 clkrate /= clkdiv;
194 if (clkrate < 980000 || clkrate > 1020000) {
195 dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
196 return -EINVAL;
197 }
198
199 writew(clkdiv - 1, &pdata->regs->time_divider);
200
201 return 0;
202}
203
204static const struct w1_ops mxc_w1_ops = {
205 .read_byte = mxc_w1_read_byte,
206 .reset = mxc_w1_reset,
207 .triplet = mxc_w1_triplet,
208 .write_byte = mxc_w1_write_byte,
209};
210
211static const struct udevice_id mxc_w1_id[] = {
212 { .compatible = "fsl,imx21-owire", .data = 1 },
213 { .compatible = "fsl,imx27-owire", .data = 1 },
214 { .compatible = "fsl,imx31-owire", .data = 1 },
215 { .compatible = "fsl,imx51-owire", .data = 1 },
216
217 { .compatible = "fsl,imx25-owire", .data = 2 },
218 { .compatible = "fsl,imx35-owire", .data = 2 },
219 { .compatible = "fsl,imx50-owire", .data = 2 },
220 { .compatible = "fsl,imx53-owire", .data = 2 },
221 { },
222};
223
224U_BOOT_DRIVER(mxc_w1_drv) = {
225 .id = UCLASS_W1,
226 .name = "mxc_w1_drv",
227 .of_match = mxc_w1_id,
228 .ofdata_to_platdata = mxc_w1_ofdata_to_platdata,
229 .ops = &mxc_w1_ops,
230 .platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata),
231 .probe = mxc_w1_probe,
232};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b6974ad619..10fd3039aa 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -11,6 +11,12 @@ config WATCHDOG
11config HW_WATCHDOG 11config HW_WATCHDOG
12 bool 12 bool
13 13
14config WATCHDOG_RESET_DISABLE
15 bool "Disable reset watchdog"
16 help
17 Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
18 that the watchdog will not be fed in u-boot.
19
14config BCM2835_WDT 20config BCM2835_WDT
15 bool "Enable BCM2835/2836 watchdog driver" 21 bool "Enable BCM2835/2836 watchdog driver"
16 select HW_WATCHDOG 22 select HW_WATCHDOG
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 74738eeaf7..d901240ad1 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o
7obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o 7obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
8ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) 8ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610))
9obj-y += imx_watchdog.o 9obj-y += imx_watchdog.o
10else
11obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o
10endif 12endif
11obj-$(CONFIG_S5P) += s5p_wdt.o 13obj-$(CONFIG_S5P) += s5p_wdt.o
12obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o 14obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 3f826d10eb..14cc618074 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -8,15 +8,20 @@
8#include <asm/io.h> 8#include <asm/io.h>
9#include <watchdog.h> 9#include <watchdog.h>
10#include <asm/arch/imx-regs.h> 10#include <asm/arch/imx-regs.h>
11#ifdef CONFIG_FSL_LSCH2
12#include <asm/arch/immap_lsch2.h>
13#endif
11#include <fsl_wdog.h> 14#include <fsl_wdog.h>
12 15
13#ifdef CONFIG_IMX_WATCHDOG 16#ifdef CONFIG_IMX_WATCHDOG
14void hw_watchdog_reset(void) 17void hw_watchdog_reset(void)
15{ 18{
19#ifndef CONFIG_WATCHDOG_RESET_DISABLE
16 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 20 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
17 21
18 writew(0x5555, &wdog->wsr); 22 writew(0x5555, &wdog->wsr);
19 writew(0xaaaa, &wdog->wsr); 23 writew(0xaaaa, &wdog->wsr);
24#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
20} 25}
21 26
22void hw_watchdog_init(void) 27void hw_watchdog_init(void)
@@ -33,8 +38,12 @@ void hw_watchdog_init(void)
33#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 38#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
34#endif 39#endif
35 timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; 40 timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
41#ifdef CONFIG_FSL_LSCH2
42 writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr);
43#else
36 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | 44 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
37 WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); 45 WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
46#endif /* CONFIG_FSL_LSCH2*/
38 hw_watchdog_reset(); 47 hw_watchdog_reset();
39} 48}
40#endif 49#endif
diff --git a/env/env.c b/env/env.c
index afed0f3c95..003509d342 100644
--- a/env/env.c
+++ b/env/env.c
@@ -71,6 +71,9 @@ static enum env_location env_locations[] = {
71#ifdef CONFIG_ENV_IS_IN_REMOTE 71#ifdef CONFIG_ENV_IS_IN_REMOTE
72 ENVL_REMOTE, 72 ENVL_REMOTE,
73#endif 73#endif
74#ifdef CONFIG_ENV_IS_IN_SATA
75 ENVL_ESATA,
76#endif
74#ifdef CONFIG_ENV_IS_IN_SPI_FLASH 77#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
75 ENVL_SPI_FLASH, 78 ENVL_SPI_FLASH,
76#endif 79#endif
diff --git a/env/sata.c b/env/sata.c
index 59aedf4d76..a2ff5c66f7 100644
--- a/env/sata.c
+++ b/env/sata.c
@@ -65,7 +65,7 @@ static int env_sata_save(void)
65 return 1; 65 return 1;
66 66
67 printf("Writing to SATA(%d)...", env_sata); 67 printf("Writing to SATA(%d)...", env_sata);
68 if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, &env_new)) { 68 if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, (u_char *)env_new)) {
69 puts("failed\n"); 69 puts("failed\n");
70 return 1; 70 return 1;
71 } 71 }
diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
index 0dce639b49..7b2513cb24 100644
--- a/fs/cbfs/cbfs.c
+++ b/fs/cbfs/cbfs.c
@@ -96,8 +96,7 @@ static int file_cbfs_next_file(u8 *start, u32 size, u32 align,
96 } 96 }
97 97
98 swap_file_header(&header, fileHeader); 98 swap_file_header(&header, fileHeader);
99 if (header.offset < sizeof(struct cbfs_fileheader) || 99 if (header.offset < sizeof(struct cbfs_fileheader)) {
100 header.offset > header.len) {
101 file_cbfs_result = CBFS_BAD_FILE; 100 file_cbfs_result = CBFS_BAD_FILE;
102 return -1; 101 return -1;
103 } 102 }
@@ -190,8 +189,8 @@ void file_cbfs_init(uintptr_t end_of_rom)
190 189
191 start_of_rom = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size); 190 start_of_rom = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size);
192 191
193 file_cbfs_fill_cache(start_of_rom + cbfs_header.offset, 192 file_cbfs_fill_cache(start_of_rom, cbfs_header.rom_size,
194 cbfs_header.rom_size, cbfs_header.align); 193 cbfs_header.align);
195 if (file_cbfs_result == CBFS_SUCCESS) 194 if (file_cbfs_result == CBFS_SUCCESS)
196 initialized = 1; 195 initialized = 1;
197} 196}
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index ac8913e719..179bf4f3d8 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -736,10 +736,7 @@ static void *next_cluster(fat_itr *itr)
736 if (itr->last_cluster) 736 if (itr->last_cluster)
737 return NULL; 737 return NULL;
738 738
739 if (itr->fsdata->fatsize != 32 && itr->is_root) 739 sect = clust_to_sect(itr->fsdata, itr->next_clust);
740 sect = mydata->rootdir_sect;
741 else
742 sect = clust_to_sect(itr->fsdata, itr->next_clust);
743 740
744 debug("FAT read(sect=%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n", 741 debug("FAT read(sect=%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",
745 sect, itr->fsdata->clust_size, DIRENTSPERBLOCK); 742 sect, itr->fsdata->clust_size, DIRENTSPERBLOCK);
diff --git a/include/altera.h b/include/altera.h
index ead5d3d810..22d55cfd73 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -39,6 +39,8 @@ enum altera_iface {
39 fast_passive_parallel, 39 fast_passive_parallel,
40 /* fast passive parallel with security (FPPS) */ 40 /* fast passive parallel with security (FPPS) */
41 fast_passive_parallel_security, 41 fast_passive_parallel_security,
42 /* secure device manager (SDM) mailbox */
43 secure_device_manager_mailbox,
42 /* insert all new types before this */ 44 /* insert all new types before this */
43 max_altera_iface_type, 45 max_altera_iface_type,
44}; 46};
@@ -54,6 +56,8 @@ enum altera_family {
54 Altera_StratixII, 56 Altera_StratixII,
55 /* StratixV Family */ 57 /* StratixV Family */
56 Altera_StratixV, 58 Altera_StratixV,
59 /* Stratix10 Family */
60 Intel_FPGA_Stratix10,
57 /* SoCFPGA Family */ 61 /* SoCFPGA Family */
58 Altera_SoCFPGA, 62 Altera_SoCFPGA,
59 63
@@ -116,4 +120,8 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
116int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); 120int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
117#endif 121#endif
118 122
123#ifdef CONFIG_FPGA_STRATIX10
124int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
125#endif
126
119#endif /* _ALTERA_H_ */ 127#endif /* _ALTERA_H_ */
diff --git a/include/bootm.h b/include/bootm.h
index 0501414e0d..dbd6f49c2d 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -35,6 +35,8 @@ typedef int boot_os_fn(int flag, int argc, char * const argv[],
35 bootm_headers_t *images); 35 bootm_headers_t *images);
36 36
37extern boot_os_fn do_bootm_linux; 37extern boot_os_fn do_bootm_linux;
38extern boot_os_fn do_bootm_vxworks;
39
38int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); 40int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
39void lynxkdi_boot(image_header_t *hdr); 41void lynxkdi_boot(image_header_t *hdr);
40 42
diff --git a/include/cbfs.h b/include/cbfs.h
index 1b88ec04ae..bd1bf75bbf 100644
--- a/include/cbfs.h
+++ b/include/cbfs.h
@@ -18,16 +18,26 @@ enum cbfs_result {
18}; 18};
19 19
20enum cbfs_filetype { 20enum cbfs_filetype {
21 CBFS_TYPE_BOOTBLOCK = 0x01,
22 CBFS_TYPE_CBFSHEADER = 0x02,
21 CBFS_TYPE_STAGE = 0x10, 23 CBFS_TYPE_STAGE = 0x10,
22 CBFS_TYPE_PAYLOAD = 0x20, 24 CBFS_TYPE_PAYLOAD = 0x20,
25 CBFS_TYPE_FIT = 0x21,
23 CBFS_TYPE_OPTIONROM = 0x30, 26 CBFS_TYPE_OPTIONROM = 0x30,
24 CBFS_TYPE_BOOTSPLASH = 0x40, 27 CBFS_TYPE_BOOTSPLASH = 0x40,
25 CBFS_TYPE_RAW = 0x50, 28 CBFS_TYPE_RAW = 0x50,
26 CBFS_TYPE_VSA = 0x51, 29 CBFS_TYPE_VSA = 0x51,
27 CBFS_TYPE_MBI = 0x52, 30 CBFS_TYPE_MBI = 0x52,
28 CBFS_TYPE_MICROCODE = 0x53, 31 CBFS_TYPE_MICROCODE = 0x53,
29 CBFS_COMPONENT_CMOS_DEFAULT = 0xaa, 32 CBFS_TYPE_FSP = 0x60,
30 CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa 33 CBFS_TYPE_MRC = 0x61,
34 CBFS_TYPE_MMA = 0x62,
35 CBFS_TYPE_EFI = 0x63,
36 CBFS_TYPE_STRUCT = 0x70,
37 CBFS_TYPE_CMOS_DEFAULT = 0xaa,
38 CBFS_TYPE_SPD = 0xab,
39 CBFS_TYPE_MRC_CACHE = 0xac,
40 CBFS_TYPE_CMOS_LAYOUT = 0x01aa
31}; 41};
32 42
33struct cbfs_header { 43struct cbfs_header {
diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
index 39ca2e0bf3..788f4af70d 100644
--- a/include/configs/bmips_common.h
+++ b/include/configs/bmips_common.h
@@ -6,6 +6,10 @@
6#ifndef __CONFIG_BMIPS_COMMON_H 6#ifndef __CONFIG_BMIPS_COMMON_H
7#define __CONFIG_BMIPS_COMMON_H 7#define __CONFIG_BMIPS_COMMON_H
8 8
9/* ETH */
10#define CONFIG_PHY_RESET_DELAY 20
11#define CONFIG_SYS_RX_ETH_BUFFER 6
12
9/* UART */ 13/* UART */
10#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 14#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
11 230400, 500000, 1500000 } 15 230400, 500000, 1500000 }
@@ -16,7 +20,7 @@
16 20
17/* Memory usage */ 21/* Memory usage */
18#define CONFIG_SYS_MAXARGS 24 22#define CONFIG_SYS_MAXARGS 24
19#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 23#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
20#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) 24#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
21#define CONFIG_SYS_CBSIZE 512 25#define CONFIG_SYS_CBSIZE 512
22 26
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
new file mode 100644
index 0000000000..9a3621329d
--- /dev/null
+++ b/include/configs/ci20.h
@@ -0,0 +1,72 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * CI20 configuration
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#ifndef __CONFIG_CI20_H__
10#define __CONFIG_CI20_H__
11
12#define CONFIG_SKIP_LOWLEVEL_INIT
13
14/* Ingenic JZ4780 clock configuration. */
15#define CONFIG_SYS_HZ 1000
16#define CONFIG_SYS_MHZ 1200
17#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
18
19/* Memory configuration */
20#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
21#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
22#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
23
24#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
25#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
26#define CONFIG_SYS_LOAD_ADDR 0x81000000
27#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
28#define CONFIG_SYS_MEMTEST_START 0x80000000
29#define CONFIG_SYS_MEMTEST_END 0x88000000
30
31#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
32
33/* NS16550-ish UARTs */
34#define CONFIG_SYS_NS16550_CLK 48000000
35#define CONFIG_SYS_CONSOLE_IS_IN_ENV
36
37/* Ethernet: davicom DM9000 */
38#define CONFIG_DRIVER_DM9000 1
39#define CONFIG_DM9000_BASE 0xb6000000
40#define DM9000_IO CONFIG_DM9000_BASE
41#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
42
43/* Environment */
44#define CONFIG_SYS_MMC_ENV_DEV 0
45#define CONFIG_ENV_SIZE (32 << 10)
46#define CONFIG_ENV_OFFSET ((14 + 512) << 10)
47#define CONFIG_ENV_OVERWRITE
48
49/* Command line configuration. */
50#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
51#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
52#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
53 /* Boot argument buffer size */
54#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
55
56/* Miscellaneous configuration options */
57#define CONFIG_SYS_BOOTM_LEN (64 << 20)
58
59/* SPL */
60#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
61
62#define CONFIG_SPL_TEXT_BASE 0xf4000a00
63#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
64
65#define CONFIG_SPL_BSS_START_ADDR 0xf4004000
66#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
67
68#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
69
70#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
71
72#endif /* __CONFIG_CI20_H__ */
diff --git a/include/configs/edison.h b/include/configs/edison.h
index 86c584d73d..a6155ba5a8 100644
--- a/include/configs/edison.h
+++ b/include/configs/edison.h
@@ -8,13 +8,6 @@
8 8
9#include <asm/ibmpc.h> 9#include <asm/ibmpc.h>
10 10
11/* ACPI */
12
13/* Boot */
14#define CONFIG_BOOTCOMMAND "run bootcmd"
15
16/* DISK Partition support */
17
18/* Miscellaneous configurable options */ 11/* Miscellaneous configurable options */
19 12
20#define CONFIG_SYS_CBSIZE 2048 13#define CONFIG_SYS_CBSIZE 2048
@@ -43,9 +36,6 @@
43#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) 36#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024)
44#define CONFIG_SUPPORT_EMMC_BOOT 37#define CONFIG_SUPPORT_EMMC_BOOT
45 38
46/* PCI */
47#define CONFIG_CMD_PCI
48
49/* RTC */ 39/* RTC */
50#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 40#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
51 41
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 71217f07e2..7e7de4dae6 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -109,6 +109,19 @@
109 109
110#include "mx6_common.h" 110#include "mx6_common.h"
111 111
112#ifdef CONFIG_SPL
113#include "imx6_spl.h"
114/* RiOTboard */
115#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
116#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
117#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb"
118
119#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */
120#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */
121#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */
122
123#endif
124
112/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, 125/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
113 * 1M script, 1M pxe and the ramdisk at the end */ 126 * 1M script, 1M pxe and the ramdisk at the end */
114#define MEM_LAYOUT_ENV_SETTINGS \ 127#define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index 3157225f06..4e98f19a40 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -118,7 +118,7 @@
118#define CONFIG_SPL_SPI_FLASH_SUPPORT 118#define CONFIG_SPL_SPI_FLASH_SUPPORT
119#define CONFIG_SPL_SPI_LOAD 119#define CONFIG_SPL_SPI_LOAD
120#define CONFIG_SPL_SPI_SUPPORT 120#define CONFIG_SPL_SPI_SUPPORT
121#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 121#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
122#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 122#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
123#endif 123#endif
124 124
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
new file mode 100644
index 0000000000..f0430224cb
--- /dev/null
+++ b/include/configs/imx8mq_evk.h
@@ -0,0 +1,246 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __IMX8M_EVK_H
7#define __IMX8M_EVK_H
8
9#include <linux/sizes.h>
10#include <asm/arch/imx-regs.h>
11
12#ifdef CONFIG_SECURE_BOOT
13#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
14#endif
15
16#define CONFIG_SPL_TEXT_BASE 0x7E1000
17#define CONFIG_SPL_MAX_SIZE (124 * 1024)
18#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
19#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
20#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
21#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
22
23#ifdef CONFIG_SPL_BUILD
24/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
25#define CONFIG_SPL_WATCHDOG_SUPPORT
26#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
27#define CONFIG_SPL_POWER_SUPPORT
28#define CONFIG_SPL_I2C_SUPPORT
29#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
30#define CONFIG_SPL_STACK 0x187FF0
31#define CONFIG_SPL_LIBCOMMON_SUPPORT
32#define CONFIG_SPL_LIBGENERIC_SUPPORT
33#define CONFIG_SPL_GPIO_SUPPORT
34#define CONFIG_SPL_MMC_SUPPORT
35#define CONFIG_SPL_BSS_START_ADDR 0x00180000
36#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
37#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
38#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
39#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
40#define CONFIG_SYS_ICACHE_OFF
41#define CONFIG_SYS_DCACHE_OFF
42
43/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
44#define CONFIG_MALLOC_F_ADDR 0x182000
45/* For RAW image gives a error info not panic */
46#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
47
48#undef CONFIG_DM_MMC
49#undef CONFIG_DM_PMIC
50#undef CONFIG_DM_PMIC_PFUZE100
51
52#define CONFIG_SYS_I2C
53#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
54#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
55#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
56
57#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
58
59#define CONFIG_POWER
60#define CONFIG_POWER_I2C
61#define CONFIG_POWER_PFUZE100
62#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
63#endif
64
65#define CONFIG_REMAKE_ELF
66
67#define CONFIG_BOARD_EARLY_INIT_F
68#define CONFIG_BOARD_LATE_INIT
69
70#undef CONFIG_CMD_EXPORTENV
71#undef CONFIG_CMD_IMPORTENV
72#undef CONFIG_CMD_IMLS
73
74#undef CONFIG_CMD_CRC32
75#undef CONFIG_BOOTM_NETBSD
76
77/* ENET Config */
78/* ENET1 */
79#if defined(CONFIG_CMD_NET)
80#define CONFIG_CMD_PING
81#define CONFIG_CMD_DHCP
82#define CONFIG_CMD_MII
83#define CONFIG_MII
84#define CONFIG_ETHPRIME "FEC"
85
86#define CONFIG_FEC_MXC
87#define CONFIG_FEC_XCV_TYPE RGMII
88#define CONFIG_FEC_MXC_PHYADDR 0
89#define FEC_QUIRK_ENET_MAC
90
91#define CONFIG_PHY_GIGE
92#define IMX_FEC_BASE 0x30BE0000
93
94#define CONFIG_PHYLIB
95#define CONFIG_PHY_ATHEROS
96#endif
97
98#define CONFIG_MFG_ENV_SETTINGS \
99 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
100 "rdinit=/linuxrc " \
101 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
102 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
103 "g_mass_storage.iSerialNumber=\"\" "\
104 "clk_ignore_unused "\
105 "\0" \
106 "initrd_addr=0x43800000\0" \
107 "initrd_high=0xffffffff\0" \
108 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
109/* Initial environment variables */
110#define CONFIG_EXTRA_ENV_SETTINGS \
111 CONFIG_MFG_ENV_SETTINGS \
112 "script=boot.scr\0" \
113 "image=Image\0" \
114 "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
115 "fdt_addr=0x43000000\0" \
116 "fdt_high=0xffffffffffffffff\0" \
117 "boot_fdt=try\0" \
118 "fdt_file=fsl-imx8mq-evk.dtb\0" \
119 "initrd_addr=0x43800000\0" \
120 "initrd_high=0xffffffffffffffff\0" \
121 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
122 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
123 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
124 "mmcautodetect=yes\0" \
125 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
126 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
127 "bootscript=echo Running bootscript from mmc ...; " \
128 "source\0" \
129 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
130 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
131 "mmcboot=echo Booting from mmc ...; " \
132 "run mmcargs; " \
133 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
134 "if run loadfdt; then " \
135 "booti ${loadaddr} - ${fdt_addr}; " \
136 "else " \
137 "echo WARN: Cannot load the DT; " \
138 "fi; " \
139 "else " \
140 "echo wait for boot; " \
141 "fi;\0" \
142 "netargs=setenv bootargs console=${console} " \
143 "root=/dev/nfs " \
144 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
145 "netboot=echo Booting from net ...; " \
146 "run netargs; " \
147 "if test ${ip_dyn} = yes; then " \
148 "setenv get_cmd dhcp; " \
149 "else " \
150 "setenv get_cmd tftp; " \
151 "fi; " \
152 "${get_cmd} ${loadaddr} ${image}; " \
153 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
154 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
155 "booti ${loadaddr} - ${fdt_addr}; " \
156 "else " \
157 "echo WARN: Cannot load the DT; " \
158 "fi; " \
159 "else " \
160 "booti; " \
161 "fi;\0"
162
163#define CONFIG_BOOTCOMMAND \
164 "mmc dev ${mmcdev}; if mmc rescan; then " \
165 "if run loadbootscript; then " \
166 "run bootscript; " \
167 "else " \
168 "if run loadimage; then " \
169 "run mmcboot; " \
170 "else run netboot; " \
171 "fi; " \
172 "fi; " \
173 "else booti ${loadaddr} - ${fdt_addr}; fi"
174
175/* Link Definitions */
176#define CONFIG_LOADADDR 0x40480000
177
178#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
179
180#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
181#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
182#define CONFIG_SYS_INIT_SP_OFFSET \
183 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
184#define CONFIG_SYS_INIT_SP_ADDR \
185 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
186
187#define CONFIG_ENV_OVERWRITE
188#define CONFIG_ENV_OFFSET (64 * SZ_64K)
189#define CONFIG_ENV_SIZE 0x1000
190#define CONFIG_ENV_IS_IN_MMC
191#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
192#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
193
194/* Size of malloc() pool */
195#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
196
197#define CONFIG_SYS_SDRAM_BASE 0x40000000
198#define PHYS_SDRAM 0x40000000
199#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
200
201#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
202#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
203 (PHYS_SDRAM_SIZE >> 1))
204
205#define CONFIG_BAUDRATE 115200
206
207#define CONFIG_MXC_UART
208#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
209
210/* Monitor Command Prompt */
211#undef CONFIG_SYS_PROMPT
212#define CONFIG_SYS_PROMPT "u-boot=> "
213#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
214#define CONFIG_SYS_CBSIZE 1024
215#define CONFIG_SYS_MAXARGS 64
216#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
217#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
218 sizeof(CONFIG_SYS_PROMPT) + 16)
219
220#define CONFIG_IMX_BOOTAUX
221
222#define CONFIG_CMD_MMC
223#define CONFIG_FSL_ESDHC
224#define CONFIG_FSL_USDHC
225
226#define CONFIG_SYS_FSL_USDHC_NUM 2
227#define CONFIG_SYS_FSL_ESDHC_ADDR 0
228
229#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
230#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
231
232#define CONFIG_MXC_GPIO
233
234#define CONFIG_MXC_OCOTP
235#define CONFIG_CMD_FUSE
236
237/* I2C Configs */
238#define CONFIG_SYS_I2C_SPEED 100000
239
240#define CONFIG_OF_SYSTEM_SETUP
241
242#ifndef CONFIG_SPL_BUILD
243#define CONFIG_DM_PMIC
244#endif
245
246#endif
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 3fca28da6b..0e03bb31a7 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -157,6 +157,9 @@
157/* IIM Fuses */ 157/* IIM Fuses */
158#define CONFIG_FSL_IIM 158#define CONFIG_FSL_IIM
159 159
160/* Watchdog */
161#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
162
160/* 163/*
161 * Boot Linux 164 * Boot Linux
162 */ 165 */
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
index 68da920e30..ba763501cf 100644
--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h
@@ -46,7 +46,7 @@
46/* DRAM */ 46/* DRAM */
47#define CONFIG_SYS_SDRAM_BASE 0x80000000 47#define CONFIG_SYS_SDRAM_BASE 0x80000000
48 48
49/* This is neede for kernel booting */ 49/* This is needed for kernel booting */
50#define FDT_HIGH "fdt_high=0xac000000\0" 50#define FDT_HIGH "fdt_high=0xac000000\0"
51 51
52/* Extra environment variables */ 52/* Extra environment variables */
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index ad77242e38..c3520bb15f 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -40,7 +40,7 @@
40/* Console configuration */ 40/* Console configuration */
41 41
42#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" 42#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot"
43#define CONFIG_DEFAULT_CONSOLE "ttySAC1,115200n8" 43#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
44 44
45#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 45#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
46 - GENERATED_GBL_DATA_SIZE) 46 - GENERATED_GBL_DATA_SIZE)
@@ -157,7 +157,7 @@
157 "elif test -e mmc 0 uImage; then; " \ 157 "elif test -e mmc 0 uImage; then; " \
158 "run boot_uimg;" \ 158 "run boot_uimg;" \
159 "fi;\0" \ 159 "fi;\0" \
160 "console=" CONFIG_DEFAULT_CONSOLE "\0" \ 160 "console=" CONFIG_DEFAULT_CONSOLE \
161 "mmcbootdev=0\0" \ 161 "mmcbootdev=0\0" \
162 "mmcbootpart=1\0" \ 162 "mmcbootpart=1\0" \
163 "mmcrootdev=0\0" \ 163 "mmcrootdev=0\0" \
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index f683ee46e3..0337c26475 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -30,7 +30,7 @@
30 30
31#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) 31#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
32 32
33#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" 33#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
34 34
35/* USB */ 35/* USB */
36#define CONFIG_USB_EHCI_EXYNOS 36#define CONFIG_USB_EHCI_EXYNOS
@@ -61,6 +61,7 @@
61 "exynos5422-odroidxu3.dtb fat 0 1;" \ 61 "exynos5422-odroidxu3.dtb fat 0 1;" \
62 "exynos5422-odroidxu3-lite.dtb fat 0 1;" \ 62 "exynos5422-odroidxu3-lite.dtb fat 0 1;" \
63 "exynos5422-odroidxu4.dtb fat 0 1;" \ 63 "exynos5422-odroidxu4.dtb fat 0 1;" \
64 "exynos5422-odroidhc1.dtb fat 0 1;" \
64 "boot part 0 1;" \ 65 "boot part 0 1;" \
65 "root part 0 2\0" 66 "root part 0 2\0"
66 67
@@ -99,7 +100,7 @@
99 MEM_LAYOUT_ENV_SETTINGS \ 100 MEM_LAYOUT_ENV_SETTINGS \
100 BOOTENV \ 101 BOOTENV \
101 "rootfstype=ext4\0" \ 102 "rootfstype=ext4\0" \
102 "console=" CONFIG_DEFAULT_CONSOLE "\0"\ 103 "console=" CONFIG_DEFAULT_CONSOLE \
103 "fdtfile=exynos5422-odroidxu3.dtb\0" \ 104 "fdtfile=exynos5422-odroidxu3.dtb\0" \
104 "boardname=odroidxu3\0" \ 105 "boardname=odroidxu3\0" \
105 "mmcbootdev=0\0" \ 106 "mmcbootdev=0\0" \
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index b9d6569752..775374cf28 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -20,10 +20,6 @@
20 20
21#define CONFIG_REVISION_TAG 1 21#define CONFIG_REVISION_TAG 1
22 22
23/* GPIO banks */
24#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
25#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
26
27/* TPS65950 */ 23/* TPS65950 */
28#define PBIASLITEVMODE1 (1 << 8) 24#define PBIASLITEVMODE1 (1 << 8)
29 25
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index 49048c163f..b9bc08b388 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h
@@ -55,6 +55,7 @@
55#define CONFIG_SYS_NAND_BASE 0x40000000 55#define CONFIG_SYS_NAND_BASE 0x40000000
56#define CONFIG_SYS_NAND_5_ADDR_CYCLE 56#define CONFIG_SYS_NAND_5_ADDR_CYCLE
57#define CONFIG_SYS_NAND_ONFI_DETECTION 57#define CONFIG_SYS_NAND_ONFI_DETECTION
58#define CONFIG_SYS_NAND_USE_FLASH_BBT
58#endif 59#endif
59 60
60/* DMA stuff, needed for GPMI/MXS NAND support */ 61/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 2bc42a04a0..1884c5844d 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -134,7 +134,19 @@
134/* FLASH and environment organization */ 134/* FLASH and environment organization */
135#define CONFIG_ENV_SIZE SZ_8K 135#define CONFIG_ENV_SIZE SZ_8K
136 136
137#define CONFIG_ENV_OFFSET (8 * SZ_64K) 137/* Environment starts at 768k = 768 * 1024 = 786432 */
138#define CONFIG_ENV_OFFSET 786432
139/*
140 * Detect overlap between U-Boot image and environment area in build-time
141 *
142 * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
143 * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
144 *
145 * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
146 * write the direct value here
147 */
148#define CONFIG_BOARD_SIZE_LIMIT 715776
149
138#define CONFIG_SYS_FSL_USDHC_NUM 2 150#define CONFIG_SYS_FSL_USDHC_NUM 2
139 151
140#define CONFIG_SYS_MMC_ENV_DEV 0 152#define CONFIG_SYS_MMC_ENV_DEV 0
diff --git a/include/configs/poplar.h b/include/configs/poplar.h
index 0a126002d7..6b93b76ab9 100644
--- a/include/configs/poplar.h
+++ b/include/configs/poplar.h
@@ -44,7 +44,7 @@
44#define CONFIG_EXTRA_ENV_SETTINGS \ 44#define CONFIG_EXTRA_ENV_SETTINGS \
45 "loader_mmc_blknum=0x0\0" \ 45 "loader_mmc_blknum=0x0\0" \
46 "loader_mmc_nblks=0x780\0" \ 46 "loader_mmc_nblks=0x780\0" \
47 "env_mmc_blknum=0x780\0" \ 47 "env_mmc_blknum=0xf80\0" \
48 "env_mmc_nblks=0x80\0" \ 48 "env_mmc_nblks=0x80\0" \
49 "kernel_addr_r=0x30000000\0" \ 49 "kernel_addr_r=0x30000000\0" \
50 "pxefile_addr_r=0x32000000\0" \ 50 "pxefile_addr_r=0x32000000\0" \
@@ -57,8 +57,8 @@
57 57
58/* Command line configuration */ 58/* Command line configuration */
59#define CONFIG_SYS_MMC_ENV_DEV 0 59#define CONFIG_SYS_MMC_ENV_DEV 0
60#define CONFIG_ENV_OFFSET (0x780 * 512) /* env_mmc_blknum */ 60#define CONFIG_ENV_OFFSET (0xf80 * 512) /* env_mmc_blknum bytes */
61#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */ 61#define CONFIG_ENV_SIZE (0x80 * 512) /* env_mmc_nblks bytes */
62 62
63/* Monitor Command Prompt */ 63/* Monitor Command Prompt */
64#define CONFIG_SYS_CBSIZE 512 64#define CONFIG_SYS_CBSIZE 512
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 87ddc20a52..ff634d91dd 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -87,7 +87,7 @@
87 87
88#define CONFIG_BOOTCOMMAND "run mmcboot" 88#define CONFIG_BOOTCOMMAND "run mmcboot"
89 89
90#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" 90#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
91 91
92#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \ 92#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \
93 " ${console} ${meminfo}" 93 " ${console} ${meminfo}"
@@ -134,7 +134,7 @@
134 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ 134 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
135 "verify=n\0" \ 135 "verify=n\0" \
136 "rootfstype=ext4\0" \ 136 "rootfstype=ext4\0" \
137 "console=" CONFIG_DEFAULT_CONSOLE "\0"\ 137 "console=" CONFIG_DEFAULT_CONSOLE \
138 "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ 138 "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
139 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ 139 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \
140 "mmcdev=0\0" \ 140 "mmcdev=0\0" \
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 999bdd1676..832032da18 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -27,7 +27,7 @@
27/* Console configuration */ 27/* Console configuration */
28 28
29#define CONFIG_BOOTCOMMAND "run mmcboot" 29#define CONFIG_BOOTCOMMAND "run mmcboot"
30#define CONFIG_DEFAULT_CONSOLE "ttySAC1,115200n8" 30#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
31 31
32#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 32#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
33 - GENERATED_GBL_DATA_SIZE) 33 - GENERATED_GBL_DATA_SIZE)
@@ -108,7 +108,7 @@
108 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 108 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
109 "verify=n\0" \ 109 "verify=n\0" \
110 "rootfstype=ext4\0" \ 110 "rootfstype=ext4\0" \
111 "console=" CONFIG_DEFAULT_CONSOLE "\0" \ 111 "console=" CONFIG_DEFAULT_CONSOLE \
112 "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ 112 "mtdparts=" CONFIG_MTDPARTS_DEFAULT \
113 "mbrparts=" MBRPARTS_DEFAULT \ 113 "mbrparts=" MBRPARTS_DEFAULT \
114 "meminfo=crashkernel=32M@0x50000000\0" \ 114 "meminfo=crashkernel=32M@0x50000000\0" \
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index a60223c623..2d4b9c9bfe 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -122,6 +122,8 @@
122#define CONFIG_ENV_OFFSET (384 * 1024) 122#define CONFIG_ENV_OFFSET (384 * 1024)
123#define CONFIG_ENV_OVERWRITE 123#define CONFIG_ENV_OVERWRITE
124 124
125#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */
126
125#define CONFIG_EXTRA_ENV_SETTINGS \ 127#define CONFIG_EXTRA_ENV_SETTINGS \
126 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ 128 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
127 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ 129 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 223fce49a7..af8e8ce3b6 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -36,7 +36,7 @@
36#define CONFIG_MACH_TYPE MACH_TYPE_TRATS 36#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
37 37
38#define CONFIG_BOOTCOMMAND "run autoboot" 38#define CONFIG_BOOTCOMMAND "run autoboot"
39#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" 39#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
40 40
41#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 41#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
42 - GENERATED_GBL_DATA_SIZE) 42 - GENERATED_GBL_DATA_SIZE)
@@ -120,7 +120,7 @@
120 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 120 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
121 "verify=n\0" \ 121 "verify=n\0" \
122 "rootfstype=ext4\0" \ 122 "rootfstype=ext4\0" \
123 "console=" CONFIG_DEFAULT_CONSOLE "\0" \ 123 "console=" CONFIG_DEFAULT_CONSOLE \
124 "meminfo=crashkernel=32M@0x50000000\0" \ 124 "meminfo=crashkernel=32M@0x50000000\0" \
125 "nfsroot=/nfsroot/arm\0" \ 125 "nfsroot=/nfsroot/arm\0" \
126 "bootblock=" CONFIG_BOOTBLOCK "\0" \ 126 "bootblock=" CONFIG_BOOTBLOCK "\0" \
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index f1e4cbad30..9c6b2bbc8d 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -34,7 +34,7 @@
34/* Console configuration */ 34/* Console configuration */
35 35
36#define CONFIG_BOOTCOMMAND "run autoboot" 36#define CONFIG_BOOTCOMMAND "run autoboot"
37#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" 37#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
38 38
39#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 39#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
40 - GENERATED_GBL_DATA_SIZE) 40 - GENERATED_GBL_DATA_SIZE)
@@ -103,7 +103,7 @@
103 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 103 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
104 "verify=n\0" \ 104 "verify=n\0" \
105 "rootfstype=ext4\0" \ 105 "rootfstype=ext4\0" \
106 "console=" CONFIG_DEFAULT_CONSOLE "\0" \ 106 "console=" CONFIG_DEFAULT_CONSOLE \
107 "kernelname=uImage\0" \ 107 "kernelname=uImage\0" \
108 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ 108 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
109 "${kernelname}\0" \ 109 "${kernelname}\0" \
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 70f8712b60..95d6452553 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -124,6 +124,8 @@
124 "third_image=u-boot.bin\0" 124 "third_image=u-boot.bin\0"
125#endif 125#endif
126 126
127#define CONFIG_PREBOOT "env exist ${bootdev}preboot && run ${bootdev}preboot"
128
127#define CONFIG_ROOTPATH "/nfs/root/path" 129#define CONFIG_ROOTPATH "/nfs/root/path"
128#define CONFIG_NFSBOOTCOMMAND \ 130#define CONFIG_NFSBOOTCOMMAND \
129 "setenv bootargs $bootargs root=/dev/nfs rw " \ 131 "setenv bootargs $bootargs root=/dev/nfs rw " \
@@ -169,8 +171,32 @@
169#define CONFIG_EXTRA_ENV_SETTINGS \ 171#define CONFIG_EXTRA_ENV_SETTINGS \
170 "netdev=eth0\0" \ 172 "netdev=eth0\0" \
171 "initrd_high=0xffffffffffffffff\0" \ 173 "initrd_high=0xffffffffffffffff\0" \
174 "script=boot.scr\0" \
172 "scriptaddr=0x85000000\0" \ 175 "scriptaddr=0x85000000\0" \
173 "nor_base=0x42000000\0" \ 176 "nor_base=0x42000000\0" \
177 "emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \
178 "nandboot=run bootcmd_ubifs0\0" \
179 "norboot=run tftpboot\0" \
180 "usbboot=run bootcmd_usb0\0" \
181 "emmcscript=setenv devtype mmc && " \
182 "mmcsetn && " \
183 "setenv devnum ${mmc_first_dev} && " \
184 "run loadscript_fat\0" \
185 "nandscript=echo Running ${script} from ubi ... && " \
186 "ubi part UBI && " \
187 "ubifsmount ubi0:boot && " \
188 "ubifsload ${loadaddr} ${script} && " \
189 "source\0" \
190 "norscript=echo Running ${script} from tftp ... && " \
191 "tftpboot ${script} &&" \
192 "source\0" \
193 "usbscript=usb start && " \
194 "setenv devtype usb && " \
195 "setenv devnum 0 && " \
196 "run loadscript_fat\0" \
197 "loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \
198 "load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \
199 "source\0" \
174 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 200 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
175 "tftpboot $tmp_addr $second_image && " \ 201 "tftpboot $tmp_addr $second_image && " \
176 "setexpr tmp_addr $nor_base + 0x70000 && " \ 202 "setexpr tmp_addr $nor_base + 0x70000 && " \
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
new file mode 100644
index 0000000000..df89cdaebf
--- /dev/null
+++ b/include/configs/vcoreiii.h
@@ -0,0 +1,82 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __VCOREIII_H
7#define __VCOREIII_H
8
9#include <linux/sizes.h>
10
11/* Onboard devices */
12
13#define CONFIG_SYS_MALLOC_LEN 0x100000
14#define CONFIG_SYS_LOAD_ADDR 0x00100000
15#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
16
17#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
18#ifdef CONFIG_SOC_LUTON
19#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
20#else
21#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
22#endif
23#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
24
25#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
26#define CONFIG_ENV_OFFSET (1024 * 1024)
27#define CONFIG_ENV_SIZE (256 * 1024)
28#define CONFIG_ENV_SECT_SIZE (256 * 1024)
29
30#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
31#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
32#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
33
34#define CONFIG_ENV_SPI_MAX_HZ 0 /* This force to read from DT */
35#define CONFIG_ENV_SPI_MODE 0 /* This force to read from DT */
36#endif
37
38#define CONFIG_SYS_SDRAM_BASE 0x80000000
39#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
40#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
41#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
42#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
43#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
44#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
45#else
46#error Unknown DDR size - please add!
47#endif
48
49#define CONFIG_CONS_INDEX 1
50
51#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
52#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
53
54#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
55
56#define CONFIG_BOARD_EARLY_INIT_R
57#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
58#define VCOREIII_DEFAULT_MTD_ENV \
59 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
60 "mtdids="CONFIG_MTDIDS_DEFAULT"\0"
61#else
62#define VCOREIII_DEFAULT_MTD_ENV /* Go away */
63#endif
64
65#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
66
67#define CONFIG_EXTRA_ENV_SETTINGS \
68 VCOREIII_DEFAULT_MTD_ENV \
69 "loadaddr=0x81000000\0" \
70 "spi_image_off=0x00100000\0" \
71 "console=ttyS0,115200\0" \
72 "setup=setenv bootargs console=${console} ${mtdparts}" \
73 "${bootargs_extra}\0" \
74 "spiboot=run setup; sf probe; sf read ${loadaddr}" \
75 "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \
76 "ubootfile=u-boot.bin\0" \
77 "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
78 "sf erase UBoot 0x100000;" \
79 "sf write ${loadaddr} UBoot ${filesize}\0" \
80 "bootcmd=run spiboot\0" \
81 ""
82#endif /* __VCOREIII_H */
diff --git a/include/cpu.h b/include/cpu.h
index 367c5f46a0..28dd48feb8 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -14,6 +14,8 @@
14 * @device_id: Driver-defined device identifier 14 * @device_id: Driver-defined device identifier
15 * @family: DMTF CPU Family identifier 15 * @family: DMTF CPU Family identifier
16 * @id: DMTF CPU Processor identifier 16 * @id: DMTF CPU Processor identifier
17 * @timebase_freq: the current frequency at which the cpu timer timebase
18 * registers are updated (in Hz)
17 * 19 *
18 * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU 20 * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU
19 * device. 21 * device.
@@ -24,6 +26,7 @@ struct cpu_platdata {
24 ulong device_id; 26 ulong device_id;
25 u16 family; 27 u16 family;
26 u32 id[2]; 28 u32 id[2];
29 u32 timebase_freq;
27}; 30};
28 31
29/* CPU features - mostly just a placeholder for now */ 32/* CPU features - mostly just a placeholder for now */
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index 63a7d55b88..ff2b82e7c2 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -355,6 +355,18 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
355int pinctrl_decode_pin_config(const void *blob, int node); 355int pinctrl_decode_pin_config(const void *blob, int node);
356 356
357/** 357/**
358 * pinctrl_decode_pin_config_dm() - decode pin configuration flags
359 *
360 * This decodes some of the PIN_CONFIG values into flags, with each value
361 * being (1 << pin_cfg). This does not support things with values like the
362 * slew rate.
363 *
364 * @pinconfig: Pinconfig udevice
365 * @return decoded flag value, or -ve on error
366 */
367int pinctrl_decode_pin_config_dm(struct udevice *dev);
368
369/**
358 * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO 370 * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO
359 * 371 *
360 * This allows the raw mux value for a GPIO to be obtained. It is 372 * This allows the raw mux value for a GPIO to be obtained. It is
diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h
index d5e13c5c2d..3f10448cef 100644
--- a/include/dt-bindings/clock/bcm6318-clock.h
+++ b/include/dt-bindings/clock/bcm6318-clock.h
@@ -33,4 +33,15 @@
33#define BCM6318_CLK_AFE 29 33#define BCM6318_CLK_AFE 29
34#define BCM6318_CLK_QPROC 30 34#define BCM6318_CLK_QPROC 30
35 35
36#define BCM6318_UCLK_ADSL 0
37#define BCM6318_UCLK_ARB 1
38#define BCM6318_UCLK_MIPS 2
39#define BCM6318_UCLK_PCIE 3
40#define BCM6318_UCLK_PERIPH 4
41#define BCM6318_UCLK_PHYMIPS 5
42#define BCM6318_UCLK_ROBOSW 6
43#define BCM6318_UCLK_SAR 7
44#define BCM6318_UCLK_SDR 8
45#define BCM6318_UCLK_USB 9
46
36#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */ 47#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */
diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
new file mode 100644
index 0000000000..73214c52c0
--- /dev/null
+++ b/include/dt-bindings/clock/jz4780-cgu.h
@@ -0,0 +1,89 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
4 *
5 * They are roughly ordered as:
6 * - external clocks
7 * - PLLs
8 * - muxes/dividers in the order they appear in the jz4780 programmers manual
9 * - gates in order of their bit in the CLKGR* registers
10 */
11
12#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
13#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
14
15#define JZ4780_CLK_EXCLK 0
16#define JZ4780_CLK_RTCLK 1
17#define JZ4780_CLK_APLL 2
18#define JZ4780_CLK_MPLL 3
19#define JZ4780_CLK_EPLL 4
20#define JZ4780_CLK_VPLL 5
21#define JZ4780_CLK_OTGPHY 6
22#define JZ4780_CLK_SCLKA 7
23#define JZ4780_CLK_CPUMUX 8
24#define JZ4780_CLK_CPU 9
25#define JZ4780_CLK_L2CACHE 10
26#define JZ4780_CLK_AHB0 11
27#define JZ4780_CLK_AHB2PMUX 12
28#define JZ4780_CLK_AHB2 13
29#define JZ4780_CLK_PCLK 14
30#define JZ4780_CLK_DDR 15
31#define JZ4780_CLK_VPU 16
32#define JZ4780_CLK_I2SPLL 17
33#define JZ4780_CLK_I2S 18
34#define JZ4780_CLK_LCD0PIXCLK 19
35#define JZ4780_CLK_LCD1PIXCLK 20
36#define JZ4780_CLK_MSCMUX 21
37#define JZ4780_CLK_MSC0 22
38#define JZ4780_CLK_MSC1 23
39#define JZ4780_CLK_MSC2 24
40#define JZ4780_CLK_UHC 25
41#define JZ4780_CLK_SSIPLL 26
42#define JZ4780_CLK_SSI 27
43#define JZ4780_CLK_CIMMCLK 28
44#define JZ4780_CLK_PCMPLL 29
45#define JZ4780_CLK_PCM 30
46#define JZ4780_CLK_GPU 31
47#define JZ4780_CLK_HDMI 32
48#define JZ4780_CLK_BCH 33
49#define JZ4780_CLK_NEMC 34
50#define JZ4780_CLK_OTG0 35
51#define JZ4780_CLK_SSI0 36
52#define JZ4780_CLK_SMB0 37
53#define JZ4780_CLK_SMB1 38
54#define JZ4780_CLK_SCC 39
55#define JZ4780_CLK_AIC 40
56#define JZ4780_CLK_TSSI0 41
57#define JZ4780_CLK_OWI 42
58#define JZ4780_CLK_KBC 43
59#define JZ4780_CLK_SADC 44
60#define JZ4780_CLK_UART0 45
61#define JZ4780_CLK_UART1 46
62#define JZ4780_CLK_UART2 47
63#define JZ4780_CLK_UART3 48
64#define JZ4780_CLK_SSI1 49
65#define JZ4780_CLK_SSI2 50
66#define JZ4780_CLK_PDMA 51
67#define JZ4780_CLK_GPS 52
68#define JZ4780_CLK_MAC 53
69#define JZ4780_CLK_SMB2 54
70#define JZ4780_CLK_CIM 55
71#define JZ4780_CLK_LCD 56
72#define JZ4780_CLK_TVE 57
73#define JZ4780_CLK_IPU 58
74#define JZ4780_CLK_DDR0 59
75#define JZ4780_CLK_DDR1 60
76#define JZ4780_CLK_SMB3 61
77#define JZ4780_CLK_TSSI1 62
78#define JZ4780_CLK_COMPRESS 63
79#define JZ4780_CLK_AIC1 64
80#define JZ4780_CLK_GPVLC 65
81#define JZ4780_CLK_OTG1 66
82#define JZ4780_CLK_UART4 67
83#define JZ4780_CLK_AHBMON 68
84#define JZ4780_CLK_SMB4 69
85#define JZ4780_CLK_DES 70
86#define JZ4780_CLK_X2D 71
87#define JZ4780_CLK_CORE1 72
88
89#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
diff --git a/include/dt-bindings/dma/bcm6318-dma.h b/include/dt-bindings/dma/bcm6318-dma.h
new file mode 100644
index 0000000000..ad7c5ac2df
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6318-dma.h
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM6318_H
9#define __DT_BINDINGS_DMA_BCM6318_H
10
11#define BCM6318_DMA_ENETSW_RX 0
12#define BCM6318_DMA_ENETSW_TX 1
13
14#endif /* __DT_BINDINGS_DMA_BCM6318_H */
diff --git a/include/dt-bindings/dma/bcm63268-dma.h b/include/dt-bindings/dma/bcm63268-dma.h
new file mode 100644
index 0000000000..7d027119e6
--- /dev/null
+++ b/include/dt-bindings/dma/bcm63268-dma.h
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM63268_H
9#define __DT_BINDINGS_DMA_BCM63268_H
10
11#define BCM63268_DMA_ENETSW_RX 0
12#define BCM63268_DMA_ENETSW_TX 1
13
14#endif /* __DT_BINDINGS_DMA_BCM63268_H */
diff --git a/include/dt-bindings/dma/bcm6328-dma.h b/include/dt-bindings/dma/bcm6328-dma.h
new file mode 100644
index 0000000000..7494df2feb
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6328-dma.h
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM6328_H
9#define __DT_BINDINGS_DMA_BCM6328_H
10
11#define BCM6328_DMA_ENETSW_RX 0
12#define BCM6328_DMA_ENETSW_TX 1
13
14#endif /* __DT_BINDINGS_DMA_BCM6328_H */
diff --git a/include/dt-bindings/dma/bcm6338-dma.h b/include/dt-bindings/dma/bcm6338-dma.h
new file mode 100644
index 0000000000..f2e0b20444
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6338-dma.h
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM6338_H
9#define __DT_BINDINGS_DMA_BCM6338_H
10
11#define BCM6338_DMA_ENET_RX 0
12#define BCM6338_DMA_ENET_TX 1
13
14#endif /* __DT_BINDINGS_DMA_BCM6338_H */
diff --git a/include/dt-bindings/dma/bcm6348-dma.h b/include/dt-bindings/dma/bcm6348-dma.h
new file mode 100644
index 0000000000..36c2ffd412
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6348-dma.h
@@ -0,0 +1,16 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM6348_H
9#define __DT_BINDINGS_DMA_BCM6348_H
10
11#define BCM6348_DMA_ENET0_RX 0
12#define BCM6348_DMA_ENET0_TX 1
13#define BCM6348_DMA_ENET1_RX 2
14#define BCM6348_DMA_ENET1_TX 3
15
16#endif /* __DT_BINDINGS_DMA_BCM6348_H */
diff --git a/include/dt-bindings/dma/bcm6358-dma.h b/include/dt-bindings/dma/bcm6358-dma.h
new file mode 100644
index 0000000000..3118b9da0a
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6358-dma.h
@@ -0,0 +1,16 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM6358_H
9#define __DT_BINDINGS_DMA_BCM6358_H
10
11#define BCM6358_DMA_ENET0_RX 0
12#define BCM6358_DMA_ENET0_TX 1
13#define BCM6358_DMA_ENET1_RX 2
14#define BCM6358_DMA_ENET1_TX 3
15
16#endif /* __DT_BINDINGS_DMA_BCM6358_H */
diff --git a/include/dt-bindings/dma/bcm6362-dma.h b/include/dt-bindings/dma/bcm6362-dma.h
new file mode 100644
index 0000000000..1e62236daa
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6362-dma.h
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM6362_H
9#define __DT_BINDINGS_DMA_BCM6362_H
10
11#define BCM6362_DMA_ENETSW_RX 0
12#define BCM6362_DMA_ENETSW_TX 1
13
14#endif /* __DT_BINDINGS_DMA_BCM6362_H */
diff --git a/include/dt-bindings/dma/bcm6368-dma.h b/include/dt-bindings/dma/bcm6368-dma.h
new file mode 100644
index 0000000000..36c6caa0e1
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6368-dma.h
@@ -0,0 +1,14 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
6 */
7
8#ifndef __DT_BINDINGS_DMA_BCM6368_H
9#define __DT_BINDINGS_DMA_BCM6368_H
10
11#define BCM6368_DMA_ENETSW_RX 0
12#define BCM6368_DMA_ENETSW_TX 1
13
14#endif /* __DT_BINDINGS_DMA_BCM6368_H */
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index e9ce06a0a6..362fbf22c6 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -47,16 +47,11 @@
47 "uuid_disk=${uuid_gpt_disk};" \ 47 "uuid_disk=${uuid_gpt_disk};" \
48 "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ 48 "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
49 "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \ 49 "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \
50 "name=reserved,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \ 50 "name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \
51 "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ 51 "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
52 "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
53 "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
54 "name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \ 52 "name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \
55 COMMON_PARTS \ 53 COMMON_PARTS \
56 "name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \ 54 "name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
57 "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
58 "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
59 "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
60 VBMETA_PART \ 55 VBMETA_PART \
61 "name=userdata,size=-,uuid=${uuid_gpt_userdata}" 56 "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
62#endif /* PARTS_DEFAULT */ 57#endif /* PARTS_DEFAULT */
diff --git a/include/imximage.h b/include/imximage.h
index 6f7ca7f5e3..544babb53a 100644
--- a/include/imximage.h
+++ b/include/imximage.h
@@ -33,6 +33,7 @@
33#define FLASH_OFFSET_NOR 0x1000 33#define FLASH_OFFSET_NOR 0x1000
34#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD 34#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
35#define FLASH_OFFSET_QSPI 0x1000 35#define FLASH_OFFSET_QSPI 0x1000
36#define FLASH_OFFSET_FLEXSPI 0x1000
36 37
37/* Initial Load Region Size */ 38/* Initial Load Region Size */
38#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF 39#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
@@ -48,6 +49,7 @@
48/* Command tags and parameters */ 49/* Command tags and parameters */
49#define IVT_HEADER_TAG 0xD1 50#define IVT_HEADER_TAG 0xD1
50#define IVT_VERSION 0x40 51#define IVT_VERSION 0x40
52#define IVT_VERSION_V3 0x41
51#define DCD_HEADER_TAG 0xD2 53#define DCD_HEADER_TAG 0xD2
52#define DCD_VERSION 0x40 54#define DCD_VERSION 0x40
53#define DCD_WRITE_DATA_COMMAND_TAG 0xCC 55#define DCD_WRITE_DATA_COMMAND_TAG 0xCC
@@ -71,6 +73,12 @@ enum imximage_cmd {
71 CMD_CHECK_BITS_CLR, 73 CMD_CHECK_BITS_CLR,
72 CMD_CSF, 74 CMD_CSF,
73 CMD_PLUGIN, 75 CMD_PLUGIN,
76 /* Follwoing on i.MX8MQ/MM */
77 CMD_FIT,
78 CMD_SIGNED_HDMI,
79 CMD_LOADER,
80 CMD_SECOND_LOADER,
81 CMD_DDR_FW,
74}; 82};
75 83
76enum imximage_fld_types { 84enum imximage_fld_types {
@@ -84,7 +92,8 @@ enum imximage_fld_types {
84enum imximage_version { 92enum imximage_version {
85 IMXIMAGE_VER_INVALID = -1, 93 IMXIMAGE_VER_INVALID = -1,
86 IMXIMAGE_V1 = 1, 94 IMXIMAGE_V1 = 1,
87 IMXIMAGE_V2 95 IMXIMAGE_V2,
96 IMXIMAGE_V3
88}; 97};
89 98
90typedef struct { 99typedef struct {
@@ -177,6 +186,12 @@ typedef struct {
177 } data; 186 } data;
178} imx_header_v2_t; 187} imx_header_v2_t;
179 188
189typedef struct {
190 flash_header_v2_t fhdr;
191 boot_data_t boot_data;
192 uint32_t padding[5];
193} imx_header_v3_t;
194
180/* The header must be aligned to 4k on MX53 for NAND boot */ 195/* The header must be aligned to 4k on MX53 for NAND boot */
181struct imx_header { 196struct imx_header {
182 union { 197 union {
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index bd88483b9f..a85c15d8dc 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -102,6 +102,18 @@
102 (((__x) - ((__d) / 2)) / (__d)); \ 102 (((__x) - ((__d) / 2)) / (__d)); \
103} \ 103} \
104) 104)
105/*
106 * Same as above but for u64 dividends. divisor must be a 32-bit
107 * number.
108 */
109#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \
110{ \
111 typeof(divisor) __d = divisor; \
112 unsigned long long _tmp = (x) + (__d) / 2; \
113 do_div(_tmp, __d); \
114 _tmp; \
115} \
116)
105 117
106/* 118/*
107 * Multiplies an integer by a fraction, while avoiding unnecessary 119 * Multiplies an integer by a fraction, while avoiding unnecessary
diff --git a/include/spl.h b/include/spl.h
index ff4e6277d3..c82f2fd033 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -118,6 +118,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
118 struct spl_load_info *info, ulong sector, void *fdt); 118 struct spl_load_info *info, ulong sector, void *fdt);
119 119
120#define SPL_COPY_PAYLOAD_ONLY 1 120#define SPL_COPY_PAYLOAD_ONLY 1
121#define SPL_FIT_FOUND 2
121 122
122/* SPL common functions */ 123/* SPL common functions */
123void preloader_console_init(void); 124void preloader_console_init(void);
@@ -353,6 +354,18 @@ void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
353void board_return_to_bootrom(void); 354void board_return_to_bootrom(void);
354 355
355/** 356/**
357 * board_spl_fit_post_load - allow process images after loading finished
358 *
359 */
360void board_spl_fit_post_load(ulong load_addr, size_t length);
361
362/**
363 * board_spl_fit_size_align - specific size align before processing payload
364 *
365 */
366ulong board_spl_fit_size_align(ulong size);
367
368/**
356 * spl_perform_fixups() - arch/board-specific callback before processing 369 * spl_perform_fixups() - arch/board-specific callback before processing
357 * the boot-payload 370 * the boot-payload
358 */ 371 */
diff --git a/include/vxworks.h b/include/vxworks.h
index 60c0efaf6e..1a29509460 100644
--- a/include/vxworks.h
+++ b/include/vxworks.h
@@ -83,6 +83,5 @@ struct efi_gop_info {
83int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); 83int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
84void boot_prep_vxworks(bootm_headers_t *images); 84void boot_prep_vxworks(bootm_headers_t *images);
85void boot_jump_vxworks(bootm_headers_t *images); 85void boot_jump_vxworks(bootm_headers_t *images);
86void do_bootvx_fdt(bootm_headers_t *images);
87 86
88#endif 87#endif
diff --git a/lib/crc32.c b/lib/crc32.c
index 71e27df78e..eee21f8d73 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -65,7 +65,8 @@ static void __efi_runtime make_crc_table(void)
65 int n, k; 65 int n, k;
66 uLong poly; /* polynomial exclusive-or pattern */ 66 uLong poly; /* polynomial exclusive-or pattern */
67 /* terms of polynomial defining this crc (except x^32): */ 67 /* terms of polynomial defining this crc (except x^32): */
68 static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; 68 static Byte __efi_runtime_data p[] = {
69 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26};
69 70
70 /* make exclusive-or pattern from polynomial (0xedb88320L) */ 71 /* make exclusive-or pattern from polynomial (0xedb88320L) */
71 poly = 0L; 72 poly = 0L;
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 95844efdb0..fff93f0960 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -436,14 +436,42 @@ static efi_status_t EFIAPI efi_set_virtual_address_map(
436 uint32_t descriptor_version, 436 uint32_t descriptor_version,
437 struct efi_mem_desc *virtmap) 437 struct efi_mem_desc *virtmap)
438{ 438{
439 ulong runtime_start = (ulong)&__efi_runtime_start &
440 ~(ulong)EFI_PAGE_MASK;
441 int n = memory_map_size / descriptor_size; 439 int n = memory_map_size / descriptor_size;
442 int i; 440 int i;
441 int rt_code_sections = 0;
443 442
444 EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size, 443 EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size,
445 descriptor_version, virtmap); 444 descriptor_version, virtmap);
446 445
446 /*
447 * TODO:
448 * Further down we are cheating. While really we should implement
449 * SetVirtualAddressMap() events and ConvertPointer() to allow
450 * dynamically loaded drivers to expose runtime services, we don't
451 * today.
452 *
453 * So let's ensure we see exactly one single runtime section, as
454 * that is the built-in one. If we see more (or less), someone must
455 * have tried adding or removing to that which we don't support yet.
456 * In that case, let's better fail rather than expose broken runtime
457 * services.
458 */
459 for (i = 0; i < n; i++) {
460 struct efi_mem_desc *map = (void*)virtmap +
461 (descriptor_size * i);
462
463 if (map->type == EFI_RUNTIME_SERVICES_CODE)
464 rt_code_sections++;
465 }
466
467 if (rt_code_sections != 1) {
468 /*
469 * We expose exactly one single runtime code section, so
470 * something is definitely going wrong.
471 */
472 return EFI_EXIT(EFI_INVALID_PARAMETER);
473 }
474
447 /* Rebind mmio pointers */ 475 /* Rebind mmio pointers */
448 for (i = 0; i < n; i++) { 476 for (i = 0; i < n; i++) {
449 struct efi_mem_desc *map = (void*)virtmap + 477 struct efi_mem_desc *map = (void*)virtmap +
@@ -483,7 +511,7 @@ static efi_status_t EFIAPI efi_set_virtual_address_map(
483 map = (void*)virtmap + (descriptor_size * i); 511 map = (void*)virtmap + (descriptor_size * i);
484 if (map->type == EFI_RUNTIME_SERVICES_CODE) { 512 if (map->type == EFI_RUNTIME_SERVICES_CODE) {
485 ulong new_offset = map->virtual_start - 513 ulong new_offset = map->virtual_start -
486 (runtime_start - gd->relocaddr); 514 map->physical_start + gd->relocaddr;
487 515
488 efi_runtime_relocate(new_offset, map); 516 efi_runtime_relocate(new_offset, map);
489 /* Once we're virtual, we can no longer handle 517 /* Once we're virtual, we can no longer handle
diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c
index d4e4fac1c7..f038da9f19 100644
--- a/lib/efi_selftest/efi_selftest_block_device.c
+++ b/lib/efi_selftest/efi_selftest_block_device.c
@@ -445,11 +445,6 @@ static int execute(void)
445 efi_st_error("Failed to write file\n"); 445 efi_st_error("Failed to write file\n");
446 return EFI_ST_FAILURE; 446 return EFI_ST_FAILURE;
447 } 447 }
448 ret = file->close(file);
449 if (ret != EFI_SUCCESS) {
450 efi_st_error("Failed to close file\n");
451 return EFI_ST_FAILURE;
452 }
453 ret = file->getpos(file, &pos); 448 ret = file->getpos(file, &pos);
454 if (ret != EFI_SUCCESS) { 449 if (ret != EFI_SUCCESS) {
455 efi_st_error("GetPosition failed\n"); 450 efi_st_error("GetPosition failed\n");
@@ -460,6 +455,11 @@ static int execute(void)
460 (unsigned int)pos); 455 (unsigned int)pos);
461 return EFI_ST_FAILURE; 456 return EFI_ST_FAILURE;
462 } 457 }
458 ret = file->close(file);
459 if (ret != EFI_SUCCESS) {
460 efi_st_error("Failed to close file\n");
461 return EFI_ST_FAILURE;
462 }
463 463
464 /* Verify file */ 464 /* Verify file */
465 boottime->set_mem(buf, sizeof(buf), 0); 465 boottime->set_mem(buf, sizeof(buf), 0);
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 2ef19bf005..29626e0025 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -87,7 +87,7 @@ endif
87endif 87endif
88 88
89libs-y += drivers/ 89libs-y += drivers/
90libs-$(CONFIG_SPL_USB_GADGET_SUPPORT) += drivers/usb/dwc3/ 90libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/dwc3/
91libs-y += dts/ 91libs-y += dts/
92libs-y += fs/ 92libs-y += fs/
93libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ 93libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
diff --git a/scripts/check-config.sh b/scripts/check-config.sh
index 4848ca6e25..583f7d0963 100755
--- a/scripts/check-config.sh
+++ b/scripts/check-config.sh
@@ -17,6 +17,15 @@
17set -e 17set -e
18set -u 18set -u
19 19
20PROG_NAME="${0##*/}"
21
22usage() {
23 echo "$PROG_NAME <path to u-boot.cfg> <path to whitelist file> <source dir>"
24 exit 1
25}
26
27[ $# -ge 3 ] || usage
28
20path="$1" 29path="$1"
21whitelist="$2" 30whitelist="$2"
22srctree="$3" 31srctree="$3"
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b8addeaf69..527050de97 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -85,7 +85,6 @@ CONFIG_AT91SAM9M10G45EK
85CONFIG_AT91_CAN 85CONFIG_AT91_CAN
86CONFIG_AT91_EFLASH 86CONFIG_AT91_EFLASH
87CONFIG_AT91_GPIO_PULLUP 87CONFIG_AT91_GPIO_PULLUP
88CONFIG_AT91_HW_WDT_TIMEOUT
89CONFIG_AT91_LED 88CONFIG_AT91_LED
90CONFIG_AT91_WANTS_COMMON_PHY 89CONFIG_AT91_WANTS_COMMON_PHY
91CONFIG_ATAPI 90CONFIG_ATAPI
@@ -354,7 +353,6 @@ CONFIG_DESIGNWARE_ETH
354CONFIG_DESIGNWARE_WATCHDOG 353CONFIG_DESIGNWARE_WATCHDOG
355CONFIG_DEVELOP 354CONFIG_DEVELOP
356CONFIG_DEVICE_TREE_LIST 355CONFIG_DEVICE_TREE_LIST
357CONFIG_DEV_USB_PHY_BASE
358CONFIG_DFU_ALT 356CONFIG_DFU_ALT
359CONFIG_DFU_ALT_BOOT_EMMC 357CONFIG_DFU_ALT_BOOT_EMMC
360CONFIG_DFU_ALT_BOOT_SD 358CONFIG_DFU_ALT_BOOT_SD
@@ -398,13 +396,11 @@ CONFIG_DRIVER_NE2000_VAL
398CONFIG_DRIVER_SMC911X_BASE 396CONFIG_DRIVER_SMC911X_BASE
399CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE 397CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
400CONFIG_DRIVER_TI_EMAC_USE_RMII 398CONFIG_DRIVER_TI_EMAC_USE_RMII
401CONFIG_DRIVER_TI_KEYSTONE_NET
402CONFIG_DRIVE_MMC 399CONFIG_DRIVE_MMC
403CONFIG_DRIVE_SATA 400CONFIG_DRIVE_SATA
404CONFIG_DRIVE_TYPES 401CONFIG_DRIVE_TYPES
405CONFIG_DSP_CLUSTER_START 402CONFIG_DSP_CLUSTER_START
406CONFIG_DUOVERO 403CONFIG_DUOVERO
407CONFIG_DV_USBPHY_CTL
408CONFIG_DWC2_DFLT_SPEED_FULL 404CONFIG_DWC2_DFLT_SPEED_FULL
409CONFIG_DWC2_DMA_BURST_SIZE 405CONFIG_DWC2_DMA_BURST_SIZE
410CONFIG_DWC2_DMA_ENABLE 406CONFIG_DWC2_DMA_ENABLE
@@ -694,7 +690,6 @@ CONFIG_FTAPBBRG020S_01_BASE
694CONFIG_FTCFC010_BASE 690CONFIG_FTCFC010_BASE
695CONFIG_FTDMAC020_BASE 691CONFIG_FTDMAC020_BASE
696CONFIG_FTGMAC100_BASE 692CONFIG_FTGMAC100_BASE
697CONFIG_FTGMAC100_EGIGA
698CONFIG_FTGPIO010_BASE 693CONFIG_FTGPIO010_BASE
699CONFIG_FTIDE020S_BASE 694CONFIG_FTIDE020S_BASE
700CONFIG_FTIIC010_BASE 695CONFIG_FTIIC010_BASE
@@ -1485,7 +1480,6 @@ CONFIG_PHY_ID
1485CONFIG_PHY_INTERFACE_MODE 1480CONFIG_PHY_INTERFACE_MODE
1486CONFIG_PHY_IRAM_BASE 1481CONFIG_PHY_IRAM_BASE
1487CONFIG_PHY_M88E1111 1482CONFIG_PHY_M88E1111
1488CONFIG_PHY_MAX_ADDR
1489CONFIG_PHY_MODE_NEED_CHANGE 1483CONFIG_PHY_MODE_NEED_CHANGE
1490CONFIG_PHY_RESET 1484CONFIG_PHY_RESET
1491CONFIG_PHY_RESET_DELAY 1485CONFIG_PHY_RESET_DELAY
@@ -4577,7 +4571,6 @@ CONFIG_USB_GADGET_PXA27X
4577CONFIG_USB_GADGET_PXA2XX 4571CONFIG_USB_GADGET_PXA2XX
4578CONFIG_USB_GADGET_SA1100 4572CONFIG_USB_GADGET_SA1100
4579CONFIG_USB_GADGET_SUPERH 4573CONFIG_USB_GADGET_SUPERH
4580CONFIG_USB_HOST_XHCI_BASE
4581CONFIG_USB_INVENTRA_DMA 4574CONFIG_USB_INVENTRA_DMA
4582CONFIG_USB_ISP1301_I2C_ADDR 4575CONFIG_USB_ISP1301_I2C_ADDR
4583CONFIG_USB_MAX_CONTROLLER_COUNT 4576CONFIG_USB_MAX_CONTROLLER_COUNT
@@ -4590,18 +4583,15 @@ CONFIG_USB_OHCI_NEW
4590CONFIG_USB_OHCI_SUNXI 4583CONFIG_USB_OHCI_SUNXI
4591CONFIG_USB_OTG 4584CONFIG_USB_OTG
4592CONFIG_USB_OTG_BLACKLIST_HUB 4585CONFIG_USB_OTG_BLACKLIST_HUB
4593CONFIG_USB_PHY_CFG_BASE
4594CONFIG_USB_PHY_TYPE 4586CONFIG_USB_PHY_TYPE
4595CONFIG_USB_PXA25X_SMALL 4587CONFIG_USB_PXA25X_SMALL
4596CONFIG_USB_R8A66597_HCD 4588CONFIG_USB_R8A66597_HCD
4597CONFIG_USB_SERIALNO 4589CONFIG_USB_SERIALNO
4598CONFIG_USB_SS_BASE
4599CONFIG_USB_TI_CPPI_DMA 4590CONFIG_USB_TI_CPPI_DMA
4600CONFIG_USB_TTY 4591CONFIG_USB_TTY
4601CONFIG_USB_TUSB_OMAP_DMA 4592CONFIG_USB_TUSB_OMAP_DMA
4602CONFIG_USB_ULPI_TIMEOUT 4593CONFIG_USB_ULPI_TIMEOUT
4603CONFIG_USB_XHCI_EXYNOS 4594CONFIG_USB_XHCI_EXYNOS
4604CONFIG_USB_XHCI_KEYSTONE
4605CONFIG_USB_XHCI_OMAP 4595CONFIG_USB_XHCI_OMAP
4606CONFIG_USER_LOWLEVEL_INIT 4596CONFIG_USER_LOWLEVEL_INIT
4607CONFIG_USE_INTERRUPT 4597CONFIG_USE_INTERRUPT
diff --git a/test/dm/video.c b/test/dm/video.c
index 5d1faac19c..6be5defc53 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -335,7 +335,7 @@ static int dm_test_video_truetype(struct unit_test_state *uts)
335 ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); 335 ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
336 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); 336 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
337 vidconsole_put_string(con, test_string); 337 vidconsole_put_string(con, test_string);
338 ut_asserteq(12619, compress_frame_buffer(dev)); 338 ut_asserteq(12237, compress_frame_buffer(dev));
339 339
340 return 0; 340 return 0;
341} 341}
@@ -356,7 +356,7 @@ static int dm_test_video_truetype_scroll(struct unit_test_state *uts)
356 ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); 356 ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
357 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); 357 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
358 vidconsole_put_string(con, test_string); 358 vidconsole_put_string(con, test_string);
359 ut_asserteq(33849, compress_frame_buffer(dev)); 359 ut_asserteq(35030, compress_frame_buffer(dev));
360 360
361 return 0; 361 return 0;
362} 362}
@@ -377,7 +377,7 @@ static int dm_test_video_truetype_bs(struct unit_test_state *uts)
377 ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); 377 ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
378 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); 378 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
379 vidconsole_put_string(con, test_string); 379 vidconsole_put_string(con, test_string);
380 ut_asserteq(34871, compress_frame_buffer(dev)); 380 ut_asserteq(29018, compress_frame_buffer(dev));
381 381
382 return 0; 382 return 0;
383} 383}
diff --git a/test/overlay/Kconfig b/test/overlay/Kconfig
index 13c85428cb..a4f154415d 100644
--- a/test/overlay/Kconfig
+++ b/test/overlay/Kconfig
@@ -1,11 +1,10 @@
1config UT_OVERLAY 1config UT_OVERLAY
2 bool "Enable Device Tree Overlays Unit Tests" 2 bool "Enable Device Tree Overlays Unit Tests"
3 depends on OF_LIBFDT_OVERLAY 3 depends on UNIT_TEST && OF_CONTROL
4 depends on UNIT_TEST 4 default y
5 select OF_LIBFDT_OVERLAY
5 help 6 help
6 This enables the 'ut overlay' command which runs a series of unit 7 This enables the 'ut overlay' command which runs a series of unit
7 tests on the fdt overlay code. 8 tests on the fdt overlay code.
8 If all is well then all tests pass although there will be a few 9 If all is well then all tests pass although there will be a few
9 messages printed along the way. 10 messages printed along the way.
10 Be warned that it requires an out-of-tree dtc compiler with patches
11 to support the DT overlays, otherwise it will fail.
diff --git a/tools/Makefile b/tools/Makefile
index 2c4d91f199..081383d7a7 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -94,6 +94,7 @@ dumpimage-mkimage-objs := aisimage.o \
94 imagetool.o \ 94 imagetool.o \
95 imximage.o \ 95 imximage.o \
96 imx8image.o \ 96 imx8image.o \
97 imx8mimage.o \
97 kwbimage.o \ 98 kwbimage.o \
98 lib/md5.o \ 99 lib/md5.o \
99 lpc32xximage.o \ 100 lpc32xximage.o \
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 3fcfb4468d..71471420f9 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -233,6 +233,7 @@ time_t imagetool_get_source_date(
233void pbl_load_uboot(int fd, struct image_tool_params *mparams); 233void pbl_load_uboot(int fd, struct image_tool_params *mparams);
234int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams); 234int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams);
235int imx8image_copy_image(int fd, struct image_tool_params *mparams); 235int imx8image_copy_image(int fd, struct image_tool_params *mparams);
236int imx8mimage_copy_image(int fd, struct image_tool_params *mparams);
236 237
237#define ___cat(a, b) a ## b 238#define ___cat(a, b) a ## b
238#define __cat(a, b) ___cat(a, b) 239#define __cat(a, b) ___cat(a, b)
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 6e8ac464e7..0d856b9d94 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -968,7 +968,7 @@ int imx8image_copy_image(int outfd, struct image_tool_params *mparams)
968 fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version); 968 fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version);
969 969
970 build_container(soc, sector_size, emmc_fastboot, 970 build_container(soc, sector_size, emmc_fastboot,
971 img_sp, false, fuse_version, sw_version, outfd); 971 img_sp, true, fuse_version, sw_version, outfd);
972 972
973 return 0; 973 return 0;
974} 974}
diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh
new file mode 100755
index 0000000000..6346fb64d8
--- /dev/null
+++ b/tools/imx8m_image.sh
@@ -0,0 +1,43 @@
1#!/bin/sh
2# SPDX-License-Identifier: GPL-2.0+
3#
4# script to check whether the file exists in imximage.cfg for i.MX8M
5#
6
7file=$1
8
9post_process=$2
10
11blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2} /^SECOND_LOADER/ {print $2} /^DDR_FW/ {print $2}' $file`
12for f in $blobs; do
13 tmp=$srctree/$f
14
15 if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then
16 continue
17 fi
18
19 if [ -f $f ]; then
20 continue
21 fi
22
23 if [ ! -f $tmp ]; then
24 echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2
25 exit 1
26 fi
27
28 sed -in "s;$f;$tmp;" $file
29done
30
31if [ $post_process == 1 ]; then
32 if [ -f $srctree/lpddr4_pmu_train_1d_imem.bin ]; then
33 objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin
34 objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin
35 objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_imem_pad.bin
36 cat lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin
37 cat lpddr4_pmu_train_2d_imem_pad.bin $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin
38 cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin
39 rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin
40 fi
41fi
42
43exit 0
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
new file mode 100644
index 0000000000..50a256cbac
--- /dev/null
+++ b/tools/imx8mimage.c
@@ -0,0 +1,623 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8
9#include "imagetool.h"
10#include <image.h>
11#include "imximage.h"
12#include "compiler.h"
13
14static uint32_t ap_start_addr, sld_start_addr, sld_src_off;
15static char *ap_img, *sld_img, *signed_hdmi;
16static imx_header_v3_t imx_header[2]; /* At most there are 3 IVT headers */
17static uint32_t rom_image_offset;
18static uint32_t sector_size = 0x200;
19static uint32_t image_off;
20static uint32_t sld_header_off;
21static uint32_t ivt_offset;
22static uint32_t using_fit;
23
24#define CSF_SIZE 0x2000
25#define HDMI_IVT_ID 0
26#define IMAGE_IVT_ID 1
27
28#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */
29#define ALIGN_SIZE 0x1000
30#define ALIGN(x,a) __ALIGN_MASK((x), (__typeof__(x))(a) - 1, a)
31#define __ALIGN_MASK(x,mask,mask2) (((x) + (mask)) / (mask2) * (mask2))
32
33static uint32_t get_cfg_value(char *token, char *name, int linenr)
34{
35 char *endptr;
36 uint32_t value;
37
38 errno = 0;
39 value = strtoul(token, &endptr, 16);
40 if (errno || token == endptr) {
41 fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
42 name, linenr, token);
43 exit(EXIT_FAILURE);
44 }
45 return value;
46}
47
48int imx8mimage_check_params(struct image_tool_params *params)
49{
50 return 0;
51}
52
53static void imx8mimage_set_header(void *ptr, struct stat *sbuf, int ifd,
54 struct image_tool_params *params)
55{
56}
57
58static void imx8mimage_print_header(const void *ptr)
59{
60}
61
62static int imx8mimage_check_image_types(uint8_t type)
63{
64 return (type == IH_TYPE_IMX8MIMAGE) ? EXIT_SUCCESS : EXIT_FAILURE;
65}
66
67static table_entry_t imx8mimage_cmds[] = {
68 {CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
69 {CMD_FIT, "FIT", "fit image", },
70 {CMD_SIGNED_HDMI, "SIGNED_HDMI", "signed hdmi image", },
71 {CMD_LOADER, "LOADER", "loader image", },
72 {CMD_SECOND_LOADER, "SECOND_LOADER", "2nd loader image", },
73 {CMD_DDR_FW, "DDR_FW", "ddr firmware", },
74 {-1, "", "", },
75};
76
77static table_entry_t imx8mimage_ivt_offset[] = {
78 {0x400, "sd", "sd/emmc",},
79 {0x400, "emmc_fastboot", "emmc fastboot",},
80 {0x1000, "fspi", "flexspi", },
81 {-1, "", "Invalid", },
82};
83
84static void parse_cfg_cmd(int32_t cmd, char *token, char *name, int lineno)
85{
86 switch (cmd) {
87 case CMD_BOOT_FROM:
88 ivt_offset = get_table_entry_id(imx8mimage_ivt_offset,
89 "imx8mimage ivt offset",
90 token);
91 if (!strncmp(token, "sd", 2))
92 rom_image_offset = 0x8000;
93 break;
94 case CMD_LOADER:
95 ap_img = token;
96 break;
97 case CMD_SECOND_LOADER:
98 sld_img = token;
99 break;
100 case CMD_SIGNED_HDMI:
101 signed_hdmi = token;
102 case CMD_FIT:
103 using_fit = 1;
104 break;
105 case CMD_DDR_FW:
106 /* Do nothing */
107 break;
108 }
109}
110
111static void parse_cfg_fld(int32_t *cmd, char *token,
112 char *name, int lineno, int fld)
113{
114 switch (fld) {
115 case CFG_COMMAND:
116 *cmd = get_table_entry_id(imx8mimage_cmds,
117 "imx8mimage commands", token);
118 if (*cmd < 0) {
119 fprintf(stderr, "Error: %s[%d] - Invalid command" "(%s)\n",
120 name, lineno, token);
121 exit(EXIT_FAILURE);
122 }
123 break;
124 case CFG_REG_SIZE:
125 parse_cfg_cmd(*cmd, token, name, lineno);
126 break;
127 case CFG_REG_ADDRESS:
128 switch (*cmd) {
129 case CMD_LOADER:
130 ap_start_addr = get_cfg_value(token, name, lineno);
131 break;
132 case CMD_SECOND_LOADER:
133 sld_start_addr = get_cfg_value(token, name, lineno);
134 break;
135 }
136 break;
137 case CFG_REG_VALUE:
138 switch (*cmd) {
139 case CMD_SECOND_LOADER:
140 sld_src_off = get_cfg_value(token, name, lineno);
141 break;
142 }
143 default:
144 break;
145 }
146}
147
148static uint32_t parse_cfg_file(char *name)
149{
150 FILE *fd = NULL;
151 char *line = NULL;
152 char *token, *saveptr1, *saveptr2;
153 int lineno = 0;
154 int fld;
155 size_t len;
156 int32_t cmd;
157
158 fd = fopen(name, "r");
159 if (fd == 0) {
160 fprintf(stderr, "Error: %s - Can't open cfg file\n", name);
161 exit(EXIT_FAILURE);
162 }
163
164 /*
165 * Very simple parsing, line starting with # are comments
166 * and are dropped
167 */
168 while ((getline(&line, &len, fd)) > 0) {
169 lineno++;
170
171 token = strtok_r(line, "\r\n", &saveptr1);
172 if (!token)
173 continue;
174
175 /* Check inside the single line */
176 for (fld = CFG_COMMAND, cmd = CFG_INVALID,
177 line = token; ; line = NULL, fld++) {
178 token = strtok_r(line, " \t", &saveptr2);
179 if (!token)
180 break;
181
182 /* Drop all text starting with '#' as comments */
183 if (token[0] == '#')
184 break;
185
186 parse_cfg_fld(&cmd, token, name, lineno, fld);
187 }
188 }
189
190 return 0;
191}
192
193static void fill_zero(int ifd, int size, int offset)
194{
195 int fill_size;
196 uint8_t zeros[4096];
197 int ret;
198
199 memset(zeros, 0, sizeof(zeros));
200
201 ret = lseek(ifd, offset, SEEK_SET);
202 if (ret < 0) {
203 fprintf(stderr, "%s seek: %s\n", __func__, strerror(errno));
204 exit(EXIT_FAILURE);
205 }
206
207 while (size) {
208 if (size > 4096)
209 fill_size = 4096;
210 else
211 fill_size = size;
212
213 if (write(ifd, (char *)&zeros, fill_size) != fill_size) {
214 fprintf(stderr, "Write error: %s\n",
215 strerror(errno));
216 exit(EXIT_FAILURE);
217 }
218
219 size -= fill_size;
220 };
221}
222
223static void copy_file(int ifd, const char *datafile, int pad, int offset,
224 int datafile_offset)
225{
226 int dfd;
227 struct stat sbuf;
228 unsigned char *ptr;
229 int tail;
230 int zero = 0;
231 uint8_t zeros[4096];
232 int size, ret;
233
234 memset(zeros, 0, sizeof(zeros));
235
236 dfd = open(datafile, O_RDONLY | O_BINARY);
237 if (dfd < 0) {
238 fprintf(stderr, "Can't open %s: %s\n",
239 datafile, strerror(errno));
240 exit(EXIT_FAILURE);
241 }
242
243 if (fstat(dfd, &sbuf) < 0) {
244 fprintf(stderr, "Can't stat %s: %s\n",
245 datafile, strerror(errno));
246 exit(EXIT_FAILURE);
247 }
248
249 ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0);
250 if (ptr == MAP_FAILED) {
251 fprintf(stderr, "Can't read %s: %s\n",
252 datafile, strerror(errno));
253 exit(EXIT_FAILURE);
254 }
255
256 size = sbuf.st_size - datafile_offset;
257 ret = lseek(ifd, offset, SEEK_SET);
258 if (ret < 0) {
259 fprintf(stderr, "lseek ifd fail\n");
260 exit(EXIT_FAILURE);
261 }
262
263 if (write(ifd, ptr + datafile_offset, size) != size) {
264 fprintf(stderr, "Write error %s\n",
265 strerror(errno));
266 exit(EXIT_FAILURE);
267 }
268
269 tail = size % 4;
270 pad = pad - size;
271 if (pad == 1 && tail != 0) {
272 if (write(ifd, (char *)&zero, 4 - tail) != 4 - tail) {
273 fprintf(stderr, "Write error on %s\n",
274 strerror(errno));
275 exit(EXIT_FAILURE);
276 }
277 } else if (pad > 1) {
278 while (pad > 0) {
279 int todo = sizeof(zeros);
280
281 if (todo > pad)
282 todo = pad;
283 if (write(ifd, (char *)&zeros, todo) != todo) {
284 fprintf(stderr, "Write error: %s\n",
285 strerror(errno));
286 exit(EXIT_FAILURE);
287 }
288 pad -= todo;
289 }
290 }
291
292 munmap((void *)ptr, sbuf.st_size);
293 close(dfd);
294}
295
296/* Return this IVT offset in the final output file */
297static int generate_ivt_for_fit(int fd, int fit_offset, uint32_t ep,
298 uint32_t *fit_load_addr)
299{
300 image_header_t image_header;
301 int ret;
302
303 uint32_t fit_size, load_addr;
304 int align_len = 64 - 1; /* 64 is cacheline size */
305
306 ret = lseek(fd, fit_offset, SEEK_SET);
307 if (ret < 0) {
308 fprintf(stderr, "lseek fd fail for fit\n");
309 exit(EXIT_FAILURE);
310 }
311
312 if (read(fd, (char *)&image_header, sizeof(image_header_t)) !=
313 sizeof(image_header_t)) {
314 fprintf(stderr, "generate_ivt_for_fit read failed: %s\n",
315 strerror(errno));
316 exit(EXIT_FAILURE);
317 }
318
319 if (be32_to_cpu(image_header.ih_magic) != FDT_MAGIC) {
320 fprintf(stderr, "%s error: not a FIT file\n", __func__);
321 exit(EXIT_FAILURE);
322 }
323
324 fit_size = fdt_totalsize(&image_header);
325 fit_size = (fit_size + 3) & ~3;
326
327 fit_size = ALIGN(fit_size, ALIGN_SIZE);
328
329 ret = lseek(fd, fit_offset + fit_size, SEEK_SET);
330 if (ret < 0) {
331 fprintf(stderr, "lseek fd fail for fit\n");
332 exit(EXIT_FAILURE);
333 }
334
335 /*
336 * ep is the u-boot entry. SPL loads the FIT before the u-boot
337 * address. 0x2000 is for CSF_SIZE
338 */
339 load_addr = (ep - (fit_size + CSF_SIZE) - 512 - align_len) &
340 ~align_len;
341
342 flash_header_v2_t ivt_header = { { 0xd1, 0x2000, 0x40 },
343 load_addr, 0, 0, 0,
344 (load_addr + fit_size),
345 (load_addr + fit_size + 0x20),
346 0 };
347
348 if (write(fd, &ivt_header, sizeof(flash_header_v2_t)) !=
349 sizeof(flash_header_v2_t)) {
350 fprintf(stderr, "IVT writing error on fit image\n");
351 exit(EXIT_FAILURE);
352 }
353
354 *fit_load_addr = load_addr;
355
356 return fit_offset + fit_size;
357}
358
359static void dump_header_v2(imx_header_v3_t *imx_header, int index)
360{
361 const char *ivt_name[2] = {"HDMI FW", "LOADER IMAGE"};
362
363 fprintf(stdout, "========= IVT HEADER [%s] =========\n",
364 ivt_name[index]);
365 fprintf(stdout, "header.tag: \t\t0x%x\n",
366 imx_header[index].fhdr.header.tag);
367 fprintf(stdout, "header.length: \t\t0x%x\n",
368 imx_header[index].fhdr.header.length);
369 fprintf(stdout, "header.version: \t0x%x\n",
370 imx_header[index].fhdr.header.version);
371 fprintf(stdout, "entry: \t\t\t0x%x\n",
372 imx_header[index].fhdr.entry);
373 fprintf(stdout, "reserved1: \t\t0x%x\n",
374 imx_header[index].fhdr.reserved1);
375 fprintf(stdout, "dcd_ptr: \t\t0x%x\n",
376 imx_header[index].fhdr.dcd_ptr);
377 fprintf(stdout, "boot_data_ptr: \t\t0x%x\n",
378 imx_header[index].fhdr.boot_data_ptr);
379 fprintf(stdout, "self: \t\t\t0x%x\n",
380 imx_header[index].fhdr.self);
381 fprintf(stdout, "csf: \t\t\t0x%x\n",
382 imx_header[index].fhdr.csf);
383 fprintf(stdout, "reserved2: \t\t0x%x\n",
384 imx_header[index].fhdr.reserved2);
385
386 fprintf(stdout, "boot_data.start: \t0x%x\n",
387 imx_header[index].boot_data.start);
388 fprintf(stdout, "boot_data.size: \t0x%x\n",
389 imx_header[index].boot_data.size);
390 fprintf(stdout, "boot_data.plugin: \t0x%x\n",
391 imx_header[index].boot_data.plugin);
392}
393
394void build_image(int ofd)
395{
396 int file_off, header_hdmi_off = 0, header_image_off;
397 int hdmi_fd, ap_fd, sld_fd;
398 uint32_t sld_load_addr = 0;
399 uint32_t csf_off, sld_csf_off = 0;
400 int ret;
401 struct stat sbuf;
402
403 if (!ap_img) {
404 fprintf(stderr, "No LOADER image specificed\n");
405 exit(EXIT_FAILURE);
406 }
407
408 file_off = 0;
409
410 if (signed_hdmi) {
411 header_hdmi_off = file_off + ivt_offset;
412
413 hdmi_fd = open(signed_hdmi, O_RDONLY | O_BINARY);
414 if (hdmi_fd < 0) {
415 fprintf(stderr, "%s: Can't open: %s\n",
416 signed_hdmi, strerror(errno));
417 exit(EXIT_FAILURE);
418 }
419
420 if (fstat(hdmi_fd, &sbuf) < 0) {
421 fprintf(stderr, "%s: Can't stat: %s\n",
422 signed_hdmi, strerror(errno));
423 exit(EXIT_FAILURE);
424 }
425 close(hdmi_fd);
426
427 /*
428 * Aligned to 104KB = 92KB FW image + 0x8000
429 * (IVT and alignment) + 0x4000 (second IVT + CSF)
430 */
431 file_off += ALIGN(sbuf.st_size,
432 HDMI_FW_SIZE + 0x2000 + 0x1000);
433 }
434
435 header_image_off = file_off + ivt_offset;
436
437 ap_fd = open(ap_img, O_RDONLY | O_BINARY);
438 if (ap_fd < 0) {
439 fprintf(stderr, "%s: Can't open: %s\n",
440 ap_img, strerror(errno));
441 exit(EXIT_FAILURE);
442 }
443 if (fstat(ap_fd, &sbuf) < 0) {
444 fprintf(stderr, "%s: Can't stat: %s\n",
445 ap_img, strerror(errno));
446 exit(EXIT_FAILURE);
447 }
448 close(ap_fd);
449
450 imx_header[IMAGE_IVT_ID].fhdr.header.tag = IVT_HEADER_TAG; /* 0xD1 */
451 imx_header[IMAGE_IVT_ID].fhdr.header.length =
452 cpu_to_be16(sizeof(flash_header_v2_t));
453 imx_header[IMAGE_IVT_ID].fhdr.header.version = IVT_VERSION_V3; /* 0x41 */
454 imx_header[IMAGE_IVT_ID].fhdr.entry = ap_start_addr;
455 imx_header[IMAGE_IVT_ID].fhdr.self = ap_start_addr -
456 sizeof(imx_header_v3_t);
457 imx_header[IMAGE_IVT_ID].fhdr.dcd_ptr = 0;
458 imx_header[IMAGE_IVT_ID].fhdr.boot_data_ptr =
459 imx_header[IMAGE_IVT_ID].fhdr.self +
460 offsetof(imx_header_v3_t, boot_data);
461 imx_header[IMAGE_IVT_ID].boot_data.start =
462 imx_header[IMAGE_IVT_ID].fhdr.self - ivt_offset;
463 imx_header[IMAGE_IVT_ID].boot_data.size =
464 ALIGN(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset,
465 sector_size);
466
467 image_off = header_image_off + sizeof(imx_header_v3_t);
468 file_off += imx_header[IMAGE_IVT_ID].boot_data.size;
469
470 imx_header[IMAGE_IVT_ID].boot_data.plugin = 0;
471 imx_header[IMAGE_IVT_ID].fhdr.csf =
472 imx_header[IMAGE_IVT_ID].boot_data.start +
473 imx_header[IMAGE_IVT_ID].boot_data.size;
474
475 imx_header[IMAGE_IVT_ID].boot_data.size += CSF_SIZE; /* 8K region dummy CSF */
476
477 csf_off = file_off;
478 file_off += CSF_SIZE;
479
480 /* Second boot loader image */
481 if (sld_img) {
482 if (!using_fit) {
483 fprintf(stderr, "Not support no fit\n");
484 exit(EXIT_FAILURE);
485 } else {
486 sld_header_off = sld_src_off - rom_image_offset;
487 /*
488 * Record the second bootloader relative offset in
489 * image's IVT reserved1
490 */
491 imx_header[IMAGE_IVT_ID].fhdr.reserved1 =
492 sld_header_off - header_image_off;
493 sld_fd = open(sld_img, O_RDONLY | O_BINARY);
494 if (sld_fd < 0) {
495 fprintf(stderr, "%s: Can't open: %s\n",
496 sld_img, strerror(errno));
497 exit(EXIT_FAILURE);
498 }
499
500 if (fstat(sld_fd, &sbuf) < 0) {
501 fprintf(stderr, "%s: Can't stat: %s\n",
502 sld_img, strerror(errno));
503 exit(EXIT_FAILURE);
504 }
505
506 close(sld_fd);
507
508 file_off = sld_header_off;
509 file_off += sbuf.st_size + sizeof(image_header_t);
510 }
511 }
512
513 if (signed_hdmi) {
514 header_hdmi_off -= ivt_offset;
515 ret = lseek(ofd, header_hdmi_off, SEEK_SET);
516 if (ret < 0) {
517 fprintf(stderr, "lseek ofd fail for hdmi\n");
518 exit(EXIT_FAILURE);
519 }
520
521 /* The signed HDMI FW has 0x400 IVT offset, need remove it */
522 copy_file(ofd, signed_hdmi, 0, header_hdmi_off, 0x400);
523 }
524
525 /* Main Image */
526 header_image_off -= ivt_offset;
527 image_off -= ivt_offset;
528 ret = lseek(ofd, header_image_off, SEEK_SET);
529 if (ret < 0) {
530 fprintf(stderr, "lseek ofd fail\n");
531 exit(EXIT_FAILURE);
532 }
533
534 /* Write image header */
535 if (write(ofd, &imx_header[IMAGE_IVT_ID], sizeof(imx_header_v3_t)) !=
536 sizeof(imx_header_v3_t)) {
537 fprintf(stderr, "error writing image hdr\n");
538 exit(1);
539 }
540
541 copy_file(ofd, ap_img, 0, image_off, 0);
542
543 csf_off -= ivt_offset;
544 fill_zero(ofd, CSF_SIZE, csf_off);
545
546 if (sld_img) {
547 sld_header_off -= ivt_offset;
548 ret = lseek(ofd, sld_header_off, SEEK_SET);
549 if (ret < 0) {
550 fprintf(stderr, "lseek ofd fail for sld_img\n");
551 exit(EXIT_FAILURE);
552 }
553
554 /* Write image header */
555 if (!using_fit) {
556 /* TODO */
557 } else {
558 copy_file(ofd, sld_img, 0, sld_header_off, 0);
559 sld_csf_off =
560 generate_ivt_for_fit(ofd, sld_header_off,
561 sld_start_addr,
562 &sld_load_addr) + 0x20;
563 }
564 }
565
566 if (!signed_hdmi)
567 dump_header_v2(imx_header, 0);
568 dump_header_v2(imx_header, 1);
569
570 fprintf(stdout, "========= OFFSET dump =========");
571 if (signed_hdmi) {
572 fprintf(stdout, "\nSIGNED HDMI FW:\n");
573 fprintf(stdout, " header_hdmi_off \t0x%x\n",
574 header_hdmi_off);
575 }
576
577 fprintf(stdout, "\nLoader IMAGE:\n");
578 fprintf(stdout, " header_image_off \t0x%x\n image_off \t\t0x%x\n csf_off \t\t0x%x\n",
579 header_image_off, image_off, csf_off);
580 fprintf(stdout, " spl hab block: \t0x%x 0x%x 0x%x\n",
581 imx_header[IMAGE_IVT_ID].fhdr.self, header_image_off,
582 csf_off - header_image_off);
583
584 fprintf(stdout, "\nSecond Loader IMAGE:\n");
585 fprintf(stdout, " sld_header_off \t0x%x\n",
586 sld_header_off);
587 fprintf(stdout, " sld_csf_off \t\t0x%x\n",
588 sld_csf_off);
589 fprintf(stdout, " sld hab block: \t0x%x 0x%x 0x%x\n",
590 sld_load_addr, sld_header_off, sld_csf_off - sld_header_off);
591}
592
593int imx8mimage_copy_image(int outfd, struct image_tool_params *mparams)
594{
595 /*
596 * SECO FW is a container image, this is to calculate the
597 * 2nd container offset.
598 */
599 fprintf(stdout, "parsing %s\n", mparams->imagename);
600 parse_cfg_file(mparams->imagename);
601
602 build_image(outfd);
603
604 return 0;
605}
606
607/*
608 * imx8mimage parameters
609 */
610U_BOOT_IMAGE_TYPE(
611 imx8mimage,
612 "NXP i.MX8M Boot Image support",
613 0,
614 NULL,
615 imx8mimage_check_params,
616 NULL,
617 imx8mimage_print_header,
618 imx8mimage_set_header,
619 NULL,
620 imx8mimage_check_image_types,
621 NULL,
622 NULL
623);
diff --git a/tools/imx_cntr_image.sh b/tools/imx_cntr_image.sh
index 4c629e8694..972b95ccbe 100755
--- a/tools/imx_cntr_image.sh
+++ b/tools/imx_cntr_image.sh
@@ -10,7 +10,7 @@ file=$1
10blobs=`awk '/^APPEND/ {print $2} /^IMAGE/ || /^DATA/ {print $3}' $file` 10blobs=`awk '/^APPEND/ {print $2} /^IMAGE/ || /^DATA/ {print $3}' $file`
11for f in $blobs; do 11for f in $blobs; do
12 tmp=$srctree/$f 12 tmp=$srctree/$f
13 if [ $f == "u-boot-dtb.bin" ]; then 13 if [ $f = "u-boot-dtb.bin" ]; then
14 continue 14 continue
15 fi 15 fi
16 16
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 38805f0c92..ea5ed542ab 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -530,6 +530,13 @@ int main(int argc, char **argv)
530 ret = imx8image_copy_image(ifd, &params); 530 ret = imx8image_copy_image(ifd, &params);
531 if (ret) 531 if (ret)
532 return ret; 532 return ret;
533 } else if (params.type == IH_TYPE_IMX8MIMAGE) {
534 /* i.MX8M has special Image format */
535 int ret;
536
537 ret = imx8mimage_copy_image(ifd, &params);
538 if (ret)
539 return ret;
533 } else { 540 } else {
534 copy_file(ifd, params.datafile, pad_len); 541 copy_file(ifd, params.datafile, pad_len);
535 } 542 }