diff options
Diffstat (limited to 'arch/arm/dts/armada-xp-mv78260.dtsi')
-rw-r--r-- | arch/arm/dts/armada-xp-mv78260.dtsi | 87 |
1 files changed, 34 insertions, 53 deletions
diff --git a/arch/arm/dts/armada-xp-mv78260.dtsi b/arch/arm/dts/armada-xp-mv78260.dtsi index c5fdc99f0d..2d85fe8ac3 100644 --- a/arch/arm/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/dts/armada-xp-mv78260.dtsi | |||
@@ -1,3 +1,4 @@ | |||
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
1 | /* | 2 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | 3 | * Device Tree Include file for Marvell Armada XP family SoC |
3 | * | 4 | * |
@@ -5,44 +6,6 @@ | |||
5 | * | 6 | * |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
7 | * | 8 | * |
8 | * This file is dual-licensed: you can use it either under the terms | ||
9 | * of the GPL or the X11 license, at your option. Note that this dual | ||
10 | * licensing only applies to this file, and not this project as a | ||
11 | * whole. | ||
12 | * | ||
13 | * a) This file is free software; you can redistribute it and/or | ||
14 | * modify it under the terms of the GNU General Public License as | ||
15 | * published by the Free Software Foundation; either version 2 of the | ||
16 | * License, or (at your option) any later version. | ||
17 | * | ||
18 | * This file is distributed in the hope that it will be useful | ||
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
21 | * GNU General Public License for more details. | ||
22 | * | ||
23 | * Or, alternatively | ||
24 | * | ||
25 | * b) Permission is hereby granted, free of charge, to any person | ||
26 | * obtaining a copy of this software and associated documentation | ||
27 | * files (the "Software"), to deal in the Software without | ||
28 | * restriction, including without limitation the rights to use | ||
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | ||
30 | * sell copies of the Software, and to permit persons to whom the | ||
31 | * Software is furnished to do so, subject to the following | ||
32 | * conditions: | ||
33 | * | ||
34 | * The above copyright notice and this permission notice shall be | ||
35 | * included in all copies or substantial portions of the Software. | ||
36 | * | ||
37 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | ||
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | ||
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | ||
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | ||
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
44 | * OTHER DEALINGS IN THE SOFTWARE. | ||
45 | * | ||
46 | * Contains definitions specific to the Armada XP MV78260 SoC that are not | 9 | * Contains definitions specific to the Armada XP MV78260 SoC that are not |
47 | * common to all Armada XP SoCs. | 10 | * common to all Armada XP SoCs. |
48 | */ | 11 | */ |
@@ -87,7 +50,7 @@ | |||
87 | * configured as x4 or quad x1 lanes. One unit is | 50 | * configured as x4 or quad x1 lanes. One unit is |
88 | * x4 only. | 51 | * x4 only. |
89 | */ | 52 | */ |
90 | pcie-controller { | 53 | pciec: pcie@82000000 { |
91 | compatible = "marvell,armada-xp-pcie"; | 54 | compatible = "marvell,armada-xp-pcie"; |
92 | status = "disabled"; | 55 | status = "disabled"; |
93 | device_type = "pci"; | 56 | device_type = "pci"; |
@@ -129,7 +92,7 @@ | |||
129 | 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ | 92 | 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ |
130 | 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; | 93 | 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; |
131 | 94 | ||
132 | pcie@1,0 { | 95 | pcie1: pcie@1,0 { |
133 | device_type = "pci"; | 96 | device_type = "pci"; |
134 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | 97 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; |
135 | reg = <0x0800 0 0 0 0>; | 98 | reg = <0x0800 0 0 0 0>; |
@@ -138,6 +101,7 @@ | |||
138 | #interrupt-cells = <1>; | 101 | #interrupt-cells = <1>; |
139 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | 102 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
140 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | 103 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
104 | bus-range = <0x00 0xff>; | ||
141 | interrupt-map-mask = <0 0 0 0>; | 105 | interrupt-map-mask = <0 0 0 0>; |
142 | interrupt-map = <0 0 0 0 &mpic 58>; | 106 | interrupt-map = <0 0 0 0 &mpic 58>; |
143 | marvell,pcie-port = <0>; | 107 | marvell,pcie-port = <0>; |
@@ -146,7 +110,7 @@ | |||
146 | status = "disabled"; | 110 | status = "disabled"; |
147 | }; | 111 | }; |
148 | 112 | ||
149 | pcie@2,0 { | 113 | pcie2: pcie@2,0 { |
150 | device_type = "pci"; | 114 | device_type = "pci"; |
151 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | 115 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; |
152 | reg = <0x1000 0 0 0 0>; | 116 | reg = <0x1000 0 0 0 0>; |
@@ -155,6 +119,7 @@ | |||
155 | #interrupt-cells = <1>; | 119 | #interrupt-cells = <1>; |
156 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | 120 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
157 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | 121 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
122 | bus-range = <0x00 0xff>; | ||
158 | interrupt-map-mask = <0 0 0 0>; | 123 | interrupt-map-mask = <0 0 0 0>; |
159 | interrupt-map = <0 0 0 0 &mpic 59>; | 124 | interrupt-map = <0 0 0 0 &mpic 59>; |
160 | marvell,pcie-port = <0>; | 125 | marvell,pcie-port = <0>; |
@@ -163,7 +128,7 @@ | |||
163 | status = "disabled"; | 128 | status = "disabled"; |
164 | }; | 129 | }; |
165 | 130 | ||
166 | pcie@3,0 { | 131 | pcie3: pcie@3,0 { |
167 | device_type = "pci"; | 132 | device_type = "pci"; |
168 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | 133 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; |
169 | reg = <0x1800 0 0 0 0>; | 134 | reg = <0x1800 0 0 0 0>; |
@@ -172,6 +137,7 @@ | |||
172 | #interrupt-cells = <1>; | 137 | #interrupt-cells = <1>; |
173 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | 138 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 |
174 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | 139 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; |
140 | bus-range = <0x00 0xff>; | ||
175 | interrupt-map-mask = <0 0 0 0>; | 141 | interrupt-map-mask = <0 0 0 0>; |
176 | interrupt-map = <0 0 0 0 &mpic 60>; | 142 | interrupt-map = <0 0 0 0 &mpic 60>; |
177 | marvell,pcie-port = <0>; | 143 | marvell,pcie-port = <0>; |
@@ -180,7 +146,7 @@ | |||
180 | status = "disabled"; | 146 | status = "disabled"; |
181 | }; | 147 | }; |
182 | 148 | ||
183 | pcie@4,0 { | 149 | pcie4: pcie@4,0 { |
184 | device_type = "pci"; | 150 | device_type = "pci"; |
185 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | 151 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; |
186 | reg = <0x2000 0 0 0 0>; | 152 | reg = <0x2000 0 0 0 0>; |
@@ -189,6 +155,7 @@ | |||
189 | #interrupt-cells = <1>; | 155 | #interrupt-cells = <1>; |
190 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | 156 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 |
191 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | 157 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; |
158 | bus-range = <0x00 0xff>; | ||
192 | interrupt-map-mask = <0 0 0 0>; | 159 | interrupt-map-mask = <0 0 0 0>; |
193 | interrupt-map = <0 0 0 0 &mpic 61>; | 160 | interrupt-map = <0 0 0 0 &mpic 61>; |
194 | marvell,pcie-port = <0>; | 161 | marvell,pcie-port = <0>; |
@@ -197,7 +164,7 @@ | |||
197 | status = "disabled"; | 164 | status = "disabled"; |
198 | }; | 165 | }; |
199 | 166 | ||
200 | pcie@5,0 { | 167 | pcie5: pcie@5,0 { |
201 | device_type = "pci"; | 168 | device_type = "pci"; |
202 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | 169 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; |
203 | reg = <0x2800 0 0 0 0>; | 170 | reg = <0x2800 0 0 0 0>; |
@@ -206,6 +173,7 @@ | |||
206 | #interrupt-cells = <1>; | 173 | #interrupt-cells = <1>; |
207 | ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 | 174 | ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 |
208 | 0x81000000 0 0 0x81000000 0x5 0 1 0>; | 175 | 0x81000000 0 0 0x81000000 0x5 0 1 0>; |
176 | bus-range = <0x00 0xff>; | ||
209 | interrupt-map-mask = <0 0 0 0>; | 177 | interrupt-map-mask = <0 0 0 0>; |
210 | interrupt-map = <0 0 0 0 &mpic 62>; | 178 | interrupt-map = <0 0 0 0 &mpic 62>; |
211 | marvell,pcie-port = <1>; | 179 | marvell,pcie-port = <1>; |
@@ -214,7 +182,7 @@ | |||
214 | status = "disabled"; | 182 | status = "disabled"; |
215 | }; | 183 | }; |
216 | 184 | ||
217 | pcie@6,0 { | 185 | pcie6: pcie@6,0 { |
218 | device_type = "pci"; | 186 | device_type = "pci"; |
219 | assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; | 187 | assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; |
220 | reg = <0x3000 0 0 0 0>; | 188 | reg = <0x3000 0 0 0 0>; |
@@ -223,6 +191,7 @@ | |||
223 | #interrupt-cells = <1>; | 191 | #interrupt-cells = <1>; |
224 | ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 | 192 | ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 |
225 | 0x81000000 0 0 0x81000000 0x6 0 1 0>; | 193 | 0x81000000 0 0 0x81000000 0x6 0 1 0>; |
194 | bus-range = <0x00 0xff>; | ||
226 | interrupt-map-mask = <0 0 0 0>; | 195 | interrupt-map-mask = <0 0 0 0>; |
227 | interrupt-map = <0 0 0 0 &mpic 63>; | 196 | interrupt-map = <0 0 0 0 &mpic 63>; |
228 | marvell,pcie-port = <1>; | 197 | marvell,pcie-port = <1>; |
@@ -231,7 +200,7 @@ | |||
231 | status = "disabled"; | 200 | status = "disabled"; |
232 | }; | 201 | }; |
233 | 202 | ||
234 | pcie@7,0 { | 203 | pcie7: pcie@7,0 { |
235 | device_type = "pci"; | 204 | device_type = "pci"; |
236 | assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; | 205 | assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; |
237 | reg = <0x3800 0 0 0 0>; | 206 | reg = <0x3800 0 0 0 0>; |
@@ -240,6 +209,7 @@ | |||
240 | #interrupt-cells = <1>; | 209 | #interrupt-cells = <1>; |
241 | ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 | 210 | ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 |
242 | 0x81000000 0 0 0x81000000 0x7 0 1 0>; | 211 | 0x81000000 0 0 0x81000000 0x7 0 1 0>; |
212 | bus-range = <0x00 0xff>; | ||
243 | interrupt-map-mask = <0 0 0 0>; | 213 | interrupt-map-mask = <0 0 0 0>; |
244 | interrupt-map = <0 0 0 0 &mpic 64>; | 214 | interrupt-map = <0 0 0 0 &mpic 64>; |
245 | marvell,pcie-port = <1>; | 215 | marvell,pcie-port = <1>; |
@@ -248,7 +218,7 @@ | |||
248 | status = "disabled"; | 218 | status = "disabled"; |
249 | }; | 219 | }; |
250 | 220 | ||
251 | pcie@8,0 { | 221 | pcie8: pcie@8,0 { |
252 | device_type = "pci"; | 222 | device_type = "pci"; |
253 | assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; | 223 | assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; |
254 | reg = <0x4000 0 0 0 0>; | 224 | reg = <0x4000 0 0 0 0>; |
@@ -257,6 +227,7 @@ | |||
257 | #interrupt-cells = <1>; | 227 | #interrupt-cells = <1>; |
258 | ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 | 228 | ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 |
259 | 0x81000000 0 0 0x81000000 0x8 0 1 0>; | 229 | 0x81000000 0 0 0x81000000 0x8 0 1 0>; |
230 | bus-range = <0x00 0xff>; | ||
260 | interrupt-map-mask = <0 0 0 0>; | 231 | interrupt-map-mask = <0 0 0 0>; |
261 | interrupt-map = <0 0 0 0 &mpic 65>; | 232 | interrupt-map = <0 0 0 0 &mpic 65>; |
262 | marvell,pcie-port = <1>; | 233 | marvell,pcie-port = <1>; |
@@ -265,7 +236,7 @@ | |||
265 | status = "disabled"; | 236 | status = "disabled"; |
266 | }; | 237 | }; |
267 | 238 | ||
268 | pcie@9,0 { | 239 | pcie9: pcie@9,0 { |
269 | device_type = "pci"; | 240 | device_type = "pci"; |
270 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | 241 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; |
271 | reg = <0x4800 0 0 0 0>; | 242 | reg = <0x4800 0 0 0 0>; |
@@ -274,6 +245,7 @@ | |||
274 | #interrupt-cells = <1>; | 245 | #interrupt-cells = <1>; |
275 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 | 246 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 |
276 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; | 247 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; |
248 | bus-range = <0x00 0xff>; | ||
277 | interrupt-map-mask = <0 0 0 0>; | 249 | interrupt-map-mask = <0 0 0 0>; |
278 | interrupt-map = <0 0 0 0 &mpic 99>; | 250 | interrupt-map = <0 0 0 0 &mpic 99>; |
279 | marvell,pcie-port = <2>; | 251 | marvell,pcie-port = <2>; |
@@ -285,29 +257,38 @@ | |||
285 | 257 | ||
286 | internal-regs { | 258 | internal-regs { |
287 | gpio0: gpio@18100 { | 259 | gpio0: gpio@18100 { |
288 | compatible = "marvell,orion-gpio"; | 260 | compatible = "marvell,armada-370-gpio", |
289 | reg = <0x18100 0x40>; | 261 | "marvell,orion-gpio"; |
262 | reg = <0x18100 0x40>, <0x181c0 0x08>; | ||
263 | reg-names = "gpio", "pwm"; | ||
290 | ngpios = <32>; | 264 | ngpios = <32>; |
291 | gpio-controller; | 265 | gpio-controller; |
292 | #gpio-cells = <2>; | 266 | #gpio-cells = <2>; |
267 | #pwm-cells = <2>; | ||
293 | interrupt-controller; | 268 | interrupt-controller; |
294 | #interrupt-cells = <2>; | 269 | #interrupt-cells = <2>; |
295 | interrupts = <82>, <83>, <84>, <85>; | 270 | interrupts = <82>, <83>, <84>, <85>; |
271 | clocks = <&coreclk 0>; | ||
296 | }; | 272 | }; |
297 | 273 | ||
298 | gpio1: gpio@18140 { | 274 | gpio1: gpio@18140 { |
299 | compatible = "marvell,orion-gpio"; | 275 | compatible = "marvell,armada-370-gpio", |
300 | reg = <0x18140 0x40>; | 276 | "marvell,orion-gpio"; |
277 | reg = <0x18140 0x40>, <0x181c8 0x08>; | ||
278 | reg-names = "gpio", "pwm"; | ||
301 | ngpios = <32>; | 279 | ngpios = <32>; |
302 | gpio-controller; | 280 | gpio-controller; |
303 | #gpio-cells = <2>; | 281 | #gpio-cells = <2>; |
282 | #pwm-cells = <2>; | ||
304 | interrupt-controller; | 283 | interrupt-controller; |
305 | #interrupt-cells = <2>; | 284 | #interrupt-cells = <2>; |
306 | interrupts = <87>, <88>, <89>, <90>; | 285 | interrupts = <87>, <88>, <89>, <90>; |
286 | clocks = <&coreclk 0>; | ||
307 | }; | 287 | }; |
308 | 288 | ||
309 | gpio2: gpio@18180 { | 289 | gpio2: gpio@18180 { |
310 | compatible = "marvell,orion-gpio"; | 290 | compatible = "marvell,armada-370-gpio", |
291 | "marvell,orion-gpio"; | ||
311 | reg = <0x18180 0x40>; | 292 | reg = <0x18180 0x40>; |
312 | ngpios = <3>; | 293 | ngpios = <3>; |
313 | gpio-controller; | 294 | gpio-controller; |