diff options
Diffstat (limited to 'arch/arm/dts/armada-xp-mv78460.dtsi')
-rw-r--r-- | arch/arm/dts/armada-xp-mv78460.dtsi | 90 |
1 files changed, 36 insertions, 54 deletions
diff --git a/arch/arm/dts/armada-xp-mv78460.dtsi b/arch/arm/dts/armada-xp-mv78460.dtsi index 0e24f1a385..230a3fd36b 100644 --- a/arch/arm/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/dts/armada-xp-mv78460.dtsi | |||
@@ -1,3 +1,4 @@ | |||
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
1 | /* | 2 | /* |
2 | * Device Tree Include file for Marvell Armada XP family SoC | 3 | * Device Tree Include file for Marvell Armada XP family SoC |
3 | * | 4 | * |
@@ -5,44 +6,6 @@ | |||
5 | * | 6 | * |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
7 | * | 8 | * |
8 | * This file is dual-licensed: you can use it either under the terms | ||
9 | * of the GPL or the X11 license, at your option. Note that this dual | ||
10 | * licensing only applies to this file, and not this project as a | ||
11 | * whole. | ||
12 | * | ||
13 | * a) This file is free software; you can redistribute it and/or | ||
14 | * modify it under the terms of the GNU General Public License as | ||
15 | * published by the Free Software Foundation; either version 2 of the | ||
16 | * License, or (at your option) any later version. | ||
17 | * | ||
18 | * This file is distributed in the hope that it will be useful | ||
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
21 | * GNU General Public License for more details. | ||
22 | * | ||
23 | * Or, alternatively | ||
24 | * | ||
25 | * b) Permission is hereby granted, free of charge, to any person | ||
26 | * obtaining a copy of this software and associated documentation | ||
27 | * files (the "Software"), to deal in the Software without | ||
28 | * restriction, including without limitation the rights to use | ||
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | ||
30 | * sell copies of the Software, and to permit persons to whom the | ||
31 | * Software is furnished to do so, subject to the following | ||
32 | * conditions: | ||
33 | * | ||
34 | * The above copyright notice and this permission notice shall be | ||
35 | * included in all copies or substantial portions of the Software. | ||
36 | * | ||
37 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | ||
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | ||
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | ||
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | ||
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
44 | * OTHER DEALINGS IN THE SOFTWARE. | ||
45 | * | ||
46 | * Contains definitions specific to the Armada XP MV78460 SoC that are not | 9 | * Contains definitions specific to the Armada XP MV78460 SoC that are not |
47 | * common to all Armada XP SoCs. | 10 | * common to all Armada XP SoCs. |
48 | */ | 11 | */ |
@@ -104,7 +67,7 @@ | |||
104 | * configured as x4 or quad x1 lanes. Two units are | 67 | * configured as x4 or quad x1 lanes. Two units are |
105 | * x4/x1. | 68 | * x4/x1. |
106 | */ | 69 | */ |
107 | pcie-controller { | 70 | pciec: pcie@82000000 { |
108 | compatible = "marvell,armada-xp-pcie"; | 71 | compatible = "marvell,armada-xp-pcie"; |
109 | status = "disabled"; | 72 | status = "disabled"; |
110 | device_type = "pci"; | 73 | device_type = "pci"; |
@@ -150,7 +113,7 @@ | |||
150 | 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ | 113 | 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ |
151 | 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; | 114 | 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; |
152 | 115 | ||
153 | pcie@1,0 { | 116 | pcie1: pcie@1,0 { |
154 | device_type = "pci"; | 117 | device_type = "pci"; |
155 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | 118 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; |
156 | reg = <0x0800 0 0 0 0>; | 119 | reg = <0x0800 0 0 0 0>; |
@@ -159,6 +122,7 @@ | |||
159 | #interrupt-cells = <1>; | 122 | #interrupt-cells = <1>; |
160 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | 123 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
161 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | 124 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
125 | bus-range = <0x00 0xff>; | ||
162 | interrupt-map-mask = <0 0 0 0>; | 126 | interrupt-map-mask = <0 0 0 0>; |
163 | interrupt-map = <0 0 0 0 &mpic 58>; | 127 | interrupt-map = <0 0 0 0 &mpic 58>; |
164 | marvell,pcie-port = <0>; | 128 | marvell,pcie-port = <0>; |
@@ -167,7 +131,7 @@ | |||
167 | status = "disabled"; | 131 | status = "disabled"; |
168 | }; | 132 | }; |
169 | 133 | ||
170 | pcie@2,0 { | 134 | pcie2: pcie@2,0 { |
171 | device_type = "pci"; | 135 | device_type = "pci"; |
172 | assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; | 136 | assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; |
173 | reg = <0x1000 0 0 0 0>; | 137 | reg = <0x1000 0 0 0 0>; |
@@ -176,6 +140,7 @@ | |||
176 | #interrupt-cells = <1>; | 140 | #interrupt-cells = <1>; |
177 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | 141 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
178 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | 142 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
143 | bus-range = <0x00 0xff>; | ||
179 | interrupt-map-mask = <0 0 0 0>; | 144 | interrupt-map-mask = <0 0 0 0>; |
180 | interrupt-map = <0 0 0 0 &mpic 59>; | 145 | interrupt-map = <0 0 0 0 &mpic 59>; |
181 | marvell,pcie-port = <0>; | 146 | marvell,pcie-port = <0>; |
@@ -184,7 +149,7 @@ | |||
184 | status = "disabled"; | 149 | status = "disabled"; |
185 | }; | 150 | }; |
186 | 151 | ||
187 | pcie@3,0 { | 152 | pcie3: pcie@3,0 { |
188 | device_type = "pci"; | 153 | device_type = "pci"; |
189 | assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; | 154 | assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; |
190 | reg = <0x1800 0 0 0 0>; | 155 | reg = <0x1800 0 0 0 0>; |
@@ -193,6 +158,7 @@ | |||
193 | #interrupt-cells = <1>; | 158 | #interrupt-cells = <1>; |
194 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | 159 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 |
195 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | 160 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; |
161 | bus-range = <0x00 0xff>; | ||
196 | interrupt-map-mask = <0 0 0 0>; | 162 | interrupt-map-mask = <0 0 0 0>; |
197 | interrupt-map = <0 0 0 0 &mpic 60>; | 163 | interrupt-map = <0 0 0 0 &mpic 60>; |
198 | marvell,pcie-port = <0>; | 164 | marvell,pcie-port = <0>; |
@@ -201,7 +167,7 @@ | |||
201 | status = "disabled"; | 167 | status = "disabled"; |
202 | }; | 168 | }; |
203 | 169 | ||
204 | pcie@4,0 { | 170 | pcie4: pcie@4,0 { |
205 | device_type = "pci"; | 171 | device_type = "pci"; |
206 | assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; | 172 | assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; |
207 | reg = <0x2000 0 0 0 0>; | 173 | reg = <0x2000 0 0 0 0>; |
@@ -210,6 +176,7 @@ | |||
210 | #interrupt-cells = <1>; | 176 | #interrupt-cells = <1>; |
211 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | 177 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 |
212 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | 178 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; |
179 | bus-range = <0x00 0xff>; | ||
213 | interrupt-map-mask = <0 0 0 0>; | 180 | interrupt-map-mask = <0 0 0 0>; |
214 | interrupt-map = <0 0 0 0 &mpic 61>; | 181 | interrupt-map = <0 0 0 0 &mpic 61>; |
215 | marvell,pcie-port = <0>; | 182 | marvell,pcie-port = <0>; |
@@ -218,7 +185,7 @@ | |||
218 | status = "disabled"; | 185 | status = "disabled"; |
219 | }; | 186 | }; |
220 | 187 | ||
221 | pcie@5,0 { | 188 | pcie5: pcie@5,0 { |
222 | device_type = "pci"; | 189 | device_type = "pci"; |
223 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | 190 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; |
224 | reg = <0x2800 0 0 0 0>; | 191 | reg = <0x2800 0 0 0 0>; |
@@ -227,6 +194,7 @@ | |||
227 | #interrupt-cells = <1>; | 194 | #interrupt-cells = <1>; |
228 | ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 | 195 | ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 |
229 | 0x81000000 0 0 0x81000000 0x5 0 1 0>; | 196 | 0x81000000 0 0 0x81000000 0x5 0 1 0>; |
197 | bus-range = <0x00 0xff>; | ||
230 | interrupt-map-mask = <0 0 0 0>; | 198 | interrupt-map-mask = <0 0 0 0>; |
231 | interrupt-map = <0 0 0 0 &mpic 62>; | 199 | interrupt-map = <0 0 0 0 &mpic 62>; |
232 | marvell,pcie-port = <1>; | 200 | marvell,pcie-port = <1>; |
@@ -235,7 +203,7 @@ | |||
235 | status = "disabled"; | 203 | status = "disabled"; |
236 | }; | 204 | }; |
237 | 205 | ||
238 | pcie@6,0 { | 206 | pcie6: pcie@6,0 { |
239 | device_type = "pci"; | 207 | device_type = "pci"; |
240 | assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; | 208 | assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; |
241 | reg = <0x3000 0 0 0 0>; | 209 | reg = <0x3000 0 0 0 0>; |
@@ -244,6 +212,7 @@ | |||
244 | #interrupt-cells = <1>; | 212 | #interrupt-cells = <1>; |
245 | ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 | 213 | ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 |
246 | 0x81000000 0 0 0x81000000 0x6 0 1 0>; | 214 | 0x81000000 0 0 0x81000000 0x6 0 1 0>; |
215 | bus-range = <0x00 0xff>; | ||
247 | interrupt-map-mask = <0 0 0 0>; | 216 | interrupt-map-mask = <0 0 0 0>; |
248 | interrupt-map = <0 0 0 0 &mpic 63>; | 217 | interrupt-map = <0 0 0 0 &mpic 63>; |
249 | marvell,pcie-port = <1>; | 218 | marvell,pcie-port = <1>; |
@@ -252,7 +221,7 @@ | |||
252 | status = "disabled"; | 221 | status = "disabled"; |
253 | }; | 222 | }; |
254 | 223 | ||
255 | pcie@7,0 { | 224 | pcie7: pcie@7,0 { |
256 | device_type = "pci"; | 225 | device_type = "pci"; |
257 | assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; | 226 | assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; |
258 | reg = <0x3800 0 0 0 0>; | 227 | reg = <0x3800 0 0 0 0>; |
@@ -261,6 +230,7 @@ | |||
261 | #interrupt-cells = <1>; | 230 | #interrupt-cells = <1>; |
262 | ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 | 231 | ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 |
263 | 0x81000000 0 0 0x81000000 0x7 0 1 0>; | 232 | 0x81000000 0 0 0x81000000 0x7 0 1 0>; |
233 | bus-range = <0x00 0xff>; | ||
264 | interrupt-map-mask = <0 0 0 0>; | 234 | interrupt-map-mask = <0 0 0 0>; |
265 | interrupt-map = <0 0 0 0 &mpic 64>; | 235 | interrupt-map = <0 0 0 0 &mpic 64>; |
266 | marvell,pcie-port = <1>; | 236 | marvell,pcie-port = <1>; |
@@ -269,7 +239,7 @@ | |||
269 | status = "disabled"; | 239 | status = "disabled"; |
270 | }; | 240 | }; |
271 | 241 | ||
272 | pcie@8,0 { | 242 | pcie8: pcie@8,0 { |
273 | device_type = "pci"; | 243 | device_type = "pci"; |
274 | assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; | 244 | assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; |
275 | reg = <0x4000 0 0 0 0>; | 245 | reg = <0x4000 0 0 0 0>; |
@@ -278,6 +248,7 @@ | |||
278 | #interrupt-cells = <1>; | 248 | #interrupt-cells = <1>; |
279 | ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 | 249 | ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 |
280 | 0x81000000 0 0 0x81000000 0x8 0 1 0>; | 250 | 0x81000000 0 0 0x81000000 0x8 0 1 0>; |
251 | bus-range = <0x00 0xff>; | ||
281 | interrupt-map-mask = <0 0 0 0>; | 252 | interrupt-map-mask = <0 0 0 0>; |
282 | interrupt-map = <0 0 0 0 &mpic 65>; | 253 | interrupt-map = <0 0 0 0 &mpic 65>; |
283 | marvell,pcie-port = <1>; | 254 | marvell,pcie-port = <1>; |
@@ -286,7 +257,7 @@ | |||
286 | status = "disabled"; | 257 | status = "disabled"; |
287 | }; | 258 | }; |
288 | 259 | ||
289 | pcie@9,0 { | 260 | pcie9: pcie@9,0 { |
290 | device_type = "pci"; | 261 | device_type = "pci"; |
291 | assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; | 262 | assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; |
292 | reg = <0x4800 0 0 0 0>; | 263 | reg = <0x4800 0 0 0 0>; |
@@ -295,6 +266,7 @@ | |||
295 | #interrupt-cells = <1>; | 266 | #interrupt-cells = <1>; |
296 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 | 267 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 |
297 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; | 268 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; |
269 | bus-range = <0x00 0xff>; | ||
298 | interrupt-map-mask = <0 0 0 0>; | 270 | interrupt-map-mask = <0 0 0 0>; |
299 | interrupt-map = <0 0 0 0 &mpic 99>; | 271 | interrupt-map = <0 0 0 0 &mpic 99>; |
300 | marvell,pcie-port = <2>; | 272 | marvell,pcie-port = <2>; |
@@ -303,7 +275,7 @@ | |||
303 | status = "disabled"; | 275 | status = "disabled"; |
304 | }; | 276 | }; |
305 | 277 | ||
306 | pcie@10,0 { | 278 | pcie10: pcie@a,0 { |
307 | device_type = "pci"; | 279 | device_type = "pci"; |
308 | assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; | 280 | assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; |
309 | reg = <0x5000 0 0 0 0>; | 281 | reg = <0x5000 0 0 0 0>; |
@@ -312,6 +284,7 @@ | |||
312 | #interrupt-cells = <1>; | 284 | #interrupt-cells = <1>; |
313 | ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 | 285 | ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 |
314 | 0x81000000 0 0 0x81000000 0xa 0 1 0>; | 286 | 0x81000000 0 0 0x81000000 0xa 0 1 0>; |
287 | bus-range = <0x00 0xff>; | ||
315 | interrupt-map-mask = <0 0 0 0>; | 288 | interrupt-map-mask = <0 0 0 0>; |
316 | interrupt-map = <0 0 0 0 &mpic 103>; | 289 | interrupt-map = <0 0 0 0 &mpic 103>; |
317 | marvell,pcie-port = <3>; | 290 | marvell,pcie-port = <3>; |
@@ -323,29 +296,38 @@ | |||
323 | 296 | ||
324 | internal-regs { | 297 | internal-regs { |
325 | gpio0: gpio@18100 { | 298 | gpio0: gpio@18100 { |
326 | compatible = "marvell,orion-gpio"; | 299 | compatible = "marvell,armada-370-gpio", |
327 | reg = <0x18100 0x40>; | 300 | "marvell,orion-gpio"; |
301 | reg = <0x18100 0x40>, <0x181c0 0x08>; | ||
302 | reg-names = "gpio", "pwm"; | ||
328 | ngpios = <32>; | 303 | ngpios = <32>; |
329 | gpio-controller; | 304 | gpio-controller; |
330 | #gpio-cells = <2>; | 305 | #gpio-cells = <2>; |
306 | #pwm-cells = <2>; | ||
331 | interrupt-controller; | 307 | interrupt-controller; |
332 | #interrupt-cells = <2>; | 308 | #interrupt-cells = <2>; |
333 | interrupts = <82>, <83>, <84>, <85>; | 309 | interrupts = <82>, <83>, <84>, <85>; |
310 | clocks = <&coreclk 0>; | ||
334 | }; | 311 | }; |
335 | 312 | ||
336 | gpio1: gpio@18140 { | 313 | gpio1: gpio@18140 { |
337 | compatible = "marvell,orion-gpio"; | 314 | compatible = "marvell,armada-370-gpio", |
338 | reg = <0x18140 0x40>; | 315 | "marvell,orion-gpio"; |
316 | reg = <0x18140 0x40>, <0x181c8 0x08>; | ||
317 | reg-names = "gpio", "pwm"; | ||
339 | ngpios = <32>; | 318 | ngpios = <32>; |
340 | gpio-controller; | 319 | gpio-controller; |
341 | #gpio-cells = <2>; | 320 | #gpio-cells = <2>; |
321 | #pwm-cells = <2>; | ||
342 | interrupt-controller; | 322 | interrupt-controller; |
343 | #interrupt-cells = <2>; | 323 | #interrupt-cells = <2>; |
344 | interrupts = <87>, <88>, <89>, <90>; | 324 | interrupts = <87>, <88>, <89>, <90>; |
325 | clocks = <&coreclk 0>; | ||
345 | }; | 326 | }; |
346 | 327 | ||
347 | gpio2: gpio@18180 { | 328 | gpio2: gpio@18180 { |
348 | compatible = "marvell,orion-gpio"; | 329 | compatible = "marvell,armada-370-gpio", |
330 | "marvell,orion-gpio"; | ||
349 | reg = <0x18180 0x40>; | 331 | reg = <0x18180 0x40>; |
350 | ngpios = <3>; | 332 | ngpios = <3>; |
351 | gpio-controller; | 333 | gpio-controller; |