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-rw-r--r--arch/arm/dts/armada-xp.dtsi214
1 files changed, 119 insertions, 95 deletions
diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi
index 3fac39e41d..d856d96022 100644
--- a/arch/arm/dts/armada-xp.dtsi
+++ b/arch/arm/dts/armada-xp.dtsi
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1/* 2/*
2 * Device Tree Include file for Marvell Armada XP family SoC 3 * Device Tree Include file for Marvell Armada XP family SoC
3 * 4 *
@@ -8,44 +9,6 @@
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * Ben Dooks <ben.dooks@codethink.co.uk>
10 * 11 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * Contains definitions specific to the Armada XP SoC that are not 12 * Contains definitions specific to the Armada XP SoC that are not
50 * common to all Armada SoCs. 13 * common to all Armada SoCs.
51 */ 14 */
@@ -53,6 +16,9 @@
53#include "armada-370-xp.dtsi" 16#include "armada-370-xp.dtsi"
54 17
55/ { 18/ {
19 #address-cells = <2>;
20 #size-cells = <2>;
21
56 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
57 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
58 24
@@ -71,12 +37,12 @@
71 }; 37 };
72 38
73 internal-regs { 39 internal-regs {
74 sdramc@1400 { 40 sdramc: sdramc@1400 {
75 compatible = "marvell,armada-xp-sdram-controller"; 41 compatible = "marvell,armada-xp-sdram-controller";
76 reg = <0x1400 0x500>; 42 reg = <0x1400 0x500>;
77 }; 43 };
78 44
79 L2: l2-cache { 45 L2: l2-cache@8000 {
80 compatible = "marvell,aurora-system-cache"; 46 compatible = "marvell,aurora-system-cache";
81 reg = <0x08000 0x1000>; 47 reg = <0x08000 0x1000>;
82 cache-id-part = <0x100>; 48 cache-id-part = <0x100>;
@@ -85,29 +51,6 @@
85 wt-override; 51 wt-override;
86 }; 52 };
87 53
88 spi0: spi@10600 {
89 compatible = "marvell,armada-xp-spi",
90 "marvell,orion-spi";
91 pinctrl-0 = <&spi0_pins>;
92 pinctrl-names = "default";
93 };
94
95 spi1: spi@10680 {
96 compatible = "marvell,armada-xp-spi",
97 "marvell,orion-spi";
98 };
99
100
101 i2c0: i2c@11000 {
102 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
103 reg = <0x11000 0x100>;
104 };
105
106 i2c1: i2c@11100 {
107 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
108 reg = <0x11100 0x100>;
109 };
110
111 uart2: serial@12200 { 54 uart2: serial@12200 {
112 compatible = "snps,dw-apb-uart"; 55 compatible = "snps,dw-apb-uart";
113 pinctrl-0 = <&uart2_pins>; 56 pinctrl-0 = <&uart2_pins>;
@@ -132,7 +75,7 @@
132 status = "disabled"; 75 status = "disabled";
133 }; 76 };
134 77
135 system-controller@18200 { 78 systemc: system-controller@18200 {
136 compatible = "marvell,armada-370-xp-system-controller"; 79 compatible = "marvell,armada-370-xp-system-controller";
137 reg = <0x18200 0x500>; 80 reg = <0x18200 0x500>;
138 }; 81 };
@@ -150,7 +93,7 @@
150 #clock-cells = <1>; 93 #clock-cells = <1>;
151 }; 94 };
152 95
153 thermal@182b0 { 96 thermal: thermal@182b0 {
154 compatible = "marvell,armadaxp-thermal"; 97 compatible = "marvell,armadaxp-thermal";
155 reg = <0x182b0 0x4 98 reg = <0x182b0 0x4
156 0x184d0 0x4>; 99 0x184d0 0x4>;
@@ -164,25 +107,9 @@
164 clocks = <&coreclk 1>; 107 clocks = <&coreclk 1>;
165 }; 108 };
166 109
167 interrupt-controller@20a00 { 110 cpu-config@21000 {
168 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 111 compatible = "marvell,armada-xp-cpu-config";
169 }; 112 reg = <0x21000 0x8>;
170
171 timer@20300 {
172 compatible = "marvell,armada-xp-timer";
173 clocks = <&coreclk 2>, <&refclk>;
174 clock-names = "nbclk", "fixed";
175 };
176
177 watchdog@20300 {
178 compatible = "marvell,armada-xp-wdt";
179 clocks = <&coreclk 2>, <&refclk>;
180 clock-names = "nbclk", "fixed";
181 };
182
183 cpurst@20800 {
184 compatible = "marvell,armada-370-cpu-reset";
185 reg = <0x20800 0x20>;
186 }; 113 };
187 114
188 eth2: ethernet@30000 { 115 eth2: ethernet@30000 {
@@ -193,15 +120,7 @@
193 status = "disabled"; 120 status = "disabled";
194 }; 121 };
195 122
196 usb@50000 { 123 usb2: usb@52000 {
197 clocks = <&gateclk 18>;
198 };
199
200 usb@51000 {
201 clocks = <&gateclk 19>;
202 };
203
204 usb@52000 {
205 compatible = "marvell,orion-ehci"; 124 compatible = "marvell,orion-ehci";
206 reg = <0x52000 0x500>; 125 reg = <0x52000 0x500>;
207 interrupts = <47>; 126 interrupts = <47>;
@@ -209,7 +128,7 @@
209 status = "disabled"; 128 status = "disabled";
210 }; 129 };
211 130
212 xor@60900 { 131 xor1: xor@60900 {
213 compatible = "marvell,orion-xor"; 132 compatible = "marvell,orion-xor";
214 reg = <0x60900 0x100 133 reg = <0x60900 0x100
215 0x60b00 0x100>; 134 0x60b00 0x100>;
@@ -237,7 +156,27 @@
237 compatible = "marvell,armada-xp-neta"; 156 compatible = "marvell,armada-xp-neta";
238 }; 157 };
239 158
240 xor@f0900 { 159 cesa: crypto@90000 {
160 compatible = "marvell,armada-xp-crypto";
161 reg = <0x90000 0x10000>;
162 reg-names = "regs";
163 interrupts = <48>, <49>;
164 clocks = <&gateclk 23>, <&gateclk 23>;
165 clock-names = "cesa0", "cesa1";
166 marvell,crypto-srams = <&crypto_sram0>,
167 <&crypto_sram1>;
168 marvell,crypto-sram-size = <0x800>;
169 };
170
171 bm: bm@c0000 {
172 compatible = "marvell,armada-380-neta-bm";
173 reg = <0xc0000 0xac>;
174 clocks = <&gateclk 13>;
175 internal-mem = <&bm_bppi>;
176 status = "disabled";
177 };
178
179 xor0: xor@f0900 {
241 compatible = "marvell,orion-xor"; 180 compatible = "marvell,orion-xor";
242 reg = <0xF0900 0x100 181 reg = <0xF0900 0x100
243 0xF0B00 0x100>; 182 0xF0B00 0x100>;
@@ -257,6 +196,35 @@
257 }; 196 };
258 }; 197 };
259 }; 198 };
199
200 crypto_sram0: sa-sram0 {
201 compatible = "mmio-sram";
202 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
203 clocks = <&gateclk 23>;
204 #address-cells = <1>;
205 #size-cells = <1>;
206 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
207 };
208
209 crypto_sram1: sa-sram1 {
210 compatible = "mmio-sram";
211 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
212 clocks = <&gateclk 23>;
213 #address-cells = <1>;
214 #size-cells = <1>;
215 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
216 };
217
218 bm_bppi: bm-bppi {
219 compatible = "mmio-sram";
220 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
221 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
222 #address-cells = <1>;
223 #size-cells = <1>;
224 clocks = <&gateclk 13>;
225 no-memory-wc;
226 status = "disabled";
227 };
260 }; 228 };
261 229
262 clocks { 230 clocks {
@@ -269,6 +237,44 @@
269 }; 237 };
270}; 238};
271 239
240&i2c0 {
241 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
242 reg = <0x11000 0x100>;
243};
244
245&i2c1 {
246 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
247 reg = <0x11100 0x100>;
248};
249
250&mpic {
251 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
252};
253
254&timer {
255 compatible = "marvell,armada-xp-timer";
256 clocks = <&coreclk 2>, <&refclk>;
257 clock-names = "nbclk", "fixed";
258};
259
260&watchdog {
261 compatible = "marvell,armada-xp-wdt";
262 clocks = <&coreclk 2>, <&refclk>;
263 clock-names = "nbclk", "fixed";
264};
265
266&cpurst {
267 reg = <0x20800 0x20>;
268};
269
270&usb0 {
271 clocks = <&gateclk 18>;
272};
273
274&usb1 {
275 clocks = <&gateclk 19>;
276};
277
272&pinctrl { 278&pinctrl {
273 ge0_gmii_pins: ge0-gmii-pins { 279 ge0_gmii_pins: ge0-gmii-pins {
274 marvell,pins = 280 marvell,pins =
@@ -309,6 +315,12 @@
309 marvell,function = "spi0"; 315 marvell,function = "spi0";
310 }; 316 };
311 317
318 spi1_pins: spi1-pins {
319 marvell,pins = "mpp13", "mpp14",
320 "mpp16", "mpp17";
321 marvell,function = "spi1";
322 };
323
312 uart2_pins: uart2-pins { 324 uart2_pins: uart2-pins {
313 marvell,pins = "mpp42", "mpp43"; 325 marvell,pins = "mpp42", "mpp43";
314 marvell,function = "uart2"; 326 marvell,function = "uart2";
@@ -319,3 +331,15 @@
319 marvell,function = "uart3"; 331 marvell,function = "uart3";
320 }; 332 };
321}; 333};
334
335&spi0 {
336 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
337 pinctrl-0 = <&spi0_pins>;
338 pinctrl-names = "default";
339};
340
341&spi1 {
342 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
343 pinctrl-0 = <&spi1_pins>;
344 pinctrl-names = "default";
345};
generated by cgit v1.2.3 (git 2.39.2)