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-rw-r--r--arch/arm/dts/r8a77995-draak.dts386
1 files changed, 319 insertions, 67 deletions
diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts
index 711d487a8e..db2bed1751 100644
--- a/arch/arm/dts/r8a77995-draak.dts
+++ b/arch/arm/dts/r8a77995-draak.dts
@@ -2,7 +2,7 @@
2/* 2/*
3 * Device Tree Source for the Draak board 3 * Device Tree Source for the Draak board
4 * 4 *
5 * Copyright (C) 2016 Renesas Electronics Corp. 5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba 6 * Copyright (C) 2017 Glider bvba
7 */ 7 */
8 8
@@ -24,18 +24,52 @@
24 stdout-path = "serial0:115200n8"; 24 stdout-path = "serial0:115200n8";
25 }; 25 };
26 26
27 vga { 27 backlight: backlight {
28 compatible = "vga-connector"; 28 compatible = "pwm-backlight";
29 pwms = <&pwm1 0 50000>;
30
31 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
32 default-brightness-level = <10>;
33
34 power-supply = <&reg_12p0v>;
35 enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
36 };
37
38 composite-in {
39 compatible = "composite-video-connector";
29 40
30 port { 41 port {
31 vga_in: endpoint { 42 composite_con_in: endpoint {
32 remote-endpoint = <&adv7123_out>; 43 remote-endpoint = <&adv7180_in>;
33 }; 44 };
34 }; 45 };
35 }; 46 };
36 47
37 vga-encoder { 48 hdmi-in {
38 compatible = "adi,adv7123"; 49 compatible = "hdmi-connector";
50 type = "a";
51
52 port {
53 hdmi_con_in: endpoint {
54 remote-endpoint = <&adv7612_in>;
55 };
56 };
57 };
58
59 hdmi-out {
60 compatible = "hdmi-connector";
61 type = "a";
62
63 port {
64 hdmi_con_out: endpoint {
65 remote-endpoint = <&adv7511_out>;
66 };
67 };
68 };
69
70 lvds-decoder {
71 compatible = "thine,thc63lvd1024";
72 vcc-supply = <&reg_3p3v>;
39 73
40 ports { 74 ports {
41 #address-cells = <1>; 75 #address-cells = <1>;
@@ -43,14 +77,15 @@
43 77
44 port@0 { 78 port@0 {
45 reg = <0>; 79 reg = <0>;
46 adv7123_in: endpoint { 80 thc63lvd1024_in: endpoint {
47 remote-endpoint = <&du_out_rgb>; 81 remote-endpoint = <&lvds0_out>;
48 }; 82 };
49 }; 83 };
50 port@1 { 84
51 reg = <1>; 85 port@2 {
52 adv7123_out: endpoint { 86 reg = <2>;
53 remote-endpoint = <&vga_in>; 87 thc63lvd1024_out: endpoint {
88 remote-endpoint = <&adv7511_in>;
54 }; 89 };
55 }; 90 };
56 }; 91 };
@@ -79,16 +114,263 @@
79 regulator-boot-on; 114 regulator-boot-on;
80 regulator-always-on; 115 regulator-always-on;
81 }; 116 };
117
118 reg_12p0v: regulator1 {
119 compatible = "regulator-fixed";
120 regulator-name = "D12.0V";
121 regulator-min-microvolt = <12000000>;
122 regulator-max-microvolt = <12000000>;
123 regulator-boot-on;
124 regulator-always-on;
125 };
126
127 vga {
128 compatible = "vga-connector";
129
130 port {
131 vga_in: endpoint {
132 remote-endpoint = <&adv7123_out>;
133 };
134 };
135 };
136
137 vga-encoder {
138 compatible = "adi,adv7123";
139
140 ports {
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 port@0 {
145 reg = <0>;
146 adv7123_in: endpoint {
147 remote-endpoint = <&du_out_rgb>;
148 };
149 };
150 port@1 {
151 reg = <1>;
152 adv7123_out: endpoint {
153 remote-endpoint = <&vga_in>;
154 };
155 };
156 };
157 };
158
159 x12_clk: x12 {
160 compatible = "fixed-clock";
161 #clock-cells = <0>;
162 clock-frequency = <74250000>;
163 };
164};
165
166&avb {
167 pinctrl-0 = <&avb0_pins>;
168 pinctrl-names = "default";
169 renesas,no-ether-link;
170 phy-handle = <&phy0>;
171 phy-mode = "rgmii-txid";
172 status = "okay";
173
174 phy0: ethernet-phy@0 {
175 rxc-skew-ps = <1500>;
176 reg = <0>;
177 interrupt-parent = <&gpio5>;
178 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
179 };
180};
181
182&du {
183 pinctrl-0 = <&du_pins>;
184 pinctrl-names = "default";
185 status = "okay";
186
187 clocks = <&cpg CPG_MOD 724>,
188 <&cpg CPG_MOD 723>,
189 <&x12_clk>;
190 clock-names = "du.0", "du.1", "dclkin.0";
191
192 ports {
193 port@0 {
194 endpoint {
195 remote-endpoint = <&adv7123_in>;
196 };
197 };
198 };
199};
200
201&ehci0 {
202 dr_mode = "host";
203 status = "okay";
82}; 204};
83 205
84&extal_clk { 206&extal_clk {
85 clock-frequency = <48000000>; 207 clock-frequency = <48000000>;
86}; 208};
87 209
210&hsusb {
211 dr_mode = "host";
212 status = "okay";
213};
214
215&i2c0 {
216 pinctrl-0 = <&i2c0_pins>;
217 pinctrl-names = "default";
218 status = "okay";
219
220 composite-in@20 {
221 compatible = "adi,adv7180cp";
222 reg = <0x20>;
223
224 ports {
225 #address-cells = <1>;
226 #size-cells = <0>;
227
228 port@0 {
229 reg = <0>;
230 adv7180_in: endpoint {
231 remote-endpoint = <&composite_con_in>;
232 };
233 };
234
235 port@3 {
236 reg = <3>;
237
238 /*
239 * The VIN4 video input path is shared between
240 * CVBS and HDMI inputs through SW[49-53]
241 * switches.
242 *
243 * CVBS is the default selection, link it to
244 * VIN4 here.
245 */
246 adv7180_out: endpoint {
247 remote-endpoint = <&vin4_in>;
248 };
249 };
250 };
251
252 };
253
254 hdmi-encoder@39 {
255 compatible = "adi,adv7511w";
256 reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
257 reg-names = "main", "edid", "packet", "cec";
258 interrupt-parent = <&gpio1>;
259 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
260
261 /* Depends on LVDS */
262 max-clock = <135000000>;
263 min-vrefresh = <50>;
264
265 adi,input-depth = <8>;
266 adi,input-colorspace = "rgb";
267 adi,input-clock = "1x";
268 adi,input-style = <1>;
269 adi,input-justification = "evenly";
270
271 ports {
272 #address-cells = <1>;
273 #size-cells = <0>;
274
275 port@0 {
276 reg = <0>;
277 adv7511_in: endpoint {
278 remote-endpoint = <&thc63lvd1024_out>;
279 };
280 };
281
282 port@1 {
283 reg = <1>;
284 adv7511_out: endpoint {
285 remote-endpoint = <&hdmi_con_out>;
286 };
287 };
288 };
289 };
290
291 hdmi-decoder@4c {
292 compatible = "adi,adv7612";
293 reg = <0x4c>;
294 default-input = <0>;
295
296 ports {
297 #address-cells = <1>;
298 #size-cells = <0>;
299
300 port@0 {
301 reg = <0>;
302
303 adv7612_in: endpoint {
304 remote-endpoint = <&hdmi_con_in>;
305 };
306 };
307
308 port@2 {
309 reg = <2>;
310
311 /*
312 * The VIN4 video input path is shared between
313 * CVBS and HDMI inputs through SW[49-53]
314 * switches.
315 *
316 * CVBS is the default selection, leave HDMI
317 * not connected here.
318 */
319 adv7612_out: endpoint {
320 pclk-sample = <0>;
321 hsync-active = <0>;
322 vsync-active = <0>;
323 };
324 };
325 };
326 };
327
328 eeprom@50 {
329 compatible = "rohm,br24t01", "atmel,24c01";
330 reg = <0x50>;
331 pagesize = <8>;
332 };
333};
334
335&i2c1 {
336 pinctrl-0 = <&i2c1_pins>;
337 pinctrl-names = "default";
338 status = "okay";
339};
340
341&lvds0 {
342 status = "okay";
343
344 clocks = <&cpg CPG_MOD 727>,
345 <&x12_clk>,
346 <&extal_clk>;
347 clock-names = "fck", "dclkin.0", "extal";
348
349 ports {
350 port@1 {
351 lvds0_out: endpoint {
352 remote-endpoint = <&thc63lvd1024_in>;
353 };
354 };
355 };
356};
357
358&lvds1 {
359 clocks = <&cpg CPG_MOD 727>,
360 <&x12_clk>,
361 <&extal_clk>;
362 clock-names = "fck", "dclkin.0", "extal";
363};
364
365&ohci0 {
366 dr_mode = "host";
367 status = "okay";
368};
369
88&pfc { 370&pfc {
89 avb0_pins: avb { 371 avb0_pins: avb {
90 mux { 372 mux {
91 groups = "avb0_link", "avb0_mdc", "avb0_mii"; 373 groups = "avb0_link", "avb0_mdio", "avb0_mii";
92 function = "avb0"; 374 function = "avb0";
93 }; 375 };
94 }; 376 };
@@ -139,62 +421,30 @@
139 groups = "usb0"; 421 groups = "usb0";
140 function = "usb0"; 422 function = "usb0";
141 }; 423 };
142};
143 424
144&i2c0 { 425 vin4_pins_cvbs: vin4 {
145 pinctrl-0 = <&i2c0_pins>; 426 groups = "vin4_data8", "vin4_sync", "vin4_clk";
146 pinctrl-names = "default"; 427 function = "vin4";
147 status = "okay";
148
149 eeprom@50 {
150 compatible = "rohm,br24t01", "atmel,24c01";
151 reg = <0x50>;
152 pagesize = <8>;
153 }; 428 };
154}; 429};
155 430
156&i2c1 { 431&pwm0 {
157 pinctrl-0 = <&i2c1_pins>; 432 pinctrl-0 = <&pwm0_pins>;
158 pinctrl-names = "default"; 433 pinctrl-names = "default";
159 status = "okay";
160};
161 434
162&du {
163 pinctrl-0 = <&du_pins>;
164 pinctrl-names = "default";
165 status = "okay"; 435 status = "okay";
166
167 ports {
168 port@0 {
169 endpoint {
170 remote-endpoint = <&adv7123_in>;
171 };
172 };
173 };
174}; 436};
175 437
176&ehci0 { 438&pwm1 {
177 status = "okay"; 439 pinctrl-0 = <&pwm1_pins>;
178}; 440 pinctrl-names = "default";
179 441
180&ohci0 {
181 status = "okay"; 442 status = "okay";
182}; 443};
183 444
184&avb { 445&rwdt {
185 pinctrl-0 = <&avb0_pins>; 446 timeout-sec = <60>;
186 pinctrl-names = "default";
187 renesas,no-ether-link;
188 phy-handle = <&phy0>;
189 phy-mode = "rgmii-txid";
190 status = "okay"; 447 status = "okay";
191
192 phy0: ethernet-phy@0 {
193 rxc-skew-ps = <1500>;
194 reg = <0>;
195 interrupt-parent = <&gpio5>;
196 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
197 };
198}; 448};
199 449
200&scif2 { 450&scif2 {
@@ -222,24 +472,26 @@
222 pinctrl-0 = <&usb0_pins>; 472 pinctrl-0 = <&usb0_pins>;
223 pinctrl-names = "default"; 473 pinctrl-names = "default";
224 474
475 renesas,no-otg-pins;
225 status = "okay"; 476 status = "okay";
226}; 477};
227 478
228&pwm0 { 479&vin4 {
229 pinctrl-0 = <&pwm0_pins>; 480 pinctrl-0 = <&vin4_pins_cvbs>;
230 pinctrl-names = "default"; 481 pinctrl-names = "default";
231 482
232 status = "okay"; 483 status = "okay";
233};
234 484
235&pwm1 { 485 ports {
236 pinctrl-0 = <&pwm1_pins>; 486 #address-cells = <1>;
237 pinctrl-names = "default"; 487 #size-cells = <0>;
238 488
239 status = "okay"; 489 port@0 {
240}; 490 reg = <0>;
241 491
242&rwdt { 492 vin4_in: endpoint {
243 timeout-sec = <60>; 493 remote-endpoint = <&adv7180_out>;
244 status = "okay"; 494 };
495 };
496 };
245}; 497};
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