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-rw-r--r--arch/arm/dts/r8a77995.dtsi1051
1 files changed, 685 insertions, 366 deletions
diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi
index 1d49279ac9..5bf3af246e 100644
--- a/arch/arm/dts/r8a77995.dtsi
+++ b/arch/arm/dts/r8a77995.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a77995 SoC 3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 * 4 *
5 * Copyright (C) 2016 Renesas Electronics Corp. 5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba 6 * Copyright (C) 2017 Glider bvba
@@ -15,9 +15,11 @@
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 psci { 18 /* External CAN clock - to be overridden by boards that provide it */
19 compatible = "arm,psci-1.0", "arm,psci-0.2"; 19 can_clk: can {
20 method = "smc"; 20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <0>;
21 }; 23 };
22 24
23 cpus { 25 cpus {
@@ -25,7 +27,7 @@
25 #size-cells = <0>; 27 #size-cells = <0>;
26 28
27 a53_0: cpu@0 { 29 a53_0: cpu@0 {
28 compatible = "arm,cortex-a53", "arm,armv8"; 30 compatible = "arm,cortex-a53";
29 reg = <0x0>; 31 reg = <0x0>;
30 device_type = "cpu"; 32 device_type = "cpu";
31 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 33 power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
@@ -48,18 +50,16 @@
48 clock-frequency = <0>; 50 clock-frequency = <0>;
49 }; 51 };
50 52
51 /* External CAN clock - to be overridden by boards that provide it */
52 can_clk: can {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 pmu_a53 { 53 pmu_a53 {
59 compatible = "arm,cortex-a53-pmu"; 54 compatible = "arm,cortex-a53-pmu";
60 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 55 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
61 }; 56 };
62 57
58 psci {
59 compatible = "arm,psci-1.0", "arm,psci-0.2";
60 method = "smc";
61 };
62
63 scif_clk: scif { 63 scif_clk: scif {
64 compatible = "fixed-clock"; 64 compatible = "fixed-clock";
65 #clock-cells = <0>; 65 #clock-cells = <0>;
@@ -73,23 +73,6 @@
73 #size-cells = <2>; 73 #size-cells = <2>;
74 ranges; 74 ranges;
75 75
76 gic: interrupt-controller@f1010000 {
77 compatible = "arm,gic-400";
78 #interrupt-cells = <3>;
79 #address-cells = <0>;
80 interrupt-controller;
81 reg = <0x0 0xf1010000 0 0x1000>,
82 <0x0 0xf1020000 0 0x20000>,
83 <0x0 0xf1040000 0 0x20000>,
84 <0x0 0xf1060000 0 0x20000>;
85 interrupts = <GIC_PPI 9
86 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
87 clocks = <&cpg CPG_MOD 408>;
88 clock-names = "clk";
89 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
90 resets = <&cpg 408>;
91 };
92
93 rwdt: watchdog@e6020000 { 76 rwdt: watchdog@e6020000 {
94 compatible = "renesas,r8a77995-wdt", 77 compatible = "renesas,r8a77995-wdt",
95 "renesas,rcar-gen3-wdt"; 78 "renesas,rcar-gen3-wdt";
@@ -100,88 +83,116 @@
100 status = "disabled"; 83 status = "disabled";
101 }; 84 };
102 85
103 ipmmu_vi0: mmu@febd0000 { 86 gpio0: gpio@e6050000 {
104 compatible = "renesas,ipmmu-r8a77995"; 87 compatible = "renesas,gpio-r8a77995",
105 reg = <0 0xfebd0000 0 0x1000>; 88 "renesas,rcar-gen3-gpio";
106 renesas,ipmmu-main = <&ipmmu_mm 14>; 89 reg = <0 0xe6050000 0 0x50>;
107 #iommu-cells = <1>; 90 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
108 status = "disabled"; 91 #gpio-cells = <2>;
109 }; 92 gpio-controller;
110 93 gpio-ranges = <&pfc 0 0 9>;
111 ipmmu_vp0: mmu@fe990000 { 94 #interrupt-cells = <2>;
112 compatible = "renesas,ipmmu-r8a77995"; 95 interrupt-controller;
113 reg = <0 0xfe990000 0 0x1000>; 96 clocks = <&cpg CPG_MOD 912>;
114 renesas,ipmmu-main = <&ipmmu_mm 16>; 97 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
115 #iommu-cells = <1>; 98 resets = <&cpg 912>;
116 status = "disabled";
117 };
118
119 ipmmu_vc0: mmu@fe6b0000 {
120 compatible = "renesas,ipmmu-r8a77995";
121 reg = <0 0xfe6b0000 0 0x1000>;
122 renesas,ipmmu-main = <&ipmmu_mm 12>;
123 #iommu-cells = <1>;
124 status = "disabled";
125 }; 99 };
126 100
127 ipmmu_pv0: mmu@fd800000 { 101 gpio1: gpio@e6051000 {
128 compatible = "renesas,ipmmu-r8a77995"; 102 compatible = "renesas,gpio-r8a77995",
129 reg = <0 0xfd800000 0 0x1000>; 103 "renesas,rcar-gen3-gpio";
130 renesas,ipmmu-main = <&ipmmu_mm 6>; 104 reg = <0 0xe6051000 0 0x50>;
131 #iommu-cells = <1>; 105 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
132 status = "disabled"; 106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 32 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 clocks = <&cpg CPG_MOD 911>;
112 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
113 resets = <&cpg 911>;
133 }; 114 };
134 115
135 ipmmu_hc: mmu@e6570000 { 116 gpio2: gpio@e6052000 {
136 compatible = "renesas,ipmmu-r8a77995"; 117 compatible = "renesas,gpio-r8a77995",
137 reg = <0 0xe6570000 0 0x1000>; 118 "renesas,rcar-gen3-gpio";
138 renesas,ipmmu-main = <&ipmmu_mm 2>; 119 reg = <0 0xe6052000 0 0x50>;
139 #iommu-cells = <1>; 120 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
140 status = "disabled"; 121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 64 32>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&cpg CPG_MOD 910>;
127 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
128 resets = <&cpg 910>;
141 }; 129 };
142 130
143 ipmmu_rt: mmu@ffc80000 { 131 gpio3: gpio@e6053000 {
144 compatible = "renesas,ipmmu-r8a77995"; 132 compatible = "renesas,gpio-r8a77995",
145 reg = <0 0xffc80000 0 0x1000>; 133 "renesas,rcar-gen3-gpio";
146 renesas,ipmmu-main = <&ipmmu_mm 10>; 134 reg = <0 0xe6053000 0 0x50>;
147 #iommu-cells = <1>; 135 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
148 status = "disabled"; 136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 96 10>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&cpg CPG_MOD 909>;
142 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
143 resets = <&cpg 909>;
149 }; 144 };
150 145
151 ipmmu_mp: mmu@ec670000 { 146 gpio4: gpio@e6054000 {
152 compatible = "renesas,ipmmu-r8a77995"; 147 compatible = "renesas,gpio-r8a77995",
153 reg = <0 0xec670000 0 0x1000>; 148 "renesas,rcar-gen3-gpio";
154 renesas,ipmmu-main = <&ipmmu_mm 4>; 149 reg = <0 0xe6054000 0 0x50>;
155 #iommu-cells = <1>; 150 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
156 status = "disabled"; 151 #gpio-cells = <2>;
152 gpio-controller;
153 gpio-ranges = <&pfc 0 128 32>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&cpg CPG_MOD 908>;
157 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
158 resets = <&cpg 908>;
157 }; 159 };
158 160
159 ipmmu_ds0: mmu@e6740000 { 161 gpio5: gpio@e6055000 {
160 compatible = "renesas,ipmmu-r8a77995"; 162 compatible = "renesas,gpio-r8a77995",
161 reg = <0 0xe6740000 0 0x1000>; 163 "renesas,rcar-gen3-gpio";
162 renesas,ipmmu-main = <&ipmmu_mm 0>; 164 reg = <0 0xe6055000 0 0x50>;
163 #iommu-cells = <1>; 165 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
164 status = "disabled"; 166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 160 21>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&cpg CPG_MOD 907>;
172 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
173 resets = <&cpg 907>;
165 }; 174 };
166 175
167 ipmmu_ds1: mmu@e7740000 { 176 gpio6: gpio@e6055400 {
168 compatible = "renesas,ipmmu-r8a77995"; 177 compatible = "renesas,gpio-r8a77995",
169 reg = <0 0xe7740000 0 0x1000>; 178 "renesas,rcar-gen3-gpio";
170 renesas,ipmmu-main = <&ipmmu_mm 1>; 179 reg = <0 0xe6055400 0 0x50>;
171 #iommu-cells = <1>; 180 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
172 status = "disabled"; 181 #gpio-cells = <2>;
182 gpio-controller;
183 gpio-ranges = <&pfc 0 192 14>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&cpg CPG_MOD 906>;
187 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
188 resets = <&cpg 906>;
173 }; 189 };
174 190
175 ipmmu_mm: mmu@e67b0000 { 191 pfc: pin-controller@e6060000 {
176 compatible = "renesas,ipmmu-r8a77995"; 192 compatible = "renesas,pfc-r8a77995";
177 reg = <0 0xe67b0000 0 0x1000>; 193 reg = <0 0xe6060000 0 0x508>;
178 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
180 #iommu-cells = <1>;
181 status = "disabled";
182 }; 194 };
183 195
184
185 cpg: clock-controller@e6150000 { 196 cpg: clock-controller@e6150000 {
186 compatible = "renesas,r8a77995-cpg-mssr"; 197 compatible = "renesas,r8a77995-cpg-mssr";
187 reg = <0 0xe6150000 0 0x1000>; 198 reg = <0 0xe6150000 0 0x1000>;
@@ -197,22 +208,24 @@
197 reg = <0 0xe6160000 0 0x0200>; 208 reg = <0 0xe6160000 0 0x0200>;
198 }; 209 };
199 210
200 pfc: pin-controller@e6060000 {
201 compatible = "renesas,pfc-r8a77995";
202 reg = <0 0xe6060000 0 0x508>;
203 };
204
205 prr: chipid@fff00044 {
206 compatible = "renesas,prr";
207 reg = <0 0xfff00044 0 4>;
208 };
209
210 sysc: system-controller@e6180000 { 211 sysc: system-controller@e6180000 {
211 compatible = "renesas,r8a77995-sysc"; 212 compatible = "renesas,r8a77995-sysc";
212 reg = <0 0xe6180000 0 0x0400>; 213 reg = <0 0xe6180000 0 0x0400>;
213 #power-domain-cells = <1>; 214 #power-domain-cells = <1>;
214 }; 215 };
215 216
217 thermal: thermal@e6190000 {
218 compatible = "renesas,thermal-r8a77995";
219 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
220 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cpg CPG_MOD 522>;
224 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
225 resets = <&cpg 522>;
226 #thermal-sensor-cells = <0>;
227 };
228
216 intc_ex: interrupt-controller@e61c0000 { 229 intc_ex: interrupt-controller@e61c0000 {
217 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 230 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
218 #interrupt-cells = <2>; 231 #interrupt-cells = <2>;
@@ -229,6 +242,178 @@
229 resets = <&cpg 407>; 242 resets = <&cpg 407>;
230 }; 243 };
231 244
245 hscif0: serial@e6540000 {
246 compatible = "renesas,hscif-r8a77995",
247 "renesas,rcar-gen3-hscif",
248 "renesas,hscif";
249 reg = <0 0xe6540000 0 0x60>;
250 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&cpg CPG_MOD 520>,
252 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
253 <&scif_clk>;
254 clock-names = "fck", "brg_int", "scif_clk";
255 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
256 <&dmac2 0x31>, <&dmac2 0x30>;
257 dma-names = "tx", "rx", "tx", "rx";
258 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
259 resets = <&cpg 520>;
260 status = "disabled";
261 };
262
263 hscif3: serial@e66a0000 {
264 compatible = "renesas,hscif-r8a77995",
265 "renesas,rcar-gen3-hscif",
266 "renesas,hscif";
267 reg = <0 0xe66a0000 0 0x60>;
268 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cpg CPG_MOD 517>,
270 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
271 <&scif_clk>;
272 clock-names = "fck", "brg_int", "scif_clk";
273 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
274 dma-names = "tx", "rx";
275 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
276 resets = <&cpg 517>;
277 status = "disabled";
278 };
279
280 i2c0: i2c@e6500000 {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 compatible = "renesas,i2c-r8a77995",
284 "renesas,rcar-gen3-i2c";
285 reg = <0 0xe6500000 0 0x40>;
286 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 931>;
288 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
289 resets = <&cpg 931>;
290 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
291 <&dmac2 0x91>, <&dmac2 0x90>;
292 dma-names = "tx", "rx", "tx", "rx";
293 i2c-scl-internal-delay-ns = <6>;
294 status = "disabled";
295 };
296
297 i2c1: i2c@e6508000 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 compatible = "renesas,i2c-r8a77995",
301 "renesas,rcar-gen3-i2c";
302 reg = <0 0xe6508000 0 0x40>;
303 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cpg CPG_MOD 930>;
305 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
306 resets = <&cpg 930>;
307 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
308 <&dmac2 0x93>, <&dmac2 0x92>;
309 dma-names = "tx", "rx", "tx", "rx";
310 i2c-scl-internal-delay-ns = <6>;
311 status = "disabled";
312 };
313
314 i2c2: i2c@e6510000 {
315 #address-cells = <1>;
316 #size-cells = <0>;
317 compatible = "renesas,i2c-r8a77995",
318 "renesas,rcar-gen3-i2c";
319 reg = <0 0xe6510000 0 0x40>;
320 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&cpg CPG_MOD 929>;
322 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
323 resets = <&cpg 929>;
324 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
325 <&dmac2 0x95>, <&dmac2 0x94>;
326 dma-names = "tx", "rx", "tx", "rx";
327 i2c-scl-internal-delay-ns = <6>;
328 status = "disabled";
329 };
330
331 i2c3: i2c@e66d0000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 compatible = "renesas,i2c-r8a77995",
335 "renesas,rcar-gen3-i2c";
336 reg = <0 0xe66d0000 0 0x40>;
337 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cpg CPG_MOD 928>;
339 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
340 resets = <&cpg 928>;
341 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
342 dma-names = "tx", "rx";
343 i2c-scl-internal-delay-ns = <6>;
344 status = "disabled";
345 };
346
347 hsusb: usb@e6590000 {
348 compatible = "renesas,usbhs-r8a77995",
349 "renesas,rcar-gen3-usbhs";
350 reg = <0 0xe6590000 0 0x200>;
351 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
353 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
354 <&usb_dmac1 0>, <&usb_dmac1 1>;
355 dma-names = "ch0", "ch1", "ch2", "ch3";
356 renesas,buswait = <11>;
357 phys = <&usb2_phy0>;
358 phy-names = "usb";
359 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
360 resets = <&cpg 704>, <&cpg 703>;
361 status = "disabled";
362 };
363
364 usb_dmac0: dma-controller@e65a0000 {
365 compatible = "renesas,r8a77995-usb-dmac",
366 "renesas,usb-dmac";
367 reg = <0 0xe65a0000 0 0x100>;
368 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-names = "ch0", "ch1";
371 clocks = <&cpg CPG_MOD 330>;
372 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
373 resets = <&cpg 330>;
374 #dma-cells = <1>;
375 dma-channels = <2>;
376 };
377
378 usb_dmac1: dma-controller@e65b0000 {
379 compatible = "renesas,r8a77995-usb-dmac",
380 "renesas,usb-dmac";
381 reg = <0 0xe65b0000 0 0x100>;
382 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-names = "ch0", "ch1";
385 clocks = <&cpg CPG_MOD 331>;
386 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
387 resets = <&cpg 331>;
388 #dma-cells = <1>;
389 dma-channels = <2>;
390 };
391
392 canfd: can@e66c0000 {
393 compatible = "renesas,r8a77995-canfd",
394 "renesas,rcar-gen3-canfd";
395 reg = <0 0xe66c0000 0 0x8000>;
396 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&cpg CPG_MOD 914>,
399 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
400 <&can_clk>;
401 clock-names = "fck", "canfd", "can_clk";
402 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
403 assigned-clock-rates = <40000000>;
404 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
405 resets = <&cpg 914>;
406 status = "disabled";
407
408 channel0 {
409 status = "disabled";
410 };
411
412 channel1 {
413 status = "disabled";
414 };
415 };
416
232 dmac0: dma-controller@e6700000 { 417 dmac0: dma-controller@e6700000 {
233 compatible = "renesas,dmac-r8a77995", 418 compatible = "renesas,dmac-r8a77995",
234 "renesas,rcar-dmac"; 419 "renesas,rcar-dmac";
@@ -251,6 +436,10 @@
251 resets = <&cpg 219>; 436 resets = <&cpg 219>;
252 #dma-cells = <1>; 437 #dma-cells = <1>;
253 dma-channels = <8>; 438 dma-channels = <8>;
439 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
440 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
441 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
442 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
254 }; 443 };
255 444
256 dmac1: dma-controller@e7300000 { 445 dmac1: dma-controller@e7300000 {
@@ -275,6 +464,10 @@
275 resets = <&cpg 218>; 464 resets = <&cpg 218>;
276 #dma-cells = <1>; 465 #dma-cells = <1>;
277 dma-channels = <8>; 466 dma-channels = <8>;
467 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
468 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
469 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
470 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
278 }; 471 };
279 472
280 dmac2: dma-controller@e7310000 { 473 dmac2: dma-controller@e7310000 {
@@ -299,175 +492,91 @@
299 resets = <&cpg 217>; 492 resets = <&cpg 217>;
300 #dma-cells = <1>; 493 #dma-cells = <1>;
301 dma-channels = <8>; 494 dma-channels = <8>;
495 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
496 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
497 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
498 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
302 }; 499 };
303 500
304 gpio0: gpio@e6050000 { 501 ipmmu_ds0: mmu@e6740000 {
305 compatible = "renesas,gpio-r8a77995", 502 compatible = "renesas,ipmmu-r8a77995";
306 "renesas,rcar-gen3-gpio", 503 reg = <0 0xe6740000 0 0x1000>;
307 "renesas,gpio-rcar"; 504 renesas,ipmmu-main = <&ipmmu_mm 0>;
308 reg = <0 0xe6050000 0 0x50>;
309 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
310 #gpio-cells = <2>;
311 gpio-controller;
312 gpio-ranges = <&pfc 0 0 9>;
313 #interrupt-cells = <2>;
314 interrupt-controller;
315 clocks = <&cpg CPG_MOD 912>;
316 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 505 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
317 resets = <&cpg 912>; 506 #iommu-cells = <1>;
318 }; 507 };
319 508
320 gpio1: gpio@e6051000 { 509 ipmmu_ds1: mmu@e7740000 {
321 compatible = "renesas,gpio-r8a77995", 510 compatible = "renesas,ipmmu-r8a77995";
322 "renesas,rcar-gen3-gpio", 511 reg = <0 0xe7740000 0 0x1000>;
323 "renesas,gpio-rcar"; 512 renesas,ipmmu-main = <&ipmmu_mm 1>;
324 reg = <0 0xe6051000 0 0x50>;
325 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
326 #gpio-cells = <2>;
327 gpio-controller;
328 gpio-ranges = <&pfc 0 32 32>;
329 #interrupt-cells = <2>;
330 interrupt-controller;
331 clocks = <&cpg CPG_MOD 911>;
332 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 513 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
333 resets = <&cpg 911>; 514 #iommu-cells = <1>;
334 }; 515 };
335 516
336 gpio2: gpio@e6052000 { 517 ipmmu_hc: mmu@e6570000 {
337 compatible = "renesas,gpio-r8a77995", 518 compatible = "renesas,ipmmu-r8a77995";
338 "renesas,rcar-gen3-gpio", 519 reg = <0 0xe6570000 0 0x1000>;
339 "renesas,gpio-rcar"; 520 renesas,ipmmu-main = <&ipmmu_mm 2>;
340 reg = <0 0xe6052000 0 0x50>;
341 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
342 #gpio-cells = <2>;
343 gpio-controller;
344 gpio-ranges = <&pfc 0 64 32>;
345 #interrupt-cells = <2>;
346 interrupt-controller;
347 clocks = <&cpg CPG_MOD 910>;
348 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 521 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
349 resets = <&cpg 910>; 522 #iommu-cells = <1>;
350 }; 523 };
351 524
352 gpio3: gpio@e6053000 { 525 ipmmu_mm: mmu@e67b0000 {
353 compatible = "renesas,gpio-r8a77995", 526 compatible = "renesas,ipmmu-r8a77995";
354 "renesas,rcar-gen3-gpio", 527 reg = <0 0xe67b0000 0 0x1000>;
355 "renesas,gpio-rcar"; 528 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
356 reg = <0 0xe6053000 0 0x50>; 529 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
357 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
358 #gpio-cells = <2>;
359 gpio-controller;
360 gpio-ranges = <&pfc 0 96 10>;
361 #interrupt-cells = <2>;
362 interrupt-controller;
363 clocks = <&cpg CPG_MOD 909>;
364 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 530 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
365 resets = <&cpg 909>; 531 #iommu-cells = <1>;
366 }; 532 };
367 533
368 gpio4: gpio@e6054000 { 534 ipmmu_mp: mmu@ec670000 {
369 compatible = "renesas,gpio-r8a77995", 535 compatible = "renesas,ipmmu-r8a77995";
370 "renesas,rcar-gen3-gpio", 536 reg = <0 0xec670000 0 0x1000>;
371 "renesas,gpio-rcar"; 537 renesas,ipmmu-main = <&ipmmu_mm 4>;
372 reg = <0 0xe6054000 0 0x50>;
373 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
374 #gpio-cells = <2>;
375 gpio-controller;
376 gpio-ranges = <&pfc 0 128 32>;
377 #interrupt-cells = <2>;
378 interrupt-controller;
379 clocks = <&cpg CPG_MOD 908>;
380 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 538 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
381 resets = <&cpg 908>; 539 #iommu-cells = <1>;
382 }; 540 };
383 541
384 gpio5: gpio@e6055000 { 542 ipmmu_pv0: mmu@fd800000 {
385 compatible = "renesas,gpio-r8a77995", 543 compatible = "renesas,ipmmu-r8a77995";
386 "renesas,rcar-gen3-gpio", 544 reg = <0 0xfd800000 0 0x1000>;
387 "renesas,gpio-rcar"; 545 renesas,ipmmu-main = <&ipmmu_mm 6>;
388 reg = <0 0xe6055000 0 0x50>;
389 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
390 #gpio-cells = <2>;
391 gpio-controller;
392 gpio-ranges = <&pfc 0 160 21>;
393 #interrupt-cells = <2>;
394 interrupt-controller;
395 clocks = <&cpg CPG_MOD 907>;
396 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 546 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
397 resets = <&cpg 907>; 547 #iommu-cells = <1>;
398 }; 548 };
399 549
400 gpio6: gpio@e6055400 { 550 ipmmu_rt: mmu@ffc80000 {
401 compatible = "renesas,gpio-r8a77995", 551 compatible = "renesas,ipmmu-r8a77995";
402 "renesas,rcar-gen3-gpio", 552 reg = <0 0xffc80000 0 0x1000>;
403 "renesas,gpio-rcar"; 553 renesas,ipmmu-main = <&ipmmu_mm 10>;
404 reg = <0 0xe6055400 0 0x50>;
405 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
406 #gpio-cells = <2>;
407 gpio-controller;
408 gpio-ranges = <&pfc 0 192 14>;
409 #interrupt-cells = <2>;
410 interrupt-controller;
411 clocks = <&cpg CPG_MOD 906>;
412 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 554 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
413 resets = <&cpg 906>; 555 #iommu-cells = <1>;
414 }; 556 };
415 557
416 can0: can@e6c30000 { 558 ipmmu_vc0: mmu@fe6b0000 {
417 compatible = "renesas,can-r8a77995", 559 compatible = "renesas,ipmmu-r8a77995";
418 "renesas,rcar-gen3-can"; 560 reg = <0 0xfe6b0000 0 0x1000>;
419 reg = <0 0xe6c30000 0 0x1000>; 561 renesas,ipmmu-main = <&ipmmu_mm 12>;
420 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cpg CPG_MOD 916>,
422 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
423 <&can_clk>;
424 clock-names = "clkp1", "clkp2", "can_clk";
425 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
426 assigned-clock-rates = <40000000>;
427 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 562 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
428 resets = <&cpg 916>; 563 #iommu-cells = <1>;
429 status = "disabled";
430 }; 564 };
431 565
432 can1: can@e6c38000 { 566 ipmmu_vi0: mmu@febd0000 {
433 compatible = "renesas,can-r8a77995", 567 compatible = "renesas,ipmmu-r8a77995";
434 "renesas,rcar-gen3-can"; 568 reg = <0 0xfebd0000 0 0x1000>;
435 reg = <0 0xe6c38000 0 0x1000>; 569 renesas,ipmmu-main = <&ipmmu_mm 14>;
436 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&cpg CPG_MOD 915>,
438 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
439 <&can_clk>;
440 clock-names = "clkp1", "clkp2", "can_clk";
441 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
442 assigned-clock-rates = <40000000>;
443 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 570 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
444 resets = <&cpg 915>; 571 #iommu-cells = <1>;
445 status = "disabled";
446 }; 572 };
447 573
448 canfd: can@e66c0000 { 574 ipmmu_vp0: mmu@fe990000 {
449 compatible = "renesas,r8a77995-canfd", 575 compatible = "renesas,ipmmu-r8a77995";
450 "renesas,rcar-gen3-canfd"; 576 reg = <0 0xfe990000 0 0x1000>;
451 reg = <0 0xe66c0000 0 0x8000>; 577 renesas,ipmmu-main = <&ipmmu_mm 16>;
452 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cpg CPG_MOD 914>,
455 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
456 <&can_clk>;
457 clock-names = "fck", "canfd", "can_clk";
458 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
459 assigned-clock-rates = <40000000>;
460 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 578 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
461 resets = <&cpg 914>; 579 #iommu-cells = <1>;
462 status = "disabled";
463
464 channel0 {
465 status = "disabled";
466 };
467
468 channel1 {
469 status = "disabled";
470 };
471 }; 580 };
472 581
473 avb: ethernet@e6800000 { 582 avb: ethernet@e6800000 {
@@ -516,87 +625,35 @@
516 status = "disabled"; 625 status = "disabled";
517 }; 626 };
518 627
519 scif2: serial@e6e88000 { 628 can0: can@e6c30000 {
520 compatible = "renesas,scif-r8a77995", 629 compatible = "renesas,can-r8a77995",
521 "renesas,rcar-gen3-scif", "renesas,scif"; 630 "renesas,rcar-gen3-can";
522 reg = <0 0xe6e88000 0 64>; 631 reg = <0 0xe6c30000 0 0x1000>;
523 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 632 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cpg CPG_MOD 310>, 633 clocks = <&cpg CPG_MOD 916>,
525 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 634 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
526 <&scif_clk>; 635 <&can_clk>;
527 clock-names = "fck", "brg_int", "scif_clk"; 636 clock-names = "clkp1", "clkp2", "can_clk";
528 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 637 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
529 <&dmac2 0x13>, <&dmac2 0x12>; 638 assigned-clock-rates = <40000000>;
530 dma-names = "tx", "rx", "tx", "rx";
531 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
532 resets = <&cpg 310>;
533 status = "disabled";
534 };
535
536 i2c0: i2c@e6500000 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "renesas,i2c-r8a77995",
540 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe6500000 0 0x40>;
542 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 931>;
544 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
545 resets = <&cpg 931>;
546 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
547 <&dmac2 0x91>, <&dmac2 0x90>;
548 dma-names = "tx", "rx", "tx", "rx";
549 i2c-scl-internal-delay-ns = <6>;
550 status = "disabled";
551 };
552
553 i2c1: i2c@e6508000 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "renesas,i2c-r8a77995",
557 "renesas,rcar-gen3-i2c";
558 reg = <0 0xe6508000 0 0x40>;
559 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&cpg CPG_MOD 930>;
561 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
562 resets = <&cpg 930>;
563 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
564 <&dmac2 0x93>, <&dmac2 0x92>;
565 dma-names = "tx", "rx", "tx", "rx";
566 i2c-scl-internal-delay-ns = <6>;
567 status = "disabled";
568 };
569
570 i2c2: i2c@e6510000 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "renesas,i2c-r8a77995",
574 "renesas,rcar-gen3-i2c";
575 reg = <0 0xe6510000 0 0x40>;
576 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cpg CPG_MOD 929>;
578 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 639 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
579 resets = <&cpg 929>; 640 resets = <&cpg 916>;
580 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
581 <&dmac2 0x95>, <&dmac2 0x94>;
582 dma-names = "tx", "rx", "tx", "rx";
583 i2c-scl-internal-delay-ns = <6>;
584 status = "disabled"; 641 status = "disabled";
585 }; 642 };
586 643
587 i2c3: i2c@e66d0000 { 644 can1: can@e6c38000 {
588 #address-cells = <1>; 645 compatible = "renesas,can-r8a77995",
589 #size-cells = <0>; 646 "renesas,rcar-gen3-can";
590 compatible = "renesas,i2c-r8a77995", 647 reg = <0 0xe6c38000 0 0x1000>;
591 "renesas,rcar-gen3-i2c"; 648 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
592 reg = <0 0xe66d0000 0 0x40>; 649 clocks = <&cpg CPG_MOD 915>,
593 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 650 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
594 clocks = <&cpg CPG_MOD 928>; 651 <&can_clk>;
652 clock-names = "clkp1", "clkp2", "can_clk";
653 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
654 assigned-clock-rates = <40000000>;
595 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 655 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
596 resets = <&cpg 928>; 656 resets = <&cpg 915>;
597 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
598 dma-names = "tx", "rx";
599 i2c-scl-internal-delay-ns = <6>;
600 status = "disabled"; 657 status = "disabled";
601 }; 658 };
602 659
@@ -640,28 +697,176 @@
640 status = "disabled"; 697 status = "disabled";
641 }; 698 };
642 699
643 sdhi2: sd@ee140000 { 700 scif0: serial@e6e60000 {
644 compatible = "renesas,sdhi-r8a77995", 701 compatible = "renesas,scif-r8a77995",
645 "renesas,rcar-gen3-sdhi"; 702 "renesas,rcar-gen3-scif", "renesas,scif";
646 reg = <0 0xee140000 0 0x2000>; 703 reg = <0 0xe6e60000 0 64>;
647 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 704 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&cpg CPG_MOD 312>; 705 clocks = <&cpg CPG_MOD 207>,
649 max-frequency = <200000000>; 706 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
707 <&scif_clk>;
708 clock-names = "fck", "brg_int", "scif_clk";
709 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
710 <&dmac2 0x51>, <&dmac2 0x50>;
711 dma-names = "tx", "rx", "tx", "rx";
650 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 712 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
651 resets = <&cpg 312>; 713 resets = <&cpg 207>;
652 status = "disabled"; 714 status = "disabled";
653 }; 715 };
654 716
655 ehci0: usb@ee080100 { 717 scif1: serial@e6e68000 {
656 compatible = "generic-ehci"; 718 compatible = "renesas,scif-r8a77995",
657 reg = <0 0xee080100 0 0x100>; 719 "renesas,rcar-gen3-scif", "renesas,scif";
658 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 720 reg = <0 0xe6e68000 0 64>;
659 clocks = <&cpg CPG_MOD 703>; 721 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
660 phys = <&usb2_phy0>; 722 clocks = <&cpg CPG_MOD 206>,
661 phy-names = "usb"; 723 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
662 companion = <&ohci0>; 724 <&scif_clk>;
725 clock-names = "fck", "brg_int", "scif_clk";
726 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
727 <&dmac2 0x53>, <&dmac2 0x52>;
728 dma-names = "tx", "rx", "tx", "rx";
729 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
730 resets = <&cpg 206>;
731 status = "disabled";
732 };
733
734 scif2: serial@e6e88000 {
735 compatible = "renesas,scif-r8a77995",
736 "renesas,rcar-gen3-scif", "renesas,scif";
737 reg = <0 0xe6e88000 0 64>;
738 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cpg CPG_MOD 310>,
740 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
741 <&scif_clk>;
742 clock-names = "fck", "brg_int", "scif_clk";
743 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
744 <&dmac2 0x13>, <&dmac2 0x12>;
745 dma-names = "tx", "rx", "tx", "rx";
746 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
747 resets = <&cpg 310>;
748 status = "disabled";
749 };
750
751 scif3: serial@e6c50000 {
752 compatible = "renesas,scif-r8a77995",
753 "renesas,rcar-gen3-scif", "renesas,scif";
754 reg = <0 0xe6c50000 0 64>;
755 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&cpg CPG_MOD 204>,
757 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
758 <&scif_clk>;
759 clock-names = "fck", "brg_int", "scif_clk";
760 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
761 dma-names = "tx", "rx";
762 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
763 resets = <&cpg 204>;
764 status = "disabled";
765 };
766
767 scif4: serial@e6c40000 {
768 compatible = "renesas,scif-r8a77995",
769 "renesas,rcar-gen3-scif", "renesas,scif";
770 reg = <0 0xe6c40000 0 64>;
771 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&cpg CPG_MOD 203>,
773 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
774 <&scif_clk>;
775 clock-names = "fck", "brg_int", "scif_clk";
776 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
777 dma-names = "tx", "rx";
778 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
779 resets = <&cpg 203>;
780 status = "disabled";
781 };
782
783 scif5: serial@e6f30000 {
784 compatible = "renesas,scif-r8a77995",
785 "renesas,rcar-gen3-scif", "renesas,scif";
786 reg = <0 0xe6f30000 0 64>;
787 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cpg CPG_MOD 202>,
789 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
790 <&scif_clk>;
791 clock-names = "fck", "brg_int", "scif_clk";
792 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
793 <&dmac2 0x5b>, <&dmac2 0x5a>;
794 dma-names = "tx", "rx", "tx", "rx";
663 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 795 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
664 resets = <&cpg 703>; 796 resets = <&cpg 202>;
797 status = "disabled";
798 };
799
800 msiof0: spi@e6e90000 {
801 compatible = "renesas,msiof-r8a77995",
802 "renesas,rcar-gen3-msiof";
803 reg = <0 0xe6e90000 0 0x64>;
804 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&cpg CPG_MOD 211>;
806 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
807 <&dmac2 0x41>, <&dmac2 0x40>;
808 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
810 resets = <&cpg 211>;
811 #address-cells = <1>;
812 #size-cells = <0>;
813 status = "disabled";
814 };
815
816 msiof1: spi@e6ea0000 {
817 compatible = "renesas,msiof-r8a77995",
818 "renesas,rcar-gen3-msiof";
819 reg = <0 0xe6ea0000 0 0x64>;
820 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cpg CPG_MOD 210>;
822 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
823 <&dmac2 0x43>, <&dmac2 0x42>;
824 dma-names = "tx", "rx", "tx", "rx";
825 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
826 resets = <&cpg 210>;
827 #address-cells = <1>;
828 #size-cells = <0>;
829 status = "disabled";
830 };
831
832 msiof2: spi@e6c00000 {
833 compatible = "renesas,msiof-r8a77995",
834 "renesas,rcar-gen3-msiof";
835 reg = <0 0xe6c00000 0 0x64>;
836 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&cpg CPG_MOD 209>;
838 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
839 dma-names = "tx", "rx";
840 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
841 resets = <&cpg 209>;
842 #address-cells = <1>;
843 #size-cells = <0>;
844 status = "disabled";
845 };
846
847 msiof3: spi@e6c10000 {
848 compatible = "renesas,msiof-r8a77995",
849 "renesas,rcar-gen3-msiof";
850 reg = <0 0xe6c10000 0 0x64>;
851 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&cpg CPG_MOD 208>;
853 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
854 dma-names = "tx", "rx";
855 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
856 resets = <&cpg 208>;
857 #address-cells = <1>;
858 #size-cells = <0>;
859 status = "disabled";
860 };
861
862 vin4: video@e6ef4000 {
863 compatible = "renesas,vin-r8a77995";
864 reg = <0 0xe6ef4000 0 0x1000>;
865 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cpg CPG_MOD 807>;
867 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
868 resets = <&cpg 807>;
869 renesas,id = <4>;
665 status = "disabled"; 870 status = "disabled";
666 }; 871 };
667 872
@@ -669,11 +874,24 @@
669 compatible = "generic-ohci"; 874 compatible = "generic-ohci";
670 reg = <0 0xee080000 0 0x100>; 875 reg = <0 0xee080000 0 0x100>;
671 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 876 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cpg CPG_MOD 703>; 877 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
878 phys = <&usb2_phy0>;
879 phy-names = "usb";
880 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
881 resets = <&cpg 703>, <&cpg 704>;
882 status = "disabled";
883 };
884
885 ehci0: usb@ee080100 {
886 compatible = "generic-ehci";
887 reg = <0 0xee080100 0 0x100>;
888 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
673 phys = <&usb2_phy0>; 890 phys = <&usb2_phy0>;
674 phy-names = "usb"; 891 phy-names = "usb";
892 companion = <&ohci0>;
675 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 893 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
676 resets = <&cpg 703>; 894 resets = <&cpg 703>, <&cpg 704>;
677 status = "disabled"; 895 status = "disabled";
678 }; 896 };
679 897
@@ -682,13 +900,42 @@
682 "renesas,rcar-gen3-usb2-phy"; 900 "renesas,rcar-gen3-usb2-phy";
683 reg = <0 0xee080200 0 0x700>; 901 reg = <0 0xee080200 0 0x700>;
684 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 902 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&cpg CPG_MOD 703>; 903 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
686 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 904 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
687 resets = <&cpg 703>; 905 resets = <&cpg 703>, <&cpg 704>;
688 #phy-cells = <0>; 906 #phy-cells = <0>;
689 status = "disabled"; 907 status = "disabled";
690 }; 908 };
691 909
910 sdhi2: sd@ee140000 {
911 compatible = "renesas,sdhi-r8a77995",
912 "renesas,rcar-gen3-sdhi";
913 reg = <0 0xee140000 0 0x2000>;
914 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&cpg CPG_MOD 312>;
916 max-frequency = <200000000>;
917 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
918 resets = <&cpg 312>;
919 status = "disabled";
920 };
921
922 gic: interrupt-controller@f1010000 {
923 compatible = "arm,gic-400";
924 #interrupt-cells = <3>;
925 #address-cells = <0>;
926 interrupt-controller;
927 reg = <0x0 0xf1010000 0 0x1000>,
928 <0x0 0xf1020000 0 0x20000>,
929 <0x0 0xf1040000 0 0x20000>,
930 <0x0 0xf1060000 0 0x20000>;
931 interrupts = <GIC_PPI 9
932 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
933 clocks = <&cpg CPG_MOD 408>;
934 clock-names = "clk";
935 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
936 resets = <&cpg 408>;
937 };
938
692 vspbs: vsp@fe960000 { 939 vspbs: vsp@fe960000 {
693 compatible = "renesas,vsp2"; 940 compatible = "renesas,vsp2";
694 reg = <0 0xfe960000 0 0x8000>; 941 reg = <0 0xfe960000 0 0x8000>;
@@ -699,18 +946,9 @@
699 renesas,fcp = <&fcpvb0>; 946 renesas,fcp = <&fcpvb0>;
700 }; 947 };
701 948
702 fcpvb0: fcp@fe96f000 {
703 compatible = "renesas,fcpv";
704 reg = <0 0xfe96f000 0 0x200>;
705 clocks = <&cpg CPG_MOD 607>;
706 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
707 resets = <&cpg 607>;
708 iommus = <&ipmmu_vp0 5>;
709 };
710
711 vspd0: vsp@fea20000 { 949 vspd0: vsp@fea20000 {
712 compatible = "renesas,vsp2"; 950 compatible = "renesas,vsp2";
713 reg = <0 0xfea20000 0 0x8000>; 951 reg = <0 0xfea20000 0 0x5000>;
714 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 952 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cpg CPG_MOD 623>; 953 clocks = <&cpg CPG_MOD 623>;
716 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 954 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@@ -718,18 +956,9 @@
718 renesas,fcp = <&fcpvd0>; 956 renesas,fcp = <&fcpvd0>;
719 }; 957 };
720 958
721 fcpvd0: fcp@fea27000 {
722 compatible = "renesas,fcpv";
723 reg = <0 0xfea27000 0 0x200>;
724 clocks = <&cpg CPG_MOD 603>;
725 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
726 resets = <&cpg 603>;
727 iommus = <&ipmmu_vi0 8>;
728 };
729
730 vspd1: vsp@fea28000 { 959 vspd1: vsp@fea28000 {
731 compatible = "renesas,vsp2"; 960 compatible = "renesas,vsp2";
732 reg = <0 0xfea28000 0 0x8000>; 961 reg = <0 0xfea28000 0 0x5000>;
733 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 962 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&cpg CPG_MOD 622>; 963 clocks = <&cpg CPG_MOD 622>;
735 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 964 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@@ -737,6 +966,24 @@
737 renesas,fcp = <&fcpvd1>; 966 renesas,fcp = <&fcpvd1>;
738 }; 967 };
739 968
969 fcpvb0: fcp@fe96f000 {
970 compatible = "renesas,fcpv";
971 reg = <0 0xfe96f000 0 0x200>;
972 clocks = <&cpg CPG_MOD 607>;
973 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
974 resets = <&cpg 607>;
975 iommus = <&ipmmu_vp0 5>;
976 };
977
978 fcpvd0: fcp@fea27000 {
979 compatible = "renesas,fcpv";
980 reg = <0 0xfea27000 0 0x200>;
981 clocks = <&cpg CPG_MOD 603>;
982 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
983 resets = <&cpg 603>;
984 iommus = <&ipmmu_vi0 8>;
985 };
986
740 fcpvd1: fcp@fea2f000 { 987 fcpvd1: fcp@fea2f000 {
741 compatible = "renesas,fcpv"; 988 compatible = "renesas,fcpv";
742 reg = <0 0xfea2f000 0 0x200>; 989 reg = <0 0xfea2f000 0 0x200>;
@@ -770,23 +1017,95 @@
770 port@1 { 1017 port@1 {
771 reg = <1>; 1018 reg = <1>;
772 du_out_lvds0: endpoint { 1019 du_out_lvds0: endpoint {
1020 remote-endpoint = <&lvds0_in>;
773 }; 1021 };
774 }; 1022 };
775 1023
776 port@2 { 1024 port@2 {
777 reg = <2>; 1025 reg = <2>;
778 du_out_lvds1: endpoint { 1026 du_out_lvds1: endpoint {
1027 remote-endpoint = <&lvds1_in>;
1028 };
1029 };
1030 };
1031 };
1032
1033 lvds0: lvds-encoder@feb90000 {
1034 compatible = "renesas,r8a77995-lvds";
1035 reg = <0 0xfeb90000 0 0x20>;
1036 clocks = <&cpg CPG_MOD 727>;
1037 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1038 resets = <&cpg 727>;
1039 status = "disabled";
1040
1041 ports {
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044
1045 port@0 {
1046 reg = <0>;
1047 lvds0_in: endpoint {
1048 remote-endpoint = <&du_out_lvds0>;
1049 };
1050 };
1051
1052 port@1 {
1053 reg = <1>;
1054 lvds0_out: endpoint {
779 }; 1055 };
780 }; 1056 };
781 }; 1057 };
782 }; 1058 };
783 1059
784 rpc: rpc@0xee200000 { 1060 lvds1: lvds-encoder@feb90100 {
785 compatible = "renesas,rpc-r8a77995", "renesas,rpc"; 1061 compatible = "renesas,r8a77995-lvds";
786 reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; 1062 reg = <0 0xfeb90100 0 0x20>;
787 clocks = <&cpg CPG_MOD 917>; 1063 clocks = <&cpg CPG_MOD 727>;
788 bank-width = <2>; 1064 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1065 resets = <&cpg 726>;
789 status = "disabled"; 1066 status = "disabled";
1067
1068 ports {
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071
1072 port@0 {
1073 reg = <0>;
1074 lvds1_in: endpoint {
1075 remote-endpoint = <&du_out_lvds1>;
1076 };
1077 };
1078
1079 port@1 {
1080 reg = <1>;
1081 lvds1_out: endpoint {
1082 };
1083 };
1084 };
1085 };
1086
1087 prr: chipid@fff00044 {
1088 compatible = "renesas,prr";
1089 reg = <0 0xfff00044 0 4>;
1090 };
1091 };
1092
1093 thermal-zones {
1094 cpu_thermal: cpu-thermal {
1095 polling-delay-passive = <250>;
1096 polling-delay = <1000>;
1097 thermal-sensors = <&thermal>;
1098
1099 trips {
1100 cpu-crit {
1101 temperature = <120000>;
1102 hysteresis = <2000>;
1103 type = "critical";
1104 };
1105 };
1106
1107 cooling-maps {
1108 };
790 }; 1109 };
791 }; 1110 };
792 1111
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