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Diffstat (limited to 'arch/arm/dts/stm32h7-u-boot.dtsi')
-rw-r--r--arch/arm/dts/stm32h7-u-boot.dtsi197
1 files changed, 181 insertions, 16 deletions
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 2525035da1..99fa0e673a 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -1,13 +1,77 @@
1// SPDX-License-Identifier: GPL-2.0+
2
3#include <dt-bindings/memory/stm32-sdram.h>
4
1/{ 5/{
2 clocks { 6 clocks {
3 u-boot,dm-pre-reloc; 7 u-boot,dm-pre-reloc;
4 }; 8 };
5 9
10 aliases {
11 gpio0 = &gpioa;
12 gpio1 = &gpiob;
13 gpio2 = &gpioc;
14 gpio3 = &gpiod;
15 gpio4 = &gpioe;
16 gpio5 = &gpiof;
17 gpio6 = &gpiog;
18 gpio7 = &gpioh;
19 gpio8 = &gpioi;
20 gpio9 = &gpioj;
21 gpio10 = &gpiok;
22 mmc0 = &sdmmc1;
23 };
24
6 soc { 25 soc {
7 u-boot,dm-pre-reloc; 26 u-boot,dm-pre-reloc;
8 pin-controller { 27 pin-controller {
9 u-boot,dm-pre-reloc; 28 u-boot,dm-pre-reloc;
10 }; 29 };
30
31 fmc: fmc@52004000 {
32 compatible = "st,stm32h7-fmc";
33 reg = <0x52004000 0x1000>;
34 clocks = <&rcc FMC_CK>;
35
36 pinctrl-0 = <&fmc_pins>;
37 pinctrl-names = "default";
38 status = "okay";
39
40 /*
41 * Memory configuration from sdram datasheet IS42S32800G-6BLI
42 * firsct bank is bank@0
43 * second bank is bank@1
44 */
45 bank1: bank@1 {
46 st,sdram-control = /bits/ 8 <NO_COL_9
47 NO_ROW_12
48 MWIDTH_32
49 BANKS_4
50 CAS_2
51 SDCLK_3
52 RD_BURST_EN
53 RD_PIPE_DL_0>;
54 st,sdram-timing = /bits/ 8 <TMRD_1
55 TXSR_1
56 TRAS_1
57 TRC_6
58 TRP_2
59 TWR_1
60 TRCD_1>;
61 st,sdram-refcount = <1539>;
62 };
63 };
64
65 sdmmc1: sdmmc@52007000 {
66 compatible = "st,stm32-sdmmc2";
67 reg = <0x52007000 0x1000>;
68 interrupts = <49>;
69 clocks = <&rcc SDMMC1_CK>;
70 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
71 st,idma = <1>;
72 cap-sd-highspeed;
73 cap-mmc-highspeed;
74 };
11 }; 75 };
12}; 76};
13 77
@@ -15,74 +79,175 @@
15 u-boot,dm-pre-reloc; 79 u-boot,dm-pre-reloc;
16}; 80};
17 81
18&clk_lse {
19 u-boot,dm-pre-reloc;
20};
21
22&clk_i2s { 82&clk_i2s {
23 u-boot,dm-pre-reloc; 83 u-boot,dm-pre-reloc;
24}; 84};
25 85
26&pwrcfg { 86&clk_lse {
27 u-boot,dm-pre-reloc; 87 u-boot,dm-pre-reloc;
28}; 88};
29 89
30&rcc {
31 u-boot,dm-pre-reloc;
32};
33 90
34&fmc { 91&fmc {
35 u-boot,dm-pre-reloc; 92 u-boot,dm-pre-reloc;
36}; 93};
37 94
38&clk_hsi {
39 u-boot,dm-pre-reloc;
40};
41
42&clk_csi {
43 u-boot,dm-pre-reloc;
44};
45
46&gpioa { 95&gpioa {
47 u-boot,dm-pre-reloc; 96 u-boot,dm-pre-reloc;
97 compatible = "st,stm32-gpio";
48}; 98};
49 99
50&gpiob { 100&gpiob {
51 u-boot,dm-pre-reloc; 101 u-boot,dm-pre-reloc;
102 compatible = "st,stm32-gpio";
52}; 103};
53 104
54&gpioc { 105&gpioc {
55 u-boot,dm-pre-reloc; 106 u-boot,dm-pre-reloc;
107 compatible = "st,stm32-gpio";
56}; 108};
57 109
58&gpiod { 110&gpiod {
59 u-boot,dm-pre-reloc; 111 u-boot,dm-pre-reloc;
112 compatible = "st,stm32-gpio";
60}; 113};
61 114
62&gpioe { 115&gpioe {
63 u-boot,dm-pre-reloc; 116 u-boot,dm-pre-reloc;
117 compatible = "st,stm32-gpio";
64}; 118};
65 119
66&gpiof { 120&gpiof {
67 u-boot,dm-pre-reloc; 121 u-boot,dm-pre-reloc;
122 compatible = "st,stm32-gpio";
68}; 123};
69 124
70&gpiog { 125&gpiog {
71 u-boot,dm-pre-reloc; 126 u-boot,dm-pre-reloc;
127 compatible = "st,stm32-gpio";
72}; 128};
73 129
74&gpioh { 130&gpioh {
75 u-boot,dm-pre-reloc; 131 u-boot,dm-pre-reloc;
132 compatible = "st,stm32-gpio";
76}; 133};
77 134
78&gpioi { 135&gpioi {
79 u-boot,dm-pre-reloc; 136 u-boot,dm-pre-reloc;
137 compatible = "st,stm32-gpio";
80}; 138};
81 139
82&gpioj { 140&gpioj {
83 u-boot,dm-pre-reloc; 141 u-boot,dm-pre-reloc;
142 compatible = "st,stm32-gpio";
84}; 143};
85 144
86&gpiok { 145&gpiok {
87 u-boot,dm-pre-reloc; 146 u-boot,dm-pre-reloc;
147 compatible = "st,stm32-gpio";
148};
149
150&pinctrl {
151 fmc_pins: fmc@0 {
152 pins {
153 pinmux = <STM32_PINMUX('D', 0, AF12)>,
154 <STM32_PINMUX('D', 1, AF12)>,
155 <STM32_PINMUX('D', 8, AF12)>,
156 <STM32_PINMUX('D', 9, AF12)>,
157 <STM32_PINMUX('D',10, AF12)>,
158 <STM32_PINMUX('D',14, AF12)>,
159 <STM32_PINMUX('D',15, AF12)>,
160
161 <STM32_PINMUX('E', 0, AF12)>,
162 <STM32_PINMUX('E', 1, AF12)>,
163 <STM32_PINMUX('E', 7, AF12)>,
164 <STM32_PINMUX('E', 8, AF12)>,
165 <STM32_PINMUX('E', 9, AF12)>,
166 <STM32_PINMUX('E',10, AF12)>,
167 <STM32_PINMUX('E',11, AF12)>,
168 <STM32_PINMUX('E',12, AF12)>,
169 <STM32_PINMUX('E',13, AF12)>,
170 <STM32_PINMUX('E',14, AF12)>,
171 <STM32_PINMUX('E',15, AF12)>,
172
173 <STM32_PINMUX('F', 0, AF12)>,
174 <STM32_PINMUX('F', 1, AF12)>,
175 <STM32_PINMUX('F', 2, AF12)>,
176 <STM32_PINMUX('F', 3, AF12)>,
177 <STM32_PINMUX('F', 4, AF12)>,
178 <STM32_PINMUX('F', 5, AF12)>,
179 <STM32_PINMUX('F',11, AF12)>,
180 <STM32_PINMUX('F',12, AF12)>,
181 <STM32_PINMUX('F',13, AF12)>,
182 <STM32_PINMUX('F',14, AF12)>,
183 <STM32_PINMUX('F',15, AF12)>,
184
185 <STM32_PINMUX('G', 0, AF12)>,
186 <STM32_PINMUX('G', 1, AF12)>,
187 <STM32_PINMUX('G', 2, AF12)>,
188 <STM32_PINMUX('G', 4, AF12)>,
189 <STM32_PINMUX('G', 5, AF12)>,
190 <STM32_PINMUX('G', 8, AF12)>,
191 <STM32_PINMUX('G',15, AF12)>,
192
193 <STM32_PINMUX('H', 5, AF12)>,
194 <STM32_PINMUX('H', 6, AF12)>,
195 <STM32_PINMUX('H', 7, AF12)>,
196 <STM32_PINMUX('H', 8, AF12)>,
197 <STM32_PINMUX('H', 9, AF12)>,
198 <STM32_PINMUX('H',10, AF12)>,
199 <STM32_PINMUX('H',11, AF12)>,
200 <STM32_PINMUX('H',12, AF12)>,
201 <STM32_PINMUX('H',13, AF12)>,
202 <STM32_PINMUX('H',14, AF12)>,
203 <STM32_PINMUX('H',15, AF12)>,
204
205 <STM32_PINMUX('I', 0, AF12)>,
206 <STM32_PINMUX('I', 1, AF12)>,
207 <STM32_PINMUX('I', 2, AF12)>,
208 <STM32_PINMUX('I', 3, AF12)>,
209 <STM32_PINMUX('I', 4, AF12)>,
210 <STM32_PINMUX('I', 5, AF12)>,
211 <STM32_PINMUX('I', 6, AF12)>,
212 <STM32_PINMUX('I', 7, AF12)>,
213 <STM32_PINMUX('I', 9, AF12)>,
214 <STM32_PINMUX('I',10, AF12)>;
215
216 slew-rate = <3>;
217 };
218 };
219
220 pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
221 pins {
222 pinmux = <STM32_PINMUX('B', 8, AF7)>,
223 <STM32_PINMUX('B', 9, AF7)>,
224 <STM32_PINMUX('C', 6, AF8)>,
225 <STM32_PINMUX('C', 7, AF8)>;
226 drive-push-pull;
227 slew-rate = <3>;
228 };
229 };
230
231 sdmmc1_pins: sdmmc@0 {
232 pins {
233 pinmux = <STM32_PINMUX('C', 8, AF12)>,
234 <STM32_PINMUX('C', 9, AF12)>,
235 <STM32_PINMUX('C',10, AF12)>,
236 <STM32_PINMUX('C',11, AF12)>,
237 <STM32_PINMUX('C',12, AF12)>,
238 <STM32_PINMUX('D', 2, AF12)>;
239
240 slew-rate = <3>;
241 drive-push-pull;
242 bias-disable;
243 };
244 };
245};
246
247&pwrcfg {
248 u-boot,dm-pre-reloc;
249};
250
251&rcc {
252 u-boot,dm-pre-reloc;
88}; 253};
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