diff options
Diffstat (limited to 'arch/arm/dts/sun5i-a10s.dtsi')
-rw-r--r-- | arch/arm/dts/sun5i-a10s.dtsi | 224 |
1 files changed, 67 insertions, 157 deletions
diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi index c41a2ba34d..316cb8b294 100644 --- a/arch/arm/dts/sun5i-a10s.dtsi +++ b/arch/arm/dts/sun5i-a10s.dtsi | |||
@@ -47,7 +47,6 @@ | |||
47 | #include "sun5i.dtsi" | 47 | #include "sun5i.dtsi" |
48 | 48 | ||
49 | #include <dt-bindings/dma/sun4i-a10.h> | 49 | #include <dt-bindings/dma/sun4i-a10.h> |
50 | #include <dt-bindings/pinctrl/sun4i-a10.h> | ||
51 | 50 | ||
52 | / { | 51 | / { |
53 | interrupt-parent = <&intc>; | 52 | interrupt-parent = <&intc>; |
@@ -61,207 +60,118 @@ | |||
61 | #size-cells = <1>; | 60 | #size-cells = <1>; |
62 | ranges; | 61 | ranges; |
63 | 62 | ||
64 | framebuffer@0 { | 63 | framebuffer@2 { |
65 | compatible = "allwinner,simple-framebuffer", | 64 | compatible = "allwinner,simple-framebuffer", |
66 | "simple-framebuffer"; | 65 | "simple-framebuffer"; |
67 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | 66 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
68 | clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, | 67 | clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>, |
69 | <&ahb_gates 43>, <&ahb_gates 44>; | 68 | <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>, |
70 | status = "disabled"; | 69 | <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>; |
71 | }; | ||
72 | |||
73 | framebuffer@1 { | ||
74 | compatible = "allwinner,simple-framebuffer", | ||
75 | "simple-framebuffer"; | ||
76 | allwinner,pipeline = "de_be0-lcd0"; | ||
77 | clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, | ||
78 | <&ahb_gates 44>; | ||
79 | status = "disabled"; | 70 | status = "disabled"; |
80 | }; | 71 | }; |
72 | }; | ||
81 | 73 | ||
82 | framebuffer@2 { | 74 | display-engine { |
83 | compatible = "allwinner,simple-framebuffer", | 75 | compatible = "allwinner,sun5i-a10s-display-engine"; |
84 | "simple-framebuffer"; | 76 | allwinner,pipelines = <&fe0>; |
85 | allwinner,pipeline = "de_be0-lcd0-tve0"; | ||
86 | clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>, | ||
87 | <&ahb_gates 36>, <&ahb_gates 44>; | ||
88 | status = "disabled"; | ||
89 | }; | ||
90 | }; | 77 | }; |
91 | 78 | ||
92 | clocks { | 79 | soc@1c00000 { |
93 | ahb_gates: clk@01c20060 { | 80 | hdmi: hdmi@1c16000 { |
94 | #clock-cells = <1>; | 81 | compatible = "allwinner,sun5i-a10s-hdmi"; |
95 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; | 82 | reg = <0x01c16000 0x1000>; |
96 | reg = <0x01c20060 0x8>; | 83 | interrupts = <58>; |
97 | clocks = <&ahb>; | 84 | clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, |
98 | clock-indices = <0>, <1>, | 85 | <&ccu CLK_PLL_VIDEO0_2X>, |
99 | <2>, <5>, <6>, | 86 | <&ccu CLK_PLL_VIDEO1_2X>; |
100 | <7>, <8>, <9>, | 87 | clock-names = "ahb", "mod", "pll-0", "pll-1"; |
101 | <10>, <13>, | 88 | dmas = <&dma SUN4I_DMA_NORMAL 16>, |
102 | <14>, <17>, <18>, | 89 | <&dma SUN4I_DMA_NORMAL 16>, |
103 | <20>, <21>, <22>, | 90 | <&dma SUN4I_DMA_DEDICATED 24>; |
104 | <26>, <28>, <32>, | 91 | dma-names = "ddc-tx", "ddc-rx", "audio-tx"; |
105 | <34>, <36>, <40>, | 92 | status = "disabled"; |
106 | <43>, <44>, | ||
107 | <46>, <51>, | ||
108 | <52>; | ||
109 | clock-output-names = "ahb_usbotg", "ahb_ehci", | ||
110 | "ahb_ohci", "ahb_ss", "ahb_dma", | ||
111 | "ahb_bist", "ahb_mmc0", "ahb_mmc1", | ||
112 | "ahb_mmc2", "ahb_nand", | ||
113 | "ahb_sdram", "ahb_emac", "ahb_ts", | ||
114 | "ahb_spi0", "ahb_spi1", "ahb_spi2", | ||
115 | "ahb_gps", "ahb_stimer", "ahb_ve", | ||
116 | "ahb_tve", "ahb_lcd", "ahb_csi", | ||
117 | "ahb_hdmi", "ahb_de_be", | ||
118 | "ahb_de_fe", "ahb_iep", | ||
119 | "ahb_mali400"; | ||
120 | }; | ||
121 | 93 | ||
122 | apb0_gates: clk@01c20068 { | 94 | ports { |
123 | #clock-cells = <1>; | 95 | #address-cells = <1>; |
124 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; | 96 | #size-cells = <0>; |
125 | reg = <0x01c20068 0x4>; | ||
126 | clocks = <&apb0>; | ||
127 | clock-indices = <0>, <3>, | ||
128 | <5>, <6>, | ||
129 | <10>; | ||
130 | clock-output-names = "apb0_codec", "apb0_iis", | ||
131 | "apb0_pio", "apb0_ir", | ||
132 | "apb0_keypad"; | ||
133 | }; | ||
134 | 97 | ||
135 | apb1_gates: clk@01c2006c { | 98 | hdmi_in: port@0 { |
136 | #clock-cells = <1>; | 99 | reg = <0>; |
137 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; | ||
138 | reg = <0x01c2006c 0x4>; | ||
139 | clocks = <&apb1>; | ||
140 | clock-indices = <0>, <1>, | ||
141 | <2>, <16>, | ||
142 | <17>, <18>, | ||
143 | <19>; | ||
144 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | ||
145 | "apb1_i2c2", "apb1_uart0", | ||
146 | "apb1_uart1", "apb1_uart2", | ||
147 | "apb1_uart3"; | ||
148 | }; | ||
149 | }; | ||
150 | 100 | ||
151 | soc@01c00000 { | 101 | hdmi_in_tcon0: endpoint { |
152 | emac: ethernet@01c0b000 { | 102 | remote-endpoint = <&tcon0_out_hdmi>; |
153 | compatible = "allwinner,sun4i-a10-emac"; | 103 | }; |
154 | reg = <0x01c0b000 0x1000>; | 104 | }; |
155 | interrupts = <55>; | ||
156 | clocks = <&ahb_gates 17>; | ||
157 | allwinner,sram = <&emac_sram 1>; | ||
158 | status = "disabled"; | ||
159 | }; | ||
160 | 105 | ||
161 | mdio: mdio@01c0b080 { | 106 | hdmi_out: port@1 { |
162 | compatible = "allwinner,sun4i-a10-mdio"; | 107 | #address-cells = <1>; |
163 | reg = <0x01c0b080 0x14>; | 108 | #size-cells = <0>; |
164 | status = "disabled"; | 109 | reg = <1>; |
165 | #address-cells = <1>; | 110 | }; |
166 | #size-cells = <0>; | 111 | }; |
167 | }; | 112 | }; |
168 | 113 | ||
169 | pwm: pwm@01c20e00 { | 114 | pwm: pwm@1c20e00 { |
170 | compatible = "allwinner,sun5i-a10s-pwm"; | 115 | compatible = "allwinner,sun5i-a10s-pwm"; |
171 | reg = <0x01c20e00 0xc>; | 116 | reg = <0x01c20e00 0xc>; |
172 | clocks = <&osc24M>; | 117 | clocks = <&ccu CLK_HOSC>; |
173 | #pwm-cells = <3>; | 118 | #pwm-cells = <3>; |
174 | status = "disabled"; | 119 | status = "disabled"; |
175 | }; | 120 | }; |
176 | |||
177 | uart0: serial@01c28000 { | ||
178 | compatible = "snps,dw-apb-uart"; | ||
179 | reg = <0x01c28000 0x400>; | ||
180 | interrupts = <1>; | ||
181 | reg-shift = <2>; | ||
182 | reg-io-width = <4>; | ||
183 | clocks = <&apb1_gates 16>; | ||
184 | status = "disabled"; | ||
185 | }; | ||
186 | |||
187 | uart2: serial@01c28800 { | ||
188 | compatible = "snps,dw-apb-uart"; | ||
189 | reg = <0x01c28800 0x400>; | ||
190 | interrupts = <3>; | ||
191 | reg-shift = <2>; | ||
192 | reg-io-width = <4>; | ||
193 | clocks = <&apb1_gates 18>; | ||
194 | status = "disabled"; | ||
195 | }; | ||
196 | }; | 121 | }; |
197 | }; | 122 | }; |
198 | 123 | ||
124 | &ccu { | ||
125 | compatible = "allwinner,sun5i-a10s-ccu"; | ||
126 | }; | ||
127 | |||
199 | &pio { | 128 | &pio { |
200 | compatible = "allwinner,sun5i-a10s-pinctrl"; | 129 | compatible = "allwinner,sun5i-a10s-pinctrl"; |
201 | 130 | ||
202 | uart0_pins_a: uart0@0 { | 131 | uart0_pins_a: uart0@0 { |
203 | allwinner,pins = "PB19", "PB20"; | 132 | pins = "PB19", "PB20"; |
204 | allwinner,function = "uart0"; | 133 | function = "uart0"; |
205 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | ||
206 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | ||
207 | }; | 134 | }; |
208 | 135 | ||
209 | uart2_pins_a: uart2@0 { | 136 | uart2_pins_b: uart2@1 { |
210 | allwinner,pins = "PC18", "PC19"; | 137 | pins = "PC18", "PC19"; |
211 | allwinner,function = "uart2"; | 138 | function = "uart2"; |
212 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | ||
213 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | ||
214 | }; | 139 | }; |
215 | 140 | ||
216 | emac_pins_a: emac0@0 { | 141 | emac_pins_b: emac0@1 { |
217 | allwinner,pins = "PA0", "PA1", "PA2", | 142 | pins = "PA0", "PA1", "PA2", |
218 | "PA3", "PA4", "PA5", "PA6", | 143 | "PA3", "PA4", "PA5", "PA6", |
219 | "PA7", "PA8", "PA9", "PA10", | 144 | "PA7", "PA8", "PA9", "PA10", |
220 | "PA11", "PA12", "PA13", "PA14", | 145 | "PA11", "PA12", "PA13", "PA14", |
221 | "PA15", "PA16"; | 146 | "PA15", "PA16"; |
222 | allwinner,function = "emac"; | 147 | function = "emac"; |
223 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | ||
224 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | ||
225 | }; | ||
226 | |||
227 | emac_pins_b: emac0@1 { | ||
228 | allwinner,pins = "PD6", "PD7", "PD10", | ||
229 | "PD11", "PD12", "PD13", "PD14", | ||
230 | "PD15", "PD18", "PD19", "PD20", | ||
231 | "PD21", "PD22", "PD23", "PD24", | ||
232 | "PD25", "PD26", "PD27"; | ||
233 | allwinner,function = "emac"; | ||
234 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | ||
235 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | ||
236 | }; | 148 | }; |
237 | 149 | ||
238 | mmc1_pins_a: mmc1@0 { | 150 | mmc1_pins_a: mmc1@0 { |
239 | allwinner,pins = "PG3", "PG4", "PG5", | 151 | pins = "PG3", "PG4", "PG5", |
240 | "PG6", "PG7", "PG8"; | 152 | "PG6", "PG7", "PG8"; |
241 | allwinner,function = "mmc1"; | 153 | function = "mmc1"; |
242 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | 154 | drive-strength = <30>; |
243 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | ||
244 | }; | 155 | }; |
245 | 156 | ||
246 | spi2_pins_a: spi2@0 { | 157 | spi2_pins_b: spi2@1 { |
247 | allwinner,pins = "PB12", "PB13", "PB14"; | 158 | pins = "PB12", "PB13", "PB14"; |
248 | allwinner,function = "spi2"; | 159 | function = "spi2"; |
249 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | ||
250 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | ||
251 | }; | 160 | }; |
252 | 161 | ||
253 | spi2_cs0_pins_a: spi2_cs0@0 { | 162 | spi2_cs0_pins_b: spi2_cs0@1 { |
254 | allwinner,pins = "PB11"; | 163 | pins = "PB11"; |
255 | allwinner,function = "spi2"; | 164 | function = "spi2"; |
256 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | ||
257 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | ||
258 | }; | 165 | }; |
259 | }; | 166 | }; |
260 | 167 | ||
261 | &sram_a { | 168 | &sram_a { |
262 | emac_sram: sram-section@8000 { | 169 | }; |
263 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | 170 | |
264 | reg = <0x8000 0x4000>; | 171 | &tcon0_out { |
265 | status = "disabled"; | 172 | tcon0_out_hdmi: endpoint@2 { |
173 | reg = <2>; | ||
174 | remote-endpoint = <&hdmi_in_tcon0>; | ||
175 | allwinner,tcon-channel = <1>; | ||
266 | }; | 176 | }; |
267 | }; | 177 | }; |