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Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/soc.h')
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h67
1 files changed, 35 insertions, 32 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 9a219a6a1d..234440b5fe 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -53,11 +53,37 @@ struct cpu_type {
53 53
54#define CPU_TYPE_ENTRY(n, v, nc) \ 54#define CPU_TYPE_ENTRY(n, v, nc) \
55 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 55 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
56
57#ifdef CONFIG_TFABOOT
58#define SMC_DRAM_BANK_INFO (0xC200FF12)
59#define SIP_SVC_RCW 0xC200FF18
60
61phys_size_t tfa_get_dram_size(void);
62
63enum boot_src {
64 BOOT_SOURCE_RESERVED = 0,
65 BOOT_SOURCE_IFC_NOR,
66 BOOT_SOURCE_IFC_NAND,
67 BOOT_SOURCE_QSPI_NOR,
68 BOOT_SOURCE_QSPI_NAND,
69 BOOT_SOURCE_XSPI_NOR,
70 BOOT_SOURCE_XSPI_NAND,
71 BOOT_SOURCE_SD_MMC,
72 BOOT_SOURCE_SD_MMC2,
73 BOOT_SOURCE_I2C1_EXTENDED,
74};
75
76enum boot_src get_boot_src(void);
77#endif
56#endif 78#endif
57#define SVR_WO_E 0xFFFFFE 79#define SVR_WO_E 0xFFFFFE
58#define SVR_LS1012A 0x870400 80#define SVR_LS1012A 0x870400
59#define SVR_LS1043A 0x879200 81#define SVR_LS1043A 0x879200
60#define SVR_LS1023A 0x879208 82#define SVR_LS1023A 0x879208
83/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
84#define SVR_LS1043A_P23 0x879202
85#define SVR_LS1023A_P23 0x87920A
86#define SVR_LS1028A 0x870B00
61#define SVR_LS1046A 0x870700 87#define SVR_LS1046A 0x870700
62#define SVR_LS1026A 0x870708 88#define SVR_LS1026A 0x870708
63#define SVR_LS1048A 0x870320 89#define SVR_LS1048A 0x870320
@@ -74,50 +100,24 @@ struct cpu_type {
74#define SVR_LS2044A 0x870930 100#define SVR_LS2044A 0x870930
75#define SVR_LS2081A 0x870918 101#define SVR_LS2081A 0x870918
76#define SVR_LS2041A 0x870914 102#define SVR_LS2041A 0x870914
103#define SVR_LX2160A 0x873601
104#define SVR_LX2120A 0x873621
105#define SVR_LX2080A 0x873603
77 106
78#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 107#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
79#define SVR_MIN(svr) (((svr) >> 0) & 0xf) 108#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
80#define SVR_REV(svr) (((svr) >> 0) & 0xff) 109#define SVR_REV(svr) (((svr) >> 0) & 0xff)
81#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 110#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
82#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 111#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
112#ifdef CONFIG_ARCH_LX2160A
113#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
114#endif
83#define IS_SVR_REV(svr, maj, min) \ 115#define IS_SVR_REV(svr, maj, min) \
84 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 116 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
85#define SVR_DEV(svr) ((svr) >> 8) 117#define SVR_DEV(svr) ((svr) >> 8)
86#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) 118#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
87 119
88/* ahci port register default value */
89#define AHCI_PORT_PHY_1_CFG 0xa003fffe
90#define AHCI_PORT_PHY2_CFG 0x28184d1f
91#define AHCI_PORT_PHY3_CFG 0x0e081509
92#define AHCI_PORT_TRANS_CFG 0x08000029
93#define AHCI_PORT_AXICC_CFG 0x3fffffff
94
95#ifndef __ASSEMBLY__ 120#ifndef __ASSEMBLY__
96/* AHCI (sata) register map */
97struct ccsr_ahci {
98 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
99 u32 pcfg; /* port config */
100 u32 ppcfg; /* port phy1 config */
101 u32 pp2c; /* port phy2 config */
102 u32 pp3c; /* port phy3 config */
103 u32 pp4c; /* port phy4 config */
104 u32 pp5c; /* port phy5 config */
105 u32 axicc; /* AXI cache control */
106 u32 paxic; /* port AXI config */
107 u32 axipc; /* AXI PROT control */
108 u32 ptc; /* port Trans Config */
109 u32 pts; /* port Trans Status */
110 u32 plc; /* port link config */
111 u32 plc1; /* port link config1 */
112 u32 plc2; /* port link config2 */
113 u32 pls; /* port link status */
114 u32 pls1; /* port link status1 */
115 u32 pcmdc; /* port CMD config */
116 u32 ppcs; /* port phy control status */
117 u32 pberr; /* port 0/1 BIST error */
118 u32 cmds; /* port 0/1 CMD status error */
119};
120
121#ifdef CONFIG_FSL_LSCH3 121#ifdef CONFIG_FSL_LSCH3
122void fsl_lsch3_early_init_f(void); 122void fsl_lsch3_early_init_f(void);
123int get_core_volt_from_fuse(void); 123int get_core_volt_from_fuse(void);
@@ -130,6 +130,9 @@ int board_setup_core_volt(u32 vdd);
130void init_pfe_scfg_dcfg_regs(void); 130void init_pfe_scfg_dcfg_regs(void);
131#endif 131#endif
132#endif 132#endif
133#ifdef CONFIG_QSPI_AHB_INIT
134int qspi_ahb_init(void);
135#endif
133 136
134void cpu_name(char *name); 137void cpu_name(char *name);
135#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 138#ifdef CONFIG_SYS_FSL_ERRATUM_A009635