diff options
Diffstat (limited to 'arch/arm/include/asm/arch-rockchip/sdram_common.h')
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/sdram_common.h | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 671c318d50..8027b53636 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h | |||
@@ -5,6 +5,44 @@ | |||
5 | 5 | ||
6 | #ifndef _ASM_ARCH_SDRAM_COMMON_H | 6 | #ifndef _ASM_ARCH_SDRAM_COMMON_H |
7 | #define _ASM_ARCH_SDRAM_COMMON_H | 7 | #define _ASM_ARCH_SDRAM_COMMON_H |
8 | |||
9 | enum { | ||
10 | DDR4 = 0, | ||
11 | DDR3 = 0x3, | ||
12 | LPDDR2 = 0x5, | ||
13 | LPDDR3 = 0x6, | ||
14 | LPDDR4 = 0x7, | ||
15 | UNUSED = 0xFF | ||
16 | }; | ||
17 | |||
18 | struct sdram_cap_info { | ||
19 | unsigned int rank; | ||
20 | /* dram column number, 0 means this channel is invalid */ | ||
21 | unsigned int col; | ||
22 | /* dram bank number, 3:8bank, 2:4bank */ | ||
23 | unsigned int bk; | ||
24 | /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ | ||
25 | unsigned int bw; | ||
26 | /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ | ||
27 | unsigned int dbw; | ||
28 | /* | ||
29 | * row_3_4 = 1: 6Gb or 12Gb die | ||
30 | * row_3_4 = 0: normal die, power of 2 | ||
31 | */ | ||
32 | unsigned int row_3_4; | ||
33 | unsigned int cs0_row; | ||
34 | unsigned int cs1_row; | ||
35 | unsigned int ddrconfig; | ||
36 | }; | ||
37 | |||
38 | struct sdram_base_params { | ||
39 | unsigned int ddr_freq; | ||
40 | unsigned int dramtype; | ||
41 | unsigned int num_channels; | ||
42 | unsigned int stride; | ||
43 | unsigned int odt; | ||
44 | }; | ||
45 | |||
8 | /* | 46 | /* |
9 | * sys_reg bitfield struct | 47 | * sys_reg bitfield struct |
10 | * [31] row_3_4_ch1 | 48 | * [31] row_3_4_ch1 |
@@ -28,30 +66,82 @@ | |||
28 | * [1:0] dbw_ch0 | 66 | * [1:0] dbw_ch0 |
29 | */ | 67 | */ |
30 | #define SYS_REG_DDRTYPE_SHIFT 13 | 68 | #define SYS_REG_DDRTYPE_SHIFT 13 |
69 | #define DDR_SYS_REG_VERSION 2 | ||
31 | #define SYS_REG_DDRTYPE_MASK 7 | 70 | #define SYS_REG_DDRTYPE_MASK 7 |
32 | #define SYS_REG_NUM_CH_SHIFT 12 | 71 | #define SYS_REG_NUM_CH_SHIFT 12 |
33 | #define SYS_REG_NUM_CH_MASK 1 | 72 | #define SYS_REG_NUM_CH_MASK 1 |
34 | #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) | 73 | #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) |
35 | #define SYS_REG_ROW_3_4_MASK 1 | 74 | #define SYS_REG_ROW_3_4_MASK 1 |
75 | #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) | ||
36 | #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) | 76 | #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) |
77 | #define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch)) | ||
78 | #define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT) | ||
79 | #define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \ | ||
80 | SYS_REG_NUM_CH_SHIFT) | ||
37 | #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) | 81 | #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) |
38 | #define SYS_REG_RANK_MASK 1 | 82 | #define SYS_REG_RANK_MASK 1 |
83 | #define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \ | ||
84 | SYS_REG_RANK_SHIFT(ch)) | ||
39 | #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) | 85 | #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) |
40 | #define SYS_REG_COL_MASK 3 | 86 | #define SYS_REG_COL_MASK 3 |
87 | #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch)) | ||
41 | #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) | 88 | #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) |
42 | #define SYS_REG_BK_MASK 1 | 89 | #define SYS_REG_BK_MASK 1 |
90 | #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ | ||
91 | SYS_REG_BK_SHIFT(ch)) | ||
43 | #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) | 92 | #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) |
44 | #define SYS_REG_CS0_ROW_MASK 3 | 93 | #define SYS_REG_CS0_ROW_MASK 3 |
45 | #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) | 94 | #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) |
46 | #define SYS_REG_CS1_ROW_MASK 3 | 95 | #define SYS_REG_CS1_ROW_MASK 3 |
47 | #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) | 96 | #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) |
48 | #define SYS_REG_BW_MASK 3 | 97 | #define SYS_REG_BW_MASK 3 |
98 | #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch)) | ||
49 | #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) | 99 | #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) |
50 | #define SYS_REG_DBW_MASK 3 | 100 | #define SYS_REG_DBW_MASK 3 |
101 | #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) | ||
102 | |||
103 | #define SYS_REG_ENC_VERSION(n) ((n) << 28) | ||
104 | #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ | ||
105 | (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ | ||
106 | (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ | ||
107 | (5 + 2 * (ch)); \ | ||
108 | } while (0) | ||
109 | |||
110 | #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ | ||
111 | (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ | ||
112 | (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ | ||
113 | (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ | ||
114 | (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ | ||
115 | (4 + 2 * (ch)); \ | ||
116 | } while (0) | ||
117 | |||
118 | #define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch)) | ||
119 | #define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch)) | ||
51 | 120 | ||
52 | /* Get sdram size decode from reg */ | 121 | /* Get sdram size decode from reg */ |
53 | size_t rockchip_sdram_size(phys_addr_t reg); | 122 | size_t rockchip_sdram_size(phys_addr_t reg); |
54 | 123 | ||
55 | /* Called by U-Boot board_init_r for Rockchip SoCs */ | 124 | /* Called by U-Boot board_init_r for Rockchip SoCs */ |
56 | int dram_init(void); | 125 | int dram_init(void); |
126 | |||
127 | #if !defined(CONFIG_RAM_ROCKCHIP_DEBUG) | ||
128 | inline void sdram_print_dram_type(unsigned char dramtype) | ||
129 | { | ||
130 | } | ||
131 | |||
132 | inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, | ||
133 | struct sdram_base_params *base) | ||
134 | { | ||
135 | } | ||
136 | |||
137 | inline void sdram_print_stride(unsigned int stride) | ||
138 | { | ||
139 | } | ||
140 | #else | ||
141 | void sdram_print_dram_type(unsigned char dramtype); | ||
142 | void sdram_print_ddr_info(struct sdram_cap_info *cap_info, | ||
143 | struct sdram_base_params *base); | ||
144 | void sdram_print_stride(unsigned int stride); | ||
145 | #endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ | ||
146 | |||
57 | #endif | 147 | #endif |