diff options
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h')
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h index 09d13f6fd3..62249b3695 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h | |||
@@ -1,9 +1,13 @@ | |||
1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | 2 | /* |
3 | * Copyright (C) 2017 Intel Corporation <www.intel.com> | 3 | * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> |
4 | * All rights reserved. | 4 | * All rights reserved. |
5 | */ | 5 | */ |
6 | 6 | ||
7 | #include <asm/cache.h> | ||
8 | #include <altera.h> | ||
9 | #include <image.h> | ||
10 | |||
7 | #ifndef _FPGA_MANAGER_ARRIA10_H_ | 11 | #ifndef _FPGA_MANAGER_ARRIA10_H_ |
8 | #define _FPGA_MANAGER_ARRIA10_H_ | 12 | #define _FPGA_MANAGER_ARRIA10_H_ |
9 | 13 | ||
@@ -51,6 +55,10 @@ | |||
51 | #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) | 55 | #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) |
52 | #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 | 56 | #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 |
53 | 57 | ||
58 | #define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c | ||
59 | #define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d | ||
60 | #define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001 | ||
61 | #define FPGA_SOCFPGA_A10_RBF_CORE 0x8001 | ||
54 | #ifndef __ASSEMBLY__ | 62 | #ifndef __ASSEMBLY__ |
55 | 63 | ||
56 | struct socfpga_fpga_manager { | 64 | struct socfpga_fpga_manager { |
@@ -88,12 +96,40 @@ struct socfpga_fpga_manager { | |||
88 | u32 imgcfg_fifo_status; | 96 | u32 imgcfg_fifo_status; |
89 | }; | 97 | }; |
90 | 98 | ||
99 | enum rbf_type { | ||
100 | unknown, | ||
101 | periph_section, | ||
102 | core_section | ||
103 | }; | ||
104 | |||
105 | enum rbf_security { | ||
106 | invalid, | ||
107 | unencrypted, | ||
108 | encrypted | ||
109 | }; | ||
110 | |||
111 | struct rbf_info { | ||
112 | enum rbf_type section; | ||
113 | enum rbf_security security; | ||
114 | }; | ||
115 | |||
116 | struct fpga_loadfs_info { | ||
117 | fpga_fs_info *fpga_fsinfo; | ||
118 | u32 remaining; | ||
119 | u32 offset; | ||
120 | struct rbf_info rbfinfo; | ||
121 | }; | ||
122 | |||
91 | /* Functions */ | 123 | /* Functions */ |
92 | int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); | 124 | int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); |
93 | int fpgamgr_program_finish(void); | 125 | int fpgamgr_program_finish(void); |
94 | int is_fpgamgr_user_mode(void); | 126 | int is_fpgamgr_user_mode(void); |
95 | int fpgamgr_wait_early_user_mode(void); | 127 | int fpgamgr_wait_early_user_mode(void); |
96 | 128 | const char *get_fpga_filename(void); | |
129 | int is_fpgamgr_early_user_mode(void); | ||
130 | int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, | ||
131 | u32 offset); | ||
132 | void fpgamgr_program(const void *buf, size_t bsize, u32 offset); | ||
97 | #endif /* __ASSEMBLY__ */ | 133 | #endif /* __ASSEMBLY__ */ |
98 | 134 | ||
99 | #endif /* _FPGA_MANAGER_ARRIA10_H_ */ | 135 | #endif /* _FPGA_MANAGER_ARRIA10_H_ */ |