diff options
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
-rw-r--r-- | arch/arm/mach-socfpga/misc.c | 168 |
1 files changed, 83 insertions, 85 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index fca86507f1..49dadd4c3d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c | |||
@@ -40,16 +40,18 @@ struct bsel bsel_str[] = { | |||
40 | 40 | ||
41 | int dram_init(void) | 41 | int dram_init(void) |
42 | { | 42 | { |
43 | gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); | 43 | if (fdtdec_setup_mem_size_base() != 0) |
44 | return -EINVAL; | ||
45 | |||
44 | return 0; | 46 | return 0; |
45 | } | 47 | } |
46 | 48 | ||
47 | void enable_caches(void) | 49 | void enable_caches(void) |
48 | { | 50 | { |
49 | #ifndef CONFIG_SYS_ICACHE_OFF | 51 | #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) |
50 | icache_enable(); | 52 | icache_enable(); |
51 | #endif | 53 | #endif |
52 | #ifndef CONFIG_SYS_DCACHE_OFF | 54 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
53 | dcache_enable(); | 55 | dcache_enable(); |
54 | #endif | 56 | #endif |
55 | } | 57 | } |
@@ -57,9 +59,30 @@ void enable_caches(void) | |||
57 | #ifdef CONFIG_SYS_L2_PL310 | 59 | #ifdef CONFIG_SYS_L2_PL310 |
58 | void v7_outer_cache_enable(void) | 60 | void v7_outer_cache_enable(void) |
59 | { | 61 | { |
62 | struct udevice *dev; | ||
63 | |||
64 | if (uclass_get_device(UCLASS_CACHE, 0, &dev)) | ||
65 | pr_err("cache controller driver NOT found!\n"); | ||
66 | } | ||
67 | |||
68 | void v7_outer_cache_disable(void) | ||
69 | { | ||
70 | /* Disable the L2 cache */ | ||
71 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); | ||
72 | } | ||
73 | |||
74 | void socfpga_pl310_clear(void) | ||
75 | { | ||
76 | u32 mask = 0xff, ena = 0; | ||
77 | |||
78 | icache_enable(); | ||
79 | |||
60 | /* Disable the L2 cache */ | 80 | /* Disable the L2 cache */ |
61 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); | 81 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
62 | 82 | ||
83 | writel(0x0, &pl310->pl310_tag_latency_ctrl); | ||
84 | writel(0x10, &pl310->pl310_data_latency_ctrl); | ||
85 | |||
63 | /* enable BRESP, instruction and data prefetch, full line of zeroes */ | 86 | /* enable BRESP, instruction and data prefetch, full line of zeroes */ |
64 | setbits_le32(&pl310->pl310_aux_ctrl, | 87 | setbits_le32(&pl310->pl310_aux_ctrl, |
65 | L310_AUX_CTRL_DATA_PREFETCH_MASK | | 88 | L310_AUX_CTRL_DATA_PREFETCH_MASK | |
@@ -67,11 +90,37 @@ void v7_outer_cache_enable(void) | |||
67 | L310_SHARED_ATT_OVERRIDE_ENABLE); | 90 | L310_SHARED_ATT_OVERRIDE_ENABLE); |
68 | 91 | ||
69 | /* Enable the L2 cache */ | 92 | /* Enable the L2 cache */ |
70 | setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); | 93 | ena = readl(&pl310->pl310_ctrl); |
71 | } | 94 | ena |= L2X0_CTRL_EN; |
95 | |||
96 | /* | ||
97 | * Invalidate the PL310 L2 cache. Keep the invalidation code | ||
98 | * entirely in L1 I-cache to avoid any bus traffic through | ||
99 | * the L2. | ||
100 | */ | ||
101 | asm volatile( | ||
102 | ".align 5 \n" | ||
103 | " b 3f \n" | ||
104 | "1: str %1, [%4] \n" | ||
105 | " dsb \n" | ||
106 | " isb \n" | ||
107 | " str %0, [%2] \n" | ||
108 | " dsb \n" | ||
109 | " isb \n" | ||
110 | "2: ldr %0, [%2] \n" | ||
111 | " cmp %0, #0 \n" | ||
112 | " bne 2b \n" | ||
113 | " str %0, [%3] \n" | ||
114 | " dsb \n" | ||
115 | " isb \n" | ||
116 | " b 4f \n" | ||
117 | "3: b 1b \n" | ||
118 | "4: nop \n" | ||
119 | : "+r"(mask), "+r"(ena) | ||
120 | : "r"(&pl310->pl310_inv_way), | ||
121 | "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) | ||
122 | : "memory", "cc"); | ||
72 | 123 | ||
73 | void v7_outer_cache_disable(void) | ||
74 | { | ||
75 | /* Disable the L2 cache */ | 124 | /* Disable the L2 cache */ |
76 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); | 125 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
77 | } | 126 | } |
@@ -86,33 +135,11 @@ int overwrite_console(void) | |||
86 | #endif | 135 | #endif |
87 | 136 | ||
88 | #ifdef CONFIG_FPGA | 137 | #ifdef CONFIG_FPGA |
89 | /* | ||
90 | * FPGA programming support for SoC FPGA Cyclone V | ||
91 | */ | ||
92 | static Altera_desc altera_fpga[] = { | ||
93 | { | ||
94 | /* Family */ | ||
95 | Altera_SoCFPGA, | ||
96 | /* Interface type */ | ||
97 | fast_passive_parallel, | ||
98 | /* No limitation as additional data will be ignored */ | ||
99 | -1, | ||
100 | /* No device function table */ | ||
101 | NULL, | ||
102 | /* Base interface address specified in driver */ | ||
103 | NULL, | ||
104 | /* No cookie implementation */ | ||
105 | 0 | ||
106 | }, | ||
107 | }; | ||
108 | |||
109 | /* add device descriptor to FPGA device table */ | 138 | /* add device descriptor to FPGA device table */ |
110 | void socfpga_fpga_add(void) | 139 | void socfpga_fpga_add(void *fpga_desc) |
111 | { | 140 | { |
112 | int i; | ||
113 | fpga_init(); | 141 | fpga_init(); |
114 | for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) | 142 | fpga_add(fpga_altera, fpga_desc); |
115 | fpga_add(fpga_altera, &altera_fpga[i]); | ||
116 | } | 143 | } |
117 | #endif | 144 | #endif |
118 | 145 | ||
@@ -140,67 +167,38 @@ int arch_cpu_init(void) | |||
140 | return 0; | 167 | return 0; |
141 | } | 168 | } |
142 | 169 | ||
143 | #ifdef CONFIG_ETH_DESIGNWARE | 170 | #ifndef CONFIG_SPL_BUILD |
144 | static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) | 171 | static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
145 | { | 172 | { |
146 | if (!phymode) | 173 | unsigned int mask = ~0; |
147 | return -EINVAL; | ||
148 | 174 | ||
149 | if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { | 175 | if (argc < 2 || argc > 3) |
150 | *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; | 176 | return CMD_RET_USAGE; |
151 | return 0; | ||
152 | } | ||
153 | |||
154 | if (!strcmp(phymode, "rgmii")) { | ||
155 | *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; | ||
156 | return 0; | ||
157 | } | ||
158 | 177 | ||
159 | if (!strcmp(phymode, "rmii")) { | 178 | argv++; |
160 | *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; | ||
161 | return 0; | ||
162 | } | ||
163 | 179 | ||
164 | return -EINVAL; | 180 | if (argc == 3) |
165 | } | 181 | mask = simple_strtoul(argv[1], NULL, 16); |
166 | 182 | ||
167 | int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, | 183 | switch (*argv[0]) { |
168 | const u8 phymode)) | 184 | case 'e': /* Enable */ |
169 | { | 185 | do_bridge_reset(1, mask); |
170 | const void *fdt = gd->fdt_blob; | 186 | break; |
171 | struct fdtdec_phandle_args args; | 187 | case 'd': /* Disable */ |
172 | const char *phy_mode; | 188 | do_bridge_reset(0, mask); |
173 | u32 phy_modereg; | 189 | break; |
174 | int nodes[2]; /* Max. two GMACs */ | 190 | default: |
175 | int ret, count; | 191 | return CMD_RET_USAGE; |
176 | int i, node; | ||
177 | |||
178 | count = fdtdec_find_aliases_for_id(fdt, "ethernet", | ||
179 | COMPAT_ALTERA_SOCFPGA_DWMAC, | ||
180 | nodes, ARRAY_SIZE(nodes)); | ||
181 | for (i = 0; i < count; i++) { | ||
182 | node = nodes[i]; | ||
183 | if (node <= 0) | ||
184 | continue; | ||
185 | |||
186 | ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", | ||
187 | "#reset-cells", 1, 0, | ||
188 | &args); | ||
189 | if (ret || (args.args_count != 1)) { | ||
190 | debug("GMAC%i: Failed to parse DT 'resets'!\n", i); | ||
191 | continue; | ||
192 | } | ||
193 | |||
194 | phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); | ||
195 | ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); | ||
196 | if (ret) { | ||
197 | debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); | ||
198 | continue; | ||
199 | } | ||
200 | |||
201 | resetfn(args.args[0], phy_modereg); | ||
202 | } | 192 | } |
203 | 193 | ||
204 | return 0; | 194 | return 0; |
205 | } | 195 | } |
196 | |||
197 | U_BOOT_CMD(bridge, 3, 1, do_bridge, | ||
198 | "SoCFPGA HPS FPGA bridge control", | ||
199 | "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" | ||
200 | "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" | ||
201 | "" | ||
202 | ); | ||
203 | |||
206 | #endif | 204 | #endif |