diff options
Diffstat (limited to 'arch/arm/mach-socfpga/misc_s10.c')
-rw-r--r-- | arch/arm/mach-socfpga/misc_s10.c | 168 |
1 files changed, 168 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c new file mode 100644 index 0000000000..29abc4a54c --- /dev/null +++ b/arch/arm/mach-socfpga/misc_s10.c | |||
@@ -0,0 +1,168 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> | ||
4 | * | ||
5 | */ | ||
6 | |||
7 | #include <altera.h> | ||
8 | #include <common.h> | ||
9 | #include <errno.h> | ||
10 | #include <fdtdec.h> | ||
11 | #include <miiphy.h> | ||
12 | #include <netdev.h> | ||
13 | #include <asm/io.h> | ||
14 | #include <asm/arch/reset_manager.h> | ||
15 | #include <asm/arch/system_manager.h> | ||
16 | #include <asm/arch/misc.h> | ||
17 | #include <asm/pl310.h> | ||
18 | #include <linux/libfdt.h> | ||
19 | #include <asm/arch/mailbox_s10.h> | ||
20 | |||
21 | #include <dt-bindings/reset/altr,rst-mgr-s10.h> | ||
22 | |||
23 | DECLARE_GLOBAL_DATA_PTR; | ||
24 | |||
25 | static struct socfpga_system_manager *sysmgr_regs = | ||
26 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; | ||
27 | |||
28 | /* | ||
29 | * FPGA programming support for SoC FPGA Stratix 10 | ||
30 | */ | ||
31 | static Altera_desc altera_fpga[] = { | ||
32 | { | ||
33 | /* Family */ | ||
34 | Intel_FPGA_Stratix10, | ||
35 | /* Interface type */ | ||
36 | secure_device_manager_mailbox, | ||
37 | /* No limitation as additional data will be ignored */ | ||
38 | -1, | ||
39 | /* No device function table */ | ||
40 | NULL, | ||
41 | /* Base interface address specified in driver */ | ||
42 | NULL, | ||
43 | /* No cookie implementation */ | ||
44 | 0 | ||
45 | }, | ||
46 | }; | ||
47 | |||
48 | /* | ||
49 | * DesignWare Ethernet initialization | ||
50 | */ | ||
51 | #ifdef CONFIG_ETH_DESIGNWARE | ||
52 | |||
53 | static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) | ||
54 | { | ||
55 | u32 modereg; | ||
56 | |||
57 | if (!phymode) | ||
58 | return -EINVAL; | ||
59 | |||
60 | if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") || | ||
61 | !strcmp(phymode, "sgmii")) | ||
62 | modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; | ||
63 | else if (!strcmp(phymode, "rgmii")) | ||
64 | modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; | ||
65 | else if (!strcmp(phymode, "rmii")) | ||
66 | modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; | ||
67 | else | ||
68 | return -EINVAL; | ||
69 | |||
70 | clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, | ||
71 | SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, | ||
72 | modereg); | ||
73 | |||
74 | return 0; | ||
75 | } | ||
76 | |||
77 | static int socfpga_set_phymode(void) | ||
78 | { | ||
79 | const void *fdt = gd->fdt_blob; | ||
80 | struct fdtdec_phandle_args args; | ||
81 | const char *phy_mode; | ||
82 | u32 gmac_index; | ||
83 | int nodes[3]; /* Max. 3 GMACs */ | ||
84 | int ret, count; | ||
85 | int i, node; | ||
86 | |||
87 | count = fdtdec_find_aliases_for_id(fdt, "ethernet", | ||
88 | COMPAT_ALTERA_SOCFPGA_DWMAC, | ||
89 | nodes, ARRAY_SIZE(nodes)); | ||
90 | for (i = 0; i < count; i++) { | ||
91 | node = nodes[i]; | ||
92 | if (node <= 0) | ||
93 | continue; | ||
94 | |||
95 | ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", | ||
96 | "#reset-cells", 1, 0, | ||
97 | &args); | ||
98 | if (ret || args.args_count != 1) { | ||
99 | debug("GMAC%i: Failed to parse DT 'resets'!\n", i); | ||
100 | continue; | ||
101 | } | ||
102 | |||
103 | gmac_index = args.args[0] - EMAC0_RESET; | ||
104 | |||
105 | phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); | ||
106 | ret = socfpga_phymode_setup(gmac_index, phy_mode); | ||
107 | if (ret) { | ||
108 | debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); | ||
109 | continue; | ||
110 | } | ||
111 | } | ||
112 | |||
113 | return 0; | ||
114 | } | ||
115 | #else | ||
116 | static int socfpga_set_phymode(void) | ||
117 | { | ||
118 | return 0; | ||
119 | }; | ||
120 | #endif | ||
121 | |||
122 | /* | ||
123 | * Print CPU information | ||
124 | */ | ||
125 | #if defined(CONFIG_DISPLAY_CPUINFO) | ||
126 | int print_cpuinfo(void) | ||
127 | { | ||
128 | puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); | ||
129 | |||
130 | return 0; | ||
131 | } | ||
132 | #endif | ||
133 | |||
134 | #ifdef CONFIG_ARCH_MISC_INIT | ||
135 | int arch_misc_init(void) | ||
136 | { | ||
137 | char qspi_string[13]; | ||
138 | |||
139 | sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); | ||
140 | env_set("qspi_clock", qspi_string); | ||
141 | |||
142 | socfpga_set_phymode(); | ||
143 | return 0; | ||
144 | } | ||
145 | #endif | ||
146 | |||
147 | int arch_early_init_r(void) | ||
148 | { | ||
149 | socfpga_fpga_add(&altera_fpga[0]); | ||
150 | |||
151 | return 0; | ||
152 | } | ||
153 | |||
154 | void do_bridge_reset(int enable, unsigned int mask) | ||
155 | { | ||
156 | /* Check FPGA status before bridge enable */ | ||
157 | if (enable) { | ||
158 | int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); | ||
159 | |||
160 | if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG) | ||
161 | ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS); | ||
162 | |||
163 | if (ret) | ||
164 | return; | ||
165 | } | ||
166 | |||
167 | socfpga_bridges_reset(enable); | ||
168 | } | ||