diff options
Diffstat (limited to 'arch/arm/mach-tegra/tegra124/cpu.c')
-rw-r--r-- | arch/arm/mach-tegra/tegra124/cpu.c | 42 |
1 files changed, 40 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 204d6e9539..992c0beb04 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c | |||
@@ -104,6 +104,43 @@ static void remove_cpu_resets(void) | |||
104 | writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); | 104 | writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); |
105 | } | 105 | } |
106 | 106 | ||
107 | static void tegra124_ram_repair(void) | ||
108 | { | ||
109 | struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; | ||
110 | u32 ram_repair_timeout; /*usec*/ | ||
111 | u32 val; | ||
112 | |||
113 | /* | ||
114 | * Request the Flow Controller perform RAM repair whenever it turns on | ||
115 | * a power rail that requires RAM repair. | ||
116 | */ | ||
117 | clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN); | ||
118 | |||
119 | /* Request SW trigerred RAM repair by setting req bit */ | ||
120 | /* cluster 0 */ | ||
121 | setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); | ||
122 | /* Wait for completion (status == 0) */ | ||
123 | ram_repair_timeout = 500; | ||
124 | do { | ||
125 | udelay(1); | ||
126 | val = readl(&flow->ram_repair); | ||
127 | } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--); | ||
128 | if (!ram_repair_timeout) | ||
129 | debug("Ram Repair cluster0 failed\n"); | ||
130 | |||
131 | /* cluster 1 */ | ||
132 | setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); | ||
133 | /* Wait for completion (status == 0) */ | ||
134 | ram_repair_timeout = 500; | ||
135 | do { | ||
136 | udelay(1); | ||
137 | val = readl(&flow->ram_repair_cluster1); | ||
138 | } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--); | ||
139 | |||
140 | if (!ram_repair_timeout) | ||
141 | debug("Ram Repair cluster1 failed\n"); | ||
142 | } | ||
143 | |||
107 | /** | 144 | /** |
108 | * Tegra124 requires some special clock initialization, including setting up | 145 | * Tegra124 requires some special clock initialization, including setting up |
109 | * the DVC I2C, turning on MSELECT and selecting the G CPU cluster | 146 | * the DVC I2C, turning on MSELECT and selecting the G CPU cluster |
@@ -254,10 +291,11 @@ void start_cpu(u32 reset_vector) | |||
254 | &pmc->pmc_pwrgate_timer_mult); | 291 | &pmc->pmc_pwrgate_timer_mult); |
255 | 292 | ||
256 | enable_cpu_power_rail(); | 293 | enable_cpu_power_rail(); |
294 | powerup_cpus(); | ||
295 | tegra124_ram_repair(); | ||
257 | enable_cpu_clocks(); | 296 | enable_cpu_clocks(); |
258 | clock_enable_coresight(1); | 297 | clock_enable_coresight(1); |
259 | remove_cpu_resets(); | ||
260 | writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); | 298 | writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); |
261 | powerup_cpus(); | 299 | remove_cpu_resets(); |
262 | debug("%s exit, should continue @ reset_vector\n", __func__); | 300 | debug("%s exit, should continue @ reset_vector\n", __func__); |
263 | } | 301 | } |