diff options
Diffstat (limited to 'arch/mips/lib/cache_init.S')
-rw-r--r-- | arch/mips/lib/cache_init.S | 118 |
1 files changed, 38 insertions, 80 deletions
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index b209f23f0a..cfad1d9c8a 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S | |||
@@ -14,12 +14,6 @@ | |||
14 | #include <asm/cacheops.h> | 14 | #include <asm/cacheops.h> |
15 | #include <asm/cm.h> | 15 | #include <asm/cm.h> |
16 | 16 | ||
17 | #ifndef CONFIG_SYS_MIPS_CACHE_MODE | ||
18 | #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT | ||
19 | #endif | ||
20 | |||
21 | #define INDEX_BASE CKSEG0 | ||
22 | |||
23 | .macro f_fill64 dst, offset, val | 17 | .macro f_fill64 dst, offset, val |
24 | LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) | 18 | LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) |
25 | LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) | 19 | LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) |
@@ -84,6 +78,7 @@ | |||
84 | 10: | 78 | 10: |
85 | .set pop | 79 | .set pop |
86 | .endm | 80 | .endm |
81 | |||
87 | /* | 82 | /* |
88 | * mips_cache_reset - low level initialisation of the primary caches | 83 | * mips_cache_reset - low level initialisation of the primary caches |
89 | * | 84 | * |
@@ -255,7 +250,7 @@ l2_probe_done: | |||
255 | /* | 250 | /* |
256 | * Now clear that much memory starting from zero. | 251 | * Now clear that much memory starting from zero. |
257 | */ | 252 | */ |
258 | PTR_LI a0, CKSEG1 | 253 | PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
259 | PTR_ADDU a1, a0, v0 | 254 | PTR_ADDU a1, a0, v0 |
260 | 2: PTR_ADDIU a0, 64 | 255 | 2: PTR_ADDIU a0, 64 |
261 | f_fill64 a0, -64, zero | 256 | f_fill64 a0, -64, zero |
@@ -271,7 +266,7 @@ l2_probe_done: | |||
271 | bnez R_L2_BYPASSED, l1_init | 266 | bnez R_L2_BYPASSED, l1_init |
272 | 267 | ||
273 | l2_init: | 268 | l2_init: |
274 | PTR_LI t0, INDEX_BASE | 269 | PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
275 | PTR_ADDU t1, t0, R_L2_SIZE | 270 | PTR_ADDU t1, t0, R_L2_SIZE |
276 | 1: cache INDEX_STORE_TAG_SD, 0(t0) | 271 | 1: cache INDEX_STORE_TAG_SD, 0(t0) |
277 | PTR_ADDU t0, t0, R_L2_LINE | 272 | PTR_ADDU t0, t0, R_L2_LINE |
@@ -307,48 +302,50 @@ l1_init: | |||
307 | * Initialize the I-cache first, | 302 | * Initialize the I-cache first, |
308 | */ | 303 | */ |
309 | blez R_IC_SIZE, 1f | 304 | blez R_IC_SIZE, 1f |
310 | PTR_LI t0, INDEX_BASE | 305 | PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
311 | PTR_ADDU t1, t0, R_IC_SIZE | 306 | PTR_ADDU t1, t0, R_IC_SIZE |
312 | /* clear tag to invalidate */ | 307 | /* clear tag to invalidate */ |
313 | cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I | 308 | cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I |
314 | #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD | 309 | #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |
315 | /* fill once, so data field parity is correct */ | 310 | /* fill once, so data field parity is correct */ |
316 | PTR_LI t0, INDEX_BASE | 311 | PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
317 | cache_loop t0, t1, R_IC_LINE, FILL | 312 | cache_loop t0, t1, R_IC_LINE, FILL |
318 | /* invalidate again - prudent but not strictly neccessary */ | 313 | /* invalidate again - prudent but not strictly neccessary */ |
319 | PTR_LI t0, INDEX_BASE | 314 | PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
320 | cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I | 315 | cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I |
321 | #endif | 316 | #endif |
322 | |||
323 | /* Enable use of the I-cache by setting Config.K0 */ | ||
324 | sync | 317 | sync |
325 | mfc0 t0, CP0_CONFIG | 318 | |
326 | li t1, CONFIG_SYS_MIPS_CACHE_MODE | 319 | /* |
327 | #if __mips_isa_rev >= 2 | 320 | * Enable use of the I-cache by setting Config.K0. The code for this |
328 | ins t0, t1, 0, 3 | 321 | * must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this. |
329 | #else | 322 | * Jump back to KSEG0 after caches are enabled and insert an |
330 | ori t0, t0, CONF_CM_CMASK | 323 | * instruction hazard barrier. |
331 | xori t0, t0, CONF_CM_CMASK | 324 | */ |
325 | PTR_LA t0, change_k0_cca | ||
326 | li t1, CPHYSADDR(~0) | ||
327 | and t0, t0, t1 | ||
328 | PTR_LI t1, CKSEG1 | ||
332 | or t0, t0, t1 | 329 | or t0, t0, t1 |
333 | #endif | 330 | li a0, CONF_CM_CACHABLE_NONCOHERENT |
334 | mtc0 t0, CP0_CONFIG | 331 | jalr.hb t0 |
335 | 332 | ||
336 | /* | 333 | /* |
337 | * then initialize D-cache. | 334 | * then initialize D-cache. |
338 | */ | 335 | */ |
339 | 1: blez R_DC_SIZE, 3f | 336 | 1: blez R_DC_SIZE, 3f |
340 | PTR_LI t0, INDEX_BASE | 337 | PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
341 | PTR_ADDU t1, t0, R_DC_SIZE | 338 | PTR_ADDU t1, t0, R_DC_SIZE |
342 | /* clear all tags */ | 339 | /* clear all tags */ |
343 | cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D | 340 | cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D |
344 | #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD | 341 | #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |
345 | /* load from each line (in cached space) */ | 342 | /* load from each line (in cached space) */ |
346 | PTR_LI t0, INDEX_BASE | 343 | PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
347 | 2: LONG_L zero, 0(t0) | 344 | 2: LONG_L zero, 0(t0) |
348 | PTR_ADDU t0, R_DC_LINE | 345 | PTR_ADDU t0, R_DC_LINE |
349 | bne t0, t1, 2b | 346 | bne t0, t1, 2b |
350 | /* clear all tags */ | 347 | /* clear all tags */ |
351 | PTR_LI t0, INDEX_BASE | 348 | PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) |
352 | cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D | 349 | cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D |
353 | #endif | 350 | #endif |
354 | 3: | 351 | 3: |
@@ -391,16 +388,9 @@ l2_unbypass: | |||
391 | beqz t0, 2f | 388 | beqz t0, 2f |
392 | 389 | ||
393 | /* Change Config.K0 to a coherent CCA */ | 390 | /* Change Config.K0 to a coherent CCA */ |
394 | mfc0 t0, CP0_CONFIG | 391 | PTR_LA t0, change_k0_cca |
395 | li t1, CONF_CM_CACHABLE_COW | 392 | li a0, CONF_CM_CACHABLE_COW |
396 | #if __mips_isa_rev >= 2 | 393 | jalr t0 |
397 | ins t0, t1, 0, 3 | ||
398 | #else | ||
399 | ori t0, t0, CONF_CM_CMASK | ||
400 | xori t0, t0, CONF_CM_CMASK | ||
401 | or t0, t0, t1 | ||
402 | #endif | ||
403 | mtc0 t0, CP0_CONFIG | ||
404 | 394 | ||
405 | /* | 395 | /* |
406 | * Join the coherent domain such that the caches of this core are kept | 396 | * Join the coherent domain such that the caches of this core are kept |
@@ -421,51 +411,19 @@ l2_unbypass: | |||
421 | return: | 411 | return: |
422 | /* Ensure all cache operations complete before returning */ | 412 | /* Ensure all cache operations complete before returning */ |
423 | sync | 413 | sync |
424 | jr ra | 414 | jr R_RETURN |
425 | END(mips_cache_reset) | 415 | END(mips_cache_reset) |
426 | 416 | ||
427 | /* | 417 | LEAF(change_k0_cca) |
428 | * dcache_status - get cache status | 418 | mfc0 t0, CP0_CONFIG |
429 | * | 419 | #if __mips_isa_rev >= 2 |
430 | * RETURNS: 0 - cache disabled; 1 - cache enabled | 420 | ins t0, a0, 0, 3 |
431 | * | 421 | #else |
432 | */ | 422 | xor a0, a0, t0 |
433 | LEAF(dcache_status) | 423 | andi a0, a0, CONF_CM_CMASK |
434 | mfc0 t0, CP0_CONFIG | 424 | xor a0, a0, t0 |
435 | li t1, CONF_CM_UNCACHED | 425 | #endif |
436 | andi t0, t0, CONF_CM_CMASK | 426 | mtc0 a0, CP0_CONFIG |
437 | move v0, zero | ||
438 | beq t0, t1, 2f | ||
439 | li v0, 1 | ||
440 | 2: jr ra | ||
441 | END(dcache_status) | ||
442 | |||
443 | /* | ||
444 | * dcache_disable - disable cache | ||
445 | * | ||
446 | * RETURNS: N/A | ||
447 | * | ||
448 | */ | ||
449 | LEAF(dcache_disable) | ||
450 | mfc0 t0, CP0_CONFIG | ||
451 | li t1, -8 | ||
452 | and t0, t0, t1 | ||
453 | ori t0, t0, CONF_CM_UNCACHED | ||
454 | mtc0 t0, CP0_CONFIG | ||
455 | jr ra | ||
456 | END(dcache_disable) | ||
457 | 427 | ||
458 | /* | 428 | jr.hb ra |
459 | * dcache_enable - enable cache | 429 | END(change_k0_cca) |
460 | * | ||
461 | * RETURNS: N/A | ||
462 | * | ||
463 | */ | ||
464 | LEAF(dcache_enable) | ||
465 | mfc0 t0, CP0_CONFIG | ||
466 | ori t0, CONF_CM_CMASK | ||
467 | xori t0, CONF_CM_CMASK | ||
468 | ori t0, CONFIG_SYS_MIPS_CACHE_MODE | ||
469 | mtc0 t0, CP0_CONFIG | ||
470 | jr ra | ||
471 | END(dcache_enable) | ||