diff options
Diffstat (limited to 'arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h')
-rw-r--r-- | arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h | 245 |
1 files changed, 245 insertions, 0 deletions
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h new file mode 100644 index 0000000000..9233f037bb --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h | |||
@@ -0,0 +1,245 @@ | |||
1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ | ||
2 | /* | ||
3 | * Copyright (c) 2018 Microsemi Corporation | ||
4 | */ | ||
5 | |||
6 | #ifndef _MSCC_OCELOT_ICPU_CFG_H_ | ||
7 | #define _MSCC_OCELOT_ICPU_CFG_H_ | ||
8 | |||
9 | #define ICPU_GPR(x) (0x4 * (x)) | ||
10 | #define ICPU_GPR_RSZ 0x4 | ||
11 | |||
12 | #define ICPU_RESET 0x20 | ||
13 | |||
14 | #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3) | ||
15 | #define ICPU_RESET_CORE_RST_PROTECT BIT(2) | ||
16 | #define ICPU_RESET_CORE_RST_FORCE BIT(1) | ||
17 | #define ICPU_RESET_MEM_RST_FORCE BIT(0) | ||
18 | |||
19 | #define ICPU_GENERAL_CTRL 0x24 | ||
20 | |||
21 | #define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6) | ||
22 | #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5) | ||
23 | #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4) | ||
24 | #define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3) | ||
25 | #define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2) | ||
26 | #define ICPU_GENERAL_CTRL_IF_MASTER_PI_ENA BIT(1) | ||
27 | |||
28 | #define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0) | ||
29 | |||
30 | #define ICPU_PI_MST_CFG 0x2c | ||
31 | |||
32 | #define ICPU_PI_MST_CFG_ATE_MODE_DIS BIT(7) | ||
33 | #define ICPU_PI_MST_CFG_CLK_POL BIT(6) | ||
34 | #define ICPU_PI_MST_CFG_TRISTATE_CTRL BIT(5) | ||
35 | #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) | ||
36 | #define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0) | ||
37 | |||
38 | #define ICPU_SPI_MST_CFG 0x50 | ||
39 | |||
40 | #define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10) | ||
41 | #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) | ||
42 | #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5) | ||
43 | #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) | ||
44 | #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) | ||
45 | #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0) | ||
46 | |||
47 | #define ICPU_SW_MODE 0x64 | ||
48 | |||
49 | #define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13) | ||
50 | #define ICPU_SW_MODE_SW_SPI_SCK BIT(12) | ||
51 | #define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11) | ||
52 | #define ICPU_SW_MODE_SW_SPI_SDO BIT(10) | ||
53 | #define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9) | ||
54 | #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) | ||
55 | #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) | ||
56 | #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) | ||
57 | #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) | ||
58 | #define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1) | ||
59 | #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) | ||
60 | #define ICPU_SW_MODE_SW_SPI_SDI BIT(0) | ||
61 | |||
62 | #define ICPU_INTR_ENA 0x88 | ||
63 | |||
64 | #define ICPU_INTR_IRQ0_ENA 0x98 | ||
65 | #define ICPU_INTR_IRQ0_ENA_IRQ0_ENA BIT(0) | ||
66 | |||
67 | #define ICPU_MEMCTRL_CTRL 0x234 | ||
68 | |||
69 | #define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3) | ||
70 | #define ICPU_MEMCTRL_CTRL_MDSET BIT(2) | ||
71 | #define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1) | ||
72 | #define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0) | ||
73 | |||
74 | #define ICPU_MEMCTRL_CFG 0x238 | ||
75 | |||
76 | #define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16) | ||
77 | #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) | ||
78 | #define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14) | ||
79 | #define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13) | ||
80 | #define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12) | ||
81 | #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) | ||
82 | #define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10) | ||
83 | #define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9) | ||
84 | #define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8) | ||
85 | #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) | ||
86 | #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4) | ||
87 | #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4) | ||
88 | #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) | ||
89 | #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0) | ||
90 | |||
91 | #define ICPU_MEMCTRL_STAT 0x23C | ||
92 | |||
93 | #define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5) | ||
94 | #define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4) | ||
95 | #define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3) | ||
96 | #define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2) | ||
97 | #define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1) | ||
98 | #define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0) | ||
99 | |||
100 | #define ICPU_MEMCTRL_REF_PERIOD 0x240 | ||
101 | |||
102 | #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16)) | ||
103 | #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16) | ||
104 | #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16) | ||
105 | #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) | ||
106 | #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0) | ||
107 | |||
108 | #define ICPU_MEMCTRL_TIMING0 0x248 | ||
109 | |||
110 | #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) | ||
111 | #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28) | ||
112 | #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) | ||
113 | #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24)) | ||
114 | #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24) | ||
115 | #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) | ||
116 | #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20)) | ||
117 | #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20) | ||
118 | #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20) | ||
119 | #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16)) | ||
120 | #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16) | ||
121 | #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) | ||
122 | #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12)) | ||
123 | #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12) | ||
124 | #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) | ||
125 | #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8)) | ||
126 | #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8) | ||
127 | #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) | ||
128 | #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4)) | ||
129 | #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4) | ||
130 | #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) | ||
131 | #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) | ||
132 | #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0) | ||
133 | |||
134 | #define ICPU_MEMCTRL_TIMING1 0x24c | ||
135 | |||
136 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24)) | ||
137 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24) | ||
138 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24) | ||
139 | #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16)) | ||
140 | #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16) | ||
141 | #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) | ||
142 | #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12)) | ||
143 | #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12) | ||
144 | #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) | ||
145 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) | ||
146 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8) | ||
147 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) | ||
148 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4)) | ||
149 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4) | ||
150 | #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) | ||
151 | #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) | ||
152 | #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0) | ||
153 | |||
154 | #define ICPU_MEMCTRL_TIMING2 0x250 | ||
155 | |||
156 | #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28)) | ||
157 | #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28) | ||
158 | #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) | ||
159 | #define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24)) | ||
160 | #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24) | ||
161 | #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) | ||
162 | #define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16)) | ||
163 | #define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16) | ||
164 | #define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) | ||
165 | #define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(x) ((x) & GENMASK(15, 0)) | ||
166 | #define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY_M GENMASK(15, 0) | ||
167 | |||
168 | #define ICPU_MEMCTRL_TIMING3 0x254 | ||
169 | |||
170 | #define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16)) | ||
171 | #define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16) | ||
172 | #define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) | ||
173 | #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12)) | ||
174 | #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12) | ||
175 | #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) | ||
176 | #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8)) | ||
177 | #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8) | ||
178 | #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) | ||
179 | #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4)) | ||
180 | #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4) | ||
181 | #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) | ||
182 | #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) | ||
183 | #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0) | ||
184 | |||
185 | #define ICPU_MEMCTRL_MR0_VAL 0x258 | ||
186 | |||
187 | #define ICPU_MEMCTRL_MR1_VAL 0x25c | ||
188 | |||
189 | #define ICPU_MEMCTRL_MR2_VAL 0x260 | ||
190 | |||
191 | #define ICPU_MEMCTRL_MR3_VAL 0x264 | ||
192 | |||
193 | #define ICPU_MEMCTRL_TERMRES_CTRL 0x268 | ||
194 | |||
195 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11) | ||
196 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7)) | ||
197 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7) | ||
198 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7) | ||
199 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6) | ||
200 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2)) | ||
201 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2) | ||
202 | #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2) | ||
203 | #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1) | ||
204 | #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0) | ||
205 | |||
206 | #define ICPU_MEMCTRL_DQS_DLY(x) (0x270) | ||
207 | |||
208 | #define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11) | ||
209 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8)) | ||
210 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8) | ||
211 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8) | ||
212 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) | ||
213 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5) | ||
214 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5) | ||
215 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0)) | ||
216 | #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0) | ||
217 | |||
218 | #define ICPU_MEMPHY_CFG 0x278 | ||
219 | |||
220 | #define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10) | ||
221 | #define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9) | ||
222 | #define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8) | ||
223 | #define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7) | ||
224 | #define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6) | ||
225 | #define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5) | ||
226 | #define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4) | ||
227 | #define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3) | ||
228 | #define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2) | ||
229 | #define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1) | ||
230 | #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) | ||
231 | #define ICPU_MEMPHY_DQ_DLY_TRM 0x180 | ||
232 | #define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4 | ||
233 | |||
234 | #define ICPU_MEMPHY_ZCAL 0x294 | ||
235 | |||
236 | #define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9) | ||
237 | #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5)) | ||
238 | #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5) | ||
239 | #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5) | ||
240 | #define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1)) | ||
241 | #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1) | ||
242 | #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1) | ||
243 | #define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0) | ||
244 | |||
245 | #endif | ||