diff options
Diffstat (limited to 'arch/mips/mach-mscc/reset.c')
-rw-r--r-- | arch/mips/mach-mscc/reset.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c new file mode 100644 index 0000000000..390bbd086a --- /dev/null +++ b/arch/mips/mach-mscc/reset.c | |||
@@ -0,0 +1,30 @@ | |||
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
2 | /* | ||
3 | * Copyright (c) 2018 Microsemi Corporation | ||
4 | */ | ||
5 | |||
6 | #include <common.h> | ||
7 | |||
8 | #include <asm/sections.h> | ||
9 | #include <asm/io.h> | ||
10 | |||
11 | #include <asm/reboot.h> | ||
12 | |||
13 | void _machine_restart(void) | ||
14 | { | ||
15 | register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST; | ||
16 | (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); | ||
17 | |||
18 | /* Make sure VCore is NOT protected from reset */ | ||
19 | clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT); | ||
20 | |||
21 | /* Change to SPI bitbang for SPI reset workaround... */ | ||
22 | writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) | | ||
23 | ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE); | ||
24 | |||
25 | /* Do the global reset */ | ||
26 | writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); | ||
27 | |||
28 | while (1) | ||
29 | ; /* NOP */ | ||
30 | } | ||