1 files changed, 10 insertions, 80 deletions

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index fcac9f63a8..af8facad53 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -12,6 +12,12 @@
 #include <usb/ehci-ci.h>
 #endif
 
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_QE
@@ -47,62 +53,6 @@ static void config_qe_ioports(void)
  */
 void cpu_init_f (volatile immap_t * im)
 {
-        __be32 acr_mask =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
-                ACR_PIPE_DEP |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
-                ACR_RPTCNT |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
-                ACR_APARK |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
-                ACR_PARKM |
-#endif
-                0;
-        __be32 acr_val =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
-                (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
-                (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
-                (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
-                (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
-#endif
-                0;
-        __be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
-                SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-                SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-                SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-                SPCR_TSEC2EP |
-#endif
-                0;
-        __be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
-                (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-                (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-                (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-                (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
-                0;
         __be32 sccr_mask =
 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
                 SCCR_ENCCM |
@@ -179,28 +129,6 @@ void cpu_init_f (volatile immap_t * im)
                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 #endif
                 0;
-        __be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-                LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
-                LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-                LCRR_CLKDIV |
-#endif
-                0;
-        __be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-                CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
-                CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-                CONFIG_SYS_LCRR_CLKDIV |
-#endif
-                0;
 
         /* Pointer is writable since we allocated a register for it */
         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -240,7 +168,7 @@ void cpu_init_f (volatile immap_t * im)
 
         /* System General Purpose Register */
 #ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
                      &im->sysconf.sicrh);
@@ -312,7 +240,7 @@ void cpu_init_f (volatile immap_t * im)
         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 #endif
-#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
         uint32_t temp;
         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 
@@ -464,6 +392,7 @@ static int print_83xx_arb_event(int force)
 }
 #endif /* CONFIG_DISPLAY_AER_xxxx */
 
+#ifndef CONFIG_CPU_MPC83XX
 /*
  * Figure out the cause of the reset
  */
@@ -505,3 +434,4 @@ int prt_83xx_rsr(void)
 
         return 0;
 }
+#endif