diff options
Diffstat (limited to 'board/CZ.NIC/turris_omnia/turris_omnia.c')
-rw-r--r-- | board/CZ.NIC/turris_omnia/turris_omnia.c | 387 |
1 files changed, 187 insertions, 200 deletions
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 160d30cd79..ad6e29021e 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c | |||
@@ -18,40 +18,38 @@ | |||
18 | #include <dm/uclass.h> | 18 | #include <dm/uclass.h> |
19 | #include <fdt_support.h> | 19 | #include <fdt_support.h> |
20 | #include <time.h> | 20 | #include <time.h> |
21 | |||
22 | #ifdef CONFIG_ATSHA204A | ||
23 | # include <atsha204a-i2c.h> | 21 | # include <atsha204a-i2c.h> |
24 | #endif | ||
25 | |||
26 | #ifdef CONFIG_WDT_ORION | ||
27 | # include <wdt.h> | ||
28 | #endif | ||
29 | 22 | ||
30 | #include "../drivers/ddr/marvell/a38x/ddr3_init.h" | 23 | #include "../drivers/ddr/marvell/a38x/ddr3_init.h" |
31 | #include <../serdes/a38x/high_speed_env_spec.h> | 24 | #include <../serdes/a38x/high_speed_env_spec.h> |
32 | 25 | ||
33 | DECLARE_GLOBAL_DATA_PTR; | 26 | DECLARE_GLOBAL_DATA_PTR; |
34 | 27 | ||
35 | #define OMNIA_I2C_EEPROM_DM_NAME "i2c@0" | 28 | #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0" |
36 | #define OMNIA_I2C_EEPROM 0x54 | 29 | |
37 | #define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 | 30 | #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a |
38 | #define OMNIA_I2C_EEPROM_ADDRLEN 2 | 31 | #define OMNIA_I2C_MCU_CHIP_LEN 1 |
32 | |||
33 | #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54 | ||
34 | #define OMNIA_I2C_EEPROM_CHIP_LEN 2 | ||
39 | #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 | 35 | #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 |
40 | 36 | ||
41 | #define OMNIA_I2C_MCU_DM_NAME "i2c@0" | 37 | enum mcu_commands { |
42 | #define OMNIA_I2C_MCU_ADDR_STATUS 0x1 | 38 | CMD_GET_STATUS_WORD = 0x01, |
43 | #define OMNIA_I2C_MCU_SATA 0x20 | 39 | CMD_GET_RESET = 0x09, |
44 | #define OMNIA_I2C_MCU_CARDDET 0x10 | 40 | CMD_WATCHDOG_STATE = 0x0b, |
45 | #define OMNIA_I2C_MCU 0x2a | 41 | }; |
46 | #define OMNIA_I2C_MCU_WDT_ADDR 0x0b | 42 | |
43 | enum status_word_bits { | ||
44 | CARD_DET_STSBIT = 0x0010, | ||
45 | MSATA_IND_STSBIT = 0x0020, | ||
46 | }; | ||
47 | 47 | ||
48 | #define OMNIA_ATSHA204_OTP_VERSION 0 | 48 | #define OMNIA_ATSHA204_OTP_VERSION 0 |
49 | #define OMNIA_ATSHA204_OTP_SERIAL 1 | 49 | #define OMNIA_ATSHA204_OTP_SERIAL 1 |
50 | #define OMNIA_ATSHA204_OTP_MAC0 3 | 50 | #define OMNIA_ATSHA204_OTP_MAC0 3 |
51 | #define OMNIA_ATSHA204_OTP_MAC1 4 | 51 | #define OMNIA_ATSHA204_OTP_MAC1 4 |
52 | 52 | ||
53 | #define MVTWSI_ARMADA_DEBUG_REG 0x8c | ||
54 | |||
55 | /* | 53 | /* |
56 | * Those values and defines are taken from the Marvell U-Boot version | 54 | * Those values and defines are taken from the Marvell U-Boot version |
57 | * "u-boot-2013.01-2014_T3.0" | 55 | * "u-boot-2013.01-2014_T3.0" |
@@ -87,48 +85,97 @@ static struct serdes_map board_serdes_map_sata[] = { | |||
87 | {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} | 85 | {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} |
88 | }; | 86 | }; |
89 | 87 | ||
90 | static bool omnia_detect_sata(void) | 88 | static struct udevice *omnia_get_i2c_chip(const char *name, uint addr, |
89 | uint offset_len) | ||
91 | { | 90 | { |
92 | struct udevice *bus, *dev; | 91 | struct udevice *bus, *dev; |
93 | int ret, retry = 3; | 92 | int ret; |
94 | u16 mode; | ||
95 | |||
96 | puts("SERDES0 card detect: "); | ||
97 | 93 | ||
98 | if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { | 94 | ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus); |
99 | puts("Cannot find MCU bus!\n"); | 95 | if (ret) { |
100 | return false; | 96 | printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n", |
97 | OMNIA_I2C_BUS_NAME, ret); | ||
98 | return NULL; | ||
101 | } | 99 | } |
102 | 100 | ||
103 | ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); | 101 | ret = i2c_get_chip(bus, addr, offset_len, &dev); |
104 | if (ret) { | 102 | if (ret) { |
105 | puts("Cannot get MCU chip!\n"); | 103 | printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n", |
106 | return false; | 104 | name, ret); |
105 | return NULL; | ||
107 | } | 106 | } |
108 | 107 | ||
109 | for (; retry > 0; --retry) { | 108 | return dev; |
110 | ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); | 109 | } |
111 | if (!ret) | 110 | |
112 | break; | 111 | static int omnia_mcu_read(u8 cmd, void *buf, int len) |
113 | } | 112 | { |
113 | struct udevice *chip; | ||
114 | |||
115 | chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, | ||
116 | OMNIA_I2C_MCU_CHIP_LEN); | ||
117 | if (!chip) | ||
118 | return -ENODEV; | ||
119 | |||
120 | return dm_i2c_read(chip, cmd, buf, len); | ||
121 | } | ||
122 | |||
123 | #ifndef CONFIG_SPL_BUILD | ||
124 | static int omnia_mcu_write(u8 cmd, const void *buf, int len) | ||
125 | { | ||
126 | struct udevice *chip; | ||
114 | 127 | ||
115 | if (!retry) { | 128 | chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, |
116 | puts("I2C read failed! Default PEX\n"); | 129 | OMNIA_I2C_MCU_CHIP_LEN); |
130 | if (!chip) | ||
131 | return -ENODEV; | ||
132 | |||
133 | return dm_i2c_write(chip, cmd, buf, len); | ||
134 | } | ||
135 | |||
136 | static bool disable_mcu_watchdog(void) | ||
137 | { | ||
138 | int ret; | ||
139 | |||
140 | puts("Disabling MCU watchdog... "); | ||
141 | |||
142 | ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1); | ||
143 | if (ret) { | ||
144 | printf("omnia_mcu_write failed: %i\n", ret); | ||
117 | return false; | 145 | return false; |
118 | } | 146 | } |
119 | 147 | ||
120 | if (!(mode & OMNIA_I2C_MCU_CARDDET)) { | 148 | puts("disabled\n"); |
121 | puts("NONE\n"); | 149 | |
150 | return true; | ||
151 | } | ||
152 | #endif | ||
153 | |||
154 | static bool omnia_detect_sata(void) | ||
155 | { | ||
156 | int ret; | ||
157 | u16 stsword; | ||
158 | |||
159 | puts("MiniPCIe/mSATA card detection... "); | ||
160 | |||
161 | ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); | ||
162 | if (ret) { | ||
163 | printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n", | ||
164 | ret); | ||
122 | return false; | 165 | return false; |
123 | } | 166 | } |
124 | 167 | ||
125 | if (mode & OMNIA_I2C_MCU_SATA) { | 168 | if (!(stsword & CARD_DET_STSBIT)) { |
126 | puts("SATA\n"); | 169 | puts("none\n"); |
127 | return true; | ||
128 | } else { | ||
129 | puts("PEX\n"); | ||
130 | return false; | 170 | return false; |
131 | } | 171 | } |
172 | |||
173 | if (stsword & MSATA_IND_STSBIT) | ||
174 | puts("mSATA\n"); | ||
175 | else | ||
176 | puts("MiniPCIe\n"); | ||
177 | |||
178 | return stsword & MSATA_IND_STSBIT ? true : false; | ||
132 | } | 179 | } |
133 | 180 | ||
134 | int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) | 181 | int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) |
@@ -153,48 +200,63 @@ struct omnia_eeprom { | |||
153 | 200 | ||
154 | static bool omnia_read_eeprom(struct omnia_eeprom *oep) | 201 | static bool omnia_read_eeprom(struct omnia_eeprom *oep) |
155 | { | 202 | { |
156 | struct udevice *bus, *dev; | 203 | struct udevice *chip; |
157 | int ret, crc, retry = 3; | 204 | u32 crc; |
205 | int ret; | ||
158 | 206 | ||
159 | if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { | 207 | chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR, |
160 | puts("Cannot find EEPROM bus\n"); | 208 | OMNIA_I2C_EEPROM_CHIP_LEN); |
209 | |||
210 | if (!chip) | ||
161 | return false; | 211 | return false; |
162 | } | ||
163 | 212 | ||
164 | ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); | 213 | ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep)); |
165 | if (ret) { | 214 | if (ret) { |
166 | puts("Cannot get EEPROM chip\n"); | 215 | printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret); |
167 | return false; | 216 | return false; |
168 | } | 217 | } |
169 | 218 | ||
170 | for (; retry > 0; --retry) { | 219 | if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { |
171 | ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); | 220 | printf("bad EEPROM magic number (%08x, should be %08x)\n", |
172 | if (ret) | 221 | oep->magic, OMNIA_I2C_EEPROM_MAGIC); |
173 | continue; | 222 | return false; |
174 | |||
175 | if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { | ||
176 | puts("I2C EEPROM missing magic number!\n"); | ||
177 | continue; | ||
178 | } | ||
179 | |||
180 | crc = crc32(0, (unsigned char *) oep, | ||
181 | sizeof(struct omnia_eeprom) - 4); | ||
182 | if (crc == oep->crc) { | ||
183 | break; | ||
184 | } else { | ||
185 | printf("CRC of EEPROM memory config failed! " | ||
186 | "calc=0x%04x saved=0x%04x\n", crc, oep->crc); | ||
187 | } | ||
188 | } | 223 | } |
189 | 224 | ||
190 | if (!retry) { | 225 | crc = crc32(0, (void *)oep, sizeof(*oep) - 4); |
191 | puts("I2C EEPROM read failed!\n"); | 226 | if (crc != oep->crc) { |
227 | printf("bad EEPROM CRC (stored %08x, computed %08x)\n", | ||
228 | oep->crc, crc); | ||
192 | return false; | 229 | return false; |
193 | } | 230 | } |
194 | 231 | ||
195 | return true; | 232 | return true; |
196 | } | 233 | } |
197 | 234 | ||
235 | static int omnia_get_ram_size_gb(void) | ||
236 | { | ||
237 | static int ram_size; | ||
238 | struct omnia_eeprom oep; | ||
239 | |||
240 | if (!ram_size) { | ||
241 | /* Get the board config from EEPROM */ | ||
242 | if (omnia_read_eeprom(&oep)) { | ||
243 | debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize); | ||
244 | |||
245 | if (oep.ramsize == 0x2) | ||
246 | ram_size = 2; | ||
247 | else | ||
248 | ram_size = 1; | ||
249 | } else { | ||
250 | /* Hardcoded fallback */ | ||
251 | puts("Memory config from EEPROM read failed!\n"); | ||
252 | puts("Falling back to default 1 GiB!\n"); | ||
253 | ram_size = 1; | ||
254 | } | ||
255 | } | ||
256 | |||
257 | return ram_size; | ||
258 | } | ||
259 | |||
198 | /* | 260 | /* |
199 | * Define the DDR layout / topology here in the board file. This will | 261 | * Define the DDR layout / topology here in the board file. This will |
200 | * be used by the DDR3 init code in the SPL U-Boot version to configure | 262 | * be used by the DDR3 init code in the SPL U-Boot version to configure |
@@ -212,7 +274,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = { | |||
212 | SPEED_BIN_DDR_1600K, /* speed_bin */ | 274 | SPEED_BIN_DDR_1600K, /* speed_bin */ |
213 | MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ | 275 | MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ |
214 | MV_DDR_DIE_CAP_4GBIT, /* mem_size */ | 276 | MV_DDR_DIE_CAP_4GBIT, /* mem_size */ |
215 | DDR_FREQ_800, /* frequency */ | 277 | MV_DDR_FREQ_800, /* frequency */ |
216 | 0, 0, /* cas_wl cas_l */ | 278 | 0, 0, /* cas_wl cas_l */ |
217 | MV_DDR_TEMP_NORMAL, /* temperature */ | 279 | MV_DDR_TEMP_NORMAL, /* temperature */ |
218 | MV_DDR_TIM_2T} }, /* timing */ | 280 | MV_DDR_TIM_2T} }, /* timing */ |
@@ -234,7 +296,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = { | |||
234 | SPEED_BIN_DDR_1600K, /* speed_bin */ | 296 | SPEED_BIN_DDR_1600K, /* speed_bin */ |
235 | MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ | 297 | MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ |
236 | MV_DDR_DIE_CAP_8GBIT, /* mem_size */ | 298 | MV_DDR_DIE_CAP_8GBIT, /* mem_size */ |
237 | DDR_FREQ_800, /* frequency */ | 299 | MV_DDR_FREQ_800, /* frequency */ |
238 | 0, 0, /* cas_wl cas_l */ | 300 | 0, 0, /* cas_wl cas_l */ |
239 | MV_DDR_TEMP_NORMAL, /* temperature */ | 301 | MV_DDR_TEMP_NORMAL, /* temperature */ |
240 | MV_DDR_TIM_2T} }, /* timing */ | 302 | MV_DDR_TIM_2T} }, /* timing */ |
@@ -246,37 +308,10 @@ static struct mv_ddr_topology_map board_topology_map_2g = { | |||
246 | 308 | ||
247 | struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) | 309 | struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) |
248 | { | 310 | { |
249 | static int mem = 0; | 311 | if (omnia_get_ram_size_gb() == 2) |
250 | struct omnia_eeprom oep; | ||
251 | |||
252 | /* Get the board config from EEPROM */ | ||
253 | if (mem == 0) { | ||
254 | if(!omnia_read_eeprom(&oep)) | ||
255 | goto out; | ||
256 | |||
257 | printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); | ||
258 | |||
259 | if (oep.ramsize == 0x2) | ||
260 | mem = 2; | ||
261 | else | ||
262 | mem = 1; | ||
263 | } | ||
264 | |||
265 | out: | ||
266 | /* Hardcoded fallback */ | ||
267 | if (mem == 0) { | ||
268 | puts("WARNING: Memory config from EEPROM read failed.\n"); | ||
269 | puts("Falling back to default 1GiB map.\n"); | ||
270 | mem = 1; | ||
271 | } | ||
272 | |||
273 | /* Return the board topology as defined in the board code */ | ||
274 | if (mem == 1) | ||
275 | return &board_topology_map_1g; | ||
276 | if (mem == 2) | ||
277 | return &board_topology_map_2g; | 312 | return &board_topology_map_2g; |
278 | 313 | else | |
279 | return &board_topology_map_1g; | 314 | return &board_topology_map_1g; |
280 | } | 315 | } |
281 | 316 | ||
282 | #ifndef CONFIG_SPL_BUILD | 317 | #ifndef CONFIG_SPL_BUILD |
@@ -293,12 +328,47 @@ static int set_regdomain(void) | |||
293 | printf("Regdomain set to %s\n", rd); | 328 | printf("Regdomain set to %s\n", rd); |
294 | return env_set("regdomain", rd); | 329 | return env_set("regdomain", rd); |
295 | } | 330 | } |
331 | |||
332 | /* | ||
333 | * default factory reset bootcommand on Omnia first sets all the front LEDs | ||
334 | * to green and then tries to load the rescue image from SPI flash memory and | ||
335 | * boot it | ||
336 | */ | ||
337 | #define OMNIA_FACTORY_RESET_BOOTCMD \ | ||
338 | "i2c dev 2; " \ | ||
339 | "i2c mw 0x2a.1 0x3 0x1c 1; " \ | ||
340 | "i2c mw 0x2a.1 0x4 0x1c 1; " \ | ||
341 | "mw.l 0x01000000 0x00ff000c; " \ | ||
342 | "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \ | ||
343 | "setenv bootargs \"$bootargs omniarescue=$omnia_reset\"; " \ | ||
344 | "sf probe; " \ | ||
345 | "sf read 0x1000000 0x100000 0x700000; " \ | ||
346 | "bootm 0x1000000; " \ | ||
347 | "bootz 0x1000000" | ||
348 | |||
349 | static void handle_reset_button(void) | ||
350 | { | ||
351 | int ret; | ||
352 | u8 reset_status; | ||
353 | |||
354 | ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1); | ||
355 | if (ret) { | ||
356 | printf("omnia_mcu_read failed: %i, reset status unknown!\n", | ||
357 | ret); | ||
358 | return; | ||
359 | } | ||
360 | |||
361 | env_set_ulong("omnia_reset", reset_status); | ||
362 | |||
363 | if (reset_status) { | ||
364 | printf("RESET button was pressed, overwriting bootcmd!\n"); | ||
365 | env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD); | ||
366 | } | ||
367 | } | ||
296 | #endif | 368 | #endif |
297 | 369 | ||
298 | int board_early_init_f(void) | 370 | int board_early_init_f(void) |
299 | { | 371 | { |
300 | u32 i2c_debug_reg; | ||
301 | |||
302 | /* Configure MPP */ | 372 | /* Configure MPP */ |
303 | writel(0x11111111, MVEBU_MPP_BASE + 0x00); | 373 | writel(0x11111111, MVEBU_MPP_BASE + 0x00); |
304 | writel(0x11111111, MVEBU_MPP_BASE + 0x04); | 374 | writel(0x11111111, MVEBU_MPP_BASE + 0x04); |
@@ -321,114 +391,36 @@ int board_early_init_f(void) | |||
321 | writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); | 391 | writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); |
322 | writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); | 392 | writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); |
323 | 393 | ||
324 | /* | ||
325 | * Disable I2C debug mode blocking 0x64 I2C address. | ||
326 | * Note: that would be redundant once Turris Omnia migrates to DM_I2C, | ||
327 | * because the mvtwsi driver includes equivalent code. | ||
328 | */ | ||
329 | i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); | ||
330 | i2c_debug_reg &= ~(1<<18); | ||
331 | writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); | ||
332 | |||
333 | return 0; | 394 | return 0; |
334 | } | 395 | } |
335 | 396 | ||
336 | #ifndef CONFIG_SPL_BUILD | ||
337 | static bool disable_mcu_watchdog(void) | ||
338 | { | ||
339 | struct udevice *bus, *dev; | ||
340 | int ret, retry = 3; | ||
341 | uchar buf[1] = {0x0}; | ||
342 | |||
343 | if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { | ||
344 | puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); | ||
345 | return false; | ||
346 | } | ||
347 | |||
348 | ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); | ||
349 | if (ret) { | ||
350 | puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); | ||
351 | return false; | ||
352 | } | ||
353 | |||
354 | for (; retry > 0; --retry) | ||
355 | if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) | ||
356 | break; | ||
357 | |||
358 | if (retry <= 0) { | ||
359 | puts("I2C MCU watchdog failed to disable!\n"); | ||
360 | return false; | ||
361 | } | ||
362 | |||
363 | return true; | ||
364 | } | ||
365 | #endif | ||
366 | |||
367 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) | ||
368 | static struct udevice *watchdog_dev = NULL; | ||
369 | #endif | ||
370 | |||
371 | int board_init(void) | 397 | int board_init(void) |
372 | { | 398 | { |
373 | /* adress of boot parameters */ | 399 | /* address of boot parameters */ |
374 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; | 400 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
375 | 401 | ||
376 | #ifndef CONFIG_SPL_BUILD | 402 | #ifndef CONFIG_SPL_BUILD |
377 | # ifdef CONFIG_WDT_ORION | 403 | disable_mcu_watchdog(); |
378 | if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { | ||
379 | puts("Cannot find Armada 385 watchdog!\n"); | ||
380 | } else { | ||
381 | puts("Enabling Armada 385 watchdog.\n"); | ||
382 | wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); | ||
383 | } | ||
384 | # endif | ||
385 | |||
386 | if (disable_mcu_watchdog()) | ||
387 | puts("Disabled MCU startup watchdog.\n"); | ||
388 | |||
389 | set_regdomain(); | ||
390 | #endif | 404 | #endif |
391 | 405 | ||
392 | return 0; | 406 | return 0; |
393 | } | 407 | } |
394 | 408 | ||
395 | #ifdef CONFIG_WATCHDOG | ||
396 | /* Called by macro WATCHDOG_RESET */ | ||
397 | void watchdog_reset(void) | ||
398 | { | ||
399 | # if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) | ||
400 | static ulong next_reset = 0; | ||
401 | ulong now; | ||
402 | |||
403 | if (!watchdog_dev) | ||
404 | return; | ||
405 | |||
406 | now = timer_get_us(); | ||
407 | |||
408 | /* Do not reset the watchdog too often */ | ||
409 | if (now > next_reset) { | ||
410 | wdt_reset(watchdog_dev); | ||
411 | next_reset = now + 1000; | ||
412 | } | ||
413 | # endif | ||
414 | } | ||
415 | #endif | ||
416 | |||
417 | int board_late_init(void) | 409 | int board_late_init(void) |
418 | { | 410 | { |
419 | #ifndef CONFIG_SPL_BUILD | 411 | #ifndef CONFIG_SPL_BUILD |
420 | set_regdomain(); | 412 | set_regdomain(); |
413 | handle_reset_button(); | ||
421 | #endif | 414 | #endif |
422 | 415 | ||
423 | return 0; | 416 | return 0; |
424 | } | 417 | } |
425 | 418 | ||
426 | #ifdef CONFIG_ATSHA204A | ||
427 | static struct udevice *get_atsha204a_dev(void) | 419 | static struct udevice *get_atsha204a_dev(void) |
428 | { | 420 | { |
429 | static struct udevice *dev = NULL; | 421 | static struct udevice *dev; |
430 | 422 | ||
431 | if (dev != NULL) | 423 | if (dev) |
432 | return dev; | 424 | return dev; |
433 | 425 | ||
434 | if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { | 426 | if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { |
@@ -438,14 +430,12 @@ static struct udevice *get_atsha204a_dev(void) | |||
438 | 430 | ||
439 | return dev; | 431 | return dev; |
440 | } | 432 | } |
441 | #endif | ||
442 | 433 | ||
443 | int checkboard(void) | 434 | int checkboard(void) |
444 | { | 435 | { |
445 | u32 version_num, serial_num; | 436 | u32 version_num, serial_num; |
446 | int err = 1; | 437 | int err = 1; |
447 | 438 | ||
448 | #ifdef CONFIG_ATSHA204A | ||
449 | struct udevice *dev = get_atsha204a_dev(); | 439 | struct udevice *dev = get_atsha204a_dev(); |
450 | 440 | ||
451 | if (dev) { | 441 | if (dev) { |
@@ -455,13 +445,13 @@ int checkboard(void) | |||
455 | 445 | ||
456 | err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, | 446 | err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, |
457 | OMNIA_ATSHA204_OTP_VERSION, | 447 | OMNIA_ATSHA204_OTP_VERSION, |
458 | (u8 *) &version_num); | 448 | (u8 *)&version_num); |
459 | if (err) | 449 | if (err) |
460 | goto out; | 450 | goto out; |
461 | 451 | ||
462 | err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, | 452 | err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, |
463 | OMNIA_ATSHA204_OTP_SERIAL, | 453 | OMNIA_ATSHA204_OTP_SERIAL, |
464 | (u8 *) &serial_num); | 454 | (u8 *)&serial_num); |
465 | if (err) | 455 | if (err) |
466 | goto out; | 456 | goto out; |
467 | 457 | ||
@@ -469,13 +459,13 @@ int checkboard(void) | |||
469 | } | 459 | } |
470 | 460 | ||
471 | out: | 461 | out: |
472 | #endif | 462 | printf("Turris Omnia:\n"); |
473 | 463 | printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); | |
474 | if (err) | 464 | if (err) |
475 | printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); | 465 | printf(" Serial Number: unknown\n"); |
476 | else | 466 | else |
477 | printf("Board: Turris Omnia SNL %08X%08X\n", | 467 | printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num), |
478 | be32_to_cpu(version_num), be32_to_cpu(serial_num)); | 468 | be32_to_cpu(serial_num)); |
479 | 469 | ||
480 | return 0; | 470 | return 0; |
481 | } | 471 | } |
@@ -493,7 +483,6 @@ static void increment_mac(u8 *mac) | |||
493 | 483 | ||
494 | int misc_init_r(void) | 484 | int misc_init_r(void) |
495 | { | 485 | { |
496 | #ifdef CONFIG_ATSHA204A | ||
497 | int err; | 486 | int err; |
498 | struct udevice *dev = get_atsha204a_dev(); | 487 | struct udevice *dev = get_atsha204a_dev(); |
499 | u8 mac0[4], mac1[4], mac[6]; | 488 | u8 mac0[4], mac1[4], mac[6]; |
@@ -538,8 +527,6 @@ int misc_init_r(void) | |||
538 | eth_env_set_enetaddr("eth2addr", mac); | 527 | eth_env_set_enetaddr("eth2addr", mac); |
539 | 528 | ||
540 | out: | 529 | out: |
541 | #endif | ||
542 | |||
543 | return 0; | 530 | return 0; |
544 | } | 531 | } |
545 | 532 | ||