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-rw-r--r--drivers/virtio/virtio_pci.h173
1 files changed, 173 insertions, 0 deletions
diff --git a/drivers/virtio/virtio_pci.h b/drivers/virtio/virtio_pci.h
new file mode 100644
index 0000000000..cc753ed7b3
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+++ b/drivers/virtio/virtio_pci.h
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1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * From Linux kernel include/uapi/linux/virtio_pci.h
6 */
7
8#ifndef _LINUX_VIRTIO_PCI_H
9#define _LINUX_VIRTIO_PCI_H
10
11#ifndef VIRTIO_PCI_NO_LEGACY
12
13/* A 32-bit r/o bitmask of the features supported by the host */
14#define VIRTIO_PCI_HOST_FEATURES 0
15
16/* A 32-bit r/w bitmask of features activated by the guest */
17#define VIRTIO_PCI_GUEST_FEATURES 4
18
19/* A 32-bit r/w PFN for the currently selected queue */
20#define VIRTIO_PCI_QUEUE_PFN 8
21
22/* A 16-bit r/o queue size for the currently selected queue */
23#define VIRTIO_PCI_QUEUE_NUM 12
24
25/* A 16-bit r/w queue selector */
26#define VIRTIO_PCI_QUEUE_SEL 14
27
28/* A 16-bit r/w queue notifier */
29#define VIRTIO_PCI_QUEUE_NOTIFY 16
30
31/* An 8-bit device status register */
32#define VIRTIO_PCI_STATUS 18
33
34/*
35 * An 8-bit r/o interrupt status register. Reading the value will return the
36 * current contents of the ISR and will also clear it. This is effectively
37 * a read-and-acknowledge.
38 */
39#define VIRTIO_PCI_ISR 19
40
41/* MSI-X registers: only enabled if MSI-X is enabled */
42
43/* A 16-bit vector for configuration changes */
44#define VIRTIO_MSI_CONFIG_VECTOR 20
45/* A 16-bit vector for selected queue notifications */
46#define VIRTIO_MSI_QUEUE_VECTOR 22
47
48/*
49 * The remaining space is defined by each driver as the per-driver
50 * configuration space
51 */
52#define VIRTIO_PCI_CONFIG_OFF(msix) ((msix) ? 24 : 20)
53
54/* Virtio ABI version, this must match exactly */
55#define VIRTIO_PCI_ABI_VERSION 0
56
57/*
58 * How many bits to shift physical queue address written to QUEUE_PFN.
59 * 12 is historical, and due to x86 page size.
60 */
61#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
62
63/*
64 * The alignment to use between consumer and producer parts of vring.
65 * x86 pagesize again.
66 */
67#define VIRTIO_PCI_VRING_ALIGN 4096
68
69#endif /* VIRTIO_PCI_NO_LEGACY */
70
71/* The bit of the ISR which indicates a device configuration change */
72#define VIRTIO_PCI_ISR_CONFIG 0x2
73/* Vector value used to disable MSI for queue */
74#define VIRTIO_MSI_NO_VECTOR 0xffff
75
76#ifndef VIRTIO_PCI_NO_MODERN
77
78/* IDs for different capabilities. Must all exist. */
79
80/* Common configuration */
81#define VIRTIO_PCI_CAP_COMMON_CFG 1
82/* Notifications */
83#define VIRTIO_PCI_CAP_NOTIFY_CFG 2
84/* ISR access */
85#define VIRTIO_PCI_CAP_ISR_CFG 3
86/* Device specific configuration */
87#define VIRTIO_PCI_CAP_DEVICE_CFG 4
88/* PCI configuration access */
89#define VIRTIO_PCI_CAP_PCI_CFG 5
90
91/* This is the PCI capability header: */
92struct virtio_pci_cap {
93 __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
94 __u8 cap_next; /* Generic PCI field: next ptr */
95 __u8 cap_len; /* Generic PCI field: capability length */
96 __u8 cfg_type; /* Identifies the structure */
97 __u8 bar; /* Where to find it */
98 __u8 padding[3]; /* Pad to full dword */
99 __le32 offset; /* Offset within bar */
100 __le32 length; /* Length of the structure, in bytes */
101};
102
103struct virtio_pci_notify_cap {
104 struct virtio_pci_cap cap;
105 __le32 notify_off_multiplier; /* Multiplier for queue_notify_off */
106};
107
108/* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
109struct virtio_pci_common_cfg {
110 /* About the whole device */
111 __le32 device_feature_select; /* read-write */
112 __le32 device_feature; /* read-only */
113 __le32 guest_feature_select; /* read-write */
114 __le32 guest_feature; /* read-write */
115 __le16 msix_config; /* read-write */
116 __le16 num_queues; /* read-only */
117 __u8 device_status; /* read-write */
118 __u8 config_generation; /* read-only */
119
120 /* About a specific virtqueue */
121 __le16 queue_select; /* read-write */
122 __le16 queue_size; /* read-write, power of 2 */
123 __le16 queue_msix_vector; /* read-write */
124 __le16 queue_enable; /* read-write */
125 __le16 queue_notify_off; /* read-only */
126 __le32 queue_desc_lo; /* read-write */
127 __le32 queue_desc_hi; /* read-write */
128 __le32 queue_avail_lo; /* read-write */
129 __le32 queue_avail_hi; /* read-write */
130 __le32 queue_used_lo; /* read-write */
131 __le32 queue_used_hi; /* read-write */
132};
133
134/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
135struct virtio_pci_cfg_cap {
136 struct virtio_pci_cap cap;
137 __u8 pci_cfg_data[4]; /* Data for BAR access */
138};
139
140/* Macro versions of offsets for the Old Timers! */
141#define VIRTIO_PCI_CAP_VNDR 0
142#define VIRTIO_PCI_CAP_NEXT 1
143#define VIRTIO_PCI_CAP_LEN 2
144#define VIRTIO_PCI_CAP_CFG_TYPE 3
145#define VIRTIO_PCI_CAP_BAR 4
146#define VIRTIO_PCI_CAP_OFFSET 8
147#define VIRTIO_PCI_CAP_LENGTH 12
148
149#define VIRTIO_PCI_NOTIFY_CAP_MULT 16
150
151#define VIRTIO_PCI_COMMON_DFSELECT 0
152#define VIRTIO_PCI_COMMON_DF 4
153#define VIRTIO_PCI_COMMON_GFSELECT 8
154#define VIRTIO_PCI_COMMON_GF 12
155#define VIRTIO_PCI_COMMON_MSIX 16
156#define VIRTIO_PCI_COMMON_NUMQ 18
157#define VIRTIO_PCI_COMMON_STATUS 20
158#define VIRTIO_PCI_COMMON_CFGGENERATION 21
159#define VIRTIO_PCI_COMMON_Q_SELECT 22
160#define VIRTIO_PCI_COMMON_Q_SIZE 24
161#define VIRTIO_PCI_COMMON_Q_MSIX 26
162#define VIRTIO_PCI_COMMON_Q_ENABLE 28
163#define VIRTIO_PCI_COMMON_Q_NOFF 30
164#define VIRTIO_PCI_COMMON_Q_DESCLO 32
165#define VIRTIO_PCI_COMMON_Q_DESCHI 36
166#define VIRTIO_PCI_COMMON_Q_AVAILLO 40
167#define VIRTIO_PCI_COMMON_Q_AVAILHI 44
168#define VIRTIO_PCI_COMMON_Q_USEDLO 48
169#define VIRTIO_PCI_COMMON_Q_USEDHI 52
170
171#endif /* VIRTIO_PCI_NO_MODERN */
172
173#endif /* _LINUX_VIRTIO_PCI_H */
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