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Diffstat (limited to 'sgx_km/eurasia_km/services4/srvkm/hwdefs/sgx540defs.h')
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diff --git a/sgx_km/eurasia_km/services4/srvkm/hwdefs/sgx540defs.h b/sgx_km/eurasia_km/services4/srvkm/hwdefs/sgx540defs.h
new file mode 100644
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+++ b/sgx_km/eurasia_km/services4/srvkm/hwdefs/sgx540defs.h
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1/*************************************************************************/ /*!
2@Title Hardware defs for SGX540.
3@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
4@License Dual MIT/GPLv2
5
6The contents of this file are subject to the MIT license as set out below.
7
8Permission is hereby granted, free of charge, to any person obtaining a copy
9of this software and associated documentation files (the "Software"), to deal
10in the Software without restriction, including without limitation the rights
11to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12copies of the Software, and to permit persons to whom the Software is
13furnished to do so, subject to the following conditions:
14
15The above copyright notice and this permission notice shall be included in
16all copies or substantial portions of the Software.
17
18Alternatively, the contents of this file may be used under the terms of
19the GNU General Public License Version 2 ("GPL") in which case the provisions
20of GPL are applicable instead of those above.
21
22If you wish to allow use of your version of this file only under the terms of
23GPL, and not to allow others to use your version of this file under the terms
24of the MIT license, indicate your decision by deleting the provisions above
25and replace them with the notice and other provisions required by GPL as set
26out in the file called "GPL-COPYING" included in this distribution. If you do
27not delete the provisions above, a recipient may use your version of this file
28under the terms of either the MIT license or GPL.
29
30This License is also included in this distribution in the file called
31"MIT-COPYING".
32
33EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
34PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
35BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
36PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
37COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
38IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
39CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40*/ /**************************************************************************/
41
42#ifndef _SGX540DEFS_KM_H_
43#define _SGX540DEFS_KM_H_
44
45/* Register EUR_CR_CLKGATECTL */
46#define EUR_CR_CLKGATECTL 0x0000
47#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U
48#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0
49#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU
50#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2
51#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U
52#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4
53#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U
54#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6
55#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U
56#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8
57#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U
58#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10
59#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U
60#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12
61#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U
62#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14
63#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U
64#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16
65#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U
66#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18
67#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
68#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
69#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U
70#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28
71/* Register EUR_CR_CLKGATECTL2 */
72#define EUR_CR_CLKGATECTL2 0x0004
73#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U
74#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0
75#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_MASK 0x0000000CU
76#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_SHIFT 2
77#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U
78#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4
79#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U
80#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6
81#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U
82#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8
83#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U
84#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10
85#define EUR_CR_CLKGATECTL2_MADD0_CLKG_MASK 0x00003000U
86#define EUR_CR_CLKGATECTL2_MADD0_CLKG_SHIFT 12
87#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U
88#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14
89#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U
90#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16
91#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U
92#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18
93#define EUR_CR_CLKGATECTL2_MADD1_CLKG_MASK 0x00300000U
94#define EUR_CR_CLKGATECTL2_MADD1_CLKG_SHIFT 20
95/* Register EUR_CR_CLKGATESTATUS */
96#define EUR_CR_CLKGATESTATUS 0x0008
97#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U
98#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0
99#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U
100#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1
101#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U
102#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2
103#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U
104#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3
105#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U
106#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4
107#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U
108#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5
109#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U
110#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6
111#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U
112#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7
113#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U
114#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8
115#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_MASK 0x00000200U
116#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_SHIFT 9
117#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U
118#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10
119#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U
120#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11
121#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U
122#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12
123#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U
124#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13
125#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_MASK 0x00004000U
126#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_SHIFT 14
127#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U
128#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15
129#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U
130#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16
131#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U
132#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17
133#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_MASK 0x00040000U
134#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_SHIFT 18
135#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U
136#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19
137#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U
138#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20
139/* Register EUR_CR_CLKGATECTLOVR */
140#define EUR_CR_CLKGATECTLOVR 0x000C
141#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U
142#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0
143#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU
144#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2
145#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U
146#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4
147#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U
148#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6
149#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U
150#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8
151#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U
152#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10
153#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U
154#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12
155#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U
156#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14
157#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U
158#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16
159#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U
160#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18
161/* Register EUR_CR_POWER */
162#define EUR_CR_POWER 0x001C
163#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U
164#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0
165/* Register EUR_CR_CORE_ID */
166#define EUR_CR_CORE_ID 0x0020
167#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU
168#define EUR_CR_CORE_ID_CONFIG_SHIFT 0
169#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U
170#define EUR_CR_CORE_ID_ID_SHIFT 16
171/* Register EUR_CR_CORE_REVISION */
172#define EUR_CR_CORE_REVISION 0x0024
173#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU
174#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0
175#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U
176#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8
177#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U
178#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16
179#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U
180#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24
181/* Register EUR_CR_DESIGNER_REV_FIELD1 */
182#define EUR_CR_DESIGNER_REV_FIELD1 0x0028
183#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU
184#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0
185/* Register EUR_CR_DESIGNER_REV_FIELD2 */
186#define EUR_CR_DESIGNER_REV_FIELD2 0x002C
187#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU
188#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0
189/* Register EUR_CR_SOFT_RESET */
190#define EUR_CR_SOFT_RESET 0x0080
191#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U
192#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0
193#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U
194#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1
195#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U
196#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2
197#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U
198#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3
199#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U
200#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4
201#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U
202#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5
203#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U
204#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6
205#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U
206#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7
207#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U
208#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8
209#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U
210#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9
211#define EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK 0x00000400U
212#define EUR_CR_SOFT_RESET_CACHEL2_RESET_SHIFT 10
213#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U
214#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11
215#define EUR_CR_SOFT_RESET_MADD_RESET_MASK 0x00001000U
216#define EUR_CR_SOFT_RESET_MADD_RESET_SHIFT 12
217#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U
218#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13
219#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U
220#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14
221#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U
222#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15
223#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U
224#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16
225#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U
226#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17
227/* Register EUR_CR_EVENT_HOST_ENABLE2 */
228#define EUR_CR_EVENT_HOST_ENABLE2 0x0110
229#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U
230#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4
231#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U
232#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3
233#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U
234#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2
235#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U
236#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1
237#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U
238#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0
239/* Register EUR_CR_EVENT_HOST_CLEAR2 */
240#define EUR_CR_EVENT_HOST_CLEAR2 0x0114
241#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U
242#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4
243#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U
244#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3
245#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U
246#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2
247#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U
248#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1
249#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U
250#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0
251/* Register EUR_CR_EVENT_STATUS2 */
252#define EUR_CR_EVENT_STATUS2 0x0118
253#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U
254#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4
255#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U
256#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3
257#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U
258#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2
259#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U
260#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1
261#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U
262#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0
263/* Register EUR_CR_EVENT_STATUS */
264#define EUR_CR_EVENT_STATUS 0x012CU
265#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U
266#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31
267#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U
268#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29
269#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U
270#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28
271#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U
272#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27
273#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
274#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26
275#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
276#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
277#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U
278#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24
279#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U
280#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23
281#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U
282#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22
283#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U
284#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21
285#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U
286#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20
287#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U
288#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19
289#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U
290#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18
291#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U
292#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17
293#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U
294#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16
295#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U
296#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15
297#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U
298#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14
299#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U
300#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13
301#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U
302#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12
303#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U
304#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11
305#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U
306#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10
307#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U
308#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9
309#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U
310#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8
311#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U
312#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7
313#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U
314#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6
315#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U
316#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5
317#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U
318#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4
319#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
320#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3
321#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
322#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
323#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
324#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1
325#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U
326#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0
327/* Register EUR_CR_EVENT_HOST_ENABLE */
328#define EUR_CR_EVENT_HOST_ENABLE 0x0130
329#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U
330#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31
331#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U
332#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29
333#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U
334#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28
335#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U
336#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27
337#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
338#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26
339#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
340#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
341#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U
342#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24
343#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U
344#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23
345#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U
346#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22
347#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U
348#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21
349#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U
350#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20
351#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U
352#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19
353#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U
354#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18
355#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U
356#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17
357#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U
358#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16
359#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U
360#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15
361#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U
362#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14
363#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U
364#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13
365#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U
366#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12
367#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U
368#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11
369#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U
370#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10
371#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U
372#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9
373#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U
374#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8
375#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U
376#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7
377#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U
378#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6
379#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U
380#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5
381#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U
382#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4
383#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
384#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3
385#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
386#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
387#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
388#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1
389#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U
390#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0
391/* Register EUR_CR_EVENT_HOST_CLEAR */
392#define EUR_CR_EVENT_HOST_CLEAR 0x0134
393#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U
394#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31
395#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U
396#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29
397#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U
398#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28
399#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U
400#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27
401#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
402#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26
403#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
404#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
405#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U
406#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24
407#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U
408#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23
409#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U
410#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22
411#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U
412#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21
413#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U
414#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20
415#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U
416#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19
417#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U
418#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18
419#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U
420#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17
421#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U
422#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16
423#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U
424#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15
425#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U
426#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14
427#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U
428#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13
429#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U
430#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12
431#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U
432#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11
433#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U
434#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10
435#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U
436#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9
437#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U
438#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8
439#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U
440#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7
441#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U
442#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6
443#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U
444#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5
445#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U
446#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4
447#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
448#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3
449#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
450#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
451#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
452#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1
453#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U
454#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0
455/* Register EUR_CR_TIMER */
456#define EUR_CR_TIMER 0x0144
457#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU
458#define EUR_CR_TIMER_VALUE_SHIFT 0
459/* Register EUR_CR_EVENT_KICK1 */
460#define EUR_CR_EVENT_KICK1 0x0AB0
461#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU
462#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0
463/* Register EUR_CR_PDS_EXEC_BASE */
464#define EUR_CR_PDS_EXEC_BASE 0x0AB8
465#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U
466#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20
467/* Register EUR_CR_EVENT_KICK2 */
468#define EUR_CR_EVENT_KICK2 0x0AC0
469#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U
470#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0
471/* Register EUR_CR_EVENT_KICKER */
472#define EUR_CR_EVENT_KICKER 0x0AC4
473#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U
474#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4
475/* Register EUR_CR_EVENT_KICK */
476#define EUR_CR_EVENT_KICK 0x0AC8
477#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U
478#define EUR_CR_EVENT_KICK_NOW_SHIFT 0
479/* Register EUR_CR_EVENT_TIMER */
480#define EUR_CR_EVENT_TIMER 0x0ACC
481#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U
482#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24
483#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU
484#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0
485/* Register EUR_CR_PDS_INV0 */
486#define EUR_CR_PDS_INV0 0x0AD0
487#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U
488#define EUR_CR_PDS_INV0_DSC_SHIFT 0
489/* Register EUR_CR_PDS_INV1 */
490#define EUR_CR_PDS_INV1 0x0AD4
491#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U
492#define EUR_CR_PDS_INV1_DSC_SHIFT 0
493/* Register EUR_CR_EVENT_KICK3 */
494#define EUR_CR_EVENT_KICK3 0x0AD8
495#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U
496#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0
497/* Register EUR_CR_PDS_INV3 */
498#define EUR_CR_PDS_INV3 0x0ADC
499#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U
500#define EUR_CR_PDS_INV3_DSC_SHIFT 0
501/* Register EUR_CR_PDS_INV_CSC */
502#define EUR_CR_PDS_INV_CSC 0x0AE0
503#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U
504#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0
505/* Register EUR_CR_PDS_PC_BASE */
506#define EUR_CR_PDS_PC_BASE 0x0B2C
507#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x00FFFFFFU
508#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0
509/* Register EUR_CR_BIF_CTRL */
510#define EUR_CR_BIF_CTRL 0x0C00
511#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U
512#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0
513#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U
514#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1
515#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U
516#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2
517#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U
518#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3
519#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U
520#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4
521#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U
522#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8
523#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U
524#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9
525#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U
526#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10
527#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U
528#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12
529#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U
530#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13
531#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U
532#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14
533#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U
534#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15
535/* Register EUR_CR_BIF_INT_STAT */
536#define EUR_CR_BIF_INT_STAT 0x0C04
537#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU
538#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0
539#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U
540#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14
541#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U
542#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15
543/* Register EUR_CR_BIF_FAULT */
544#define EUR_CR_BIF_FAULT 0x0C08
545#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U
546#define EUR_CR_BIF_FAULT_SB_SHIFT 4
547#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U
548#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12
549/* Register EUR_CR_BIF_DIR_LIST_BASE0 */
550#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84
551#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U
552#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12
553/* Register EUR_CR_BIF_TA_REQ_BASE */
554#define EUR_CR_BIF_TA_REQ_BASE 0x0C90
555#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U
556#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20
557/* Register EUR_CR_BIF_MEM_REQ_STAT */
558#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8
559#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU
560#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0
561/* Register EUR_CR_BIF_3D_REQ_BASE */
562#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC
563#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U
564#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20
565/* Register EUR_CR_BIF_ZLS_REQ_BASE */
566#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0
567#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U
568#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20
569/* Register EUR_CR_2D_BLIT_STATUS */
570#define EUR_CR_2D_BLIT_STATUS 0x0E04
571#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
572#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
573#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U
574#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24
575/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */
576#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10
577#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U
578#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0
579#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU
580#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1
581#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U
582#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4
583#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U
584#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12
585/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */
586#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14
587#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU
588#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0
589#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U
590#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12
591#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U
592#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24
593/* Table EUR_CR_USE_CODE_BASE */
594/* Register EUR_CR_USE_CODE_BASE */
595#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
596#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x00FFFFFFU
597#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
598#define EUR_CR_USE_CODE_BASE_DM_MASK 0x03000000U
599#define EUR_CR_USE_CODE_BASE_DM_SHIFT 24
600/* Number of entries in table EUR_CR_USE_CODE_BASE */
601#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16
602#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16
603
604#endif /* _SGX540DEFS_KM_H_ */
605