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authorOlivier Deprez2020-12-03 05:02:26 -0600
committerTrustedFirmware Code Review2020-12-03 05:02:26 -0600
commit5e8911a035e93233ed9d7047f2684006bf634cd3 (patch)
treef00ec869328c0994a91f2bddf582320dab7cddc3
parent08886940764be20d1b4db447193230845e76604e (diff)
parent0563ab08e892b899905193d4e482440eecd2d36a (diff)
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Merge "Aarch64: Add support for FEAT_MTE3" into integration
-rw-r--r--include/arch/aarch64/arch.h14
-rw-r--r--lib/el3_runtime/aarch64/context_mgmt.c31
2 files changed, 28 insertions, 17 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 33e1134dd..2518e5c27 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -266,9 +266,17 @@
266#define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 266#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
267#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 267#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
268 268
269#define MTE_UNIMPLEMENTED ULL(0) 269/* Memory Tagging Extension is not implemented */
270#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ 270#define MTE_UNIMPLEMENTED U(0)
271#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ 271/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
272#define MTE_IMPLEMENTED_EL0 U(1)
273/* FEAT_MTE2: Full MTE is implemented */
274#define MTE_IMPLEMENTED_ELX U(2)
275/*
276 * FEAT_MTE3: MTE is implemented with support for
277 * asymmetric Tag Check Fault handling
278 */
279#define MTE_IMPLEMENTED_ASY U(3)
272 280
273#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 281#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
274#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 282#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index b460731e8..72d463b71 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -144,30 +144,33 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
144 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 144 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
145#endif /* !CTX_INCLUDE_PAUTH_REGS */ 145#endif /* !CTX_INCLUDE_PAUTH_REGS */
146 146
147#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
148 /* Get Memory Tagging Extension support level */
149 unsigned int mte = get_armv8_5_mte_support();
150#endif
147 /* 151 /*
148 * Enable MTE support. Support is enabled unilaterally for the normal 152 * Enable MTE support. Support is enabled unilaterally for the normal
149 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 153 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
150 * set. 154 * set.
151 */ 155 */
152#if CTX_INCLUDE_MTE_REGS 156#if CTX_INCLUDE_MTE_REGS
153 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 157 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
154 scr_el3 |= SCR_ATA_BIT; 158 scr_el3 |= SCR_ATA_BIT;
155#else 159#else
156 unsigned int mte = get_armv8_5_mte_support(); 160 /*
157 if (mte == MTE_IMPLEMENTED_EL0) { 161 * When MTE is only implemented at EL0, it can be enabled
158 /* 162 * across both worlds as no MTE registers are used.
159 * Can enable MTE across both worlds as no MTE registers are 163 */
160 * used 164 if ((mte == MTE_IMPLEMENTED_EL0) ||
161 */ 165 /*
162 scr_el3 |= SCR_ATA_BIT; 166 * When MTE is implemented at all ELs, it can be only enabled
163 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 167 * in Non-Secure world without register saving.
164 /* 168 */
165 * Can only enable MTE in Non-Secure world without register 169 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) &&
166 * saving 170 (security_state == NON_SECURE))) {
167 */
168 scr_el3 |= SCR_ATA_BIT; 171 scr_el3 |= SCR_ATA_BIT;
169 } 172 }
170#endif 173#endif /* CTX_INCLUDE_MTE_REGS */
171 174
172#ifdef IMAGE_BL31 175#ifdef IMAGE_BL31
173 /* 176 /*