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-rw-r--r--build/config.bld4
-rw-r--r--platform/ti/dce/baseimage/dce_dsp.cfg29
2 files changed, 31 insertions, 2 deletions
diff --git a/build/config.bld b/build/config.bld
index fb3d988..74815a5 100644
--- a/build/config.bld
+++ b/build/config.bld
@@ -29,7 +29,7 @@ for (x = 0; x < arguments.length; x++)
29 * 9540_0000 ????_???? 280_0000 ( 40 MB) EXT_HEAP 29 * 9540_0000 ????_???? 280_0000 ( 40 MB) EXT_HEAP
30 * 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF 30 * 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
31 * 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA 31 * 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
32 * 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt) 32 * 9F07_0000 9F07_0000 6_0000 ( 384 kB) PM_DATA (Power mgmt)
33 */ 33 */
34var evmDRA7XX_ExtMemMapDsp1 = { 34var evmDRA7XX_ExtMemMapDsp1 = {
35 EXT_CODE: { name: "EXT_CODE", base: 0x95000000, len: 0x200000, space: "code", access: "RWX" }, 35 EXT_CODE: { name: "EXT_CODE", base: 0x95000000, len: 0x200000, space: "code", access: "RWX" },
@@ -37,7 +37,7 @@ var evmDRA7XX_ExtMemMapDsp1 = {
37 EXT_HEAP: { name: "EXT_HEAP", base: 0x95400000, len: 0x02800000, space: "data", access: "RW" }, 37 EXT_HEAP: { name: "EXT_HEAP", base: 0x95400000, len: 0x02800000, space: "data", access: "RW" },
38 TRACE_BUF: { name: "TRACE_BUF", base: 0x9F000000, len: 0x00060000, space: "data", access: "RW" }, 38 TRACE_BUF: { name: "TRACE_BUF", base: 0x9F000000, len: 0x00060000, space: "data", access: "RW" },
39 EXC_DATA: { name: "EXC_DATA", base: 0x9F060000, len: 0x00010000, space: "data", access: "RW" }, 39 EXC_DATA: { name: "EXC_DATA", base: 0x9F060000, len: 0x00010000, space: "data", access: "RW" },
40 PM_DATA: { name: "PM_DATA", base: 0x9F070000, len: 0x00020000, space: "data", access: "RWX" } 40 PM_DATA: { name: "PM_DATA", base: 0x9F070000, len: 0x00060000, space: "data", access: "RWX" }
41}; 41};
42 42
43Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = { 43Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
diff --git a/platform/ti/dce/baseimage/dce_dsp.cfg b/platform/ti/dce/baseimage/dce_dsp.cfg
index 9669492..77b5762 100644
--- a/platform/ti/dce/baseimage/dce_dsp.cfg
+++ b/platform/ti/dce/baseimage/dce_dsp.cfg
@@ -228,6 +228,35 @@ BIOS.smpEnabled = false;
228 228
229 229
230var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); 230var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
231
232
233/* Modules used in Power Management */
234xdc.loadPackage('ti.pm');
235var Power = xdc.useModule('ti.sysbios.family.c66.vayu.Power');
236Power.loadSegment = "PM_DATA";
237
238/* Idle functions - PM functions should be last */
239var Idle = xdc.useModule('ti.sysbios.knl.Idle');
240
241/* DEH Exception Handling */
242var Deh = xdc.useModule('ti.deh.Deh');
243
244/* Watchdog detection functions in each core */
245/* Must be placed before pwr mgmt */
246Idle.addFunc('&ti_deh_Deh_idleBegin');
247
248/* Idle Power Management functions for each core */
249Idle.addFunc('&IpcPower_idle');
250
251/*
252 * Workaround for silicon bug - enable if power management is desired
253 *
254 * IpcPower_callIdle must be placed in L2SRAM and not external memory
255 * to avoid CPU hang when going into idle
256 */
257Program.sectMap[".text:IpcPower_callIdle"] = "L2SRAM";
258
259
231/* 260/*
232BIOS assumes that default frequency is 38.4 MHz. On OMAP5, SYS_CLK is used to source 261BIOS assumes that default frequency is 38.4 MHz. On OMAP5, SYS_CLK is used to source
233Hence it is clocked at 19.2 MHz. 262Hence it is clocked at 19.2 MHz.