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* HACK: ARM: DRA7xx: Add VPE crossbar settingHEADmasterSomnath Mukherjee2013-08-141-0/+2
| | | | Signed-off-by: Somnath Mukherjee <somnath@ti.com>
* ARM: DRA7xx: Enable CPSW Ethernet supportMugunthan V N2013-08-141-0/+19
| | | | | | | | | Enabling CPSW Ethernet support in DRA7xx EVM. Change-Id: I870a812e72995106dd5a6eb2566e2ebff814eea7 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Resolved merge conflicts and added change id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* ARM: DRA7xx: Add CPSW and MDIO pinmux supportMugunthan V N2013-08-141-0/+14
| | | | | | | | | Adding CPSW Slave 0 and MDIO pinmux support for DRA7xx EVM Change-Id: I562fecee5194f9498d1e8387e1e3888e3ebb3fbd Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Resolved merge conflict and added change id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* ARM: DRA7xx: Add CPSW support to DRA7xx EVMMugunthan V N2013-08-145-5/+185
| | | | | | | | | Adding support for CPSW Ethernet support found in DRA7xx EVM Change-Id: Id68e606967aeeecaaf991eb26ef94d2119dc7a83 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Resolved merge conflicts and added change id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* ARM: DRA7xx: Enable GMAC clock controlMugunthan V N2013-08-143-1/+12
| | | | | | | | | Enabling CPSW module by enabling GMAC clock control Change-Id: I6b48ee2ba5dd400b3f9e1744933e7dbc09e4a13e Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Resolved merge conflicts and added change id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* ARM: DRA7xx: Lock DPLL_GMACLokesh Vutla2013-08-144-0/+32
| | | | | | | | | | | | Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Change-Id: I5b3cffa699f83cf88ee98086ba2dc9a8586a1074 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Added change-id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* drivers: net: cpsw: Enable statistics for all portMugunthan V N2013-08-141-0/+1
| | | | | | | | | Enable hardware statistics for all ports, enabling only to host port is useless Change-Id: I0dd84448a5c002a8280275e6ed253fa61576e467 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Added change-id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* drivers: net: cpsw: remove hard coding bd ram for cpswMugunthan V N2013-08-144-3/+4
| | | | | | | | | | BD ram address may vary in various SOC, so removing the hardcoding and passing the same information through platform data Change-Id: Ib36d34f66f741321abdf06575010c87c99d49085 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Added change-id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* HACK: ARM: DRA7xx: Add Ethernet crossbar settingSomnath Mukherjee2013-08-141-0/+8
| | | | Signed-off-by: Somnath Mukherjee <somnath@ti.com>
* dra7xx: Enabled UART-boot modeMinal2013-08-133-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART-boot is considered as a peripheral boot. For dra7xx Peripheral boot UART3 is used as default console. The ROM code transfers MLO over UART3 in this case. For Memory boot UART1 is used as default console. Which UART to be used is decided by parameter CONS_INDEX. For peripheral boot this should be set to 3. Changes common to memory boot and peripheral boot: -------------------------------------------------- boards.cfg: Moved definition of CONS_INDEX in boards.cfg to make it configurable between memory boot and peripheral boot. spl.h: Added #define BOOT_DEVICE_UART for UART boot device code. Changes specific to peripheral boot: ------------------------------------ boards.cfg: Added a build variant "dra7xx_evm_uart3" for dra7xx that sets UART to UART3 and enables YMODEM support. MLO->u-boot needs YMODEM support enabled. By default it is disabled. Changes needed in addition to the above: ---------------------------------------- 1. When building u-boot ensure usage of dra7xx_evm_uart3_config instead of dra7xx_evm_config. 2. Please note that apart from the above changes CONFIG_SPL_TEXT_BASE should point to base of OCMC_RAM1 for proper execution. In memory boot mode ROM code transfers MLO to location OCMC_RAM1 base+offset (CONFIG_SPL_TEXT_BASE = 0x40300000+350). In peripheral boot mode ROM code transfers MLO to location OCMC_RAM1 base (0x40300000). Hence is is a must to change CONFIG_SPL_TEXT_BASE in include/configs/omap5_common.h from 0x40300350 to 0x40300000 Signed-off-by: Minal <minal.shah@ti.com>
* arm: omap5: dra7xx: Rework bootcmd to handle two MMC devsti2013.04.02.prod.13.08.001alaganraj2013-08-081-20/+24
| | | | | | | | | | | | omap5_uevm and dra7xx_evm both can boot from either the MMC card or eMMC chip on board. We should try both interfaces. This modification also allows a graceful fallback if a device exists but boot images are not present on it. This is adopted from am335x_evm patch. Signed-off-by: alaganraj <alaganraj.s@ti.com>
* HACK: ARM: DRA7xx: crossbar: Add support for crossbarAmarinder Bindra2013-08-083-0/+58
| | | | | | | | | | | | | | | | | | | DRA7xx has a large number of interrupts/dma requests to service the needs of its many peripherals and subsystems. All of the requests lines from the subsystems are not needed at the same time, so they have to be muxed to the controllers appropriately. In such places a interrupt/dma controllers are preceded by an IRQ/DMA CROSSBAR that provides flexibility in muxing the device requests to the controller inputs. This configures some of the MPU IRQs and SDMA DREQ at the u-boot until this functionality is available at the kernel. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
* configs: DRA7: include Bank Address register supportRavikumar Kattekola2013-08-081-0/+1
| | | | | | | | | CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg This option adds the Bank addr/Extended addr support on SPI flashes which has size > 16Mbytes. Signed-off-by: Ravikumar Kattekola <rk@ti.com>
* README: qspi usecase and testing documentation.Sourav Poddar2013-08-082-0/+85
| | | | | | | Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* driver: spi: Add memory mapped read supportSourav Poddar2013-08-085-17/+90
| | | | | | | | | Qspi controller has a memory mapped port which can be used for data transfers. First controller need to be configured through configuration port, then for data read switch the controller to memory mapped and read from the predefined location. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* drivers: mtd: qspi: Add quad read supportRavikumar Kattekola2013-08-085-6/+129
| | | | | | | | | | | | Add Quad read mode (6 pin interface) support to spi flash and ti qspi driver. Quad mode (0x6bh on spansion) uses two extra pins (D2 and D3) for data transfer apart from the usual D0 and D1 pins thus transfering 4 bits per cycle. Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* dra7xx_evm: add SPL API, QSPI, and serial flash supportMatt Porter2013-08-082-0/+28
| | | | | | | | Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* spi: add TI QSPI driverMatt Porter2013-08-082-0/+263
| | | | | | | Adds a SPI master driver for the TI QSPI peripheral. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* armv7: hw_data: change clock divider setting.Sourav Poddar2013-08-081-1/+1
| | | | | | | | | | | | | Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* omap5: add qspi supportMatt Porter2013-08-085-0/+13
| | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* sf: Warn to use BAR for > 16MiB flashesJagannadha Sutradharudu Teki2013-08-081-0/+6
| | | | | | Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add debug messages on spi_flash_read_commonJagannadha Sutradharudu Teki2013-08-081-1/+11
| | | | | | | - Added debug's on spi_flash_read_common() - Added space Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Place the sf calls in proper orderJagannadha Sutradharudu Teki2013-08-081-92/+92
| | | | | | Placed the sf calls in proper order - erase/write/read Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Unify spi_flash write codeJagannadha Sutradharudu Teki2013-08-082-72/+63
| | | | | | | Move common flash write code into spi_flash_write_common(). Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
* sf: Add flag status register polling supportJagannadha Sutradharudu Teki2013-08-084-4/+21
| | | | | | | | | | | | Flag status register polling is required for micron 512Mb flash devices onwards, for performing erase/program operations. Like polling for WIP(Write-In-Progress) bit in read status register, spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control) bit in flag status register. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: Remove spi_flash_cmd_poll_bit()Jagannadha Sutradharudu Teki2013-08-082-12/+3
| | | | | | | | | There is no other call other than spi_flash_cmd_wait_ready(), hence removed spi_flash_cmd_poll_bit and use the poll status code spi_flash_cmd_wait_ready() itself. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: spansion: Add support for S25FL512S_64KJagannadha Sutradharudu Teki2013-08-081-0/+7
| | | | | | Add support for Spansion S25FL512S_64K SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Use spi_flash_addr() in write callJagannadha Sutradharudu Teki2013-08-081-5/+2
| | | | | | | | Use the existing spi_flash_addr() for 3-byte addressing cmd filling in write call. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: Add bank addr code in CONFIG_SPI_FLASH_BARJagannadha Sutradharudu Teki2013-08-084-11/+32
| | | | | | | | | | | Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: Update sf read to support all sizes of flashesJagannadha Sutradharudu Teki2013-08-081-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updated the spi_flash read func to support all sizes of flashes using bank reg addr facility. The same support has been added in below patch for erase/write spi_flash functions: "sf: Support all sizes of flashes using bank addr reg facility" (sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415) With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~460 bytes. sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: Update sf to support all sizes of flashesJagannadha Sutradharudu Teki2013-08-081-14/+26
| | | | | | | | | | | | | | | | | Updated the spi_flash framework to handle all sizes of flashes using bank/extd addr reg facility The current implementation in spi_flash supports 3-byte address mode due to this up to 16Mbytes amount of flash is able to access for those flashes which has an actual size of > 16MB. As most of the flashes introduces a bank/extd address registers for accessing the flashes in 16Mbytes of banks if the flash size is > 16Mbytes, this new scheme will add the bank selection feature for performing write/erase operations on all flashes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: Read flash bank addr register at probe timeJagannadha Sutradharudu Teki2013-08-083-0/+31
| | | | | | | | | | | | | | | Read the flash bank addr register to get the state of bank in a perticular flash. and also bank write happens only when there is a change in bank selection from user. bank read only valid for flashes which has > 16Mbytes those are opearted in 3-byte addr mode, each bank occupies 16Mytes. Suppose if the flash has 64Mbytes size consists of 4 banks like bank0, bank1, bank2 and bank3. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: Discover the bank addr commandsJagannadha Sutradharudu Teki2013-08-083-0/+39
| | | | | | | | | | Bank/Extended addr commands are specific to particular flash vendor so discover them based on the idocode0. Assign the discovered bank commands to spi_flash members so-that the bank read/write will use their specific operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add bank address register writing supportJagannadha Sutradharudu Teki2013-08-082-0/+29
| | | | | | | | | | | | | | | This patch provides support to program a flash bank address register. extended/bank address register contains an information to access the 4th byte addressing in 3-byte address mode. reff' the spec for more details about bank addr register in Page-63, Table 8.16 http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: spansion: Correct name of S25FL128S 64K Sector partJagannadha Sutradharudu Teki2013-08-081-1/+1
| | | | | | | | | Corrected the name of S25FL128S 64K sector part SPI flash, S25FL128S supported has been added in below commit "sf: spansion: Add support for S25FL128S" (sha1: 1bfb9f156aa66cca6bb9c773867a1f02a84b14be) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* DRA7: Revert QSPI v1 patchset to apply v2 with code clean upRavikumar Kattekola2013-08-0812-695/+30
| | | | | | | | | | | | | | | | | | | | | | This patch is a squash of 8 reverted patches as mentioned below. This was required inorder to apply a later version of the same patchset with code clean up and fixes. Revert "arm: omap5: hw_data: Enable clock selectively." Revert "board: dra7xxx: modfiy mux data." Revert "Fix offset detail and add sysboot settings" Revert "README: qspi usecase and testing documentation." Revert "drivers: mtd: spi: Modify read/write command for sfl256s flash." Revert "dra7xx_evm: add SPL API, QSPI, and serial flash support" Revert "spi: add TI QSPI driver" Revert "omap5: add qspi support"
* arm: omap5: hw_data: Enable clock selectively.ti2013.04.02.prod.13.07.001Sourav Poddar2013-06-281-0/+2
| | | | | | | | | | | Api to enable clock is common for both dra and omap5, hence selectively enable qspi clock. Without this, omap5 is not working properly at u-boot level. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reported-by: Amarinder Bindra <a-bindra@ti.com> Signed-off-by: Somnath Mukherjee <somnath@ti.com>
* board: dra7xxx: modfiy mux data.ti2013.04.02Sourav Poddar2013-06-081-10/+11
| | | | | | Modify qspi pin configuartions Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* Fix offset detail and add sysboot settingsSourav Poddar2013-06-071-9/+8
| | | | | | Fix u-bot offset details and add qspi sysboot setings. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* README: qspi usecase and testing documentation.Sourav Poddar2013-06-072-0/+76
| | | | | | | Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* drivers: mtd: spi: Modify read/write command for sfl256s flash.Sourav Poddar2013-06-071-5/+34
| | | | | | | | | | Reading using the already supported read command is causing regression even while reading 4k bytes, as a result doing a page by page read. At the end of the write sequence, write enable latch should be disabled and re enabled while doing the next page programming. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* dra7xx_evm: add SPL API, QSPI, and serial flash supportMatt Porter2013-06-072-24/+310
| | | | | | | | Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* spi: add TI QSPI driverMatt Porter2013-06-072-0/+263
| | | | | | | Adds a SPI master driver for the TI QSPI peripheral. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* omap5: add qspi supportMatt Porter2013-06-075-1/+10
| | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R2013-05-298-31/+220
| | | | | | | | | | | DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla2013-05-297-46/+72
| | | | | | | | | | | Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: DRA7xx: Update pinmux dataLokesh Vutla2013-05-292-16/+29
| | | | | | | Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
* mmc: omap_hsmmc: add mmc1 pbias, ldo1Balaji T K2013-05-296-20/+48
| | | | | | | add dra mmc pbias support and ldo1 power on Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7xx: Correct SRAM END addressSricharan R2013-05-293-7/+6
| | | | | | | NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: DRA7xx: Correct the SYS_CLK to 20MHZSricharan R2013-05-293-1/+7
| | | | | | | The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. Signed-off-by: Sricharan R <r.sricharan@ti.com>