diff options
author | Nikhil Devshatwar | 2020-04-15 04:33:21 -0500 |
---|---|---|
committer | Nikhil Devshatwar | 2020-04-15 06:22:15 -0500 |
commit | 380ee019ef4c0ed879ec35badf95e827ae37d622 (patch) | |
tree | 63f274fcaafe02782aa8cfa1c883bc9b28a8692b | |
parent | 659637b47d155713da5244f2bc52cc073e5a0359 (diff) | |
download | host-tools-380ee019ef4c0ed879ec35badf95e827ae37d622.tar.gz host-tools-380ee019ef4c0ed879ec35badf95e827ae37d622.tar.xz host-tools-380ee019ef4c0ed879ec35badf95e827ae37d622.zip |
RM-autogen-data.py: Add support for am65x SR1 and SR2
Auto generate the python headers from documentation
Update the argparse to support both Silicon revisions.
Create baseline excel sheet for am6x and am65x_sr2
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
-rwxr-xr-x | respart/RM-autogen-data.py | 2 | ||||
-rwxr-xr-x | respart/RM-autogen.py | 2 | ||||
-rwxr-xr-x | respart/SYSFW-NAVSS-ResAssg.xlsx | bin | 19530 -> 26639 bytes | |||
-rw-r--r-- | respart/am65x.py | 364 | ||||
-rw-r--r-- | respart/am65x_sr2.py | 70 | ||||
-rw-r--r-- | respart/am6x.py | 70 |
6 files changed, 142 insertions, 366 deletions
diff --git a/respart/RM-autogen-data.py b/respart/RM-autogen-data.py index 2654a1f..c845004 100755 --- a/respart/RM-autogen-data.py +++ b/respart/RM-autogen-data.py | |||
@@ -98,7 +98,7 @@ parser = argparse.ArgumentParser(prog='RM-autogen.py', formatter_class=argparse. | |||
98 | description='RM-autogen.py - Auto generate the Resource Management data') | 98 | description='RM-autogen.py - Auto generate the Resource Management data') |
99 | 99 | ||
100 | parser.add_argument('-s', '--soc', required=True, dest='soc', | 100 | parser.add_argument('-s', '--soc', required=True, dest='soc', |
101 | action='store', choices=['j721e', 'am65x'], | 101 | action='store', choices=['j721e', 'am6x', 'am65x_sr2'], |
102 | help='SoC name') | 102 | help='SoC name') |
103 | 103 | ||
104 | parser.add_argument('-o', '--output', required=True, dest='output', | 104 | parser.add_argument('-o', '--output', required=True, dest='output', |
diff --git a/respart/RM-autogen.py b/respart/RM-autogen.py index d8d55e5..c70df3b 100755 --- a/respart/RM-autogen.py +++ b/respart/RM-autogen.py | |||
@@ -117,7 +117,7 @@ parser = argparse.ArgumentParser(prog='RM-autogen.py', formatter_class=argparse. | |||
117 | description='RM-autogen.py - Auto generate the Resource Management data') | 117 | description='RM-autogen.py - Auto generate the Resource Management data') |
118 | 118 | ||
119 | parser.add_argument('-s', '--soc', required=True, dest='soc', | 119 | parser.add_argument('-s', '--soc', required=True, dest='soc', |
120 | action='store', choices=['j721e', 'am65x'], | 120 | action='store', choices=['j721e', 'am6x', 'am65x_sr2'], |
121 | help='SoC name') | 121 | help='SoC name') |
122 | 122 | ||
123 | parser.add_argument('-o', '--output', required=True, dest='output', | 123 | parser.add_argument('-o', '--output', required=True, dest='output', |
diff --git a/respart/SYSFW-NAVSS-ResAssg.xlsx b/respart/SYSFW-NAVSS-ResAssg.xlsx index e9dbcd2..aeae01d 100755 --- a/respart/SYSFW-NAVSS-ResAssg.xlsx +++ b/respart/SYSFW-NAVSS-ResAssg.xlsx | |||
Binary files differ | |||
diff --git a/respart/am65x.py b/respart/am65x.py deleted file mode 100644 index 17c7b12..0000000 --- a/respart/am65x.py +++ /dev/null | |||
@@ -1,364 +0,0 @@ | |||
1 | ''' | ||
2 | Generated from the SYSFW headers | ||
3 | cat include/soc/am65x/devices.h | grep "#define AM6_DEV" | awk -F"[ ()]*" '{print "\""$2"\" : "$3","}' | ||
4 | cat include/soc/am65x/resasg_types.h | grep "#define RESASG_SUBTYPE" | awk -F"[ ()]*" '{print "\""$2"\" : " substr($3, 1, length($3)-1)","}' | ||
5 | cat include/soc/am65x/hosts.h | grep "#define HOST_ID" | awk -F"[ ()]*" '{print "\""$2"\" : " substr($3, 1, length($3)-1)","}' | ||
6 | ''' | ||
7 | |||
8 | |||
9 | RESASG_TYPE_SHIFT = 6 | ||
10 | RESASG_SUBTYPE_SHIFT = 0 | ||
11 | |||
12 | const_values = { | ||
13 | "AM6_DEV_DCC4" : 13, | ||
14 | "AM6_DEV_DCC6" : 15, | ||
15 | "AM6_DEV_DCC0" : 9, | ||
16 | "AM6_DEV_MCU_DCC2" : 19, | ||
17 | "AM6_DEV_DCC5" : 14, | ||
18 | "AM6_DEV_MCU_DCC0" : 17, | ||
19 | "AM6_DEV_MCU_DCC1" : 18, | ||
20 | "AM6_DEV_DCC1" : 10, | ||
21 | "AM6_DEV_DCC3" : 12, | ||
22 | "AM6_DEV_DCC7" : 16, | ||
23 | "AM6_DEV_DCC2" : 11, | ||
24 | "AM6_DEV_MCU_I2C0" : 114, | ||
25 | "AM6_DEV_I2C3" : 113, | ||
26 | "AM6_DEV_I2C2" : 112, | ||
27 | "AM6_DEV_WKUP_I2C0" : 115, | ||
28 | "AM6_DEV_I2C0" : 110, | ||
29 | "AM6_DEV_I2C1" : 111, | ||
30 | "AM6_DEV_TIMER5" : 30, | ||
31 | "AM6_DEV_TIMER6" : 31, | ||
32 | "AM6_DEV_TIMER7" : 32, | ||
33 | "AM6_DEV_MCU_TIMER0" : 35, | ||
34 | "AM6_DEV_TIMER8" : 33, | ||
35 | "AM6_DEV_TIMER2" : 27, | ||
36 | "AM6_DEV_MCU_TIMER1" : 36, | ||
37 | "AM6_DEV_MCU_TIMER2" : 37, | ||
38 | "AM6_DEV_TIMER4" : 29, | ||
39 | "AM6_DEV_TIMER3" : 28, | ||
40 | "AM6_DEV_TIMER9" : 34, | ||
41 | "AM6_DEV_TIMER11" : 26, | ||
42 | "AM6_DEV_TIMER10" : 25, | ||
43 | "AM6_DEV_TIMER0" : 23, | ||
44 | "AM6_DEV_MCU_TIMER3" : 38, | ||
45 | "AM6_DEV_TIMER1" : 24, | ||
46 | "AM6_DEV_WKUP_PSC0" : 79, | ||
47 | "AM6_DEV_CBASS0" : 82, | ||
48 | "AM6_DEV_PLL_MMR0" : 101, | ||
49 | "AM6_DEV_MCU_CPT2_AGGR0" : 7, | ||
50 | "AM6_DEV_CPT2_AGGR0" : 6, | ||
51 | "AM6_DEV_DEBUGSS0" : 68, | ||
52 | "AM6_DEV_EHRPWM4" : 44, | ||
53 | "AM6_DEV_EHRPWM1" : 41, | ||
54 | "AM6_DEV_EHRPWM0" : 40, | ||
55 | "AM6_DEV_EHRPWM3" : 43, | ||
56 | "AM6_DEV_EHRPWM5" : 45, | ||
57 | "AM6_DEV_EHRPWM2" : 42, | ||
58 | "AM6_DEV_ELM0" : 46, | ||
59 | "AM6_DEV_MCU_UART0" : 149, | ||
60 | "AM6_DEV_WKUP_UART0" : 150, | ||
61 | "AM6_DEV_UART1" : 147, | ||
62 | "AM6_DEV_UART0" : 146, | ||
63 | "AM6_DEV_UART2" : 148, | ||
64 | "AM6_DEV_SA2_UL0" : 136, | ||
65 | "AM6_DEV_CAL0" : 2, | ||
66 | "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4" : 206, | ||
67 | "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3" : 207, | ||
68 | "AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0" : 208, | ||
69 | "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3" : 209, | ||
70 | "AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1" : 210, | ||
71 | "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5" : 211, | ||
72 | "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6" : 212, | ||
73 | "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0" : 213, | ||
74 | "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2" : 214, | ||
75 | "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2" : 215, | ||
76 | "AM6_DEV_PBIST0" : 73, | ||
77 | "AM6_DEV_PBIST1" : 74, | ||
78 | "AM6_DEV_MCU_PBIST0" : 75, | ||
79 | "AM6_DEV_NAVSS0" : 118, | ||
80 | "AM6_DEV_DSS0" : 67, | ||
81 | "AM6_DEV_GPMC0" : 60, | ||
82 | "AM6_DEV_MMCSD1" : 48, | ||
83 | "AM6_DEV_WKUP_PLLCTRL0" : 77, | ||
84 | "AM6_DEV_PLLCTRL0" : 76, | ||
85 | "AM6_DEV_USB3SS1" : 152, | ||
86 | "AM6_DEV_USB3SS0" : 151, | ||
87 | "AM6_DEV_MCU_MCSPI0" : 142, | ||
88 | "AM6_DEV_MCSPI2" : 139, | ||
89 | "AM6_DEV_MCU_MCSPI2" : 144, | ||
90 | "AM6_DEV_MCSPI0" : 137, | ||
91 | "AM6_DEV_MCSPI1" : 138, | ||
92 | "AM6_DEV_MCSPI4" : 141, | ||
93 | "AM6_DEV_MCSPI3" : 140, | ||
94 | "AM6_DEV_MCU_MCSPI1" : 143, | ||
95 | "AM6_DEV_DEBUGSS_WRAP0" : 21, | ||
96 | "AM6_DEV_CBASS_INFRA0" : 85, | ||
97 | "AM6_DEV_STM0" : 8, | ||
98 | "AM6_DEV_MCU_RTI1" : 135, | ||
99 | "AM6_DEV_RTI0" : 130, | ||
100 | "AM6_DEV_RTI3" : 133, | ||
101 | "AM6_DEV_RTI1" : 131, | ||
102 | "AM6_DEV_MCU_RTI0" : 134, | ||
103 | "AM6_DEV_RTI2" : 132, | ||
104 | "AM6_DEV_PSRAMECC0" : 128, | ||
105 | "AM6_DEV_EFUSE0" : 69, | ||
106 | "AM6_DEV_MCASP0" : 104, | ||
107 | "AM6_DEV_MCASP1" : 105, | ||
108 | "AM6_DEV_MCASP2" : 106, | ||
109 | "AM6_DEV_MCU_ARMSS0" : 129, | ||
110 | "AM6_DEV_MCU_ARMSS0_CPU0" : 159, | ||
111 | "AM6_DEV_MCU_ARMSS0_CPU1" : 245, | ||
112 | "AM6_DEV_CCDEBUGSS0" : 66, | ||
113 | "AM6_DEV_WKUP_CTRL_MMR0" : 155, | ||
114 | "AM6_DEV_MCU_CBASS_FW0" : 91, | ||
115 | "AM6_DEV_MCU_CPSW0" : 5, | ||
116 | "AM6_DEV_SERDES0" : 153, | ||
117 | "AM6_DEV_SERDES1" : 154, | ||
118 | "AM6_DEV_OLDI_TX_CORE_MAIN_0" : 216, | ||
119 | "AM6_DEV_MCU_ADC1" : 1, | ||
120 | "AM6_DEV_MCU_ADC0" : 0, | ||
121 | "AM6_DEV_WKUP_DMSC0" : 22, | ||
122 | "AM6_DEV_MCU_PLL_MMR0" : 108, | ||
123 | "AM6_DEV_MCU_SEC_MMR0" : 109, | ||
124 | "AM6_DEV_GIC0" : 56, | ||
125 | "AM6_DEV_MCU_DEBUGSS0" : 71, | ||
126 | "AM6_DEV_EQEP0" : 49, | ||
127 | "AM6_DEV_EQEP2" : 51, | ||
128 | "AM6_DEV_EQEP1" : 50, | ||
129 | "AM6_DEV_WKUP_GPIO0" : 59, | ||
130 | "AM6_DEV_GPIO0" : 57, | ||
131 | "AM6_DEV_GPIO1" : 58, | ||
132 | "AM6_DEV_COMPUTE_CLUSTER_MSMC0" : 196, | ||
133 | "AM6_DEV_COMPUTE_CLUSTER_PBIST0" : 197, | ||
134 | "AM6_DEV_COMPUTE_CLUSTER_CPAC0" : 198, | ||
135 | "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0" : 199, | ||
136 | "AM6_DEV_COMPUTE_CLUSTER_CPAC1" : 200, | ||
137 | "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1" : 201, | ||
138 | "AM6_DEV_COMPUTE_CLUSTER_A53_0" : 202, | ||
139 | "AM6_DEV_COMPUTE_CLUSTER_A53_1" : 203, | ||
140 | "AM6_DEV_COMPUTE_CLUSTER_A53_2" : 204, | ||
141 | "AM6_DEV_COMPUTE_CLUSTER_A53_3" : 205, | ||
142 | "AM6_DEV_WKUP_CBASS0" : 94, | ||
143 | "AM6_DEV_MCU_ROM0" : 78, | ||
144 | "AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0" : 217, | ||
145 | "AM6_DEV_ESM0" : 52, | ||
146 | "AM6_DEV_PRU_ICSSG2" : 64, | ||
147 | "AM6_DEV_PRU_ICSSG0" : 62, | ||
148 | "AM6_DEV_PRU_ICSSG1" : 63, | ||
149 | "AM6_DEV_MCU_ESM0" : 53, | ||
150 | "AM6_DEV_ECAP0" : 39, | ||
151 | "AM6_DEV_WKUP_ESM0" : 54, | ||
152 | "AM6_DEV_MCU_EFUSE0" : 72, | ||
153 | "AM6_DEV_MCU_CTRL_MMR0" : 107, | ||
154 | "AM6_DEV_PSC0" : 70, | ||
155 | "AM6_DEV_CTRL_MMR0" : 99, | ||
156 | "AM6_DEV_MCU_MCAN0" : 102, | ||
157 | "AM6_DEV_MCU_MCAN1" : 103, | ||
158 | "AM6_DEV_DDRSS0" : 20, | ||
159 | "AM6_DEV_MCU_NAVSS0" : 119, | ||
160 | "AM6_DEV_MCU_FSS0" : 55, | ||
161 | "AM6_DEV_DFTSS0" : 117, | ||
162 | "AM6_DEV_WKUP_GPIOMUX_INTRTR0" : 156, | ||
163 | "AM6_DEV_GPIOMUX_INTRTR0" : 100, | ||
164 | "AM6_DEV_MAIN2MCU_LVL_INTRTR0" : 97, | ||
165 | "AM6_DEV_MAIN2MCU_PLS_INTRTR0" : 98, | ||
166 | "AM6_DEV_ICEMELTER_WKUP_0" : 218, | ||
167 | "AM6_DEV_GPU0" : 65, | ||
168 | "AM6_DEV_PDMA_DEBUG0" : 122, | ||
169 | "AM6_DEV_PDMA0" : 123, | ||
170 | "AM6_DEV_PDMA1" : 124, | ||
171 | "AM6_DEV_MCU_PDMA0" : 125, | ||
172 | "AM6_DEV_MCU_PDMA1" : 126, | ||
173 | "AM6_DEV_MCU_MSRAM0" : 116, | ||
174 | "AM6_DEV_CMPEVENT_INTRTR0" : 3, | ||
175 | "AM6_DEV_DEBUGSUSPENDRTR0" : 81, | ||
176 | "AM6_DEV_TIMESYNC_INTRTR0" : 145, | ||
177 | "AM6_DEV_CBASS_DEBUG0" : 83, | ||
178 | "AM6_DEV_CBASS_FW0" : 84, | ||
179 | "AM6_DEV_MCU_CBASS_DEBUG0" : 90, | ||
180 | "AM6_DEV_WKUP_CBASS_FW0" : 96, | ||
181 | "AM6_DEV_PCIE0" : 120, | ||
182 | "AM6_DEV_PCIE1" : 121, | ||
183 | "AM6_DEV_GTC0" : 61, | ||
184 | "AM6_DEV_K3_LED_MAIN_0" : 219, | ||
185 | "AM6_DEV_WKUP_VTM0" : 80, | ||
186 | "AM6_DEV_MMCSD0" : 47, | ||
187 | "AM6_DEV_MCU_ECC_AGGR0" : 92, | ||
188 | "AM6_DEV_ECC_AGGR1" : 87, | ||
189 | "AM6_DEV_ECC_AGGR2" : 88, | ||
190 | "AM6_DEV_MCU_ECC_AGGR1" : 93, | ||
191 | "AM6_DEV_WKUP_ECC_AGGR0" : 95, | ||
192 | "AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU" : 220, | ||
193 | "AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP" : 221, | ||
194 | "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU" : 222, | ||
195 | "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN" : 223, | ||
196 | "AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC" : 224, | ||
197 | "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA" : 225, | ||
198 | "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA" : 226, | ||
199 | "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU" : 227, | ||
200 | "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN" : 228, | ||
201 | "AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU" : 229, | ||
202 | "AM6_DEV_ECC_AGGR0" : 86, | ||
203 | "AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU" : 230, | ||
204 | "AM6_DEV_MCU_PSRAM0" : 127, | ||
205 | "AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0" : 231, | ||
206 | "AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0" : 232, | ||
207 | "AM6_DEV_MCU_CBASS0" : 89, | ||
208 | "AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0" : 233, | ||
209 | "AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0" : 234, | ||
210 | "AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0" : 235, | ||
211 | "AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU" : 236, | ||
212 | "AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA" : 237, | ||
213 | "AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC" : 238, | ||
214 | "AM6_DEV_DUMMY_IP_LPSC_DMSC" : 239, | ||
215 | "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA" : 240, | ||
216 | "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN" : 241, | ||
217 | "AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP" : 242, | ||
218 | "AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU" : 243, | ||
219 | "AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA" : 244, | ||
220 | "AM6_DEV_BOARD0" : 157, | ||
221 | "AM6_DEV_WKUP_DMSC0_CORTEX_M3_0" : 161, | ||
222 | "AM6_DEV_WKUP_DMSC0_INTR_AGGR_0" : 162, | ||
223 | "AM6_DEV_NAVSS0_CPTS0" : 163, | ||
224 | "AM6_DEV_NAVSS0_INTR_ROUTER_0" : 182, | ||
225 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0" : 164, | ||
226 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1" : 165, | ||
227 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2" : 166, | ||
228 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3" : 167, | ||
229 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4" : 168, | ||
230 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5" : 169, | ||
231 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6" : 170, | ||
232 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7" : 171, | ||
233 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8" : 172, | ||
234 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9" : 173, | ||
235 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10" : 174, | ||
236 | "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11" : 175, | ||
237 | "AM6_DEV_NAVSS0_MCRC0" : 176, | ||
238 | "AM6_DEV_NAVSS0_MODSS_INTA0" : 180, | ||
239 | "AM6_DEV_NAVSS0_MODSS_INTA1" : 181, | ||
240 | "AM6_DEV_NAVSS0_PROXY0" : 185, | ||
241 | "AM6_DEV_NAVSS0_PVU0" : 177, | ||
242 | "AM6_DEV_NAVSS0_PVU1" : 178, | ||
243 | "AM6_DEV_NAVSS0_RINGACC0" : 187, | ||
244 | "AM6_DEV_NAVSS0_SEC_PROXY0" : 186, | ||
245 | "AM6_DEV_NAVSS0_TIMER_MGR0" : 183, | ||
246 | "AM6_DEV_NAVSS0_TIMER_MGR1" : 184, | ||
247 | "AM6_DEV_NAVSS0_UDMAP0" : 188, | ||
248 | "AM6_DEV_NAVSS0_UDMASS_INTA0" : 179, | ||
249 | "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0" : 189, | ||
250 | "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0" : 190, | ||
251 | "AM6_DEV_MCU_NAVSS0_MCRC0" : 193, | ||
252 | "AM6_DEV_MCU_NAVSS0_PROXY0" : 191, | ||
253 | "AM6_DEV_MCU_NAVSS0_RINGACC0" : 195, | ||
254 | "AM6_DEV_MCU_NAVSS0_SEC_PROXY0" : 192, | ||
255 | "AM6_DEV_MCU_NAVSS0_UDMAP0" : 194, | ||
256 | |||
257 | "RESASG_SUBTYPE_SHIFT" : 0x0000, | ||
258 | "RESASG_SUBTYPE_MASK" : 0x003F, | ||
259 | "RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT" : 0x00, | ||
260 | "RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI" : 0x01, | ||
261 | "RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI" : 0x02, | ||
262 | "RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI" : 0x03, | ||
263 | "RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT" : 0x04, | ||
264 | "RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT" : 0x00, | ||
265 | "RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI" : 0x01, | ||
266 | "RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT" : 0x02, | ||
267 | "RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT" : 0x00, | ||
268 | "RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI" : 0x01, | ||
269 | "RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT" : 0x02, | ||
270 | "RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT" : 0x00, | ||
271 | "RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI" : 0x01, | ||
272 | "RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI" : 0x02, | ||
273 | "RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI" : 0x03, | ||
274 | "RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT" : 0x04, | ||
275 | "RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI" : 0x00, | ||
276 | "RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT" : 0x01, | ||
277 | "RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI" : 0x00, | ||
278 | "RESASG_SUBTYPE_MCU_NAV_MCRC_CNT" : 0x01, | ||
279 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER" : 0x00, | ||
280 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN" : 0x01, | ||
281 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN" : 0x02, | ||
282 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN" : 0x03, | ||
283 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN" : 0x04, | ||
284 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN" : 0x05, | ||
285 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON" : 0x06, | ||
286 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES" : 0x07, | ||
287 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_GCFG" : 0x08, | ||
288 | "RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT" : 0x09, | ||
289 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER" : 0x00, | ||
290 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN" : 0x01, | ||
291 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN" : 0x02, | ||
292 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN" : 0x03, | ||
293 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN" : 0x04, | ||
294 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON" : 0x05, | ||
295 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES" : 0x06, | ||
296 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_GCFG" : 0x07, | ||
297 | "RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT" : 0x08, | ||
298 | "RESASG_SUBTYPE_MSMC_DRU" : 0x00, | ||
299 | "RESASG_SUBTYPE_MSMC_CNT" : 0x01, | ||
300 | "RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX" : 0x00, | ||
301 | "RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX" : 0x01, | ||
302 | "RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP" : 0x02, | ||
303 | "RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES" : 0x03, | ||
304 | "RESASG_SUBTYPE_MAIN_NAV_RA_VIRTID" : 0x04, | ||
305 | "RESASG_SUBTYPE_MAIN_NAV_RA_MONITOR" : 0x05, | ||
306 | "RESASG_SUBTYPE_MAIN_NAV_RA_CNT" : 0x06, | ||
307 | "RESASG_SUBTYPE_MAIN_NAV_PROXY_PROXIES" : 0x00, | ||
308 | "RESASG_SUBTYPE_MAIN_NAV_PROXY_CNT" : 0x01, | ||
309 | "RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX" : 0x00, | ||
310 | "RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX" : 0x01, | ||
311 | "RESASG_SUBTYPE_MCU_NAV_RA_RING_GP" : 0x02, | ||
312 | "RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES" : 0x03, | ||
313 | "RESASG_SUBTYPE_MCU_NAV_RA_VIRTID" : 0x04, | ||
314 | "RESASG_SUBTYPE_MCU_NAV_RA_MONITOR" : 0x05, | ||
315 | "RESASG_SUBTYPE_MCU_NAV_RA_CNT" : 0x06, | ||
316 | "RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0" : 0x00, | ||
317 | "RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO" : 0x01, | ||
318 | "RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1" : 0x02, | ||
319 | "RESASG_SUBTYPE_GIC_IRQ_COMP_EVT" : 0x03, | ||
320 | "RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO" : 0x04, | ||
321 | "RESASG_SUBTYPE_GIC_IRQ_CNT" : 0x05, | ||
322 | "RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV" : 0x00, | ||
323 | "RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO" : 0x01, | ||
324 | "RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL" : 0x02, | ||
325 | "RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS" : 0x03, | ||
326 | "RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT" : 0x04, | ||
327 | "RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV" : 0x00, | ||
328 | "RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO" : 0x01, | ||
329 | "RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL" : 0x02, | ||
330 | "RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS" : 0x03, | ||
331 | "RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT" : 0x04, | ||
332 | "RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV" : 0x00, | ||
333 | "RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO" : 0x01, | ||
334 | "RESASG_SUBTYPE_ICSSG0_IRQ_CNT" : 0x02, | ||
335 | "RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV" : 0x00, | ||
336 | "RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO" : 0x01, | ||
337 | "RESASG_SUBTYPE_ICSSG1_IRQ_CNT" : 0x02, | ||
338 | "RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV" : 0x00, | ||
339 | "RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO" : 0x01, | ||
340 | "RESASG_SUBTYPE_ICSSG2_IRQ_CNT" : 0x02, | ||
341 | "RESASG_SUBTYPE_MCU_NAV_PROXY_PROXIES" : 0x00, | ||
342 | "RESASG_SUBTYPE_MCU_NAV_PROXY_CNT" : 0x01, | ||
343 | |||
344 | "HOST_ID_DMSC" : 0, | ||
345 | "HOST_ID_R5_0" : 3, | ||
346 | "HOST_ID_R5_1" : 4, | ||
347 | "HOST_ID_R5_2" : 5, | ||
348 | "HOST_ID_R5_3" : 6, | ||
349 | "HOST_ID_A53_0" : 10, | ||
350 | "HOST_ID_A53_1" : 11, | ||
351 | "HOST_ID_A53_2" : 12, | ||
352 | "HOST_ID_A53_3" : 13, | ||
353 | "HOST_ID_A53_4" : 14, | ||
354 | "HOST_ID_A53_5" : 15, | ||
355 | "HOST_ID_A53_6" : 16, | ||
356 | "HOST_ID_A53_7" : 17, | ||
357 | "HOST_ID_GPU_0" : 30, | ||
358 | "HOST_ID_GPU_1" : 31, | ||
359 | "HOST_ID_ICSSG_0" : 50, | ||
360 | "HOST_ID_ICSSG_1" : 51, | ||
361 | "HOST_ID_ICSSG_2" : 52, | ||
362 | "HOST_ID_ALL" : 128, | ||
363 | "HOST_ID_CNT" : 19, | ||
364 | } | ||
diff --git a/respart/am65x_sr2.py b/respart/am65x_sr2.py new file mode 100644 index 0000000..6294a79 --- /dev/null +++ b/respart/am65x_sr2.py | |||
@@ -0,0 +1,70 @@ | |||
1 | # am65x_sr2.py - Auto generated SoC data | ||
2 | |||
3 | |||
4 | RESASG_TYPE_SHIFT = 6 | ||
5 | RESASG_SUBTYPE_SHIFT = 0 | ||
6 | |||
7 | const_values = { | ||
8 | "AM6_DEV_CMPEVENT_INTRTR0" : 3, | ||
9 | "AM6_DEV_MAIN2MCU_LVL_INTRTR0" : 97, | ||
10 | "AM6_DEV_MAIN2MCU_PLS_INTRTR0" : 98, | ||
11 | "AM6_DEV_GPIOMUX_INTRTR0" : 100, | ||
12 | "AM6_DEV_TIMESYNC_INTRTR0" : 145, | ||
13 | "AM6_DEV_WKUP_GPIOMUX_INTRTR0" : 156, | ||
14 | "AM6_DEV_NAVSS0_UDMASS_INTA0" : 179, | ||
15 | "AM6_DEV_NAVSS0_MODSS_INTA0" : 180, | ||
16 | "AM6_DEV_NAVSS0_MODSS_INTA1" : 181, | ||
17 | "AM6_DEV_NAVSS0_INTR_ROUTER_0" : 182, | ||
18 | "AM6_DEV_NAVSS0_PROXY0" : 185, | ||
19 | "AM6_DEV_NAVSS0_RINGACC0" : 187, | ||
20 | "AM6_DEV_NAVSS0_UDMAP0" : 188, | ||
21 | "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0" : 189, | ||
22 | "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0" : 190, | ||
23 | "AM6_DEV_MCU_NAVSS0_PROXY0" : 191, | ||
24 | "AM6_DEV_MCU_NAVSS0_UDMAP0" : 194, | ||
25 | "AM6_DEV_MCU_NAVSS0_RINGACC0" : 195, | ||
26 | |||
27 | "RESASG_SUBTYPE_IR_OUTPUT" : 0, | ||
28 | "RESASG_SUBTYPE_PROXY_PROXIES" : 0, | ||
29 | "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON" : 0, | ||
30 | "RESASG_SUBTYPE_RA_ERROR_OES" : 0, | ||
31 | "RESASG_SUBTYPE_RA_GP" : 1, | ||
32 | "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES" : 1, | ||
33 | "RESASG_SUBTYPE_RA_UDMAP_RX" : 2, | ||
34 | "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER" : 2, | ||
35 | "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG" : 3, | ||
36 | "RESASG_SUBTYPE_RA_UDMAP_TX" : 3, | ||
37 | "RESASG_SUBTYPE_RA_UDMAP_TX_EXT" : 4, | ||
38 | "RESASG_SUBTYPE_RA_UDMAP_RX_H" : 5, | ||
39 | "RESASG_SUBTYPE_RA_UDMAP_TX_H" : 7, | ||
40 | "RESASG_SUBTYPE_RA_VIRTID" : 10, | ||
41 | "RESASG_SUBTYPE_IA_VINT" : 10, | ||
42 | "RESASG_SUBTYPE_UDMAP_RX_CHAN" : 10, | ||
43 | "RESASG_SUBTYPE_UDMAP_RX_HCHAN" : 11, | ||
44 | "RESASG_SUBTYPE_RA_MONITORS" : 11, | ||
45 | "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT" : 13, | ||
46 | "RESASG_SUBTYPE_UDMAP_TX_CHAN" : 13, | ||
47 | "RESASG_SUBTYPE_UDMAP_TX_ECHAN" : 14, | ||
48 | "RESASG_SUBTYPE_UDMAP_TX_HCHAN" : 15, | ||
49 | |||
50 | "HOST_ID_DMSC" : 0, | ||
51 | "HOST_ID_R5_0" : 3, | ||
52 | "HOST_ID_R5_1" : 4, | ||
53 | "HOST_ID_R5_2" : 5, | ||
54 | "HOST_ID_R5_3" : 6, | ||
55 | "HOST_ID_A53_0" : 10, | ||
56 | "HOST_ID_A53_1" : 11, | ||
57 | "HOST_ID_A53_2" : 12, | ||
58 | "HOST_ID_A53_3" : 13, | ||
59 | "HOST_ID_A53_4" : 14, | ||
60 | "HOST_ID_A53_5" : 15, | ||
61 | "HOST_ID_A53_6" : 16, | ||
62 | "HOST_ID_A53_7" : 17, | ||
63 | "HOST_ID_CNT" : 19, | ||
64 | "HOST_ID_GPU_0" : 30, | ||
65 | "HOST_ID_GPU_1" : 31, | ||
66 | "HOST_ID_ICSSG_0" : 50, | ||
67 | "HOST_ID_ICSSG_1" : 51, | ||
68 | "HOST_ID_ICSSG_2" : 52, | ||
69 | "HOST_ID_ALL" : 128, | ||
70 | } \ No newline at end of file | ||
diff --git a/respart/am6x.py b/respart/am6x.py new file mode 100644 index 0000000..e56f6aa --- /dev/null +++ b/respart/am6x.py | |||
@@ -0,0 +1,70 @@ | |||
1 | # am6x.py - Auto generated SoC data | ||
2 | |||
3 | |||
4 | RESASG_TYPE_SHIFT = 6 | ||
5 | RESASG_SUBTYPE_SHIFT = 0 | ||
6 | |||
7 | const_values = { | ||
8 | "AM6_DEV_CMPEVENT_INTRTR0" : 3, | ||
9 | "AM6_DEV_MAIN2MCU_LVL_INTRTR0" : 97, | ||
10 | "AM6_DEV_MAIN2MCU_PLS_INTRTR0" : 98, | ||
11 | "AM6_DEV_GPIOMUX_INTRTR0" : 100, | ||
12 | "AM6_DEV_TIMESYNC_INTRTR0" : 145, | ||
13 | "AM6_DEV_WKUP_GPIOMUX_INTRTR0" : 156, | ||
14 | "AM6_DEV_NAVSS0_UDMASS_INTA0" : 179, | ||
15 | "AM6_DEV_NAVSS0_MODSS_INTA0" : 180, | ||
16 | "AM6_DEV_NAVSS0_MODSS_INTA1" : 181, | ||
17 | "AM6_DEV_NAVSS0_INTR_ROUTER_0" : 182, | ||
18 | "AM6_DEV_NAVSS0_PROXY0" : 185, | ||
19 | "AM6_DEV_NAVSS0_RINGACC0" : 187, | ||
20 | "AM6_DEV_NAVSS0_UDMAP0" : 188, | ||
21 | "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0" : 189, | ||
22 | "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0" : 190, | ||
23 | "AM6_DEV_MCU_NAVSS0_PROXY0" : 191, | ||
24 | "AM6_DEV_MCU_NAVSS0_UDMAP0" : 194, | ||
25 | "AM6_DEV_MCU_NAVSS0_RINGACC0" : 195, | ||
26 | |||
27 | "RESASG_SUBTYPE_IR_OUTPUT" : 0, | ||
28 | "RESASG_SUBTYPE_PROXY_PROXIES" : 0, | ||
29 | "RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON" : 0, | ||
30 | "RESASG_SUBTYPE_RA_ERROR_OES" : 0, | ||
31 | "RESASG_SUBTYPE_RA_GP" : 1, | ||
32 | "RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES" : 1, | ||
33 | "RESASG_SUBTYPE_RA_UDMAP_RX" : 2, | ||
34 | "RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER" : 2, | ||
35 | "RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG" : 3, | ||
36 | "RESASG_SUBTYPE_RA_UDMAP_TX" : 3, | ||
37 | "RESASG_SUBTYPE_RA_UDMAP_TX_EXT" : 4, | ||
38 | "RESASG_SUBTYPE_RA_UDMAP_RX_H" : 5, | ||
39 | "RESASG_SUBTYPE_RA_UDMAP_TX_H" : 7, | ||
40 | "RESASG_SUBTYPE_RA_VIRTID" : 10, | ||
41 | "RESASG_SUBTYPE_IA_VINT" : 10, | ||
42 | "RESASG_SUBTYPE_UDMAP_RX_CHAN" : 10, | ||
43 | "RESASG_SUBTYPE_UDMAP_RX_HCHAN" : 11, | ||
44 | "RESASG_SUBTYPE_RA_MONITORS" : 11, | ||
45 | "RESASG_SUBTYPE_GLOBAL_EVENT_SEVT" : 13, | ||
46 | "RESASG_SUBTYPE_UDMAP_TX_CHAN" : 13, | ||
47 | "RESASG_SUBTYPE_UDMAP_TX_ECHAN" : 14, | ||
48 | "RESASG_SUBTYPE_UDMAP_TX_HCHAN" : 15, | ||
49 | |||
50 | "HOST_ID_DMSC" : 0, | ||
51 | "HOST_ID_R5_0" : 3, | ||
52 | "HOST_ID_R5_1" : 4, | ||
53 | "HOST_ID_R5_2" : 5, | ||
54 | "HOST_ID_R5_3" : 6, | ||
55 | "HOST_ID_A53_0" : 10, | ||
56 | "HOST_ID_A53_1" : 11, | ||
57 | "HOST_ID_A53_2" : 12, | ||
58 | "HOST_ID_A53_3" : 13, | ||
59 | "HOST_ID_A53_4" : 14, | ||
60 | "HOST_ID_A53_5" : 15, | ||
61 | "HOST_ID_A53_6" : 16, | ||
62 | "HOST_ID_A53_7" : 17, | ||
63 | "HOST_ID_CNT" : 19, | ||
64 | "HOST_ID_GPU_0" : 30, | ||
65 | "HOST_ID_GPU_1" : 31, | ||
66 | "HOST_ID_ICSSG_0" : 50, | ||
67 | "HOST_ID_ICSSG_1" : 51, | ||
68 | "HOST_ID_ICSSG_2" : 52, | ||
69 | "HOST_ID_ALL" : 128, | ||
70 | } \ No newline at end of file | ||