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authorNikhil Devshatwar2018-02-28 03:58:17 -0600
committerNikhil Devshatwar2018-02-28 03:58:21 -0600
commit0a35fa4788862a93bcb15ad80e89c23d56c03fa4 (patch)
tree11c488c6905dc8d4a9bc0a1d0734d0a083e19eb8
parentce834862e50ec4c5dff2ea2cf63b5bc6ebdfc6a2 (diff)
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arm: dt-bindings: dra: Correct VIP MUX bindingsp-ti-lsk-linux-4.4.y-3.x
Compiler macros used for the fields used to select the VIP MUX are wrong. This causes to fail the configuration of the internal MUX in the dra72x SoCs. Correct the definition in the dt-bindings. Also updated the DTS file using these to setup correct MUX Change-Id: I6140bd5c4d3162e5d658b96018ae659d042956db Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
-rw-r--r--arch/arm/boot/dts/dra72-evm-vision.dts7
-rw-r--r--include/dt-bindings/pinctrl/dra.h18
2 files changed, 15 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/dra72-evm-vision.dts b/arch/arm/boot/dts/dra72-evm-vision.dts
index b59d44f20772..877077fce9a6 100644
--- a/arch/arm/boot/dts/dra72-evm-vision.dts
+++ b/arch/arm/boot/dts/dra72-evm-vision.dts
@@ -44,8 +44,11 @@ i2cexp: &i2c5 {
44 * vin2B <= vin2B (default) 44 * vin2B <= vin2B (default)
45 */ 45 */
46 vip_mux: pinmux_vin5a_pins { 46 vip_mux: pinmux_vin5a_pins {
47 pinctrl-single,pins = < 47 pinctrl-single,pins = <0x0 (
48 0x0 (VIP_VIN3A | VIP_VIN4B | VIP_VIN2A | VIP_VIN2B) 48 VIP_VIN1A_GRP3A |
49 VIP_VIN1B_GRP4B |
50 VIP_VIN2A_GRP2A |
51 VIP_VIN2B_GRP2B)
49 >; 52 >;
50 }; 53 };
51}; 54};
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
index 50c3f1b97560..5a33a723bb07 100644
--- a/include/dt-bindings/pinctrl/dra.h
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -80,16 +80,18 @@
80#define G_DELAY(val) (((val) & 0xFFFF) << 16) 80#define G_DELAY(val) (((val) & 0xFFFF) << 16)
81 81
82/* DRA72 VIP MUX selection parameters */ 82/* DRA72 VIP MUX selection parameters */
83#define VIP_VIN3A (0x0 << 4) 83#define VIP_VIN1A_GRP3A (0x0 << 4)
84#define VIP_VIN5A (0x1 << 4) 84#define VIP_VIN1A_GRP5A (0x1 << 4)
85#define VIP_VIN6A (0x2 << 4) 85#define VIP_VIN1A_GRP6A (0x2 << 4)
86#define VIP_VIN1A_GRP4A (0x3 << 4)
86 87
87#define VIP_VIN4B (0x0 << 3) 88#define VIP_VIN1B_GRP4B (0x0 << 3)
89#define VIP_VIN1B_GRP3B (0x1 << 3)
88 90
89#define VIP_VIN2A (0x0 << 1) 91#define VIP_VIN2A_GRP2A (0x0 << 1)
90#define VIP_VIN4A (0x1 << 1) 92#define VIP_VIN2a_GRP4A (0x1 << 1)
91 93
92#define VIP_VIN3B (0x0 << 0) 94#define VIP_VIN2B_GRP2B (0x0 << 0)
93#define VIP_VIN2B (0x1 << 0) 95#define VIP_VIN2B_GRP3B (0x1 << 0)
94 96
95#endif 97#endif